CN116661998A - Method for improving OPC operation efficiency - Google Patents

Method for improving OPC operation efficiency Download PDF

Info

Publication number
CN116661998A
CN116661998A CN202310626744.3A CN202310626744A CN116661998A CN 116661998 A CN116661998 A CN 116661998A CN 202310626744 A CN202310626744 A CN 202310626744A CN 116661998 A CN116661998 A CN 116661998A
Authority
CN
China
Prior art keywords
opc
improving
available
product chip
operation efficiency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310626744.3A
Other languages
Chinese (zh)
Inventor
王丹
陈燕鹏
于世瑞
张瑜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Original Assignee
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Integrated Circuit Manufacturing Co Ltd filed Critical Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority to CN202310626744.3A priority Critical patent/CN116661998A/en
Publication of CN116661998A publication Critical patent/CN116661998A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention provides a method for improving OPC operation efficiency, which comprises the following steps: calculating to obtain the initial recommended number of the blade servers according to the area of the product chip; determining a range of available numbers of the blade servers from the initial recommended number; determining CPU resource usage and the optimal available quantity according to the available quantity and OPC running time within the range of the available quantity; wherein the result of multiplying the optimal available quantity by the OPC running time is minimized on the premise of meeting the running speed on the factory line. The invention solves the problem that the prior fixed number of blade servers are used for publishing the mask plate, which easily leads to lower CPU utilization rate.

Description

Method for improving OPC operation efficiency
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving OPC operation efficiency.
Background
In the photolithography process, a pattern structure corresponding to a layout on a Mask, i.e., a Mask (Mask), is projected into a photoresist through an exposure system and forms a corresponding pattern structure in the photoresist, however, due to an optical reason or a chemical reaction of the photoresist in an exposure process, a deviation exists between the pattern structure formed in the photoresist and the pattern structure on the Mask, and the deviation needs to be modified in advance by OPC (optical proximity correction), and when the Mask after OPC correction is used for exposure, the pattern structure formed in the photoresist is in accordance with the designed pattern structure and meets the process production requirements.
When preparing the mask, the OPC hardware resource = OPC hierarchical number (CPU core number) occupied by product publishing and DMPL are calculated, wherein the OPC hierarchical number is determined by the process nodes and the process platform of the product; DMPL (number of days required to average out a layer) is related to the speed of the running on the factory line; how many CPU cores (blade servers) are determines how much OPC hardware resources a product publication occupies.
However, the prior art generally uses fixed blade servers based on process nodes and process platforms, and there is no in-depth study on OPC operational efficiency.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for improving OPC operation efficiency, so as to solve the problem that the existing fixed number of blade servers are prone to lower CPU utilization rate when used for publishing masks.
To achieve the above and other related objects, the present invention provides a method for OPC operation efficiency, the method comprising:
calculating to obtain the initial recommended number of the blade servers according to the area of the product chip;
determining a range of available numbers of the blade servers from the initial recommended number;
determining CPU resource usage and the optimal available quantity according to the available quantity and OPC running time within the range of the available quantity;
wherein the result of multiplying the optimal available quantity by the OPC running time is minimized on the premise of meeting the running speed on the factory line.
Optionally, the product coreThe maximum value of the sheet area is 858mm 2 Wherein the length is 26mm and the width is 33mm.
Optionally, the calculation formula for calculating the initial recommended number of the blade servers according to the product chip area is as follows:
Num＝A*S+B*S 1/2
wherein Num represents the initial recommended number, S represents the product chip area, a represents a first coefficient, and B represents a second coefficient.
Optionally, the first coefficient and the second coefficient are determined by using a first product chip and a second product chip, wherein the area of the first product chip is 2 times or more than that of the second product chip, and the total CPU utilization rate of the first product chip and the second product chip is 80% or more.
Optionally, the first product chip and the second product chip are selected from an OPC script running log.
Optionally, the range of available numbers of blade servers includes: 0.2-5 times the initial recommended number.
Optionally, the method for determining the CPU resource usage and the best available number according to the available number and the OPC runtime comprises:
and determining the CPU resource usage amount by utilizing the product of the available amount and the OPC running time within the range of the available amount, wherein the available amount is the optimal available amount when the CPU resource usage amount reaches the minimum value on the premise of meeting the running speed on the factory line.
Optionally, the OPC run time decreases as the number of blade servers increases.
Accordingly, the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method of improving OPC operation efficiency as described above.
Correspondingly, the terminal comprises a processor and a memory, wherein the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory, so that the terminal executes the method for improving OPC operation efficiency.
As described above, the method for improving OPC operation efficiency of the present invention determines the initial recommended number of the blade server by using the product chip area, determines the available number according to the initial recommended number, measures the CPU resource usage amount by using the available number and OPC running time, determines the best available number, and achieves the purpose of improving OPC operation efficiency by publishing the mask by using the best available number.
Drawings
FIG. 1 is a flow chart of a method for improving OPC operation efficiency in accordance with the present invention.
FIG. 2 shows a graph of OPC run time run versus number of blade server CPU cores of the present invention.
FIG. 3 is a graph showing the relationship between CPU resource usage and CPU core number according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the present embodiment provides a method for improving OPC operation efficiency, which includes:
calculating to obtain the initial recommended number of the blade servers according to the area of the product chip;
determining a range of available numbers of the blade servers from the initial recommended number;
determining CPU resource usage and the optimal available quantity according to the available quantity and OPC running time within the range of the available quantity;
wherein the result of multiplying the optimal available quantity by the OPC running time is minimized on the premise of meeting the running speed on the factory line.
In this embodiment, the chip (chip) area of each NTO product of each process platform is different, and when publishing, the number of large-area required blade servers (CPU cores) is large, and the number of small-area required CPU cores is small, so that the CPU cores can be allocated according to the chip area to avoid waste. OPC publishing can formulate a range of the number of CPU cores to use based on chip area to ensure higher CPU utilization and relatively shorter run time. In this embodiment, the product chip area is the layout area, and may be obtained from the GDS file.
Specifically, the maximum value of the chip area of the product is 858mm 2 Wherein the length is 26mm and the width is 33mm.
Specifically, the calculation formula for calculating the initial recommended number of the blade server according to the area of the product chip is as follows:
Num＝A*S+B*S 1/2
wherein Num represents the initial recommended number, S represents the product chip area, a represents a first coefficient, and B represents a second coefficient.
Specifically, the first coefficient and the second coefficient are determined by using a first product chip and a second product chip, wherein the area of the first product chip is 2 times or more than that of the second product chip, and the total CPU utilization rate of the first product chip and the second product chip is 80% or more.
More specifically, the first product chip and the second product chip are selected from an OPC script running log.
In this embodiment, when determining the first coefficient a and the second coefficient B,the OPC script obtained from previous runs of a process platform (any of the process platforms requiring OPC, 65nm, 55nm, 50nm, 40nm, 28nm, or 22nm, etc.) allows two product chips to be selected from the log. Table 1 gives the relevant information of the two selected product chips, and the specific formula for obtaining the initial recommended number of CPU cores of the process platform by bringing the area and the number of allocated CPU into the above formula to obtain the first coefficient a=4.3 and the second coefficient b=2.87 is as follows: num=4.3×s+2.87×s 1 /2 It is assumed that the process platform has a product chip area of 8.41mm 2 The initial recommended number of corresponding blade servers may be calculated as 44.
Table 1:
chip area 1.9mm*1.8mm＝3.42mm 2 4.5mm*4.5mm＝20.25mm 2
Distributing CPU number 20 100
Total CPU utilization ≥80％ ≥80％
Specifically, the range of available numbers of blade servers includes: 0.2-5 times the initial recommended number.
Specifically, the method for determining the CPU resource usage and the optimal available quantity according to the available quantity and the OPC running time comprises the following steps: and determining the CPU resource usage amount by utilizing the product of the available amount and the OPC running time within the range of the available amount, wherein the CPU resource usage amount reaches the minimum value on the premise of meeting the running speed on the factory line, and the corresponding available amount is the optimal available amount.
Specifically, the OPC run time decreases as the number of blade servers increases.
In this embodiment, the CPU resource usage is measured as the product of the number of blade servers (CPU cores) and the OPC runtime (runtimes). And on the premise that the chip area of the product and the initial recommended number of the CPU cores are known, the CPU core number and the runtime are subjected to split test within the range of 0.2-5 times of the initial recommended number of the CPU cores.
In this embodiment, the number of CPU cores 20, 40, 60, and 100 is selected for testing, where the number of CPU cores 40, 60, 80, or 100 may not be in a completely linear relationship (as shown in fig. 2), and all of the number of CPU cores 40, 60, 80, or 100 may satisfy the DMPL requirement (i.e., satisfy the requirement of the running speed on the factory line), and when the number of CPU cores is 60, not only the DPML requirement but also the CPU resource usage amount is the lowest (as shown in fig. 3), i.e., the OPC operation efficiency is the highest, so, when the process platform performs the subsequent publishing on the same chip area, the CPU core usage amount may be reduced from 100 to 60, and after using the method provided in this embodiment, 300 CPU cores may support 5 publications, so that the OPC operation efficiency is improved by about 67%, and it should be noted that 100 is the number of CPU cores that are used fixedly before the process platform.
Accordingly, the present embodiment also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of improving OPC operation efficiency as described above.
In particular, the computer-readable storage medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (compact disk-read-Only memory), magneto-optical disks, ROMs (read-Only memory), RAMs (random Access memory), EPROMs (erasable programmable read-Only memory), EEPROMs (electrically erasable programmable read-Only memory), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing executable instructions, and may be an article of manufacture, not having access to a computer device, or a component that has access to a computer device for use.
Correspondingly, the embodiment also provides a terminal, which comprises a processor and a memory, wherein the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory, so that the terminal executes the method for improving the OPC operation efficiency.
In summary, the method for improving the OPC operation efficiency of the present invention determines the initial recommended number of the blade server by using the product chip area, determines the available number according to the initial recommended number, measures the CPU resource usage by using the available number and the OPC running time, determines the best available number, and achieves the purpose of improving the OPC operation efficiency by publishing the mask by using the best available number. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A method for improving OPC operation efficiency, the method comprising:
calculating to obtain the initial recommended number of the blade servers according to the area of the product chip;
determining a range of available numbers of the blade servers from the initial recommended number;
determining CPU resource usage and the optimal available quantity according to the available quantity and OPC running time within the range of the available quantity;
wherein the result of multiplying the optimal available quantity by the OPC running time is minimized on the premise of meeting the running speed on the factory line.
2. The method for improving OPC operation efficiency as in claim 1, wherein the maximum value of the product chip area is 858mm 2 Wherein the length is 26mm and the width is 33mm.
3. The method for improving OPC operation efficiency according to claim 1 or 2, wherein the calculation formula for calculating the initial recommended number of the blade server according to the product chip area is:
Num＝A*S+B*S 1/2
wherein Num represents the initial recommended number, S represents the product chip area, a represents a first coefficient, and B represents a second coefficient.
4. The method of improving OPC operation efficiency as recited in claim 3 wherein the first coefficient and the second coefficient are determined by a first product chip and a second product chip, wherein the area of the first product chip is 2 times or more larger than the area of the second product chip, and the total CPU utilization of both is 80% or more.
5. The method of claim 4, wherein the first product chip and the second product chip are selected from an OPC script running log.
6. The method of improving OPC operational efficiency of claim 1 wherein the range of available numbers of blade servers comprises: 0.2-5 times the initial recommended number.
7. The method of improving OPC operating efficiency of claim 6 wherein the method of determining CPU resource usage and determining the best available amount based on the available amount and OPC run time comprises:
and determining the CPU resource usage amount by utilizing the product of the available amount and the OPC running time within the range of the available amount, wherein the available amount is the optimal available amount when the CPU resource usage amount reaches the minimum value on the premise of meeting the running speed on the factory line.
8. The method of improving OPC operating efficiency of claim 7 wherein the OPC run time decreases as the number of blade servers increases.
9. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements a method of improving the efficiency of OPC operations according to any of claims 1 to 8.
10. A terminal, characterized in that the terminal comprises a processor and a memory, the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory, so that the terminal executes the method for improving the OPC operation efficiency according to any one of claims 1-8.
CN202310626744.3A 2023-05-30 2023-05-30 Method for improving OPC operation efficiency Pending CN116661998A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310626744.3A CN116661998A (en) 2023-05-30 2023-05-30 Method for improving OPC operation efficiency

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310626744.3A CN116661998A (en) 2023-05-30 2023-05-30 Method for improving OPC operation efficiency

Publications (1)

Publication Number Publication Date
CN116661998A true CN116661998A (en) 2023-08-29

Family

ID=87720068

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310626744.3A Pending CN116661998A (en) 2023-05-30 2023-05-30 Method for improving OPC operation efficiency

Country Status (1)

Country Link
CN (1) CN116661998A (en)

Similar Documents

Publication Publication Date Title
CN103309149B (en) Optical proximity correction method
US11763058B2 (en) Method and computing device for manufacturing semiconductor device
US7454302B2 (en) Method of inspecting integrated circuits during fabrication
US20140162460A1 (en) Method of forming a pattern
CN112655071A (en) Learning device, estimation device, and learned model
CN101661219A (en) Method and device for correcting mask plate patterns
US8458631B2 (en) Cycle time reduction in data preparation
US7709300B2 (en) Structure and method for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks
CN116661998A (en) Method for improving OPC operation efficiency
JP3223965B2 (en) Calculation method of chemically amplified resist shape and recording medium
CN101458719B (en) Method for verifying optical approximatino correction
CN112818632B (en) Analysis method and device for pattern density of chip and electronic equipment
CN114488681A (en) Optical proximity correction method and device
CN114818395B (en) Production scheduling simulation method and device based on ROPN model
CN110928149B (en) Control method and control system for critical dimension
CN101286015B (en) Developing method for improving critical dimension uniformity
CN112882946B (en) PDK test optimization method, device, storage medium and equipment
CN106873305B (en) Optical proximity effect correction method
CN210776174U (en) Combined light shield
CN111400993B (en) Layout design rule verification graph generation method, device, equipment and graph library
JP6167663B2 (en) Development loading correction program, computer, drawing system, development loading correction method
CN113990777A (en) Method and device for forming yield wafer map, readable storage medium and terminal
CN112415864A (en) Method for determining OPC minimum segmentation length
CN102623302B (en) Reworking control method and control system thereof
Berglund et al. The potential for economic application of maskless lithography in semiconductor manufacturing

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination