CN116661964A - Task processing method and device and electronic equipment - Google Patents
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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Abstract
The application provides a task processing method, a task processing device and electronic equipment, and relates to the technical field of computers, wherein the task processing method comprises the following steps: determining a scheduling priority of a first task according to first parameter information of the first task, wherein the first parameter information comprises at least one of a task type and a task importance level; selecting a target processor core from N processor cores according to second parameter information of the first task, wherein the second parameter information comprises calculation force demand information and scheduling priority, and N is an integer greater than 1; and executing the first task on the target processor core according to the scheduling priority of the first task.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a task processing method, a task processing device, and an electronic device.
Background
A multi-core central processing unit (Central Processing Unit, CPU) is a CPU having multiple processor cores, where each processor core may independently execute instructions and multiple processor cores may simultaneously perform different tasks, thereby improving performance and efficiency of the processor. Furthermore, today's operating systems are typically multi-threaded environments in which each processor core may execute multiple threads simultaneously, thereby enabling concurrent execution. At present, a fair scheduling algorithm (Completely Fair Scheduler, CFS) is generally used for realizing fair scheduling of tasks on a CPU, wherein the CFS is a scheduling algorithm based on time, divides the time of the CPU into time slices, allocates a certain time slice to each process respectively, and processes each task are processed in the corresponding time slice, however, the fair scheduling manner is difficult to ensure the processing effect of some tasks.
Disclosure of Invention
The embodiment of the application provides a task processing method, a task processing device and electronic equipment, which can ensure the processing speed of some tasks and further improve the fluency of the tasks.
In a first aspect, an embodiment of the present application provides a task processing method, where the method includes:
determining a scheduling priority of a first task according to first parameter information of the first task, wherein the first parameter information comprises at least one of a task type and a task importance level;
selecting a target processor core from N processor cores according to second parameter information of the first task, wherein the second parameter information comprises calculation force demand information and scheduling priority, and N is an integer greater than 1;
and executing the first task on the target processor core according to the scheduling priority of the first task.
In a second aspect, an embodiment of the present application provides a task processing device, including:
the first determining module is used for determining the scheduling priority of a first task according to first parameter information of the first task, wherein the first parameter information comprises at least one of a task type and a task importance level;
A first selection module, configured to select a target processor core from N processor cores according to second parameter information of the first task, where the second parameter information includes calculation power demand information and scheduling priority, and N is an integer greater than 1;
and the execution module is used for executing the first task on the target processor core according to the scheduling priority of the first task.
In a third aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, where the memory stores a program or instructions executable on the processor, the program or instructions implementing the steps in the task processing method according to the first aspect when executed by the processor.
In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement the steps in the task processing method according to the first aspect.
In a fifth aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and where the processor is configured to execute a program or instructions to implement a method according to the first aspect.
In a sixth aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement the method according to the first aspect.
In the embodiment of the application, the scheduling priority of the task is determined according to at least one of the task type and the task importance level of the task, and the task is processed based on the scheduling priority, so that the priority scheduling of some tasks (such as foreground tasks and the like) can be realized, and the processing speed of the tasks can be improved.
Drawings
FIG. 1 is a flow chart of a task processing method provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of a multiprocessor core provided by an embodiment of the present application;
FIG. 3 is a flowchart of another task processing method according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a task processing device according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 6 is a second schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The task processing method, the task processing device and the electronic equipment provided by the embodiment of the application are described in detail through specific embodiments and application scenes thereof by combining the attached drawings.
Referring to fig. 1, fig. 1 is a flowchart of a task processing method according to an embodiment of the present application, as shown in fig. 1, including the following steps:
step 101, determining a scheduling priority of a first task according to first parameter information of the first task, wherein the first parameter information comprises at least one of a task type and a task importance level.
In this embodiment, the first task may be any task to be processed or scheduled.
The task types can be reasonably set according to actual requirements, for example, the task types can comprise foreground tasks or background tasks, or the task types can comprise multimedia tasks (such as audio tasks, video tasks or game tasks) or non-multimedia tasks. In some alternative embodiments, the foregoing front-to-back tasks may be further divided into video tasks in the foreground, game tasks in the foreground, tasks for widget applications in the foreground, and the like. By way of example, the task type may be identified based on one or more of the information of the application package name, whether it is visible, whether there is focus, the status of the audio, and whether the input operation is frequent.
The task importance level is determined according to at least one of task type, load size, calculation force demand information and the like of the task. The above-mentioned calculation force demand information may be used to indicate a calculation force value required for executing a task, for example, may be a calculation force value counted based on a calculation force value consumed for executing the same task a plurality of times, or may be divided in advance into a plurality of calculation force classes, and may be used to indicate a calculation force class corresponding to a task, for example, a first calculation force class indicating that the required calculation force is relatively large and a second calculation force class indicating that the required calculation force is relatively small are divided in advance, and may be used to establish in advance a correspondence between different tasks and calculation force classes, for example, a multimedia-based task (for example, an audio task, a video task, a game task, or the like) corresponds to the first calculation force class, and a non-multimedia-based task corresponds to the second calculation force class.
In some alternative embodiments, the task types may be divided first, and for the tasks of the same task type, the task importance levels of the tasks may be further determined, for example, the tasks may be divided into two classes, a foreground task and a background task, and for the foreground task, the task importance levels of the foreground tasks may be further determined, for example, the task importance levels of the foreground tasks of the multimedia class (for example, the audio task, the video task, or the game task, etc.) are greater than the task importance levels of the foreground tasks of the non-multimedia class.
The above-mentioned scheduling priority may be used to indicate the sequence in which the tasks are scheduled, where the higher the scheduling priority, the more preferentially the tasks are scheduled, for example, the scheduling priority of the task a is the scheduling priority a1, the scheduling priority of the task b is the scheduling priority b1 in the same processor core, and if the scheduling priority a1 is higher than the scheduling priority b1, the task a is scheduled in preference to the task b.
In an embodiment, if the first parameter information includes a task type, the scheduling priority of the first task may be determined according to the task type of the first task, for example, a correspondence between the task type and the scheduling priority may be pre-established, for example, a foreground task corresponds to the scheduling priority a1, a background task corresponds to the second scheduling priority b1, and the first scheduling priority a1 is higher than the second scheduling priority b1, so that the scheduling priority of the first task may be rapidly determined based on the correspondence and the task type of the first task.
In another embodiment, if the first parameter information includes a task importance level, the scheduling priority of the first task may be determined according to the task importance level of the first task, for example, a correspondence between the task importance level and the scheduling priority may be pre-established, for example, the higher the task importance level, the higher the scheduling priority corresponding to the task, and further the scheduling priority of the first task may be rapidly determined based on the correspondence and the task importance level of the first task.
In still another embodiment, if the first parameter information includes a task type and a task importance level, the scheduling priority of the first task may be determined according to the task type and the task importance level of the first task, for example, a correspondence relationship between the task type, the task importance level and the scheduling priority may be established, for example, a foreground task with a task importance level of a and corresponding to the scheduling priority a11, a foreground task with a task importance level of b corresponds to the scheduling priority a12, a background task corresponds to the scheduling priority a2, and if a is greater than b, the scheduling priority a11 is higher than the scheduling priority a12, and the scheduling priority a12 is higher than the scheduling priority a2, and further, the scheduling priority of the first task may be rapidly determined based on the correspondence relationship and the task type and the task importance level of the first task.
Step 102, selecting a target processor core from N processor cores according to second parameter information of the first task, where the second parameter information includes calculation force demand information and scheduling priority, and N is an integer greater than 1.
In this embodiment, the force demand information and the scheduling priority may be referred to the above description, and will not be described herein.
The processing capabilities of each of the N processor cores may be the same; alternatively, the N processor cores may include at least two types of processor cores having different processing capacities, for example, the N processor cores may include a first type of processor core, a second type of processor core, and a third type of processor core, where the processing capacity of the first type of processor core is greater than that of the second type of processor core, and the processing capacity of the second type of processor core is greater than that of the third type of processor core. Illustratively, as shown in FIG. 2, comprising 1 large processor core, 4 medium processor cores, and 3 small processor cores, wherein different sizes of processor cores correspond to different processing capabilities, e.g., the capability of a large processor core may be 3 times or even more than 4 times the processing capability of a small processor core. The measure of the processing capability of the processor core may include, but is not limited to, a total computing power value of the processor core, that is, the greater the total computing power value is, the stronger the processing capability is, where the measure of the total computing power value may include, but is not limited to, a computing speed, a cache size, and the like.
For example, in a case where the scheduling priority of the first task is higher than the preset priority, determining a processor core selection range of the first task from the N processor cores according to the computing power demand information of the first task, and selecting a target processor core from the processor core selection range; alternatively, the target load of each processor core may be calculated according to the scheduling priority of the first task, where the target load may be a sum of loads of all tasks on the processor cores whose scheduling priorities satisfy a preset condition, and the target processor core may be selected from the N processor cores according to the calculation power demand information of the first task and the target load of each processor core, for example, a processor core selection range of the first task may be determined from the N processor cores according to the calculation power demand information of the first task, and a processor core with the smallest target load may be selected from the processor core selection range as the target processor core.
Step 103, executing the first task on the target processor core according to the scheduling priority of the first task.
In this embodiment, the higher the scheduling priority, the more preferentially the task is scheduled by the target processor core. For example, if the target processor core includes a foreground task a and a background task b, and the scheduling priority of the foreground task a is higher than that of the background task b, the target processor core schedules the foreground task a preferentially, and schedules the background task b after processing all the foreground tasks a. It should be noted that, for tasks with the same scheduling priority, the tasks may be scheduled sequentially based on the sequence of each task in the task queue.
According to the task processing method provided by the embodiment of the application, the scheduling priority of the task is determined according to at least one of the task type and the task importance level of the task, and the task is processed based on the scheduling priority, so that the priority scheduling of some tasks (such as foreground tasks and the like) can be realized, and the processing speed of the tasks can be further improved.
Optionally, the selecting the target processor core from the N processor cores according to the second parameter information of the first task includes:
respectively calculating a first residual calculation force value of each processor core in the N processor cores according to the scheduling priority of the first task, wherein the first residual calculation force value of the processor core is a difference value between a total calculation force value of the processor cores and the first calculation force value, and the first calculation force value is a sum of calculation force values required by loads of all tasks with scheduling priorities higher than or equal to the scheduling priority of the first task in the processor cores;
and determining a target processor core according to the computing power demand information of the first task and the first residual computing power value of each processor core in the N processor cores.
The above calculation force demand information, the scheduling priority and the N processor cores may be referred to the related descriptions of the foregoing embodiments, and are not described herein.
In this embodiment, the sum of the calculated force values required by the loads of all the tasks with the scheduling priority higher than or equal to the scheduling priority of the first task in each processor core, that is, the first calculated force value of each processor core, may be calculated, and then the difference between the total calculated force value and the first calculated force value of each processor core is used as the first remaining calculated force value of the processor core. For example, the first task has a scheduling priority of 3, and for the processor core CPU-7, the load required calculation force value load-7 for all tasks in the CPU-7 having scheduling priorities higher than or equal to 3 may be calculated, and the first remaining calculation force value free-7, that is, free-7=cap-7-load-7, may be calculated from the total calculation force value cap-7 of the CPU-7.
After the first remaining power value of each of the N processor cores is obtained, a target processor core may be determined according to the power demand information of the first task and the first remaining power value of each of the N processor cores, for example, a processor core may be selected as the target processor core from the processor cores whose first remaining power values are capable of satisfying the power demand information of the first task.
In this embodiment, in the case where the N processor cores include at least two types of processor cores with different processing capacities, the processor core selection is performed based on the first remaining power value of each processor core, so that it is beneficial to preferentially select to a processor with a higher processing capacity to check and process a task with a higher scheduling priority, so that the processing speed and smoothness of the task with a higher scheduling priority can be improved; under the condition that the processing capacities of the N processor cores can be the same, the processor core selection is performed based on the first residual calculation force value of each processor core, so that the influence of the task with lower scheduling priority on the task with higher scheduling priority is reduced, and the processing speed of the task with higher scheduling priority is improved.
Optionally, the determining the target processor core according to the computing power requirement information of the first task and the first remaining computing power value of each of the N processor cores includes:
determining a first processor core selection range according to the computational power demand information of the first task, wherein the N processor cores comprise at least two types of processor cores, the processing capacities of different types of processor cores in the at least two types of processor cores are different, and the first processor core selection range comprises at least two processor cores in the N processor cores;
and determining a target processor core according to the first residual calculation force value of each processor core in the first processor core selection range.
In this embodiment, each of the above-described processor cores may include one or more processor cores. For example, the N processor cores may include a first type processor core and a second type processor core, where the first type processor core includes L processor cores, the second type processor core includes K processor cores, and l+k=n, and a processing capability of the first type processor core is greater than a processing capability of the second type processor core, and the processor core with the smallest first load may be selected from the L processor cores as the first processor core.
It should be noted that the processing capacities of the plurality of processor cores included in each of the processor cores may be identical, or the difference between the processing capacities of the plurality of processor cores included in each of the processor cores may be within a predetermined range. It should be noted that the structures, models, and the like of the plurality of processor cores included in each type of processor core may be the same or different.
In practical application, the calculation power demand information of each task can be counted in advance in a mode of experimental simulation and the like, and then the corresponding relation between the calculation power demand information and the selection range of the processor cores can be established based on the calculation power demand information of each task, wherein the calculation power of the processor cores in the selection range of the processor cores can meet the calculation power demand information of the corresponding task.
In some alternative embodiments, in the case that the above-mentioned calculation force demand information is a calculation force level, a correspondence relationship between the calculation force level and the selection range of the processor core may be established, where different calculation force levels correspond to different selection ranges of the processor core, and the higher the calculation force level (i.e. the more calculation force is required), the stronger the processing capability of the processor core in the corresponding selection range of the processor core is, so that it is advantageous to prefer to select a task with a higher processing capability and a higher calculation force required for the processor core.
For example, the N processor cores include 8 processor cores, that is, CPU-0 to CPU-7, where CPU-7 is a large processor core, CPU-4 to CPU-6 are all middle processor cores, and CPU-0 to CPU-3 are all small processor cores, where the processing capacity of the large processor core is stronger than that of the middle processor core, the processing capacity of the middle processor core is stronger than that of the small processor core, the task a is a task of a small window application (for example, a small window task of a video application or a small window task of an instant messaging type, etc.), the required computation power is less, the corresponding processor core selection range is CPU-0 to CPU-6, that is, the task a may select a processor core from CPU-0 to CPU-6; the B task is a game task, the required calculation force is more, and the corresponding processor core selection range is from CPU-0 to CPU-7, namely the B task can select the processor core from CPU-0 to CPU-7.
In this embodiment, when there are a plurality of tasks (for example, a plurality of foreground tasks) with the same scheduling priority, the selection range of the processor core corresponding to each task may be determined based on the calculation power requirement information of each task, and the processor core corresponding to each task may be selected from the selection ranges of the processor cores corresponding to each task, so that the occurrence of the situation that a plurality of tasks with the same scheduling priority but different calculation power requirements are selected to the same processor core may be reduced, the interaction between the plurality of tasks may be reduced, and the migration overhead of the tasks on different processor cores may be reduced.
In some alternative embodiments, the first processor core selection range may be determined according to the computing power requirement information of the first task, then the first remaining computing power value of each processor core in the first processor core selection range is calculated based on the scheduling priority of the first task, and the target processor core is determined according to the first remaining computing power value of each processor core in the first processor core selection range, so that the calculation of the remaining computing power of the processor cores may be reduced, and the system resources may be saved.
Optionally, the determining the target processor core according to the first remaining power value of each processor core in the first processor core selection range includes:
determining the processor core with the maximum first residual calculation force value in the first processor core selection range as a target processor core;
or,
and determining the processor core with the largest first residual calculation force value in the target class processor core in the first processor core selection range as a target processor core, wherein the target class processor core is the processor core with the strongest processing capacity in the first processor core selection range.
In an embodiment, the processor core with the largest first residual power value in the selection range of the first processor core is determined as the target processor core, so that the first task can be ensured to be processed as soon as possible, and the timeliness of the first task processing is improved.
In another embodiment, the processor core with the largest first residual calculation force value is selected from the processor cores with the strongest processing capacity, so that the first task is checked to be processed through the processor core with the strongest processing capacity, and the processing speed of the first task and the fluency of the first task can be improved.
The processor core with the strongest processing capability in the first processor core selection range may be, for example, the processor core with the largest total computing power value in the first processor core selection range.
Optionally, the selecting the target processor core from the N processor cores according to the second parameter information of the first task includes:
selecting a target processor core from N processor cores according to second parameter information of the first task under the condition that the first task meets a first condition;
wherein the first condition includes any one of: the task type is a foreground task, the importance level of the task is larger than the preset level, and the scheduling priority is larger than the preset priority.
The preset level and the preset priority level can be set reasonably according to actual requirements, which is not limited in this embodiment.
Specifically, the processor core selection manner provided by the embodiment of the present application may be adopted to select a processor core for a first task only when the first task meets a first condition, for example, a first calculation force value of each of the N processor cores is calculated according to a scheduling priority of the first task, where the first calculation force value is a sum of calculation force values required by loads of all tasks with a scheduling priority higher than or equal to the scheduling priority of the first task in the processor cores, and a first remaining calculation force value of each of the N processor cores is determined according to the first calculation force value and a total calculation force value of each of the N processor cores, and the processor core for executing the first task is determined according to calculation force requirement information of the first task and the first remaining calculation force value of each of the N processor cores.
In the case that the first task does not satisfy the first condition, an existing processor core selection manner may be adopted, for example, load calculation force values corresponding to each of the N processor cores are calculated respectively, the load calculation force values are a sum of calculation force values required by all loads in the processor cores, and a processor core with a minimum load calculation force value may be selected as the processor core for executing the first task.
In this embodiment, when the first condition is met, the target processor core is selected from the N processor cores according to the second parameter information of the first task, so that not only can the processing effect, such as the processing efficiency and smoothness, of the foreground task or some important tasks be ensured, but also the complexity of the selection of the processor cores of the tasks (such as the background task or some tasks with lower importance) which do not meet the first condition can be reduced, and further the system resource overhead can be reduced.
Optionally, the first parameter information includes the task type, and the task type includes a foreground task or a background task;
the determining the scheduling priority of the first task according to the first parameter information of the first task comprises:
under the condition that the task type of the first task is a foreground task, determining that the scheduling priority of the first task is a first scheduling priority;
determining that the scheduling priority of the first task is a second scheduling priority under the condition that the task type of the first task is a background task;
wherein the first scheduling priority is higher than the second scheduling priority.
For example, it may be determined that a task is a background task based on whether a certain task has a visible interface, whether a foreground service and a foreground dependent service are executing, whether a broadcast is executing, whether a foreground dependent database is executing, etc., whether the task is a foreground task or a background task, e.g., if a certain task does not have a visible interface, no foreground service and a foreground dependent service are executing, no broadcast is executing, and no foreground dependent database is executing, then the task is determined to be a background task, otherwise the task is determined to be a foreground task.
In the embodiment, the scheduling priority of the foreground task is higher than that of the background task, so that the foreground task can be guaranteed to be scheduled in preference to the background task, the blocking of the foreground task can be reduced, and the fluency of the foreground task is improved.
An embodiment of the present application is illustrated in the following with reference to fig. 3.
Step 201, scene recognition.
In this embodiment, the scene recognition module may recognize the scenes of multiple foreground applications, and set the highest scheduling priority for all foreground processes (i.e. tasks), otherwise, under unfair scheduling, the foreground application with low priority is easily affected by the foreground with high priority, which easily causes a jam.
For example, application a switches to the foreground, triggering a scene change notification to the scene recognition module, application B switches to the foreground, triggering a scene change notification to the scene recognition module.
Step 202, it is determined whether there are multiple foreground applications.
For example, the scene recognition module determines foreground processes of the application a and the application B, and if the application a and the application B are foreground applications, the scene recognition module belongs to a multi-foreground application scene. In this step, if there are multiple foreground applications, step 203 may be performed.
In step 203, the calculation force values (i.e., the calculation force demand information described above) required for the respective foreground applications are calculated.
For example, the demand of each foreground process for CPU computing power can be evaluated according to the type of the foreground process (i.e. task) so as to allocate CPU resources. For example, a usage scenario (e.g., play a game, listen to music, slide a widget, etc.) may be identified based on information such as application package name, whether visible, whether focus is present, status of audio, whether input operations are frequent, etc., and the need for computing power by the application process is determined.
For example, a game process requires high computational effort, and may run preferentially on a large processor core and a medium processor core, and a foreground process (e.g., a small window application process) with low computational effort may run on other medium processor cores or small processor cores, so that additional overhead caused by frequent migration due to running of different foreground processes on the same processor core may be reduced.
It should be noted that, the scheduling system may only perform scheduling management on the process, and does not care about information such as application types, calculation force requirements, and the like, so the above process may be completed through the above scene recognition module.
In step 204, if the scene recognition module determines that the demand of the application a for CPU computing power is high, it may be determined that the processor core selection range of the application a (e.g., the game application) is from CPU-0 to CPU-7.
Illustratively, CPU-7 is a large processor core, CPU-4 through CPU-6 are all medium processor cores, and CPU-0 through CPU-3 are all small processor cores, wherein the large processor core has a processing power greater than that of the medium processor core, and the medium processor core has a processing power greater than that of the small processor core
It should be noted that, the calculation force required by each application process may be determined in advance through an experimental simulation manner, for example, each application process may be tested through an experimental simulation manner, how much calculation force can meet the requirements of not dropping frames, not blocking sounds, and the like, and then the selection range of the processor core corresponding to each application process may be determined.
Step 205, selecting processor cores by unfair scheduling, preferentially selecting processor cores CPU-7 and CPU-6 for the A application.
Because the application A belongs to the process with high scheduling priority, the running cores of the CPU are not limited, and the application A can run on the CPU-7 and the CPU-6, so that the application A can be preferentially scheduled on the CPU-7 and the CPU-6 according to the load core selection logic of unfair scheduling, and the application A has strong calculation power on the CPU-7 and the CPU-6, does not run on other processes with high scheduling priority, and has more residual capacity.
Illustratively, in the case where the a application is a foreground process and the demand for CPU computing power is high, the a application may be preferentially scheduled to the large processor core and the medium processor core by unfair scheduling. For example, recognizing that the A application is a game application (e.g., determined to be a game application based on the application package name) and is in the foreground (e.g., known to be in a combat scenario based on the software development tool (sdk) of the game), the scheduling priority of the A application process may be set to the highest scheduling priority, e.g., 3 to the highest scheduling priority, and the A application process may be scheduled onto CPU-7 and CPU-6 preferentially.
In step 206, if the scene recognition module determines that the computing power requirement of the B application on the CPU is low, it may be determined that the processor core selection range of the B application (e.g., the widget application) is from CPU-0 to CPU-5.
Step 207, selecting processor cores by unfair scheduling, preferentially selecting processor cores CPU-5 and CPU-4 for the B application.
Because the B application can only run from CPU-0 to CPU-5, the B application can be preferentially scheduled to the CPU-5 and the CPU-4 according to the load kernel selection logic of unfair scheduling, because the B application is selected from the CPU-0 to CPU-5, the processing capacity of the CPU-5 and the CPU-4 is strong, the calculated residual capacity is more, the B application can easily run to the CPU-5 and the CPU-4, and the high scheduling priority application processes running on the CPU-5 and the CPU-4 are not more.
From the above, in the example, the application B (such as the video widget application) occupies at most CPU-4 to CPU-5, so that preemption of CPU-6 and CPU-7 with the application a (such as the game application) can be avoided, and thus, in the case that the application a and the application B are both the highest scheduling priorities, the highest priority is guaranteed on each processor core for scheduling, and thus, the smoothness of each application can be guaranteed.
It should be noted that, in the unfair scheduling processor core selecting manner of this example, the process with high scheduling priority selects the processor core to ignore the load of the process with low scheduling priority on each processor core, calculates the remaining power value (i.e., the first remaining power value described above) on each processor core, and then selects the processor core with the largest remaining power value, for example, in the case of selecting the processor core for the application process with scheduling priority 3 a, since CPU-7 to CPU-0 may be allowed to be selected, in the case of calculating the remaining power value of CPU-7, the load of the process with 3 or more in the task queue on this CPU-7 is calculated, but the load of the process with 3 or less is not calculated (because the process loads of priority 2 and priority 1 do not affect the process with priority 3, where the scheduling priority order is 3 is higher than 2 and 2 is higher than 1).
It should be noted that, for the background task, the scheduling priority thereof may be set to a low scheduling priority of unfair scheduling, for example, the scheduling priority thereof may be set to 0.
According to the task processing method provided by the embodiment of the application, the execution main body can be a task processing device. In the embodiment of the application, a task processing device is described by taking a task processing method executed by the task processing device as an example.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a task processing device according to an embodiment of the present application, as shown in fig. 4, the task processing device 400 includes:
a first determining module 401, configured to determine a scheduling priority of a first task according to first parameter information of the first task, where the first parameter information includes at least one of a task type and a task importance level;
a first selection module 402, configured to select a target processor core from N processor cores according to second parameter information of the first task, where the second parameter information includes power demand information and scheduling priority, and N is an integer greater than 1;
an execution module 403, configured to execute the first task on the target processor core according to a scheduling priority of the first task.
Optionally, the second parameter information includes calculation power demand information and scheduling priority;
the first selection module includes:
a computing unit, configured to respectively compute a first remaining power value of each of the N processor cores according to a scheduling priority of the first task, where the first remaining power value of the processor core is a difference value between a total power value of the processor cores and a first power value, and the first power value is a sum of power values required by loads of all tasks in the processor cores with scheduling priorities higher than or equal to the scheduling priority of the first task;
and the determining unit is used for determining a target processor core according to the computing power demand information of the first task and the first residual computing power value of each of the N processor cores.
Optionally, the determining unit is specifically configured to:
determining a first processor core selection range according to the computational power demand information of the first task, wherein the N processor cores comprise at least two types of processor cores, the processing capacities of different types of processor cores in the at least two types of processor cores are different, and the first processor core selection range comprises at least two processor cores in the N processor cores;
And determining a target processor core according to the first residual calculation force value of each processor core in the first processor core selection range.
Optionally, the determining unit is specifically configured to:
determining the processor core with the maximum first residual calculation force value in the first processor core selection range as a target processor core;
or,
and determining the processor core with the largest first residual calculation force value in the target class processor core in the first processor core selection range as a target processor core, wherein the target class processor core is the processor core with the strongest processing capacity in the first processor core selection range.
Optionally, the first selecting module is specifically configured to:
selecting a target processor core from N processor cores according to second parameter information of the first task under the condition that the first task meets a first condition;
wherein the first condition includes any one of: the task type is a foreground task, the importance level of the task is larger than the preset level, and the scheduling priority is larger than the preset priority.
Optionally, the first parameter information includes the task type, and the task type includes a foreground task or a background task;
The first determining module is specifically configured to:
under the condition that the task type of the first task is a foreground task, determining that the scheduling priority of the first task is a first scheduling priority;
determining that the scheduling priority of the first task is a second scheduling priority under the condition that the task type of the first task is a background task;
wherein the first scheduling priority is higher than the second scheduling priority.
The task processing device in the embodiment of the application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device may be a terminal, or may be other devices than a terminal. By way of example, the electronic device may be a mobile phone, tablet computer, notebook computer, palm computer, vehicle-mounted electronic device, mobile internet appliance (Mobile Internet Device, MID), augmented reality (augmented reality, AR)/Virtual Reality (VR) device, robot, wearable device, ultra-mobile personal computer, UMPC, netbook or personal digital assistant (personal digital assistant, PDA), etc., but may also be a server, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (TV), teller machine or self-service machine, etc., and the embodiments of the present application are not limited in particular.
The task processing device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an ios operating system, or other possible operating systems, and the embodiment of the present application is not limited specifically.
The task processing device provided by the embodiment of the application can realize each process realized by the embodiment of the method and can achieve the same technical effect, and in order to avoid repetition, the description is omitted here.
Optionally, as shown in fig. 5, the embodiment of the present application further provides an electronic device 500, including a processor 501 and a memory 502, where the memory 502 stores a program or an instruction that can be executed on the processor 501, and the program or the instruction implements each step of the above task processing method embodiment when executed by the processor 501, and the steps achieve the same technical effect, so that repetition is avoided, and no further description is given here.
It should be noted that, the electronic device in the embodiment of the present application includes a mobile electronic device and a non-mobile electronic device.
Fig. 6 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.
The electronic device 600 includes, but is not limited to: radio frequency unit 601, network module 602, audio output unit 603, input unit 604, sensor 605, display unit 606, user input unit 607, interface unit 608, memory 609, and processor 610.
Those skilled in the art will appreciate that the electronic device 600 may further include a power source (e.g., a battery) for powering the various components, which may be logically connected to the processor 610 by a power management system to perform functions such as managing charge, discharge, and power consumption by the power management system. The electronic device structure shown in fig. 6 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than shown, or may combine certain components, or may be arranged in different components, which are not described in detail herein.
Wherein the processor 610 is configured to determine a scheduling priority of a first task according to first parameter information of the first task, where the first parameter information includes at least one of a task type and a task importance level;
the processor 610 is further configured to select a target processor core from N processor cores according to second parameter information of the first task, where the second parameter information includes calculation power requirement information and scheduling priority, and N is an integer greater than 1;
the processor 610 is further configured to execute the first task on the target processor core according to a scheduling priority of the first task.
Optionally, the second parameter information includes calculation power demand information and scheduling priority;
the processor 610 is specifically configured to:
respectively calculating a first residual calculation force value of each processor core in the N processor cores according to the scheduling priority of the first task, wherein the first calculation force value is the sum of calculation force values required by loads of all tasks with the scheduling priority higher than or equal to the scheduling priority of the first task in the processor cores;
and determining a target processor core according to the computing power demand information of the first task and the first residual computing power value of each processor core in the N processor cores.
Optionally, the processor 610 is specifically configured to:
determining a first processor core selection range according to the computational power demand information of the first task, wherein the N processor cores comprise at least two types of processor cores, the processing capacities of different types of processor cores in the at least two types of processor cores are different, and the first processor core selection range comprises at least two processor cores in the N processor cores;
and determining a target processor core according to the first residual calculation force value of each processor core in the first processor core selection range.
Optionally, the processor 610 is specifically configured to:
determining the processor core with the maximum first residual calculation force value in the first processor core selection range as a target processor core;
or,
and determining the processor core with the largest first residual calculation force value in the target class processor core in the first processor core selection range as a target processor core, wherein the target class processor core is the processor core with the strongest processing capacity in the first processor core selection range.
Optionally, the processor 610 is specifically configured to:
selecting a target processor core from N processor cores according to second parameter information of the first task under the condition that the first task meets a first condition;
wherein the first condition includes any one of: the task type is a foreground task, the importance level of the task is larger than the preset level, and the scheduling priority is larger than the preset priority.
Optionally, the first parameter information includes the task type, and the task type includes a foreground task or a background task;
the processor 610 is specifically configured to:
under the condition that the task type of the first task is a foreground task, determining that the scheduling priority of the first task is a first scheduling priority;
Determining that the scheduling priority of the first task is a second scheduling priority under the condition that the task type of the first task is a background task;
wherein the first scheduling priority is higher than the second scheduling priority.
It should be understood that in an embodiment of the present application, the input unit 604 may include a graphics processor (Graphics Processing Unit, GPU) 6041 and a microphone 6042, and the graphics processor 6041 processes image data of still pictures or video obtained by an image capturing apparatus (e.g., a camera) in a video capturing mode or an image capturing mode. The display unit 606 may include a display panel 6061, and the display panel 6061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 607 includes at least one of a touch panel 6071 and other input devices 6072. The touch panel 6071 is also called a touch screen. The touch panel 6071 may include two parts of a touch detection device and a touch controller. Other input devices 6072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein.
The memory 609 may be used to store software programs as well as various data. The memory 609 may mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 609 may include volatile memory or nonvolatile memory, or the memory 609 may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (ddr SDRAM), enhanced SDRAM (Enhanced SDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DRRAM). Memory 609 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.
The processor 610 may include one or more processing units; optionally, the processor 610 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, etc., and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 610.
The embodiment of the application also provides a readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements each process of the task processing method embodiment described above, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here.
Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes computer readable storage medium such as computer readable memory ROM, random access memory RAM, magnetic or optical disk, etc.
The embodiment of the application further provides a chip, which comprises a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used for running programs or instructions to realize the processes of the task processing method embodiment, and the same technical effects can be achieved, so that repetition is avoided, and the description is omitted here.
It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.
Embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the respective processes of the task processing method embodiments described above, and achieve the same technical effects, and for avoiding repetition, a detailed description is omitted herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.
Claims (14)
1. A method of task processing, the method comprising:
determining a scheduling priority of a first task according to first parameter information of the first task, wherein the first parameter information comprises at least one of a task type and a task importance level;
selecting a target processor core from N processor cores according to second parameter information of the first task, wherein the second parameter information comprises calculation force demand information and scheduling priority, and N is an integer greater than 1;
and executing the first task on the target processor core according to the scheduling priority of the first task.
2. The method of claim 1, wherein selecting the target processor core from the N processor cores according to the second parameter information of the first task comprises:
respectively calculating a first residual calculation force value of each processor core in the N processor cores according to the scheduling priority of the first task, wherein the first residual calculation force value of the processor core is a difference value between a total calculation force value of the processor cores and the first calculation force value, and the first calculation force value is a sum of calculation force values required by loads of all tasks with scheduling priorities higher than or equal to the scheduling priority of the first task in the processor cores;
And determining a target processor core according to the computing power demand information of the first task and the first residual computing power value of each processor core in the N processor cores.
3. The method of claim 2, wherein the determining a target processor core from the computing power demand information for the first task and the first remaining computing power value for each of the N processor cores comprises:
determining a first processor core selection range according to the computational power demand information of the first task, wherein the N processor cores comprise at least two types of processor cores, the processing capacities of different types of processor cores in the at least two types of processor cores are different, and the first processor core selection range comprises at least two processor cores in the N processor cores;
and determining a target processor core according to the first residual calculation force value of each processor core in the first processor core selection range.
4. The method of claim 3, wherein the determining a target processor core from the first remaining power values of the respective processor cores within the first processor core selection range comprises:
determining the processor core with the maximum first residual calculation force value in the first processor core selection range as a target processor core;
Or,
and determining the processor core with the largest first residual calculation force value in the target class processor core in the first processor core selection range as a target processor core, wherein the target class processor core is the processor core with the strongest processing capacity in the first processor core selection range.
5. The method according to any one of claims 1 to 4, wherein selecting a target processor core from N processor cores according to second parameter information of the first task comprises:
selecting a target processor core from N processor cores according to second parameter information of the first task under the condition that the first task meets a first condition;
wherein the first condition includes any one of: the task type is a foreground task, the importance level of the task is larger than the preset level, and the scheduling priority is larger than the preset priority.
6. The method according to any one of claims 1 to 4, wherein the first parameter information includes the task type, the task type including a foreground task or a background task;
the determining the scheduling priority of the first task according to the first parameter information of the first task comprises:
Under the condition that the task type of the first task is a foreground task, determining that the scheduling priority of the first task is a first scheduling priority;
determining that the scheduling priority of the first task is a second scheduling priority under the condition that the task type of the first task is a background task;
wherein the first scheduling priority is higher than the second scheduling priority.
7. A task processing device, the device comprising:
the first determining module is used for determining the scheduling priority of a first task according to first parameter information of the first task, wherein the first parameter information comprises at least one of a task type and a task importance level;
a first selection module, configured to select a target processor core from N processor cores according to second parameter information of the first task, where the second parameter information includes calculation power demand information and scheduling priority, and N is an integer greater than 1;
and the execution module is used for executing the first task on the target processor core according to the scheduling priority of the first task.
8. The apparatus of claim 7, wherein the first selection module comprises:
A computing unit, configured to respectively compute a first remaining power value of each of the N processor cores according to a scheduling priority of the first task, where the first remaining power value of the processor core is a difference value between a total power value of the processor cores and a first power value, and the first power value is a sum of power values required by loads of all tasks in the processor cores with scheduling priorities higher than or equal to the scheduling priority of the first task;
and the determining unit is used for determining a target processor core according to the computing power demand information of the first task and the first residual computing power value of each of the N processor cores.
9. The apparatus according to claim 8, wherein the determining unit is specifically configured to:
determining a first processor core selection range according to the computational power demand information of the first task, wherein the N processor cores comprise at least two types of processor cores, the processing capacities of different types of processor cores in the at least two types of processor cores are different, and the first processor core selection range comprises at least two processor cores in the N processor cores;
and determining a target processor core according to the first residual calculation force value of each processor core in the first processor core selection range.
10. The apparatus according to claim 9, wherein the determining unit is specifically configured to:
determining the processor core with the maximum first residual calculation force value in the first processor core selection range as a target processor core;
or,
and determining the processor core with the largest first residual calculation force value in the target class processor core in the first processor core selection range as a target processor core, wherein the target class processor core is the processor core with the strongest processing capacity in the first processor core selection range.
11. The apparatus according to any one of claims 7 to 10, wherein the first selection module is specifically configured to:
selecting a target processor core from N processor cores according to second parameter information of the first task under the condition that the first task meets a first condition;
wherein the first condition includes any one of: the task type is a foreground task, the importance level of the task is larger than the preset level, and the scheduling priority is larger than the preset priority.
12. The apparatus according to any one of claims 7 to 10, wherein the first parameter information comprises the task type, the task type comprising a foreground task or a background task;
The first determining module is specifically configured to:
under the condition that the task type of the first task is a foreground task, determining that the scheduling priority of the first task is a first scheduling priority;
determining that the scheduling priority of the first task is a second scheduling priority under the condition that the task type of the first task is a background task;
wherein the first scheduling priority is higher than the second scheduling priority.
13. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the task processing method as claimed in any one of claims 1 to 6.
14. A readable storage medium, wherein a program or instructions is stored on the readable storage medium, which when executed by a processor, implements the steps of the task processing method according to any one of claims 1-6.
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| CN117389711A (en) * | 2023-12-11 | 2024-01-12 | 腾讯科技（深圳）有限公司 | Scheduling method and device for terminal resources, terminal and computer readable storage medium |
| CN117389711B (en) * | 2023-12-11 | 2024-04-09 | 腾讯科技（深圳）有限公司 | Scheduling method and device for terminal resources, terminal and computer readable storage medium |
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