CN116648058B

CN116648058B - Semiconductor device, manufacturing method thereof and electronic equipment

Info

Publication number: CN116648058B
Application number: CN202310450191.0A
Authority: CN
Inventors: 李玉科; 毛淑娟; 梁鸿刚
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2023-04-24
Filing date: 2023-04-24
Publication date: 2024-04-09
Anticipated expiration: 2043-04-24
Also published as: CN116648058A

Abstract

A semiconductor device, a method of manufacturing the same, and an electronic apparatus, the semiconductor device including: a first wafer and a second wafer disposed on the first wafer, the first wafer comprising a substrate and a bit line disposed on the substrate; the second wafer comprises at least one transistor, the transistor comprises a semiconductor column extending along the direction perpendicular to the substrate, the semiconductor column comprises a channel region, a first region and a second region, the first region and the second region are respectively arranged on two sides of the channel region, the second region is arranged on one side, facing the substrate, of the channel region, and the bit line is in contact with the second region. According to the scheme provided by the embodiment of the disclosure, the transistors are prepared on one wafer and the bit lines are prepared on the other wafer by using the two wafers, so that the process is simple, the formation of the holes in the bit lines can be avoided, the bit lines are more stable, and the contact resistance between the bit lines and the semiconductor columns is more stable.

Description

Semiconductor device, manufacturing method thereof and electronic equipment

Technical Field

Embodiments of the present disclosure relate to, but not limited to, semiconductor technology, and more particularly, to a semiconductor device, a method of manufacturing the same, and an electronic apparatus.

Background

The conventional vertical gate-all-around dynamic random access memory (Dynamic Random Acess Memory, DRAM) array is fabricated by forming buried bit lines and then word lines, and then forming storage capacitors (storage nodes) on top.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a semiconductor device, a manufacturing method thereof and electronic equipment, which reduce the process difficulty and improve the device performance.

The disclosed embodiment provides a semiconductor device, comprising: a first wafer and a second wafer disposed on the first wafer, the first wafer comprising a substrate and a bit line disposed on the substrate; the second wafer comprises at least one transistor, the transistor comprises a semiconductor column extending along the direction perpendicular to the substrate, the semiconductor column comprises a channel region, a first region and a second region, the first region and the second region are respectively arranged on two sides of the channel region, the second region is arranged on one side, facing the substrate, of the channel region, and the bit line is in contact with the second region.

In some embodiments, a contact surface of the bit line and the second region is parallel to the substrate.

In some embodiments, a surface of the bit line adjacent to a side of the substrate is parallel to the substrate.

In some embodiments, the orthographic projection of the bit line comprises a rectangle on a plane parallel to the substrate.

In some embodiments, the second wafer includes a plurality of the transistors distributed in an array along a first direction and a second direction, respectively, the first wafer includes a plurality of the bit lines extending along the second direction, wherein second regions of the transistors of a same column distributed along the second direction connect a same bit line, the first direction and the second direction intersecting.

In some embodiments, the transistor further comprises: and the gate electrode surrounds the side wall of the channel region, and the gate electrodes of the transistors in the same row distributed along the first direction are connected to form a word line.

In some embodiments, the semiconductor device further comprises: logic circuitry disposed on a side of the bit line remote from the second wafer.

In some embodiments, there is overlap between the orthographic projection of the logic circuit on the substrate and the orthographic projection of the transistor on the substrate.

An embodiment of the present disclosure provides an electronic device including the semiconductor device described in any one of the embodiments above.

In some embodiments, the semiconductor device further comprises: the capacitor is arranged on one side, far away from the first wafer, of the transistor and comprises a first polar plate, a second polar plate and a dielectric layer arranged between the first polar plate and the second polar plate, and the first polar plate is connected with the first area through a node contact layer.

Embodiments of the present disclosure provide a method of manufacturing a semiconductor device including at least one transistor including a semiconductor pillar, the method comprising:

providing a first wafer comprising a substrate, and forming a bit line layer on the substrate;

providing a second wafer, wherein the second wafer comprises a substrate and a semiconductor layer arranged on the substrate, overturning the second wafer, bonding the second wafer with the first wafer at one side far away from the substrate, and etching to remove the substrate so as to expose the semiconductor layer, wherein the bit line layer is in contact with the semiconductor layer;

and etching the semiconductor layer and the bit line layer to form at least one semiconductor column extending along the direction perpendicular to the substrate, wherein the semiconductor column comprises a channel region, a first region and a second region which are respectively arranged at two sides of the channel region, the second region is arranged at one side of the channel region facing the substrate, and at least one bit line is formed, and the second region is contacted with the bit line.

In some embodiments, the etching the semiconductor layer and the bit line layer includes:

forming a plurality of word line isolation trenches extending in a first direction, the word line isolation trenches penetrating the semiconductor layer and exposing the bit line layer, the word line isolation trenches dividing the semiconductor layer into a plurality of semiconductor portions;

a plurality of bit line isolation trenches extending along a second direction and penetrating the bit line layer are formed, the bit line isolation trenches divide the bit line layer into a plurality of bit lines, and the second direction crosses the first direction.

In some embodiments, the providing the second wafer comprises: and epitaxially growing and doping on the substrate to form a semiconductor layer.

In some embodiments, the forming a bit line layer on the substrate includes:

depositing a first insulating film on the substrate to form a first insulating layer;

sequentially depositing a first conductive film and a connecting layer film on the first insulating layer, and patterning to form a bit line layer;

or, depositing a first insulating film on the substrate to form a first insulating layer;

a first conductive film is deposited after the first insulating layer is grooved, and the first conductive layer arranged in the groove is formed by grinding;

And depositing a connecting layer film, patterning to form a connecting layer, wherein the first conductive layer and the connecting layer form the bit line layer, and the orthographic projection of the connecting layer on the substrate overlaps with the orthographic projection of the first conductive layer on the substrate.

In some embodiments, forming a logic circuit on the substrate is further included before forming a bit line layer on the substrate.

Embodiments of the present disclosure include a semiconductor device, a method of manufacturing the same, and an electronic apparatus, the semiconductor device including: a first wafer and a second wafer disposed on the first wafer, the first wafer comprising a substrate and a bit line disposed on the substrate; the second wafer comprises at least one transistor, the transistor comprises a semiconductor column extending along the direction perpendicular to the substrate, the semiconductor column comprises a channel region, a first region and a second region, the first region and the second region are respectively arranged on two sides of the channel region, the second region is arranged on one side, facing the substrate, of the channel region, and the bit line is in contact with the second region. According to the scheme provided by the embodiment of the disclosure, the transistors are prepared on one wafer and the bit lines are prepared on the other wafer by using the two wafers, compared with the scheme that the bottom of the semiconductor column is grooved and filled with the conductive material to form the bit lines in the related art, the scheme provided by the embodiment of the disclosure is simple in process, the formation of the holes in the bit lines can be avoided, the shape of the bit lines is more stable, and the contact resistance between the bit lines and the semiconductor column is more stable. In addition, the size and shape of different bit lines of the same memory array are easier to control, so that the size and shape of different bit lines are consistent, and the resistance of the bit lines is stable.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities particularly pointed out in the specification and the appended drawings.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, and not constitute a limitation of the technical aspects.

Fig. 1A is a schematic plan view of a semiconductor device according to an exemplary embodiment;

FIG. 1B is a cross-sectional view taken along the direction AA' in FIG. 1A;

FIG. 2A is a top view of an exemplary embodiment after forming a bit line layer;

FIG. 2B is a cross-sectional view along the AA' direction after forming a bit line layer according to one exemplary embodiment;

FIG. 2C is a cross-sectional view along the AA' direction after forming a bit line layer according to another exemplary embodiment;

FIG. 3 is a cross-sectional view of a second wafer along a direction perpendicular to a substrate provided by an exemplary embodiment;

FIG. 4 is a cross-sectional view taken along a direction perpendicular to a substrate after bonding, as provided by an exemplary embodiment;

FIG. 5 is a cross-sectional view along the AA' direction after forming word line isolation trenches, as provided by an exemplary embodiment;

FIG. 6 is a cross-sectional view along the AA' direction after forming a third insulating layer and a fourth insulating layer according to one exemplary embodiment;

FIG. 7A is a cross-sectional view along the AA' direction after forming bit lines according to one exemplary embodiment;

FIG. 7B is a cross-sectional view in the CC' direction after forming bit lines, according to an exemplary embodiment;

FIG. 8 is a cross-sectional view along the AA' direction after exposing the channel region and the first region, as provided by an exemplary embodiment;

fig. 9 is a cross-sectional view along the AA' direction after forming a gate insulating layer and a gate electrode according to an exemplary embodiment;

FIG. 10 is a cross-sectional view along the AA' direction after forming a node contact layer according to an exemplary embodiment;

FIG. 11 is a cross-sectional view along the AA' direction after forming a capacitor according to an exemplary embodiment;

FIG. 12 is a cross-sectional view along the AA' direction after interconnection is achieved in accordance with an exemplary embodiment;

fig. 13 is a flowchart of a method of manufacturing a semiconductor device according to an exemplary embodiment.

Reference numerals illustrate:

1-a substrate; 2-a first insulating layer; 3-a second insulating layer; 4-a third insulating layer; 5-a fourth insulating layer; 6-a fifth insulating layer; 7-a sixth insulating layer; 8-a seventh insulating layer; 9-a semiconductor layer; a 9' -semiconductor portion; 10-semiconductor pillars; 11-a channel region; 12-a first region; 13-a second region; 14-a gate insulation layer; 20-word lines; 21-gate electrode; 30-bit lines; a 30' -bit line layer; 31-a first conductive layer; a 32-connection layer; 40-node contact layer; 41-a first plate; 42-a second plate; 43-dielectric layer; 81-a first connection electrode; 82-a second connection electrode; 100-a first wafer; 110-logic circuitry; 200-a second wafer; 210-substrate.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments of the present disclosure and features in the embodiments may be arbitrarily combined with each other without collision.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.

Embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, the shapes and sizes of the various components in the drawings do not reflect true proportions. Furthermore, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or the numerical values shown in the drawings.

The ordinal numbers of "first", "second", "third", etc. in the present disclosure are provided to avoid intermixing of constituent elements, and do not denote any order, quantity, or importance.

In the present disclosure, for convenience, terms such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe positional relationships of the constituent elements with reference to the drawings, only for convenience in describing the present specification and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the disclosure, and may be replaced as appropriate.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.

In this disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, for example, and thus, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less, for example, and thus includes a state in which an angle is 85 ° or more and 95 ° or less.

The term "the front projection of B is within the range of the front projection of a" in this disclosure means that the boundary of the front projection of B falls within the boundary of the front projection of a, or that the boundary of the front projection of a overlaps with the boundary of the front projection of B.

The "a and B integrated structure" in the embodiments of the present disclosure may refer to a microstructure without obvious boundary interfaces such as obvious faults or gaps. Typically, the connected film layers are patterned on one film layer as one piece. For example, a and B use the same material to form a film and simultaneously form a structure with a connection relationship through the same patterning process.

In one technical scheme, bit lines are formed by grooving the bottoms of semiconductor columns and filling conductive materials, so that the process difficulty is high, the formed bit lines are poor in uniformity, holes are easy to form in the bit lines, and different bit lines are different in resistance and higher in resistance. In addition, it is difficult to form reliable ohmic contact between the bit line and the drain terminal, resulting in high contact resistance.

In the embodiment of the disclosure, by using two wafers, a transistor is prepared on one wafer, a bit line layer is prepared on the other wafer, and then the bit line layer is directly etched to form the bit line, so that the process can be simplified without preparing the bit line by grooving the bottom of the semiconductor column.

Fig. 1A is a schematic plan view of a semiconductor device according to an embodiment of the disclosure, and fig. 1B is a schematic sectional view along AA' in fig. 1A. As shown in fig. 1A and 1B, the embodiment of the present disclosure provides a semiconductor device, which may include: a first wafer 100 and a second wafer 200 disposed on the first wafer 100, the first wafer 100 including a substrate 1 and a bit line 30 disposed on the substrate 1; the second wafer 200 comprises at least one transistor, the transistor comprises a semiconductor pillar 10 extending along a direction perpendicular to the substrate 1, the semiconductor pillar 10 comprises a channel region 11, and a first region 12 and a second region 13 respectively arranged at two sides of the channel region 11, the second region 13 is arranged at one side of the channel region 11 facing the substrate 1, and the bit line 30 is in contact with the second region 13.

The channel region 11 may be substantially differentiated from the first region 12 and the second region 13 by the position of the gate electrode, or may be substantially differentiated from the channel region 11 by the difference in the degree of conduction between the first region 12 and the second region 13. The second region 13, the channel region 11, and the first region 13 are sequentially distributed along the extending direction of the semiconductor pillar 10, that is, the semiconductor pillar 10 is divided into 3 parts along the extending direction of the semiconductor pillar 10, as the second region 13, the channel region 11, and the first region 12, respectively.

The first region 12 and the second region 13 may be regions in which the semiconductor pillar 10 is doped with impurities, and in an embodiment, the conductivity type of the first region 12 and the second region 13 may be n-type or p-type. The first region 12 may be a source region, the second region 13 may be a drain region, or the first region 12 may be a drain region, and the second region 13 may be a source region. The doping of the channel region 11 may be performed, and the doping concentrations of the first region 12 and the second region 13 may be greater than the doping concentration of the channel region 11, and the doping concentrations of the sidewalls of the first region 12 and the second region 13 may be greater than the doping concentration of the channel region 11.

Compared with the scheme that in the related art, the bottom of the semiconductor column is grooved and filled with the conductive material to form the bit line, the scheme provided by the embodiment of the invention has the advantages that the process is simple, the formation of a cavity in the bit line can be avoided, the bit line shape is more stable, and the contact resistance between the bit line and the semiconductor column is more stable. In addition, the size and shape of different bit lines of the same memory array are easier to control, so that the size and shape of different bit lines are consistent, and the resistance of the bit lines is stable.

In an exemplary embodiment, the semiconductor pillars 10 extending in a direction perpendicular to the substrate 1 may be understood as extending only in a direction perpendicular to the substrate 1 as a whole, and the sidewalls of the semiconductor pillars 10 may have a smooth and defect-free morphology.

In an exemplary embodiment, the transistor may further include a gate electrode 21, and the gate electrode 21 may surround a sidewall of the channel region 11. The semiconductor pillar 10 may include a bottom surface (a surface on a side close to the substrate 1), a top surface (a surface on a side away from the substrate 1), and a side surface (i.e., a sidewall of the semiconductor pillar 10) between the top surface and the bottom surface, the sidewall of the channel region 11 being a portion of the sidewall of the semiconductor pillar 10.

In an exemplary embodiment, the transistor may further include a gate insulating layer 14 surrounding sidewalls of the semiconductor pillar 10, the gate insulating layer 14 being located between the gate electrode 21 and the semiconductor pillar 10 to insulate the gate electrode 21 from the semiconductor pillar 10.

In an exemplary embodiment, the contact surface of the bit line 30 and the second region 13 may be parallel to the substrate 1. In this embodiment, since the bit line 30 is formed on the top of the first wafer 100 without being formed by recessing at the bottom of the semiconductor pillar 10, the upper surface (surface on the side away from the substrate 1) of the bit line 30 may be parallel to the substrate 1.

In an exemplary embodiment, the surface of the bit line 30 on the side close to the substrate 1 is parallel to the substrate 1. In this embodiment, the upper and lower surfaces of the bit line 30 are parallel to the substrate 1, and the bit line resistance is stable.

In an exemplary embodiment, the bit line 30 may have substantially the same size and shape at different locations in cross-section in a direction parallel to the substrate. Compared with the scheme of forming the bit line by recessing the bottom of the semiconductor pillar 10 in the related art, the bit line 30 of the present embodiment has a stable cross-sectional shape and a more stable resistance.

In an exemplary embodiment, the channel region 11 may have substantially the same size and shape at different locations in cross-section in a direction parallel to the substrate.

In an exemplary embodiment, the first region 12 may have substantially the same size and shape at different locations in cross-section in a direction parallel to the substrate.

In an exemplary embodiment, the second region 13 may have substantially the same size and shape at different locations in cross-section in a direction parallel to the substrate.

In an exemplary embodiment, the orthographic projections of the channel region 11, the first region 12, and the second region 13 on the substrate 1 may overlap. However, embodiments of the present disclosure are not limited thereto, and the front projection of the channel region 11 on the substrate 1 may be located within the front projection of the first region 12 on the substrate 1, or the front projection of the channel region 11 on the substrate 1 may be located within the front projection of the second region 13 on the substrate 1.

In an exemplary embodiment, the channel region 11, the first region 12, and the second region 13 may be connected to form a unitary structure, i.e., the channel region 11, the first region 12, and the second region 13 are patterned from the same film layer.

In an exemplary embodiment, the orthographic projection of the bit line 30 comprises a rectangle in a plane parallel to the substrate 1. The embodiments of the present disclosure are not limited thereto and the orthographic projection of the bit line 30 may have other shapes.

In an exemplary embodiment, the semiconductor device may include a memory array including a plurality of transistors distributed in an array, that is, the second wafer 200 may include a plurality of transistors distributed in an array along a first direction X and a second direction Y, respectively, and the first wafer 100 may include a plurality of bit lines 30 extending along the second direction Y, wherein the second regions 13 of the transistors of the same column distributed along the second direction Y are connected to the same bit line 30, and the first direction X and the second direction Y may intersect.

In an exemplary embodiment, the first direction X and the second direction Y may be perpendicular.

In an exemplary embodiment, the first direction X may be parallel to the substrate, and the second direction Y may be parallel to the substrate.

In an exemplary embodiment, the gate electrodes 21 of the transistors of the same row distributed along the first direction X are connected to form one word line 20. The semiconductor device may include a plurality of word lines 20 spaced apart along the second direction Y.

In an exemplary embodiment, the semiconductor device may further include: logic 110 is disposed on a side of the bit line 30 remote from the second wafer 200.

In an exemplary embodiment, the logic 110 overlaps the front projection of the substrate 1 with the front projection of the transistor on the substrate 1. Compared with the scheme that the logic circuit and the transistor are tiled on the same wafer, the scheme provided by the embodiment has the advantages that the logic circuit and the transistor are overlapped in orthographic projection of the substrate, namely, the logic circuit and the transistor are stacked, so that the occupied area of a semiconductor device can be reduced, more semiconductor devices can be prepared on the same plane, and the density of the semiconductor device is improved.

In an exemplary embodiment, the semiconductor device may further include an isolation structure filled between the transistors, and a material of the isolation structure may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

In an exemplary embodiment, the semiconductor device may further include: a data storage element.

In an exemplary embodiment, the data storage element is, for example, a capacitor, i.e., a memory structure forming 1T 1C. Embodiments of the present disclosure are not limited thereto and may be combined with other transistor-based memory structures of 2T0C, and so forth.

In an exemplary embodiment, as shown in fig. 1B, the capacitor may include a first plate 41 and a second plate 42, and a dielectric layer 43 disposed between the first plate 41 and the second plate 42. The first plate 41 is connected to the first region 12.

In an exemplary embodiment, the first plate 41 may be connected to the first region 12 through a node contact layer 40.

The semiconductor device structure shown in fig. 1A and 1B is only an example, and the embodiments of the present disclosure are not limited thereto and may be other structures.

The technical scheme of this embodiment will be further described below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, photoresist stripping, etc., and is a well-known preparation process in the related art. The "photolithography process" in this embodiment includes coating a film layer, mask exposure and development, and is a well-known preparation process in the related art. The deposition may be performed by known processes such as sputtering, vapor deposition, chemical vapor deposition, etc., the coating may be performed by known coating processes, and the etching may be performed by known methods, which are not particularly limited herein. In the description of the present embodiment, it is to be understood that "thin film" refers to a thin film made by depositing or coating a certain material on a substrate. The "thin film" may also be referred to as a "layer" if the "thin film" does not require a patterning process or a photolithography process throughout the fabrication process. If the "film" is also subjected to a patterning process or a photolithography process during the entire fabrication process, it is referred to as a "film" before the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

In an exemplary embodiment, the manufacturing process of the semiconductor device may include:

1) Forming a bit line layer 30';

the forming of the bit line layer 30' may include:

providing a first wafer 100, wherein the first wafer 100 comprises a substrate 1, and preparing a logic circuit 110 on the substrate 1;

depositing a first insulating film on the substrate 1 with the structure to form a first insulating layer 2; the first insulating layer 2 covers the logic circuit 110;

sequentially depositing a first conductive film and a connecting layer film on the first insulating layer 2, and patterning to form a first conductive layer 31 and a connecting layer 32; the first conductive layer 31 and the connection layer 32 constitute a bit line layer 30'; the subsequent bit line layer 30' may form a plurality of bit lines 30;

depositing a second insulating film on the substrate 1 having the above structure to form a second insulating layer 3 as shown in fig. 2A and 2B, wherein fig. 2A is a top view after forming a bit line layer 30'; fig. 2B is a cross-sectional view along the AA 'direction after forming the bit line layer 30'. The AA' direction is perpendicular to the substrate 1. The logic circuit 110 shown in fig. 2B is only a part of the logic circuit, the logic circuit 110 may be distributed in other positions, and the orthographic projection of the logic circuit 110 on the substrate 1 may overlap with the orthographic projection of the bit line layer 30', so that the area of the semiconductor device may be reduced, and the density of the semiconductor device may be improved.

In an exemplary embodiment, the orthographic projections of the first conductive layer 31 and the connection layer 32 may overlap on a plane parallel to the substrate 1.

In an exemplary embodiment, the front projection of the first conductive layer 31 and the connection layer 32 on a plane parallel to the substrate 1 may be square, for example, but not limited to, square, and may be other shapes, and the front projection of the first conductive layer 31 and the connection layer 32 on the substrate 1 may be adapted to the shape of the subsequent memory array, and the front projection of the semiconductor pillar 10 on the substrate 1 falls within the front projection of the first conductive layer 31 and the connection layer 32 on the substrate 1.

In an exemplary embodiment, the first conductive film includes, but is not limited to, tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and the like.

In an exemplary embodiment, the connection layer film may be titanium (Ti), cobalt (Co), nickel platinum (NiPt), or the like.

In an exemplary embodiment, the first and second insulating films may be one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON), silicon carbide (SiC).

In another exemplary embodiment, the first conductive film may be copper (Cu), for example, a copper film may be deposited after the first insulating layer 2 is grooved, and after the first conductive layer 31 disposed in the groove is ground, a connection layer film is deposited, and patterned to form the connection layer 32, and then the third insulating layer 3 is formed, where the first conductive layer 31 and the connection layer 32 form the bit line layer, as shown in fig. 2C. The front projection of the connection layer 32 on the substrate 1 and the front projection of the first conductive layer 31 on the substrate 1 may overlap.

2) A second wafer 200 is provided, which second wafer 200 may comprise a substrate 210 and a semiconductor layer 9 provided on the substrate 210, as shown in fig. 3, fig. 3 being a cross-sectional view of the second wafer 200 along a direction perpendicular to the substrate 210.

In an exemplary embodiment, the semiconductor layer 9 may include, for example, at least one elemental semiconductor material (e.g., silicon (Si), germanium (Ge), etc.), at least one III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

In an exemplary embodiment, the semiconductor layer 9 may be epitaxially grown on the substrate 210. And the semiconductor layer is doped according to the doping requirements of the source region, the channel region and the drain region, and the doping concentration of the channel region can be different from the doping concentration of the source region and the drain region. In an exemplary embodiment, doping may be achieved during epitaxial growth.

3) After the second wafer 200 is inverted, it is bonded to the first wafer 100, the substrate 210 is removed, and the semiconductor layer 9 is exposed, as shown in fig. 4, and fig. 4 is a cross-sectional view along a direction perpendicular to the substrate 1 after bonding. The semiconductor layer 9 is in contact with the connection layer 32. The connection layer 32 may form a metal silicide to reduce contact resistance of the bit line layer 30' and the semiconductor layer 9.

In an exemplary embodiment, the second wafer 200 and the first wafer 100 bonding may be Hybrid bonding (Hybrid bonding), and then an alloy (alloy) process and rapid thermal annealing (Rapid Thermal Annealing, RTA) are performed.

In an exemplary embodiment, the substrate 210 may be removed by a process such as grinding (grind), chemical mechanical polishing (Chemical Mechanical Polishing, CMP) or wet etching (wet etching), and combinations thereof.

4) Forming a word line isolation groove T1;

the forming of the word line isolation groove T1 may include: etching the semiconductor layer 9 to form a plurality of word line isolation grooves T1 extending along a first direction X; the bottom of the word line isolation trench T1 exposes the bit line layer 30', i.e., exposes the connection layer 32, as shown in fig. 5, and fig. 5 is a cross-sectional view along the AA' direction after forming the word line isolation trench T1. The word line isolation trenches T1 may be spaced apart along the second direction Y. At this time, the semiconductor layer 9 is cut into a plurality of individual planar semiconductor portions 9'.

5) Forming a third insulating layer 4 and a fourth insulating layer 5;

the forming of the third insulating layer 4 and the fourth insulating layer 5 may include: depositing a third insulating film on the substrate 1 having the above structure to form a third insulating layer 4; and depositing a fourth insulating film to form a fourth insulating layer 5, and leveling the surfaces of the third insulating layer 4 and the fourth insulating layer 5 on the side far away from the substrate 1 and the surface of the semiconductor layer 9 on the side far away from the substrate 1, as shown in fig. 6, fig. 6 is a schematic cross-sectional view along the AA' direction after forming the third insulating layer 4 and the fourth insulating layer 5.

In an exemplary embodiment, the third and fourth insulating films may be deposited by ALD.

In an exemplary embodiment, the third insulating film and the fourth insulating film may be low-K dielectric layers, i.e., dielectric layers having a dielectric constant K < 3.9. For example, any one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC) may be used.

In an exemplary embodiment, the third insulating film may be silicon oxide.

In an exemplary embodiment, the fourth insulating film may be silicon nitride.

6) Forming a bit line 30;

the forming of the bit line 30 may include:

a plurality of bit line isolation trenches T2 extending in the second direction Y are formed, the bit line isolation trenches T2 exposing the first insulating layer 2, the bit line isolation trenches T2 dividing the bit line layer 30 'into a plurality of bit lines 30 and the semiconductor portion 9' into a plurality of semiconductor pillars 10.

A fifth insulating film is deposited on the substrate 1 having the above structure to form a fifth insulating layer 6 filling the bit line isolation trench T2, as shown in fig. 7A and 7B, fig. 7A is a cross-sectional view along AA 'direction after forming the bit line 30, and fig. 7B is a cross-sectional view along CC' direction after forming the bit line 30. The bit line isolation trenches T2 may be spaced apart along the first direction X.

In some embodiments, the number of bit lines 30 may be related to the number of columns of semiconductor pillars 10, and one bit line 30 may correspond to one column of semiconductor pillars 10.

In some embodiments, the bit line 30 may be a stripe electrode.

In some embodiments, the orthographic projection of the bit line 30 may be rectangular in a plane parallel to the substrate 1.

In some embodiments, each of the bit lines 30 may connect a column of semiconductor pillars 10 distributed along the second direction Y.

In an exemplary embodiment, the depositing the fifth insulating film on the substrate 1 forming the foregoing structure may include: a sixth insulating film is deposited on the substrate 1 with the structure by an ALD method to form a first insulating sub-layer, and then a fifth insulating film is deposited by a spin-on oxide dielectric (Spin Oxide Dielectric, SOD) coating method to form a second insulating sub-layer, wherein the first insulating sub-layer and the second insulating sub-layer form a fifth insulating layer 6.

In an exemplary embodiment, the fifth insulating film may be a low-K dielectric layer, such as any one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON), silicon carbide (SiC), and black diamond (black diamond).

7) Exposing the channel region 11 and the first region 12;

the exposing the channel region 11 and the first region 12 may include: the fourth insulating layer 5 and the third insulating layer 4 are etched to expose the channel region 11 and the first region 12, as shown in fig. 8, and fig. 8 is a cross-sectional view along the AA' direction after exposing the channel region 11 and the first region 12. Exposing the channel region 11 includes exposing sidewalls of the channel region 11, and exposing the first region 12 includes exposing sidewalls and a top surface (a surface on a side away from the substrate 1) of the first region 11.

8) Forming a gate insulating layer 14 and a gate electrode 21;

the forming of the gate insulating layer 14 and the gate electrode 21 may include: sequentially depositing a gate insulating film and a gate electrode film on the substrate 1 having the above structure;

the gate insulating film and the gate electrode film are etched to expose the first region 12, and the gate insulating layer 14 and the gate electrode 21 are formed, as shown in fig. 9, and fig. 9 is a cross-sectional view along the AA' direction after the gate insulating layer 14 and the gate electrode 21 are formed. The gate electrodes 21 of the transistors of the same column are connected to form a word line 20. The gate insulating layer 14 is provided between the gate electrode 21 and the semiconductor pillar 10, isolating the semiconductor pillar 10 from the gate electrode 21. The exposing the first region 12 may include exposing sidewalls and a top surface of the first region 12.

In an exemplary embodiment, the gate insulating film may be a High-K dielectric material including, but not limited to, at least one of: a single-layer structure or a multi-layer structure of at least one of silicon oxide, aluminum oxide, silicon nitride, hafnium oxide, and silicon oxynitride.

In an exemplary embodiment, the gate electrode thin film may be formed of or include a conductive material, and the conductive material may be, for example, one of a doped semiconductor material, a conductive metal nitride, a metal material, and a metal-semiconductor compound.

9) Forming a node contact layer 40;

the forming of the node contact layer 40 may include:

depositing a sixth insulating film on the substrate 1 having the above-described structure to form a sixth insulating layer 7; the first distance between the surface of the sixth insulating layer 7 on the side far from the substrate 1 and the substrate 1 is greater than the second distance between the surface of the semiconductor pillar 10 on the side far from the substrate 1 and the substrate 1, for example, the difference between the first distance and the second distance may be 50 angstroms to 1000 angstroms.

A plurality of vias exposing the top ends of the semiconductor pillars 10 are formed on the sixth insulating layer 7, and the second conductive film is deposited on the vias and then ground down to form the node contact layer 40, as shown in fig. 10, and fig. 10 is a cross-sectional view along the AA' direction after forming the node contact layer 40. The node contact layer 40 is in contact with the surface of the first region 12 on the side remote from the substrate 1.

In an exemplary embodiment, the front projection of the node contact layer 40 on the substrate 1 overlaps with the front projection of the first region 12 on the substrate 1.

In an exemplary embodiment, the second conductive film may be a polysilicon film, such as high phosphorus doped polysilicon. The node contact layer 40 may reduce the contact resistance between the subsequently formed first plate 41 and the first region 12.

10 A) forming a capacitance;

the forming of the capacitor may include:

depositing a first conductor material on the substrate 1 with the structure, and patterning to form a first polar plate 41 arranged on the surface of the node contact layer 40;

depositing a dielectric material on the substrate 1 with the structure, and patterning to form a dielectric layer 43;

depositing a second conductor material on the substrate 1 with the structure, and patterning to form a second electrode plate 42;

depositing a seventh insulating film on the substrate 1 having the above structure to form a seventh insulating layer 8; as shown in fig. 11, fig. 11 is a schematic cross-sectional view along AA' after forming a capacitor.

In an exemplary embodiment, the first or second conductor material may include at least one of a metal material (e.g., titanium, tantalum, tungsten, copper, and aluminum), a conductive metal nitride (e.g., titanium nitride and tantalum nitride), and a doped semiconductor material (e.g., doped silicon and doped germanium) formed or include at least one of a metal material (e.g., titanium, tantalum, tungsten, copper, and aluminum), a conductive metal nitride (e.g., titanium nitride and tantalum nitride), and a doped semiconductor material (e.g., doped silicon and doped germanium), for example.

In an exemplary embodiment, the dielectric material includes, for example, one or a combination of the following: zirconia (ZrO) ₂ ) Alumina (Al) ₂ O ₃ ) Zirconium oxide (ZrO) ₂ ) At least one of a laminated structure, hafnium oxide, strontium titanate, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

In an exemplary embodiment, dielectric layers 43 of transistor-connected capacitors in the memory array may be connected to form a unitary structure.

In an exemplary embodiment, the second plates 42 of the transistor-connected capacitors in the memory array may be connected to form a unitary structure. The one-piece structure may be, for example, a full-face electrode.

In an exemplary embodiment, the first plate 41 may have a U-shape in a cross section perpendicular to the substrate 1, the first plate 41 may have a cylindrical shape having one open end, and the second plate 42 may fill the cylindrical inner space.

11 The interconnection of the logic circuit and the memory array is realized;

the interconnecting the implementation logic and the storage array may include: forming a first via hole penetrating through the seventh insulating layer 8, the sixth insulating layer 7, the fourth insulating layer 5, the third insulating layer 4, the second insulating layer 3 and the first insulating layer 2, and forming a second via hole penetrating through the seventh insulating layer 8, the sixth insulating layer 7, the fourth insulating layer 5 and the third insulating layer 4, the first via hole exposing the logic circuit 110 and the second via hole exposing the bit line 30; a third conductive film is deposited in the first via hole to form a first connection electrode 81, and a third conductive film is deposited in the second via hole to form a second connection electrode 82, as shown in fig. 12, fig. 12 is a cross-sectional view along the AA' direction after interconnection is achieved. The first connection electrode 81 and the second connection electrode 82 may be connected to an external circuit, and then a signal may be applied to the logic circuit through the first connection electrode 81, a signal may be applied to the bit line 30 through the second connection electrode 82, and so on. A rewiring layer (ReDistribution Layer, RDL) may also be provided, and the package is post-rewiring. A portion of the pads of the rewiring layer is illustrated in fig. 12 by way of example only, and the embodiments of the present disclosure are not limited in this regard.

In an exemplary embodiment, the first via and the first connection electrode, the second via and the second connection electrode may be formed by a through silicon via (Through Silicon Via, TSV), for example, after the first via is formed, a seed layer including tantalum (Ta) or tantalum nitride (TaN), and copper (Cu) is deposited in the first via, a copper (Cu) thin film is formed on the seed layer by ECP, and then the copper thin film is planarized, for example, by CMP, to form the first connection electrode. Or after the TSV is formed, growing a Ti and TiN film, then forming a metal tungsten filling, and finally flattening through CMP. The second connection electrode is similar and will not be described again.

In the above embodiment, 1T1C is taken as an example for illustration, but the embodiments of the disclosure are not limited thereto, and the transistor may be combined with other devices, for example, a memory structure of 2T0C with another transistor, and so on.

In the above embodiment, by using two wafers, a transistor is fabricated on one wafer, a bit line layer is fabricated on the other wafer, and then the bit line layer is directly etched to form the bit line. In addition, the size and shape of different bit lines of the same memory array are easier to control, so that the size and shape of different bit lines are consistent, and the resistance of the bit lines is stable.

The structure shown in this embodiment and the process of preparing it are merely exemplary. In actual implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.

The embodiment of the disclosure also provides electronic equipment, which comprises the semiconductor device of the embodiment. The electronic device may be: storage, smart phones, computers, tablet computers, artificial intelligence devices, wearable devices, graphics processors (Graphics Processing Unit, GPU), off-the-shelf computing or mobile power supplies, and the like. The storage device may include, without limitation, memory in a computer, and the like.

Fig. 13 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in fig. 13, an embodiment of the present disclosure provides a method of manufacturing a semiconductor device including at least one transistor including a semiconductor pillar, the method comprising:

step 1301, providing a first wafer comprising a substrate, forming a bit line layer on the substrate;

step 1302, providing a second wafer, wherein the second wafer comprises a substrate and a semiconductor layer arranged on the substrate, turning over the second wafer, bonding the second wafer with the first wafer at one side far away from the substrate, and etching to remove the substrate so as to expose the semiconductor layer, wherein the bit line layer is in contact with the semiconductor layer;

And step 1303, etching the semiconductor layer and the bit line layer to form at least one semiconductor pillar extending along a direction perpendicular to the substrate, wherein the semiconductor pillar comprises a channel region, and a first region and a second region respectively arranged at two sides of the channel region, the second region is arranged at one side of the channel region facing the substrate, and at least one bit line is formed, and the second region is contacted with the bit line.

In this embodiment, the structure, materials, related parameters and detailed preparation process of each film layer are described in the foregoing embodiments, and are not described herein.

According to the manufacturing method of the semiconductor device, the bit line and the transistor are respectively manufactured on different wafers, the process is simple, the formation of the cavity of the bit line can be avoided, the bit line is more stable, and the contact resistance between the bit line and the semiconductor column is more stable. In addition, when the memory array is manufactured, the size and shape of different bit lines of the same memory array are easier to control, the size and shape of different bit lines can be consistent, and the bit line resistance is stable. The manufacturing method can be realized by using the existing equipment, and is easy to implement.

In an exemplary embodiment, the etching the semiconductor layer and the bit line layer may include:

In an exemplary embodiment, the providing the second wafer may include: and epitaxially growing and doping on the substrate to form a semiconductor layer.

In an exemplary embodiment, the forming the bit line layer on the substrate may include:

And depositing a connecting layer film, patterning to form a connecting layer, wherein the first conductive layer and the connecting layer form the bit line layer, and the orthographic projection of the connecting layer on the substrate overlaps with the orthographic projection of the first conductive layer on the substrate. In an exemplary embodiment, before forming the bit line layer on the substrate, logic circuitry is further included on the substrate.

Although the embodiments of the present invention are described above, the embodiments are only used for facilitating understanding of the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is to be determined by the appended claims.

Claims

1. A semiconductor device, comprising: a first wafer and a second wafer disposed on the first wafer, the first wafer comprising a substrate and a bit line disposed on the substrate; the second wafer comprises at least one transistor, the transistor comprises a semiconductor column extending along the direction perpendicular to the substrate, the semiconductor column comprises a channel region, a first region and a second region, the first region and the second region are respectively arranged on two sides of the channel region, the second region is arranged on one side of the channel region, which faces the substrate, the bit line comprises a first conductive layer arranged on the substrate and a connecting layer arranged on one side, which faces away from the substrate, of the first conductive layer, the connecting layer comprises metal silicide, and the connecting layer of the bit line is in contact with the second region.

2. The semiconductor device of claim 1, wherein a contact surface of the bit line with the second region is parallel to the substrate.

3. The semiconductor device according to claim 1, wherein a surface of the bit line on a side close to the substrate is parallel to the substrate.

4. The semiconductor device of claim 1, wherein the orthographic projection of the bit line comprises a rectangle on a plane parallel to the substrate.

5. The semiconductor device of claim 1, wherein the second wafer comprises a plurality of the transistors arranged in an array along a first direction and a second direction, respectively, the first wafer comprising a plurality of the bit lines extending along the second direction, wherein second regions of the transistors of a same column arranged along the second direction connect a same bit line, the first direction and the second direction intersecting.

6. The semiconductor device according to claim 5, wherein the transistor further comprises: and the gate electrode surrounds the side wall of the channel region, and the gate electrodes of the transistors in the same row distributed along the first direction are connected to form a word line.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that the semiconductor device further comprises: logic circuitry disposed on a side of the bit line remote from the second wafer.

8. The semiconductor device of claim 7, wherein there is overlap between an orthographic projection of the logic circuit at the substrate and an orthographic projection of the transistor at the substrate.

9. An electronic device comprising the semiconductor device according to any one of claims 1 to 8.

10. The electronic device according to claim 9, wherein the semiconductor device further comprises: the capacitor is arranged on one side, far away from the first wafer, of the transistor and comprises a first polar plate, a second polar plate and a dielectric layer arranged between the first polar plate and the second polar plate, and the first polar plate is connected with the first area through a node contact layer.

11. A method of manufacturing a semiconductor device, the semiconductor device comprising at least one transistor, the transistor comprising a semiconductor pillar, the method comprising:

providing a first wafer comprising a substrate, and forming a bit line layer on the substrate, wherein the bit line layer comprises a first conductive layer arranged on the substrate and a connecting layer arranged on one side of the first conductive layer away from the substrate;

Providing a second wafer, wherein the second wafer comprises a substrate and a semiconductor layer arranged on the substrate, turning over the second wafer, bonding one side of the second wafer away from the substrate with the first wafer, siliciding the connecting layer into metal silicide, and etching to remove the substrate to expose the semiconductor layer, wherein the connecting layer of the bit line layer is in contact with the semiconductor layer;

the semiconductor layer and the bit line layer are etched to form at least one semiconductor column extending along the direction perpendicular to the substrate, the semiconductor column comprises a channel region, a first region and a second region, the first region and the second region are respectively arranged on two sides of the channel region, the second region is arranged on one side, facing the substrate, of the channel region, at least one bit line is formed, and the second region is in contact with the connecting layer of the bit line.

12. The method of manufacturing a semiconductor device according to claim 11, wherein the etching the semiconductor layer and the bit line layer comprises:

13. The method of manufacturing a semiconductor device according to claim 11, wherein the providing the second wafer comprises: and epitaxially growing and doping on the substrate to form a semiconductor layer.

14. The method of manufacturing a semiconductor device according to claim 11, wherein the forming a bit line layer over the substrate comprises:

and depositing a connecting layer film, patterning to form the connecting layer, wherein the first conductive layer and the connecting layer form the bit line layer, and the orthographic projection of the connecting layer on the substrate overlaps with the orthographic projection of the first conductive layer on the substrate.

15. The method for manufacturing a semiconductor device according to any one of claims 11 to 14, further comprising, before forming a bit line layer over the substrate, forming a logic circuit over the substrate.