CN116647524A - Acceleration unit, host, computing device, system on chip, and related methods - Google Patents

Acceleration unit, host, computing device, system on chip, and related methods Download PDF

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Publication number
CN116647524A
CN116647524A CN202310370010.3A CN202310370010A CN116647524A CN 116647524 A CN116647524 A CN 116647524A CN 202310370010 A CN202310370010 A CN 202310370010A CN 116647524 A CN116647524 A CN 116647524A
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China
Prior art keywords
host
virtual machine
memory buffer
physical address
target virtual
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CN202310370010.3A
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Chinese (zh)
Inventor
梁晨
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Pingtouge Shanghai Semiconductor Co Ltd
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Pingtouge Shanghai Semiconductor Co Ltd
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Priority to CN202310370010.3A priority Critical patent/CN116647524A/en
Publication of CN116647524A publication Critical patent/CN116647524A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4641—Virtual LANs, VLANs, e.g. virtual private networks [VPN]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/70—Virtual switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements

Abstract

The embodiment of the application provides an acceleration unit, a host machine, a computing device, a system-on-chip and a related method, wherein the acceleration unit comprises: a forwarding subunit, configured to determine a target virtual machine of a received data packet according to forwarding information included in the data packet; a writing subunit, configured to write data content included in the data packet into a first memory buffer area allocated by the host; and the notification subunit is used for sending a packet receiving instruction to the target virtual machine after the forwarding subunit determines the target virtual machine, so that the target virtual machine reads the data content from the first memory buffer area according to the packet receiving instruction. The scheme can reduce the cost of the chip where the acceleration unit is located.

Description

Acceleration unit, host, computing device, system on chip, and related methods
Technical Field
The embodiment of the application relates to the technical field of chips, in particular to an acceleration unit, a host machine, a computing device, a system on a chip and a related method.
Background
In a cloud computing scenario, a network, storage, etc. need to be virtualized, a host (host) constructs a plurality of Virtual Machines (VMs), a cloud infrastructure processor (Cloud infrastructure Processing Units, CIPU) serves as an acceleration unit, and after receiving a data packet, the data packet needs to be forwarded through a Virtual Switch (vSwitch) to determine which Virtual Machine to send the data packet to, and because the Virtual Switch forwarding process needs a certain time, the cloud infrastructure processor needs to buffer the data packet in a period of time for forwarding by the Virtual Switch.
Currently, a buffer is set in a chip where a cloud infrastructure processor is located, the cloud infrastructure processor caches a data packet in the buffer in a period of time of forwarding by a virtual switch, and after the virtual switch forwards, the data packet in the buffer is sent to a corresponding virtual machine according to a forwarding result.
However, providing a buffer in the chip where the cloud infrastructure processor is located creates additional costs, resulting in a higher cost for the chip.
Disclosure of Invention
Accordingly, embodiments of the present application provide an acceleration unit, a host, a computing device, a system-on-chip and related methods to solve or alleviate at least the above-mentioned problems.
According to a first aspect of an embodiment of the present application, there is provided an acceleration unit including: a forwarding subunit, configured to determine a target virtual machine of a received data packet according to forwarding information included in the data packet; a writing subunit, configured to write data content included in the data packet into a first memory buffer area allocated by the host; and the notification subunit is used for sending a packet receiving instruction to the target virtual machine after the forwarding subunit determines the target virtual machine, so that the target virtual machine reads the data content from the first memory buffer area according to the packet receiving instruction.
According to a second aspect of embodiments of the present application, there is provided a host computer comprising: an allocation subunit, configured to allocate a first memory buffer area; the storage subunit is configured to receive data content included in a data packet sent by the acceleration unit, and store the data content in the first memory buffer area, so that after a target virtual machine of the data packet receives a packet receiving instruction sent by the acceleration unit, the target virtual machine reads the data content from the first memory buffer area according to the packet receiving instruction, where the target virtual machine is located on the host, and the target virtual machine is determined by the acceleration unit according to forwarding information included in the data packet.
According to a third aspect of embodiments of the present application, there is provided a computing device comprising: a processing unit for constructing the host machine according to the second aspect; the acceleration unit according to the first aspect described above.
According to a fourth aspect of embodiments of the present application, there is provided a system on a chip comprising an acceleration unit according to the first aspect described above.
According to a fifth aspect of embodiments of the present application, there is provided a data center comprising a computing device according to the third aspect described above.
According to a sixth aspect of the embodiment of the present application, there is provided a message transmission method, including: receiving a message through a network; determining a target virtual machine of the message according to an outer layer message header included in the message; writing an inner layer message included in the message into a first memory buffer area allocated by the host; and sending a packet receiving instruction to the target virtual machine, so that the target virtual machine reads the inner layer message from the first memory buffer area according to the packet receiving instruction.
According to a seventh aspect of an embodiment of the present application, there is provided a data reading method including: receiving the data packet read from the memory through the network; determining a target virtual machine of the data packet according to forwarding information included in the data packet; writing data content included in the data packet into a first memory buffer area allocated by a host; and sending a packet receiving instruction to the target virtual machine so that the target virtual machine reads the data content from the first memory buffer area according to the packet receiving instruction.
According to the scheme provided by the embodiment of the application, after the accelerating unit receives the data packet, the target virtual machine of the data packet is determined through forwarding, meanwhile, the data content included in the data packet is stored in the first memory buffer area allocated by the host machine, after the target virtual machine of the data packet is determined, the mapping relation between the client machine physical address of the second memory buffer area allocated by the target virtual machine and the host machine physical address of the first memory buffer area is created on the host machine, and then the target virtual machine can read the data content from the first memory buffer area according to the mapping relation, and the buffer area of the data content is not required to be set in the chip where the accelerating unit is located, so that the cost of the chip can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.
FIG. 1 is a schematic diagram of a data center of one embodiment of the present application;
FIG. 2 is a schematic diagram of a server according to one embodiment of the application;
FIG. 3 is a schematic diagram of an acceleration unit according to one embodiment of the present application;
FIG. 4 is a schematic diagram of an acceleration unit according to another embodiment of the present application;
FIG. 5 is a schematic diagram of a host according to one embodiment of the application;
FIG. 6 is a schematic diagram of a host according to another embodiment of the present application;
FIG. 7 is a schematic diagram of a messaging system according to one embodiment of the present application;
FIG. 8 is a flow chart of a message transmission method according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a data reading system according to one embodiment of the application;
fig. 10 is a flowchart of a data reading method according to an embodiment of the present application.
Detailed Description
The present application is described below based on examples, but the present application is not limited to only these examples. In the following detailed description of the present application, certain specific details are set forth in detail. The present application will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the application. The figures are not necessarily drawn to scale.
First, partial terms or terminology appearing in the course of describing the embodiments of the application are applicable to the following explanation.
Cloud infrastructure processor: the cloud infrastructure processor (Cloud Infrastructure Processing Units, CIPU) is a special processor designed for a cloud data center, which is connected to physical computing, storage and network resources downwards, quickly clouds and accelerates hardware, and is connected to a cloud operating system upwards to control a server of the cloud data center. The cloud infrastructure processor can solve the problem of data migration bandwidth, and can also cloud and virtualize a management and control data center.
Host machine: a host (host) is a cloud server, a physical server, a virtual host, or the like that deploys a virtualized environment. The host may create multiple virtual machines providing software and hardware support for the operation of the virtual machines.
Virtual machine: a Virtual Machine (VM) refers to a complete computer system that has complete hardware system functions through software emulation and runs in an isolated environment.
Buffer zone: a Buffer is a storage space of a designated size reserved in a memory for temporarily storing input/output (I/O) data.
Acceleration unit: for the case that the conventional processing unit is not efficient in some special-purpose fields (for example, displaying images, processing images, data forwarding, message forwarding, etc.), the processing unit is designed to increase the data processing speed in these special-purpose fields. The acceleration unit in embodiments of the present application refers to a cloud infrastructure processor, an infrastructure processor (Infrastructure Processing Units, IPU) or a data processing unit (Data Processing Unit, DPU).
System on chip: system on a chip (SoC) refers to a technology of integrating a complete system on a single chip and grouping all or part of necessary electronic circuits. So-called complete systems typically include a processor (CPU) or acceleration unit, memory, and peripheral circuitry, etc. Socs are developed in parallel with other technologies, such as silicon-on-insulator (SOI), which can provide enhanced clock frequencies, thereby reducing the power consumption of the microchip.
Data center
Data centers are globally coordinated, specific networks of devices used to communicate, accelerate, display, calculate, store data information over an internet network infrastructure. In future developments, data centers will also become an asset for enterprise competition. With the widespread application of data centers, virtualization technology is increasingly applied to data centers. Cloud infrastructure processors have been largely applied to input/output virtualization scenarios in data centers as an important support for virtualization technology.
In a conventional large data center, the network architecture is generally shown in fig. 1, i.e., an interconnection network model (hierarchical inter-networking model). This model contains the following parts:
server 140: each server 140 is a processing and storage entity of a data center in which the processing and storage of large amounts of data is accomplished by these servers 140.
Access switch 130: access switch 130 is a switch used to allow server 140 access to a data center. An access switch 130 accesses a plurality of servers 140. The access switches 130 are typically located at the Top of the Rack, so they are also referred to as Top of Rack switches, which physically connect to the servers.
Aggregation switch 120: each aggregation switch 120 connects multiple access switches 130 while providing other services such as firewall, intrusion detection, network analysis, etc.
Core switch 110: core switch 110 provides high speed forwarding of packets into and out of the data center and connectivity for aggregation switch 120. The entire data center network is divided into an L3 layer routing network and an L2 layer routing network, and the core switch 110 typically provides a flexible L3 layer routing network for the entire data center network.
Typically, the aggregation switch 120 is a demarcation point for L2 and L3 layer routing networks, below the aggregation switch 120 is an L2 network, above is an L3 network. Each group of aggregation switches manages one transport point (Point Of Delivery, POD), within which is a separate VLAN network. The server migration within the POD does not have to modify the IP address and default gateway because one POD corresponds to one L2 broadcast domain.
Spanning tree protocol (Spanning Tree Protocol, STP) is typically used between the aggregation switch 120 and the access switch 130. STP makes only one aggregation switch 120 available for one VLAN network, the other aggregation switches 120 being used in the event of a failure. That is, at the level of the aggregation switch 120, no horizontal expansion is made, since only one is working even if multiple aggregation switches 120 are added.
The embodiment of the application can be applied to an input/output virtualization scene, a virtualization environment can be deployed on the server 140, a plurality of virtual machines are created based on the virtualization environment, network messages are sent between the virtual machines or between the virtual machines and clients through a network, and the virtual machines can also read data from the server through the network.
Server device
The computing device in the embodiment of the present application may be used as a server 140 included in a data center, where the server 140 is a real processing device of the data center, and fig. 2 shows a block diagram of the structure inside the server 140. The server 140 comprises a memory 210, a processing unit cluster 270 and an acceleration unit cluster 280 with a bus connection. The processing unit cluster 270 includes a plurality of processing units 220. The acceleration unit cluster 280 includes a plurality of acceleration units 230. The acceleration unit 220 is a special processor designed mainly for accelerating the input/output speed of the virtual machine in the embodiment of the present application, and may be embodied as a Graphics Processing Unit (GPU), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Cloud Infrastructure Processor (CIPU), an Infrastructure Processor (IPU), a Data Processing Unit (DPU), or the like, which is designed specifically for input/output virtualization.
The traditional architecture design of the processing unit makes the control unit and the storage unit occupy a large part of space in the architecture, but the space occupied by the calculation unit is insufficient, so that the processing unit is very effective in logic control and not efficient in massive parallel calculation. Therefore, various specialized acceleration units have been developed for more efficient processing to increase the speed of computation for different functions and different fields of computation. In the embodiment of the present application, the acceleration unit 230 is a hardware accelerator specially used for accelerating the input/output speed design of the virtual machine, after receiving the data packet, the acceleration unit 230 may store the data packet into the memory of the host machine, then establish the mapping relationship between the client physical address (Guest Physical Address, GPA) and the host physical address (Host Physical Address, HPA), and then the virtual machine may read the data packet from the corresponding buffer area on the host machine according to the client physical address, so that the buffer area for buffering the data packet does not need to be set on the chip where the acceleration unit 230 is located, and the cost of the chip is reduced, which will be described in detail below.
The processing unit 220 is configured to construct a host machine, on which a plurality of virtual machines can be created, which input/output through the acceleration unit 230, for example, the virtual machines receive network messages through the acceleration unit 230, or read data from a storage server through the acceleration unit 230. The host may be built based on one or more processing units 220, a plurality of virtual machines may be created based on one processing unit 220, a plurality of virtual machines created in the same host may input/output through one or more acceleration units 230, a plurality of virtual machines input/output through one acceleration unit 230 may be created based on the same processing unit 220, or may be created based on different processing units 220. In the embodiment of the present application, the host machine constructed by the processing unit 220 may allocate a memory buffer, and after the acceleration unit 230 writes the data packet into the memory buffer, the host machine constructs a mapping relationship between the GPA and the HPA, and the virtual machine on the host machine may read the data packet from the memory buffer of the host machine according to the mapping relationship.
The embodiments of the present application mainly focus on the structures and configurations of the acceleration unit 230 and the host built based on the processing unit 220, and the structures and configurations of the acceleration unit 230 and the host will be described in detail hereinafter.
Internal structure of acceleration unit
Next, in conjunction with the internal structural diagram of the acceleration unit 230 shown in fig. 3, how the acceleration unit 230 operates will be described in detail.
As shown in fig. 3, the acceleration unit 230 includes a forwarding sub-unit 231, a writing sub-unit 232, and a notification sub-unit 233. The forwarding sub-unit 231 may determine a target virtual machine of the data packet according to forwarding information included in the received data packet. The writing subunit 232 may write the data content included in the data packet into the first memory buffer allocated by the host. After the forwarding subunit 231 determines the target virtual machine, the notification subunit 233 may send a packet receiving instruction to the target virtual machine, so that the target virtual machine reads, according to the packet receiving instruction, the data content included in the data packet from the first memory buffer. The target virtual machine of the data packet refers to a virtual machine that the data content included in the data packet needs to reach, that is, the data content included in the data packet needs to be sent to the target virtual machine.
The host has a plurality of virtual machines running thereon, and the acceleration unit 230, after receiving the data packet, needs the forwarding subunit 231 to determine the receiving party of the data packet. The data packet includes forwarding information defining a routing path of the data packet, including a destination MAC address, a destination IP address, etc., and data content, which is specific data to be transmitted to a receiving side. After the acceleration unit 230 receives the data packet, the forwarding sub-unit 231 may determine a target virtual machine as a receiving party of the data packet according to forwarding information included in the data packet. The forwarding sub-unit 231 may transmit the forwarding information to a virtual router included in the acceleration unit 230, and the virtual router performs forwarding processing to determine a target virtual machine of the data packet.
It should be understood that multiple virtual machines may be run on the host, or one virtual machine may be run, where the number of virtual machines on the host does not affect the transmission of data or messages by the acceleration unit 230, and the acceleration unit 230 may respectively perform data or message transmission for different virtual machines on the host.
The forwarding subunit 231 determines, according to the forwarding information, that a certain time is required for the target virtual machine of the data packet, and in order to ensure continuity of input/output of the acceleration unit 230, after the acceleration unit 230 receives the data packet, the writing subunit 232 may write the data content included in the data packet into the first memory buffer allocated by the host. After the acceleration unit 230 receives the data packet, the forwarding subunit 231 and the writing subunit 232 operate in parallel, the forwarding subunit 231 determines a target virtual machine of the data packet according to forwarding information included in the data packet, and the writing subunit 232 writes data content included in the data packet into the first memory buffer.
The first memory buffer is allocated by the host, and after the host allocates the first memory buffer, the Host Physical Address (HPA) of the first memory buffer is sent to the acceleration unit 230. After the acceleration unit 230 receives the data packet, the writing subunit 232 may send a data writing instruction to the host according to the host physical address of the first memory buffer area, so as to write the data content included in the data packet into the first memory buffer area.
The first memory buffer area allocated by the host machine can be recycled, for example, after a program running on the virtual machine reads data from the first memory buffer area, the first memory buffer area can be released, so that the first memory buffer area can be reused for caching new data. Therefore, after the forwarding subunit 231 determines the target virtual machine of the data packet and the writing subunit 232 writes the data content included in the data packet into the first memory buffer, the notifying subunit 233 sends a packet receiving instruction to the target virtual machine, so as to ensure that the target virtual machine can read correct data from the first memory buffer according to the packet receiving instruction, and avoid that the target virtual machine has received the packet receiving instruction when the writing subunit 232 has not written the data content included in the data packet into the first memory buffer, and further reads old data from the first memory buffer according to the packet receiving instruction.
If the time consumption of the forwarding sub-unit 231 determines the target virtual machine is greater than the time consumption of the writing sub-unit 232 for writing the data content into the first memory buffer, when the forwarding sub-unit 231 determines the target virtual machine of the data packet, the writing sub-unit 232 has already written the data content into the first memory buffer, so after the forwarding sub-unit 231 determines the target virtual machine, the notification sub-unit 233 can immediately send a packet receiving instruction to the target virtual machine, so that the target virtual machine reads the data content included in the data packet from the first memory buffer according to the packet receiving instruction.
If the time consuming time of the forwarding sub-unit 231 determining the target virtual machine is less than the time consuming time of the writing sub-unit 232 writing the data content into the first memory buffer, for example, a scenario where the data volume of the data packet is large, when the forwarding sub-unit 231 determining the target virtual machine of the data packet, the writing sub-unit 232 does not write the data content into the first memory buffer yet, it is necessary to wait for the writing sub-unit 232 to write the data content into the first memory buffer, and then notify the sub-unit 233 to send a packet receiving instruction to the target virtual machine.
When sending the packet-receiving instruction to the target virtual machine, the notification subunit 233 may perform a write operation on the memory of the target virtual machine, or perform a write operation on the memory of the target virtual machine, and send an interrupt to the target virtual machine after performing the write operation. When the notification subunit 233 performs a write operation on the memory of the target virtual machine, one or more flag bits in the memory of the target virtual machine may be modified, and the target virtual machine may determine whether the data content has been stored in the first memory buffer according to the flag bits, and further, after determining that the data content has been stored in the first memory buffer, read the data content from the first memory buffer.
In this embodiment of the present application, the acceleration unit 230 includes a forwarding subunit 231, a writing subunit 232, and a notification subunit 233, after receiving a data packet, the forwarding subunit 231 and the writing subunit 232 work in parallel, the forwarding subunit 231 determines a target virtual machine of the data packet according to forwarding information included in the data packet, the writing subunit 232 writes data content included in the data packet into a first memory buffer area allocated by a host machine, and after the forwarding subunit 231 determines the target virtual machine of the data packet, the notification subunit 233 sends a packet receiving instruction to the target virtual machine, so that the target virtual machine reads the data content of the data packet from the first memory buffer area. Therefore, after receiving the data packet, the acceleration unit 230 writes the data content included in the data packet into the first memory buffer area allocated by the host machine, and after determining the target virtual machine of the data packet, notifies the target virtual machine to read the data content from the first memory buffer area, without setting a buffer area in the chip where the acceleration unit 230 is located, thereby reducing the cost of the chip.
Fig. 4 is an internal structural diagram of an acceleration unit 230 according to another embodiment of the present application, and as shown in fig. 4, the acceleration unit 230 further includes an update subunit 234. The update subunit 234 may form a mapping relationship between the Guest Physical Address (GPA) and the Host Physical Address (HPA) on the host according to the Guest Physical Address (GPA) of the second memory buffer and the Host Physical Address (HPA) of the first memory buffer allocated by the target virtual machine, and after notifying the subunit 233 to send the packet-receiving instruction to the target virtual machine, the target virtual machine may read the data content from the first memory buffer according to the mapping relationship.
The host creates a plurality of virtual machines, the network card driver of the virtual machine can allocate a second memory buffer area for receiving packets, and send buffer area information of the second memory buffer area to the acceleration unit 230, where the buffer area information of the second memory buffer area includes a memory size of the second memory buffer area, a physical address (GPA) of the client, and the like. The host allocates a first memory buffer and transmits buffer information of the first memory buffer, which includes a length of the first memory buffer, a Host Physical Address (HPA), and the like, to the acceleration unit 230.
The available memory space of the virtual machine is a continuous physical memory space starting from zero addresses, and a new layer of address space, namely a client physical address space, is introduced, the client physical address space is not a real hardware address space, and the host physical address space is a real hardware address space, so that there is a mapping between the client physical address space and the host physical address space, namely a mapping relation between a client physical address (GPA) and a Host Physical Address (HPA), and the virtual machine can determine the Host Physical Address (HPA) mapped with the client physical address (GPA) according to the mapping relation, and further read data from a buffer indicated by the Host Physical Address (HPA).
In one example, a host machine runs a plurality of virtual machines, and a plurality of virtual network cards virtualized by the acceleration unit 230 are connected to the virtual machines. Before the virtual network card receives the packets, a network card driver of the virtual machine allocates a plurality of queues for receiving the packets for the virtual network card, wherein the queues comprise a plurality of buffers. When receiving a plurality of data packets, the virtual network card can buffer the data packets in different queues in a parallel mode, so that the parallelism of data transmission is improved, and the efficiency of data forwarding is improved. The virtual machine may include multiple processor cores, each of which may read data from one or more queues, and different processor cores may read data from different queues in parallel, thereby improving the data processing efficiency of the virtual machine.
And running a plurality of virtual machines on the host, wherein each virtual machine is connected with a plurality of virtual network cards, and when each virtual network card corresponds to a plurality of queues, the forwarding result of the forwarding subunit 231 indicates which queue corresponding to which virtual network card needs to be cached with the data content. For example, if the forwarding result of the forwarding subunit 231 includes the network card identifier a and the queue identifier B, the writing subunit 232 writes the data content into the queue identified by the network card identifier a and corresponding to the virtual network card as the queue identifier B.
When the network card driver of the virtual machine allocates the second memory buffer, the allocated second memory buffer may be a virtual buffer, instead of the real memory space on the host. When the second memory buffer is allocated, the mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) of the second memory buffer is dynamically updated according to the forwarding result of the forwarding subunit 231 instead of establishing the Host Physical Address (HPA) and the client physical address (GPA) of the first memory buffer.
The acceleration unit 230 stores a Host Physical Address (HPA) of the first memory buffer and a Guest Physical Address (GPA) of the second memory buffer, and after the forwarding subunit 231 determines the target virtual machine of the packet, the update subunit 234 may form a mapping relationship between the Guest Physical Address (GPA) and the Host Physical Address (HPA) on the host based on the Guest Physical Address (GPA) of the second memory buffer allocated by the target virtual machine and the Host Physical Address (HPA) of the first memory buffer allocated by the host. After the notification subunit 233 sends the packet-receiving instruction to the target virtual machine, the target virtual machine may determine the Host Physical Address (HPA) to which the Guest Physical Address (GPA) is mapped based on the Guest Physical Address (GPA) of the second memory buffer allocated by the target virtual machine and the mapping relationship between the Guest Physical Address (GPA) and the Host Physical Address (HPA) stored on the host, and then the target virtual machine may read the data content from the first memory buffer indicated by the Host Physical Address (HPA).
In this embodiment of the present application, the host allocates a first memory buffer, sends a Host Physical Address (HPA) of the first memory buffer to the acceleration unit 230, the target virtual machine allocates a second memory buffer, and sends a client physical address (GPA) of the second memory buffer to the acceleration unit 230, and further after the forwarding subunit 231 determines the target virtual machine of the data packet, the update subunit 234 may form a mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) on the host, and further the target virtual machine may read the data content included in the data packet from the first memory buffer according to the mapping relationship. The data content included in the data packet is written into the memory of the host, and then a mapping relation between the physical address (GPA) of the client and the physical address (HPA) of the host is established, so that the target virtual machine can read the data content according to the mapping relation, so that a buffer area for caching the data content is not required to be set in the chip where the acceleration unit 230 is located, and the cost of the chip can be reduced.
According to the target virtual machines of the data packets, a mapping relation between a client physical address (GPA) and a Host Physical Address (HPA) is formed on the host, and the plurality of target virtual machines share the first memory buffer area distributed by the host, so that the memory consumption of the host for data caching can be saved, and the performance of the host is improved.
In one possible implementation, update subunit 234 may create a mapping of a Guest Physical Address (GPA) to a Host Physical Address (HPA) on the host based on the Host Physical Address (HPA) of the first memory buffer and the Guest Physical Address (GPA) of the second memory buffer.
After forwarding sub-unit 231 determines the target virtual machine of the packet, update sub-unit 234 may create a mapping relationship between the Guest Physical Address (GPA) and the Host Physical Address (HPA) on the host based on the Host Physical Address (HPA) of the first memory buffer and the Guest Physical Address (GPA) of the second memory buffer. Specifically, the update subunit 234 may create a mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) on the acceleration unit 230, and then send the mapping relationship to the host to store the mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) on the host. Alternatively, the update subunit 234 may access the memory of the host through Direct Memory Access (DMA), and create a mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) in the memory of the host, without the participation of the processing unit (CPU) of the host.
In the embodiment of the present application, the acceleration unit 230 includes an update subunit 234, after the forwarding subunit 231 determines the target virtual machine of the data packet, the update subunit 234 may create, on the host, a mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) according to the Host Physical Address (HPA) of the first memory buffer area and the client physical address (GPA) of the second memory buffer area, and the process of creating the mapping relationship is implemented by hardware of the acceleration unit 230 without participation of a processing unit (CPU) of the host, so that the input/output scheme provided in this embodiment may be applicable to hosts constructed by various types of processing units (CPUs), and thus the applicability of the input/output scheme may be improved.
In one possible implementation, update subunit 234 may send a Guest Physical Address (GPA) and a Host Physical Address (HPA) to the host to cause the host to create a mapping of the Guest Physical Address (GPA) and the Host Physical Address (HPA) from the received GPA and HPA and store the created mapping.
In this embodiment of the present application, after the forwarding subunit 231 determines the target virtual machine of the data packet, the updating subunit 234 may send the client physical address (GPA) and the Host Physical Address (HPA) to the host, and the processing unit (CPU) of the host creates, through a software program, a mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) on the host, so that the target virtual machine may read, according to the mapping relationship, the data content included in the data packet from the first memory buffer allocated by the host. After the client physical address (GPA) and the Host Physical Address (HPA) are sent to the host, the processing unit (CPU) of the host constructs the mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) through a software program, without setting a hardware circuit for creating the mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) in the acceleration unit 230, so that the cost of the chip where the acceleration unit 230 is located can be reduced.
In one possible implementation, the target virtual machine may allocate at least two second memory buffers and send the Guest Physical Addresses (GPA) of the created second memory buffers to the acceleration unit 230. After the forwarding subunit 231 determines the target virtual machine of the data packet, the updating subunit 234 may determine, according to the writing order of the second memory buffer, the second memory buffer for creating the mapping relationship from the second memory buffer, and further the updating subunit 234 may create, on the host, the mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) of the first memory buffer based on the client physical address (GPA) of the second memory buffer and the Host Physical Address (HPA).
When the virtual machine allocates a plurality of second memory buffers, the acceleration unit 230 may set a write order of the plurality of second memory buffers allocated by the virtual machine, and after receiving a data packet targeting the virtual machine, the update subunit 234 may sequentially create a mapping relationship between a client physical address (GPA) and a Host Physical Address (HPA) using each second memory buffer allocated by the virtual machine according to the write order.
For example, the virtual machine allocates 3 second memory buffers, and the writing sequence of the 3 second memory buffers is the second memory buffer 1, the second memory buffer 2 and the second memory buffer 3. If the acceleration unit 230 creates a mapping relationship between a GPA and an HPA on the host using the physical address (GPA) of the second memory buffer 2 when the acceleration unit 230 last receives a packet with the virtual machine as a target virtual machine, the acceleration unit 230 creates a mapping relationship between a GPA and an HPA on the host using the physical address (GPA) of the second memory buffer 3 when the acceleration unit receives a packet with the virtual machine as a target virtual machine again. If the acceleration unit 230 creates a mapping relationship between a GPA and an HPA on the host using the physical address (GPA) of the second memory buffer 3 when the acceleration unit 230 last receives a packet with the virtual machine as a target virtual machine, the acceleration unit 230 creates a mapping relationship between a GPA and an HPA on the host using the physical address (GPA) of the second memory buffer 1 when receiving a packet with the virtual machine as a target virtual machine again.
When allocating buffers for receiving packets, the network card driver of the virtual machine may allocate a plurality of queues for each virtual machine, where each queue includes a plurality of second memory buffers, for example, each queue includes 256 second memory buffers (buffers). After determining that the data content needs to be written into a certain queue according to the forwarding result of the forwarding subunit 231, the data content may be written into the next buffer of the buffers into which data is written last time in the queue according to the order of each buffer in the queue.
In the embodiment of the present application, the virtual machine allocates a plurality of second memory buffers, and sends the client physical addresses (GPA) of the second memory buffers to the acceleration unit 230, and after the forwarding subunit 231 determines the target virtual machine of the data packet, the update subunit 234 selects one second memory buffer allocated by the target virtual machine according to the writing sequence of the second memory buffers allocated by the target virtual machine, and creates a mapping relationship between the client physical addresses (GPA) and the Host Physical Addresses (HPA) on the host based on the client physical addresses (GPA) of the second memory buffers. When the acceleration unit 230 receives a plurality of data packets with a certain virtual machine as a target virtual machine, the update subunit 234 may select different second memory buffers for different data packets to create a mapping relationship between a client physical address (GPA) and a Host Physical Address (HPA), so that the target virtual machine may read data contents included in different data packets according to the client physical addresses (GPA) of different second memory buffers in a parallel manner, without waiting for the completion of reading the data contents of a previous data packet, and then can read the data contents of a subsequent data packet, thereby improving the efficiency of input/output of the virtual machine.
In one possible implementation, the host may allocate at least two first memory buffers and send the Host Physical Addresses (HPAs) of the created first memory buffers to the acceleration unit 230. After the acceleration unit 230 receives the data packet, the writing subunit 232 may determine a first memory buffer area for writing the data content in each first memory buffer area according to the writing sequence of the first memory buffer areas, and then write the data content included in the data packet into the first memory buffer area through direct memory access (Direct Memory Access, DMA).
When the host allocates a plurality of first memory buffers, the acceleration unit 230 may set a writing order of the plurality of first memory buffers allocated by the host, and after the acceleration unit 230 receives the data packet, the writing subunit 232 may determine the first memory buffer for storing the data content according to the writing order, and then write the data content included in the data packet into the first memory buffer.
For example, the host allocates 10 first memory buffers, and the writing sequence of the 10 first memory buffers is from the first memory buffer 1 to the first memory buffer 10. If the writing subunit 232 writes the data content included in the data packet into the first memory buffer n when the accelerating unit 230 receives the data packet last time, the writing subunit 232 writes the data content included in the data packet into the first memory buffer n+1 when the accelerating unit 230 receives the data packet again, where n is a positive integer less than 10. If the writing subunit 232 writes the data content included in the data packet into the first memory buffer 10 when the acceleration unit 230 receives the data packet last time, the writing subunit 232 writes the data content included in the data packet into the first memory buffer 1 when the acceleration unit 230 receives the data packet again.
When writing the data content included in the data packet into the first memory buffer, the writing subunit 232 initiates a DMA write operation using the Host Physical Address (HPA) of the first memory buffer, and writes the data content included in the data packet into the first memory buffer. When writing the data content into the first memory buffer, the writing subunit 232 overwrites the data originally stored in the first memory buffer if other data is stored in the first memory buffer.
In the embodiment of the present application, the host allocates a plurality of first memory buffers, and sends the Host Physical Address (HPA) of the first memory buffers to the acceleration unit 230, and after the acceleration unit 230 receives the data packet, the writing subunit 232 selects, according to the writing sequence of the first memory buffers, the data content included in the data packet written in the first memory buffers. When the acceleration unit 230 receives a plurality of data packets, the writing subunit 232 can write the data contents included in different data packets into different first memory buffers, without waiting for the data contents of the preceding data packet to be read by the virtual machine, and then can write the data contents of the following data packet into the first memory buffers, so that the efficiency of inputting/outputting by the virtual machine can be improved. The writing subunit 232 writes the data content into the first memory buffer area through the DMA writing operation, so that the writing process of the data content does not need the participation of a processing unit (CPU) of the host machine, and the performance of the host machine is ensured.
Internal structure of host machine
Next, in conjunction with the internal structural diagram of the host 500 shown in fig. 5, how the host 500 operates will be described in detail.
As shown in fig. 5, host 500 includes an allocation subunit 501 and a storage subunit 502. The allocation subunit 501 may allocate a first memory buffer. The storage subunit 502 may receive the data content included in the data packet sent by the acceleration unit 230, and store the data content in the first memory buffer allocated by the allocation subunit 501, so as to read the data content from the first memory buffer according to the packet receiving instruction after the target virtual machine of the data packet receives the packet receiving instruction sent by the acceleration unit 230. The target virtual machine is located on the host 500, and is determined by the acceleration unit 230 according to forwarding information included in the data packet.
The allocation subunit 501 allocates a first memory buffer for buffering the data packet, and sends information such as the length of the first memory buffer and a Host Physical Address (HPA) to the acceleration unit 230. After receiving the data packet, the acceleration unit 230 sends the data content included in the data packet to the host according to the Host Physical Address (HPA) of the first memory buffer, and the storage subunit 502 stores the data content received by the host in the first memory buffer.
The host machine is provided with a plurality of virtual machines, when the acceleration unit 230 receives the data packet and determines a target virtual machine of the data packet according to forwarding information included in the data packet, the acceleration unit 230 sends a packet receiving instruction to the target virtual machine, and after the target virtual machine receives the packet receiving instruction, the data content can be read from the first memory buffer.
In this embodiment of the present application, the host 500 includes an allocation subunit 501 and a storage subunit 502, the allocation subunit 501 allocates a first memory buffer, the acceleration unit 230 receives a data packet, sends data content included in the data packet to the storage subunit 502, the storage subunit 502 stores the data content in the first memory buffer, and after determining a target virtual machine of the data packet according to forwarding information included in the data packet, the acceleration unit 230 sends a packet receiving instruction to the target virtual machine, and the target virtual machine reads the data content from the first memory buffer according to the packet receiving instruction. After the acceleration unit 230 receives the data packet, the storage subunit 502 writes the data content included in the data packet into the first memory buffer area allocated by the allocation subunit 501, and after the acceleration unit 230 determines the target virtual machine of the data packet, the target virtual machine is notified to read the data content from the first memory buffer area, so that the cost of the chip can be reduced without setting a buffer area in the chip where the acceleration unit 230 is located.
Fig. 6 is an internal structural diagram of a host 500 according to another embodiment of the present application, and as shown in fig. 6, the host 500 further includes a mapping subunit 503. Mapping subunit 503 may obtain a mapping relationship between a Guest Physical Address (GPA) of the second memory buffer and a Host Physical Address (HPA) of the first memory buffer, and store the mapping relationship. After the target virtual machine receives the packet collecting instruction, the target virtual machine can read the data content from the first memory buffer according to the mapping relation. The second memory buffer is a memory buffer allocated to the target virtual machine.
The host machine is provided with a plurality of virtual machines, the network card driver of the virtual machine can allocate a second memory buffer area for receiving packets, and send information such as the memory size of the second memory buffer area, the physical address (GPA) of the client machine, and the like to the acceleration unit 230. The allocation subunit 501 allocates a first memory buffer, and sends information such as the length of the first memory buffer, the Host Physical Address (HPA), and the like to the acceleration unit 230.
The acceleration unit 230 stores a Host Physical Address (HPA) of the first memory buffer and a Guest Physical Address (GPA) of the second memory buffer, after the acceleration unit 230 determines the target virtual machine of the data packet, the mapping subunit 503 may obtain the mapping relationship based on the Guest Physical Address (GPA) of the second memory buffer allocated by the target virtual machine and the Host Physical Address (HPA) of the first memory buffer allocated by the host, and store the mapping relationship. After the acceleration unit 230 sends the packet receiving instruction to the target virtual machine, the target virtual machine may determine the Host Physical Address (HPA) mapped by the Guest Physical Address (GPA) based on the Guest Physical Address (GPA) of the second memory buffer allocated by the target virtual machine and the mapping relationship between the Guest Physical Address (GPA) and the Host Physical Address (HPA) stored on the host, and then the target virtual machine may read the data content from the first memory buffer indicated by the Host Physical Address (HPA).
In the embodiment of the present application, the mapping subunit 503 may obtain a mapping relationship between a client physical address (GPA) and a Host Physical Address (HPA), and then the target virtual machine may read data content from the first memory buffer according to the mapping relationship. The data content included in the data packet is written into the memory of the host, and then a mapping relation between the physical address (GPA) of the client and the physical address (HPA) of the host is established, so that the target virtual machine can read the data content according to the mapping relation, without setting a buffer area for caching the data content in the chip where the acceleration unit 230 is located, thereby reducing the cost of the chip.
In one possible implementation, mapping subunit 503 may receive mapping information from acceleration unit 230, where the mapping information may indicate a mapping relationship between a client physical address (GPA) and a Host Physical Address (HPA), and may further store, on a host, the mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) according to the mapping information.
In the embodiment of the present application, after determining the target virtual machine of the data packet, the acceleration unit 230 may create, on the host, a mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) according to the Host Physical Address (HPA) of the first memory buffer area and the client physical address (GPA) of the second memory buffer area, so that the mapping subunit 503 may obtain the mapping relationship and store the mapping relationship, and the process of creating the mapping relationship is implemented by hardware of the acceleration unit 230 without participation of a processing unit (CPU) of the host, so that the input/output scheme provided in this embodiment may be applicable to a host constructed by various types of processing units (CPUs), and thus may improve applicability of the input/output scheme.
In one possible implementation, mapping subunit 503 may receive a Guest Physical Address (GPA) and a Host Physical Address (HPA) from acceleration unit 230, and may further construct a mapping relationship between the Guest Physical Address (GPA) and the Host Physical Address (HPA) according to the received Guest Physical Address (GPA) and Host Physical Address (HPA), and store the constructed mapping relationship.
In this embodiment of the present application, after the acceleration unit 230 determines the target virtual machine of the data packet, the client physical address (GPA) and the Host Physical Address (HPA) may be sent to the host, so that the mapping subunit 503 may create, by using a software program, a mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) on the host, and the target virtual machine may read, according to the mapping relationship, data content included in the data packet from the first memory buffer allocated by the host. After the client physical address (GPA) and the Host Physical Address (HPA) are sent to the host, the mapping subunit 503 builds the mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) through a software program, without setting a hardware circuit for creating the mapping relationship between the GPA and the HPA in the acceleration unit 230, so that the cost of the chip where the acceleration unit 230 is located can be reduced.
It should be noted that, in the embodiment of the present application, the host 500 interacts with the acceleration unit 230 in the foregoing embodiment, and the working process of the host 500 may be referred to the description in the foregoing embodiment of the acceleration unit, which is not described herein.
System on chip
The embodiment of the present application further provides a system on a chip, which includes the acceleration unit 230 in any of the above embodiments.
It should be noted that, the application of the acceleration unit 230 in the embodiment of the present application is not limited to a system on a chip, but may be applied in other various suitable manners, for example, the acceleration unit 230 and interactive components such as a processing unit (CPU), a main memory, etc. are disposed on a printed circuit board, and the acceleration unit 230 interacts with the processing unit (CPU), the main memory, etc. through a bus on the printed circuit board.
Message transmission method
The acceleration unit 230 and the host 500 in the foregoing embodiments may be applied to a network virtualization scenario to implement transmission of network messages to a virtual machine, and the working process of the acceleration unit 230 and the host 500 in the network virtualization scenario will be described below through an embodiment of a message transmission method.
Fig. 7 is a schematic diagram of a message transmission system according to an embodiment of the present application. As shown in fig. 7, a host runs a plurality of virtual machines, and the host is allocated a plurality of first memory buffers, which have corresponding Host Physical Addresses (HPAs). The network card driver of the virtual machine allocates a second memory buffer having a corresponding Guest Physical Address (GPA). The acceleration unit includes a virtual switch. In the message transmission system shown in fig. 7, the acceleration unit may be the acceleration unit 230 in the foregoing embodiment, and the host may be the host 500 in the foregoing embodiment.
Based on the message transmission system shown in fig. 7, the embodiment of the application provides a message transmission method applied to an acceleration unit, as shown in fig. 8, the message transmission method includes the following steps:
step 801, a message is received through a network.
The acceleration unit can receive the message through the network, and the receiving party of the message is a certain virtual machine running on the host machine.
Step 802, determining a target virtual machine of the message according to an outer layer message header included in the message.
After receiving the message, the acceleration unit can send an outer layer message head of the message to the virtual switch, wherein the outer layer message head comprises forwarding information of the message. The virtual switch can perform forwarding processing according to forwarding information included in the outer layer header, and determine a target virtual machine serving as a receiving party of the message.
Step 803, writing an inner layer message included in the message into a first memory buffer area allocated by the host.
After receiving the message, the acceleration unit can write the inner layer message of the message into a first memory buffer area allocated by the host. The inner layer message is the data content which is actually needed to be sent to the target virtual machine.
It should be noted that, the above steps 802 and 803 may be performed synchronously.
And 804, sending a packet receiving instruction to the target virtual machine, so that the target virtual machine reads the inner layer message from the first memory buffer area according to the packet receiving instruction.
When the acceleration unit writes the inner layer message into the first memory buffer area, the acceleration unit can sequentially send the inner layer message, the identification bit (address length, verification result and the like) and the interrupt to the host machine, and the interrupt can be used as a packet receiving instruction. After receiving the interrupt, a processing unit (CPU) of the host may determine that the inner layer packet has been stored in the first memory buffer, and may further read the inner layer packet from the first memory buffer.
The host allocates a first memory buffer for buffering the message and sends a Host Physical Address (HPA) of the first memory buffer to the acceleration unit. The virtual machine running on the host allocates a second memory buffer and sends a Guest Physical Address (GPA) of the second memory buffer to the acceleration unit. After the virtual switch determines the target virtual machine of the message, a mapping relation between the client physical address (GPA) and the Host Physical Address (HPA) can be created on the host according to the client physical address (GPA) of the second memory buffer area and the Host Physical Address (HPA) of the first memory buffer area allocated by the target virtual machine, and then the target virtual machine can read the inner layer message from the first memory buffer area according to the mapping relation after receiving the packet collecting instruction.
In the embodiment of the application, after a message is received through a network, a target virtual machine of the message is determined according to an outer layer message header of the message, an inner layer message of the message is written into a first memory buffer area allocated by a host machine, and after the target virtual machine of the message is determined, a packet receiving instruction is sent to the target virtual machine, so that the target virtual machine reads the inner layer message from the first memory buffer area. After the accelerating unit receives the message, writing the inner layer message into a first memory buffer area allocated by the host machine, and after the target virtual machine of the message is determined, informing the target virtual machine to read the inner layer message from the first memory buffer area, and the buffer area is not required to be arranged in a chip where the accelerating unit is located, so that the cost of the chip can be reduced.
It should be noted that, the message transmission method in the embodiment of the present application is a specific application of the acceleration unit 230 in the network virtualization scenario in the foregoing embodiment, and the specific message transmission method may be referred to the description in the foregoing acceleration unit embodiment, which is not repeated herein.
Data reading method
The acceleration unit 230 and the host 500 in the foregoing embodiments may be applied to a storage virtualization scenario to implement transferring data read from a memory to a virtual machine, and a working process of the acceleration unit 230 and the host 500 in the storage virtualization scenario is described below through an embodiment of a data reading method.
FIG. 9 is a schematic diagram of a data reading system according to one embodiment of the application. As shown in fig. 9, a host runs a plurality of virtual machines, and the host is allocated a plurality of first memory buffers, which have corresponding Host Physical Addresses (HPAs). The network card driver of the virtual machine allocates a second memory buffer having a corresponding Guest Physical Address (GPA). The acceleration unit includes a virtual switch. The acceleration unit is connected with the memory through a network. In the data reading system shown in fig. 9, the acceleration unit may be the acceleration unit 230 in the foregoing embodiment, and the host may be the host 500 in the foregoing embodiment.
Based on the data reading system shown in fig. 9, an embodiment of the present application provides a data reading method applied to an acceleration unit, as shown in fig. 10, the data reading method includes the following steps:
step 1001, receiving a data packet read from a memory through a network.
The virtual machine can send a data reading request to the memory through the acceleration unit, and the memory responds to the data reading request and sends data to be read by the virtual machine to the acceleration unit through a network in the form of data packets.
Step 1002, determining a target virtual machine of the data packet according to forwarding information included in the data packet.
The acceleration unit may acquire forwarding information of the data packet after receiving the data packet, and send the forwarding information to the virtual switch. The virtual switch may perform forwarding processing according to the forwarding information, and determine a target virtual machine that is a receiving party of the data packet.
Step 1003, writing the data content included in the data packet into a first memory buffer area allocated by the host.
After receiving the data packet, the acceleration unit may write the data content included in the data packet into the first memory buffer area allocated by the host.
It should be noted that, the above step 1002 and step 1003 may be performed synchronously.
And step 1004, sending a packet receiving instruction to the target virtual machine, so that the target virtual machine reads the data content from the first memory buffer area according to the packet receiving instruction.
The acceleration unit may sequentially send the data content, the identification bit (address length, check result, etc.) and the interrupt to the host when writing the data content into the first memory buffer, where the interrupt may be used as a packet receiving instruction. After receiving the interrupt, a processing unit (CPU) of the host may determine that the data content has been stored in the first memory buffer, and may then read the data content from the first memory buffer.
The host allocates a first memory buffer for buffering the message and sends a Host Physical Address (HPA) of the first memory buffer to the acceleration unit. The virtual machine running on the host allocates a second memory buffer and sends a Guest Physical Address (GPA) of the second memory buffer to the acceleration unit. After the virtual switch determines the target virtual machine of the data packet, a mapping relationship between the client physical address (GPA) and the Host Physical Address (HPA) can be created on the host according to the client physical address (GPA) of the second memory buffer area and the Host Physical Address (HPA) of the first memory buffer area allocated by the target virtual machine, and then the target virtual machine can read the data content from the first memory buffer area according to the mapping relationship after receiving the packet collecting instruction.
In the embodiment of the application, after receiving the data packet read from the memory through the network, determining the target virtual machine of the message according to the forwarding information included in the data packet, writing the data content included in the data packet into the first memory buffer area allocated by the host machine, and after determining the target virtual machine of the data packet, sending a packet receiving instruction to the target virtual machine so as to enable the target virtual machine to read the data content from the first memory buffer area. After the acceleration unit receives the data packet, the data content is written into a first memory buffer area allocated by the host machine, and after the target virtual machine of the data packet is determined, the target virtual machine is informed to read the data content from the first memory buffer area, and a buffer area is not required to be arranged in a chip where the acceleration unit is located, so that the cost of the chip can be reduced.
It should be noted that, the data reading method in the embodiment of the present application is a specific application of the acceleration unit 230 in the foregoing embodiment to storing the virtualized scene, and the specific data reading method can be referred to the description in the foregoing acceleration unit embodiment, and will not be described herein.
Commercial value of embodiments of the application
In the embodiment of the application, after receiving the data packet, the acceleration unit stores the data content included in the data packet into the first memory buffer area allocated by the host machine while determining the target virtual machine of the data packet through forwarding, and after determining the target virtual machine of the data packet, creates a mapping relation between the client physical address (GPA) of the second memory buffer area allocated by the target virtual machine and the Host Physical Address (HPA) of the first memory buffer area on the host machine, so that the target virtual machine can read the data content from the first memory buffer area according to the mapping relation, and the buffer area of the data content does not need to be set in the chip where the acceleration unit is located, thereby reducing the cost of the chip. The scheme can be applied to the scenes of network, storage and the like involving input/output (I/O) virtualization, and has good market prospect.
The size of the buffer inside the chip is one of the key indexes of the chip, but is limited by the conditions of chip area, power consumption, cost and the like, and the buffer with larger capacity can not be arranged inside the chip, so that the situation of data overflow can occur when the instantaneous flow is larger. According to the acceleration unit in the embodiment of the application, the buffer area for data caching is not arranged in the chip, the data content included in the received data packet is cached in the memory of the host (host), and compared with the buffer area with smaller capacity in the chip, the memory of the host has larger capacity, so that the caching capacity is improved, the problem of packet loss when the instantaneous flow is larger is avoided, and the burst resistance capacity in a virtualization scene is improved.
It should be noted that, the information related to the user (including, but not limited to, user equipment information, user personal information, etc.) and the data related to the embodiment of the present application (including, but not limited to, sample data for training the model, data for analyzing, stored data, displayed data, etc.) are information and data authorized by the user or fully authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards of the related country and region, and are provided with corresponding operation entries for the user to select authorization or rejection.
It should be understood that each embodiment in this specification is described in an incremental manner, and the same or similar parts between each embodiment are referred to each other, and each embodiment focuses on differences from other embodiments. In particular, for method embodiments, the description is relatively simple as it is substantially similar to the methods described in the apparatus and system embodiments, with reference to the description of other embodiments being relevant.
It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
It should be understood that elements described herein in the singular or shown in the drawings are not intended to limit the number of elements to one. Furthermore, modules or elements described or illustrated herein as separate may be combined into a single module or element, and modules or elements described or illustrated herein as a single may be split into multiple modules or elements.
It is also to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting. The use of these terms and expressions is not meant to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible and are intended to be included within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims should be looked to in order to cover all such equivalents.

Claims (15)

1. An acceleration unit comprising:
a forwarding subunit, configured to determine a target virtual machine of a received data packet according to forwarding information included in the data packet;
a writing subunit, configured to write data content included in the data packet into a first memory buffer area allocated by the host;
And the notification subunit is used for sending a packet receiving instruction to the target virtual machine after the forwarding subunit determines the target virtual machine, so that the target virtual machine reads the data content from the first memory buffer area according to the packet receiving instruction.
2. The acceleration unit of claim 1, further comprising:
and the updating subunit is used for forming a mapping relation between the client physical address and the host physical address on the host according to the client physical address of the second memory buffer area and the host physical address of the first memory buffer area allocated by the target virtual machine, so that the target virtual machine can read the data content from the first memory buffer area according to the mapping relation after receiving the packet receiving instruction.
3. The acceleration unit of claim 2, wherein,
and the updating subunit is used for creating a mapping relation between the client physical address and the host physical address on the host according to the client physical address of the second memory buffer area allocated by the target virtual machine and the host physical address of the first memory buffer area.
4. The acceleration unit of claim 2, wherein,
and the updating subunit is used for sending the client physical address and the host physical address to the host computer so that the host computer creates a mapping relation between the client physical address and the host physical address.
5. The acceleration unit of claim 2, wherein the target virtual machine allocates at least two second memory buffers;
and the updating subunit is used for determining the second memory buffer areas corresponding to the mapping relation according to the writing sequence of the at least two second memory buffer areas.
6. The acceleration unit of any one of claims 1-5, wherein the host allocates at least two first memory buffers;
the writing subunit is configured to write, according to the writing order of the at least two first memory buffers, data contents included in the data packet into the first memory buffers through direct memory access.
7. A host machine, comprising:
an allocation subunit, configured to allocate a first memory buffer area;
the storage subunit is configured to receive data content included in a data packet sent by the acceleration unit, and store the data content in the first memory buffer area, so that after a target virtual machine of the data packet receives a packet receiving instruction sent by the acceleration unit, the target virtual machine reads the data content from the first memory buffer area according to the packet receiving instruction, where the target virtual machine is located on the host, and the target virtual machine is determined by the acceleration unit according to forwarding information included in the data packet.
8. The host of claim 7, the host further comprising:
and the mapping subunit is used for acquiring the mapping relation between the client physical address of the second memory buffer zone and the host physical address of the first memory buffer zone, and storing the mapping relation so that the target virtual machine can read the data content from the first memory buffer zone according to the mapping relation after receiving the packet receiving instruction, wherein the second memory buffer zone is the memory buffer zone allocated by the target virtual machine.
9. The host of claim 8, wherein,
the mapping subunit is configured to receive mapping information from the acceleration unit, where the mapping information is used to indicate a mapping relationship between the client physical address and the host physical address, and store the mapping relationship according to the mapping information.
10. The host of claim 8, wherein,
the mapping subunit is configured to receive the client physical address and the host physical address from the acceleration unit, construct a mapping relationship between the client physical address and the host physical address, and store the mapping relationship.
11. A computing device, comprising:
a processing unit for constructing the host of any one of claims 7-10;
acceleration unit according to any one of claims 1-6.
12. A system on a chip, comprising: acceleration unit according to any one of claims 1-6.
13. A data center, comprising: the computing device of claim 11.
14. A message transmission method comprises the following steps:
receiving a message through a network;
determining a target virtual machine of the message according to an outer layer message header included in the message;
writing an inner layer message included in the message into a first memory buffer area allocated by the host;
and sending a packet receiving instruction to the target virtual machine, so that the target virtual machine reads the inner layer message from the first memory buffer area according to the packet receiving instruction.
15. A data reading method, comprising:
receiving the data packet read from the memory through the network;
determining a target virtual machine of the data packet according to forwarding information included in the data packet;
writing data content included in the data packet into a first memory buffer area allocated by a host;
and sending a packet receiving instruction to the target virtual machine so that the target virtual machine reads the data content from the first memory buffer area according to the packet receiving instruction.
CN202310370010.3A 2023-04-07 2023-04-07 Acceleration unit, host, computing device, system on chip, and related methods Pending CN116647524A (en)

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