CN116647302A - PTP protocol-based time synchronization method, device and medium - Google Patents

Abstract

The embodiment of the specification discloses a time synchronization method, equipment and medium based on a PTP protocol, wherein the method comprises the following steps: based on a preset time interval, acquiring a time stamp and a calibration domain of the synchronous message; calculating clock deviation and link delay between the master device and the slave device according to the time stamp and the calibration domain; performing recursive median average filtering processing on the clock deviation and the link delay to obtain smooth timestamp data; carrying out Kalman filtering on the smooth time stamp to calculate estimated time stamp data; and carrying out time calibration on the system clock according to the estimated time stamp data. The invention carries out algorithm filtering and estimation on the time stamp and the clock deviation, so that the calculated link delay and the clock deviation are more accurate, and the system time is more stable after the calibration to the chip clock.

Description

PTP protocol-based time synchronization method, device and medium

Technical Field

The present disclosure relates to the field of accurate time synchronization of network switch devices, and in particular, to a time synchronization method, device, and medium based on PTP protocol.

Background

With the rapid development of distributed network technology, the operation of each system in a network environment needs to refer to a uniform and accurate time standard, so as to coordinate each subsystem in the network. PTP (Precision Time Protocol, precision time protocol, also known as IEEE1588 protocol) defines a widely used time synchronization protocol that enables accurate synchronization of time between network nodes in a distributed system. Usually, the PTP time synchronization protocol can be implemented by two schemes of software or hardware, wherein if a software scheme is adopted, the implementation difficulty is relatively simple, and a perfect protocol function can be implemented, but in practice, the synchronization accuracy can only reach millisecond level under the delay influence of an operating system and a network protocol stack. Meanwhile, the protocol stack is realized by adopting a hardware scheme, and a programmable hardware platform is needed to be relied on to realize the protocol stack, so that the synchronous precision can reach nanosecond level, but the development and realization difficulties are high and the cost is high.

In practical applications, the clock bias and delay calculated due to time synchronization measurement are directly associated with the acquired system time stamp. The system time stamp is affected by the frequency synchronization of the master clock and the slave clock, noise, clock jitter, network delay and other factors, so that the acquired time stamp data is unstable due to the noise, clock jitter, network delay and other factors in the actual application scene, and further the clock deviation and link delay result calculated by the time synchronization are unstable and the error is large.

Disclosure of Invention

One or more embodiments of the present disclosure provide a time synchronization method, device, and medium based on PTP protocol, for solving the following technical problems: in the currently used time synchronization application based on the PTP protocol, due to poor time stamp precision or abnormal time stamp data, abnormal jump of a calibration value calculated by time synchronization is caused, so that the problem of deviation accuracy of PTP time calculation is further affected.

One or more embodiments of the present disclosure adopt the following technical solutions:

one or more embodiments of the present specification provide a PTP protocol-based time synchronization method, including:

based on a preset time interval, acquiring a time stamp and a calibration domain of the synchronous message;

calculating clock deviation and link delay between the master device and the slave device according to the time stamp and the calibration domain;

performing recursive median average filtering processing on the clock deviation and the link delay to obtain smooth timestamp data;

carrying out Kalman filtering on the smooth time stamp to calculate estimated time stamp data;

and carrying out time calibration on the system clock according to the estimated time stamp data.

Further, the acquiring the timestamp and the calibration field of the synchronization message based on the preset time interval includes:

the slave device acquires a synchronous message sent by a CPU timer of the master device based on the preset time interval;

and the slave equipment analyzes the synchronous message to obtain a first time stamp and a first calibration domain.

Further, before the step of obtaining the synchronization message sent by the cpu timer of the master device, the method further includes:

the protocol stack acquires the system time sent by the CPU and fills the system time into the synchronous message as a first time stamp;

the protocol stack sends the synchronous message filled with the first time stamp to a chip;

and the chip calculates a first time difference consumed from the cpu to the chip, and fills the time difference into a first calibration domain of the synchronous message.

Further, the calculating clock bias and link delay between the master device and the slave device according to the time stamp and the calibration domain includes:

acquiring a second timestamp of the synchronous message received by the slave device;

and calculating clock deviation between the master device and the slave device according to the first timestamp, the second timestamp and the first calibration domain.

Further, the calculating clock bias and link delay between the master device and the slave device according to the time stamp and the calibration domain further includes:

the slave device sends a delay message to the master device;

the master device analyzes the delay message to obtain a third timestamp and a second calibration domain;

and calculating the link delay between the master device and the slave device according to the third timestamp and the second calibration domain.

Further, before the slave device sends a delay message to the master device, the method further includes:

the protocol stack acquires the system time sent by the CPU and fills the system time into the delay message as a third time stamp;

the protocol stack sends the delay message filled with the third time stamp to a chip;

and the chip calculates a second time difference consumed from the cpu to the chip, and fills the second time difference into a second calibration field of the delay message.

Further, the calculating clock bias and link delay between the master device and the slave device according to the time stamp and the calibration domain further includes:

acquiring a fourth timestamp of the synchronous message received by the slave device;

and calculating the link delay between the master device and the slave device according to the third timestamp, the fourth timestamp and the second calibration domain.

Further, the performing system clock time calibration according to the estimated timestamp data includes:

calculating a filtered time compensation value according to the filtered time stamp data;

and if the time compensation value is normal, the time compensation value is used for adjusting a clock, otherwise, the time compensation value is discarded.

One or more embodiments of the present specification provide a PTP protocol-based time synchronization device, which includes:

at least one processor; the method comprises the steps of,

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to:

based on a preset time interval, acquiring a time stamp and a calibration domain of the synchronous message;

calculating clock deviation and link delay between the master device and the slave device according to the time stamp and the calibration domain;

performing recursive median average filtering processing on the clock deviation and the link delay to obtain smooth timestamp data;

carrying out Kalman filtering on the smooth time stamp to calculate estimated time stamp data;

and carrying out time calibration on the system clock according to the estimated time stamp data.

One or more embodiments of the present specification provide a non-volatile computer storage medium storing computer-executable instructions configured to:

based on a preset time interval, acquiring a time stamp and a calibration domain of the synchronous message;

calculating clock deviation and link delay between the master device and the slave device according to the time stamp and the calibration domain;

performing recursive median average filtering processing on the clock deviation and the link delay to obtain smooth timestamp data;

carrying out Kalman filtering on the smooth time stamp to calculate estimated time stamp data;

and carrying out time calibration on the system clock according to the estimated time stamp data.

The above-mentioned at least one technical scheme that this description embodiment adopted can reach following beneficial effect: the master clock is locked through the phase-locked loop, so that the frequency synchronization of the master clock and the slave clock is realized, unstable time stamps are avoided, and the influence on the protocol stack time synchronization delay and clock deviation calculation is reduced. By adopting a correction and compensation method in the time synchronization calculation, the time error from the software protocol layer to the chip layer in the synchronization time calculation is reduced. The calculated link delay and clock deviation are more accurate by carrying out algorithm filtering and estimation on the time stamp and the clock deviation, and the system time is more stable after the calibration to the chip clock.

Drawings

In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some of the embodiments described in the present description, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. In the drawings:

fig. 1 is a flowchart of a time synchronization method based on PTP protocol according to an embodiment of the present disclosure.

Fig. 2 is a block diagram of main components of a PTP software protocol stack according to an embodiment of the present disclosure.

Fig. 3 is a PTP time synchronization message exchange flow provided in the embodiment of the present specification.

Fig. 4 is a data result of a kalman filter according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions in the present specification better understood by those skilled in the art, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present disclosure.

Referring to fig. 2, the PTP software protocol stack of the present invention includes several modules, specifically as follows:

PROTOCOL state machine (PROTOCOL):

the module is realized according to IEEE1588v2 protocol standard and mainly consists of a function protocol. The state machine realizes the analysis of the synchronous message and the sending of the synchronous message, the overtime mechanism of the timer, the zero clearing control of the timer, the port state condition control and the state switching. The protocol state machine keeps running after the system is started, and monitors the port of the PTP function of the current system running environment.

Optimal master clock algorithm module (BMC):

the module mainly realizes an optimal master clock algorithm according to the definition of an IEEE1588v2 protocol, and determines the master or slave state of the equipment port through the arbitration of the algorithm module according to the configuration of the port clock priority and the like and the analyzed message clock content.

Clock SERVO module (SERVO):

the module is mainly used for calculating time deviation and link delay of a master clock and a slave clock, obtaining time stamp data of each measuring point from a protocol message and time calibration data, calculating the link delay and the time deviation of the master clock and the slave clock according to a protocol formula, and synchronously correcting the time of a local clock.

FILTER module (FILTER):

the module mainly realizes a filtering algorithm by software, and filters timestamp data and a calculation result, so as to achieve the purpose of reducing errors caused by jitter when synchronizing the message Wen Yan.

Message processing Module (MSG):

the module is mainly used for executing operations such as adding and extracting timestamp data of a corresponding synchronous message interacted by the master device and the slave device, packaging the message, analyzing and the like according to a protocol state machine and a port state output by a BMC algorithm and a message format defined by a protocol.

Network layer transceiver module (NET):

the module is mainly used for realizing the message receiving and sending of a network layer, and comprises the steps of initializing a network communication interface, encapsulating and analyzing an Ethernet or UDP message, supporting the sending and receiving of the Ethernet and UDP message, and acquiring the receiving time stamp information.

Timer module (timer):

the module is mainly used for controlling the sending period of the master clock or slave clock synchronous message Sync, delay_req and pdelay_req messages, and the receiving timeout of the optimal master clock algorithm and the Sync message.

The embodiment of the present disclosure provides a time synchronization method based on PTP, and it should be noted that, in the embodiment of the present disclosure, the execution body may be a server, or may be any device having a data processing capability.

Fig. 1 is a flow chart of a PTP protocol-based time synchronization method according to an embodiment of the present disclosure, and as shown in fig. 1, the method mainly includes the following steps:

step S101, based on a preset time interval, a time stamp and a calibration domain of the synchronous message are obtained.

The device starts a ptpd module, configures related configuration parameters of PTP time synchronization, starts a PTP synchronization function, receives an annouce message by the PTP module, and decides a master-slave state of each node port according to a BMC algorithm module. And each node port sends a synchronous message in a corresponding state based on the rule of the PTP protocol according to the state and the configuration information determined by the node port.

Taking the single-step measurement mode as an example, specific configuration parameters are as follows: the time delay measuring mode is one-step; the PTP protocol packet format is 1588v2 ETH; the message sending frequency of sync (synchronous message) is 1 second, and the message sending frequency of delay_req (delay request message) is 1 second; the specific message interaction, delay and deviation calculation flow is shown in fig. 3:

according to the protocol requirements, in the clock deviation measuring stage, the master device sends a synchronous message sync, and according to the configuration setting, the sending frequency is 1 second, and the CPU timer sends a sync message every 1 second. Before Sync message is sent, the PTP protocol stack obtains the system time T sent by the CPU ₁ And T is taken ₁ And the time stamp is filled in a field of the Sync message and then is sent to the chip. When the MAC layer detects the Sync message sent by the protocol stack, the chip calculates the time difference consumed by the path from the CPU to the MAC layer of the chip, records the time difference in the first calibration domain of the correction field of the Sync message, and finally sends the time difference out.

Step S102, calculating clock deviation and link delay between the master device and the slave device according to the time stamp and the calibration domain.

After receiving the Sync message, the slave device records a receiving time stamp T2, and the PTP message processing module analyzes the T in the Sync message ₁ And its corresponding correction field calibration timestamp CF ₁₂ . The slave device can calculate the formula and the time stamp T according to the protocol clock deviation ₁ 、T ₂ And correctfiled, calculating clock offset of the slave device relative to the master device, i.e

In the Delay measurement stage, the slave device sends a delay_req message (i.e. Delay message) to the master device, and the PTP protocol stack firstly acquires the system time T3 sent by the CPU, and fills the T3 timestamp into a field of the delay_req message and then sends the field to the chip. When the chip detects the delay_req message sent by the protocol stack, the time difference consumed by the path from the CPU to the chip MAC layer is calculated, the time difference is recorded in the correction field of the delay_req message, and finally the time difference is sent out.

After receiving the delay_req message, the master device first records a receiving timestamp T4. And then analyzing a correction field (second calibration domain) time stamp in the delay_req message by a message processing Module (MSG), and sending the delay_resp message filled with the correction field time stamp to the slave device. After receiving the delay_resp Delay message, the slave device extracts the correction field (the calibration timestamp CF in the second calibration domain) corresponding to the fourth timestamp T4 and the third timestamp T3 from the delay_resp message ₃₄ (i.e., the second time difference).

At this time, the slave device acquires the time stamp data T3, T4, and CF ₃₄ Input to a clock SERVO module (SERVO), the link Delay between the master and slave devices is calculated according to the protocol, i.e

According to the steps, the time Offset Offset and the link Delay of the clocks of the master device and the slave device can be calculated, and finally, the two calculation results are respectively configured to the chip through corresponding interfaces, so that the calibration of the chip system time is realized.

And step S103, performing recursive median average filtering processing on the clock deviation and the link delay to obtain smooth timestamp data.

The time stamp data obtained from the chip MAC layer is affected by the clock jitter of the device and the network delay, so that the deviation and the delay calculated by the protocol stack time synchronization flow are caused to have errors with the actual situation. Therefore, in order to solve the problem and improve the time precision of measurement, a filter module is added to process the time stamp data before a clock servo module.

The filtering module mainly comprises two parts, namely a recursive median average filter and a Kalman filter. The recursive median average filter can be used for eliminating impulse interference of the timestamp data, the Kalman filter is used for estimating the timestamp data, errors of measured values are eliminated, and accuracy of time synchronization is further improved.

The kernel of the recursive median averaging filter is a recursive median averaging algorithm, and the algorithm is realized by setting a queue with a fixed length of N, and inputting continuous N time stamp sampling values into the queue in a recursive manner. According to the first-in first-out principle, one new data sampled each time is put into the tail of the queue, and one data at the head of the original queue is lost. And (3) arranging the N data in the queue in a descending order, removing the maximum value and the minimum value after the sorting, calculating an average value of the rest N-2 data, and finally outputting the average value as a filtering result.

The recursive median average filtering algorithm is a digital signal processing method, integrates the advantages of the median filtering algorithm and the recursive average filtering algorithm, has good filtering capability on the recurrent impulse noise, and can eliminate the sampling data deviation caused by the recurrent impulse noise. Obviously, after the maximum value and the minimum value are eliminated, the average value is calculated by the algorithm, and the obtained filtering result tends to be smoother and more reliable.

Step S104, carrying out Kalman filtering on the smooth time stamp to calculate estimated time stamp data.

The Kalman filter is realized by using a Kalman filtering algorithm, and the Kalman filtering algorithm is a recursive prediction calibration method and is divided into two processes of a prediction stage and an updating stage.

And in the prediction stage, estimating the state of the current k moment according to the posterior estimation value of the k-1 moment to obtain the prior estimation value of the k moment. And (3) a time updating equation (a prediction equation), and calculating a state variable prior estimated value and an error covariance prior estimated value at the current moment according to the state estimated value at the previous moment.

And in the updating stage, namely correcting the estimated value of the prediction stage by using the measured value at the current moment to obtain the posterior estimated value at the current moment. The kalman algorithm can be divided into a time update equation and a measurement update equation.

The measurement update equation (correction equation) is duplicated to combine the a priori estimate with the new measurement, and the construction is improved to a posterior estimate.

In the above-mentioned formula(s),and->The posterior estimates at time k and time k-1, respectively, are the optimal estimates of the Kalman filter calculation results. />The a priori state estimate representing time k is the result of time k predicted from the optimal estimate of time k-1 by the predictive equation. P (P) _k And P _k-1 The a posteriori estimated covariance at time k and time k-1 are shown, respectively. />Representing the a priori estimated covariance at time k, is the intermediate calculation result of the filtering. H represents the state variable to observation conversion matrix, z _k Representing the input observations, K _k Representing the kalman gain coefficient, and a representing the state transition matrix is a guessing model for the target state transition. R represents the measurement noise covariance. Q represents the process noise covariance.

The Kalman gain K is actually characterized by the specific gravity of the prediction error and the measurement error in the state optimal estimation process, namely the range of K is [0,1]. When k=0, that is, the system noise R is large, the state value of the system depends on the predicted value; when k=1, i.e. the system noise R is small, the state value of the system depends on the measured value. The estimation principle of the Kalman filtering algorithm is covariance P of the optimal state estimation _k The minimum, the result is made to approach the true value more and more. The data results before and after the kalman filter are shown in fig. 4.

Step S105, performing system clock time calibration according to the estimated time stamp data.

When the measured data passes through the filtering module, impulse noise appearing in the timestamp data is removed by a recursive median average algorithm in the step 1, then the acquired timestamp data is input into a filter by a Kalman filtering algorithm in the step 2, the predicted value and the measured value are fused, an estimated value is calculated, and the obtained estimated value can be used for carrying out time correction on a chip clock.

And judging the time compensation value obtained after filtering, if the time compensation value is normal, adjusting a clock, otherwise, discarding.

In summary, the invention aims at clock frequency synchronization, by adding a clock chip phase-locked loop in a hardware clock system, extracts serdes recovered clock signals from data streams sent by a main equipment port, locks the extracted recovered clock by using the clock chip phase-locked loop, and then inputs the locked clock signals to a chip PTP processing clock after frequency multiplication. By the method and the device, clock frequency synchronization of a physical layer is realized, and the slave device clock generates a PTP time stamp by using the locked system clock, so that phase synchronization of system time is realized. For clock time synchronization, a time synchronization protocol stack based on 1588v2 protocol is realized in a software layer.

The method and the device eliminate the influence on protocol stack time synchronization delay and time deviation calculation through a physical layer phase-locked loop for clock instability factors generated by clock frequency asynchronization. For the conditions of time stamp fluctuation or abrupt change caused by noise, jitter, network delay or other reasons, the interference factors can be timely found and filtered through a two-stage filtering algorithm, and abnormal calibration of chip time caused by calculating an erroneous correction value is avoided. By using the method provided by the invention, the precision and stability of PTP time synchronization can be effectively provided.

The embodiment of the present disclosure further provides a time synchronization device based on PTP protocol, as shown in fig. 2, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executable by the at least one processor to enable the at least one processor to:

based on a preset time interval, acquiring a time stamp and a calibration domain of the synchronous message;

calculating clock deviation and link delay between the master device and the slave device according to the time stamp and the calibration domain;

performing recursive median average filtering processing on the clock deviation and the link delay to obtain smooth timestamp data;

carrying out Kalman filtering on the smooth time stamp to calculate estimated time stamp data;

and carrying out time calibration on the system clock according to the estimated time stamp data.

The present specification embodiments also provide a non-volatile computer storage medium storing computer-executable instructions configured to:

based on a preset time interval, acquiring a time stamp and a calibration domain of the synchronous message;

calculating clock deviation and link delay between the master device and the slave device according to the time stamp and the calibration domain;

performing recursive median average filtering processing on the clock deviation and the link delay to obtain smooth timestamp data;

carrying out Kalman filtering on the smooth time stamp to calculate estimated time stamp data;

and carrying out time calibration on the system clock according to the estimated time stamp data.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for apparatus, devices, non-volatile computer storage medium embodiments, the description is relatively simple, as it is substantially similar to method embodiments, with reference to the section of the method embodiments being relevant.

The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

The devices and media provided in the embodiments of the present disclosure are in one-to-one correspondence with the methods, so that the devices and media also have similar beneficial technical effects as the corresponding methods, and since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media are not repeated here.

It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present description is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the specification. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

The foregoing is merely one or more embodiments of the present description and is not intended to limit the present description. Various modifications and alterations to one or more embodiments of this description will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present description, is intended to be included within the scope of the claims of the present description.

Claims (10)

1. A PTP protocol based time synchronization method, said method comprising:

based on a preset time interval, acquiring a time stamp and a calibration domain of the synchronous message;

calculating clock deviation and link delay between the master device and the slave device according to the time stamp and the calibration domain;

performing recursive median average filtering processing on the clock deviation and the link delay to obtain smooth timestamp data;

carrying out Kalman filtering on the smooth time stamp to calculate estimated time stamp data;

and carrying out time calibration on the system clock according to the estimated time stamp data.

2. The PTP protocol-based time synchronization method according to claim 1, wherein the acquiring the time stamp and the calibration field of the synchronization message based on the preset time interval includes:

the slave device acquires a synchronous message sent by a CPU timer of the master device based on the preset time interval;

and the slave equipment analyzes the synchronous message to obtain a first time stamp and a first calibration domain.

3. The PTP protocol-based time synchronization method according to claim 2, further comprising, before the acquiring the synchronization message sent by the cpu timer of the master device:

the protocol stack acquires the system time sent by the CPU and fills the system time into the synchronous message as a first time stamp;

the protocol stack sends the synchronous message filled with the first time stamp to a chip;

and the chip calculates a first time difference consumed from the cpu to the chip, and fills the time difference into a first calibration domain of the synchronous message.

4. The PTP protocol based time synchronization method according to claim 2, wherein said calculating clock skew and link delay between a master device and a slave device from said time stamp and said calibration field comprises:

acquiring a second timestamp of the synchronous message received by the slave device;

and calculating clock deviation between the master device and the slave device according to the first timestamp, the second timestamp and the first calibration domain.

5. The PTP protocol based time synchronization method of claim 4, wherein said calculating clock skew and link delay between a master device and a slave device from said time stamp and said calibration field further comprises:

the slave device sends a delay message to the master device;

the master device analyzes the delay message to obtain a third timestamp and a second calibration domain;

and calculating the link delay between the master device and the slave device according to the third timestamp and the second calibration domain.

6. The PTP protocol based time synchronization method of claim 5, further comprising, prior to said slave device sending a delay message to said master device:

the protocol stack acquires the system time sent by the CPU and fills the system time into the delay message as a third time stamp;

the protocol stack sends the delay message filled with the third time stamp to a chip;

and the chip calculates a second time difference consumed from the cpu to the chip, and fills the second time difference into a second calibration field of the delay message.

7. The PTP protocol based time synchronization method of claim 6, wherein said calculating clock skew and link delay between a master device and a slave device from said time stamp and said calibration field further comprises:

acquiring a fourth timestamp of the synchronous message received by the slave device;

and calculating the link delay between the master device and the slave device according to the third timestamp, the fourth timestamp and the second calibration domain.

8. The PTP protocol based time synchronization method of claim 7, wherein performing system clock time calibration based on the estimated time stamp data comprises:

calculating a filtered time compensation value according to the filtered time stamp data;

and if the time compensation value is normal, the time compensation value is used for adjusting a clock, otherwise, the time compensation value is discarded.

9. A PTP protocol based time synchronization device, said device comprising:

at least one processor; the method comprises the steps of,

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to:

based on a preset time interval, acquiring a time stamp and a calibration domain of the synchronous message;

calculating clock deviation and link delay between the master device and the slave device according to the time stamp and the calibration domain;

performing recursive median average filtering processing on the clock deviation and the link delay to obtain smooth timestamp data;

carrying out Kalman filtering on the smooth time stamp to calculate estimated time stamp data;

and carrying out time calibration on the system clock according to the estimated time stamp data.

10. A non-transitory computer storage medium storing computer-executable instructions, the computer-executable instructions configured to:

based on a preset time interval, acquiring a time stamp and a calibration domain of the synchronous message;

calculating clock deviation and link delay between the master device and the slave device according to the time stamp and the calibration domain;

performing recursive median average filtering processing on the clock deviation and the link delay to obtain smooth timestamp data;

carrying out Kalman filtering on the smooth time stamp to calculate estimated time stamp data;

and carrying out time calibration on the system clock according to the estimated time stamp data.