CN116647246A

CN116647246A - Analog front-end circuit and communication system including the same

Info

Publication number: CN116647246A
Application number: CN202310123802.0A
Authority: CN
Inventors: 阿利·法兹利·叶克纳米; 安普·P·若泽
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-02-24
Filing date: 2023-02-16
Publication date: 2023-08-25

Abstract

An Analog Front End (AFE) circuit and a communication system including the same are disclosed. The AFE circuit includes: a Continuous Time Linear Equalizer (CTLE) circuit; a transimpedance amplifier (TIA) connected to the CTLE circuit; and a feedback circuit comprising: a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source; a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and a first tunable resistor coupled between the first node and the second node, wherein: a first input of the feedback circuit is connected to a first output of the TIA; a second input of the feedback circuit is connected to a second output of the TIA; a second output of the feedback circuit is connected to a first input of the TIA; and a first output of the feedback circuit is connected to a second input of the TIA.

Description

Analog front-end circuit and communication system including the same

Cross Reference to Related Applications

The present application claims priority and benefit from U.S. provisional patent application No. 63/313,383 filed 24 at 2 months 2022 and U.S. non-provisional patent application No. 17/725,392 filed 20 at 4 months 2022, the entire contents of which are incorporated herein by reference.

Technical Field

The present application relates generally to Continuous Time Linear Equalization (CTLE) feedback circuits, and more particularly to CTLE feedback for adjustable Direct Current (DC) gain and mid-band correction.

Background

High-speed serial links, commonly referred to as serializers/deserializers (SerDes), are widely used as interfaces in electronic devices such as electronic displays. As more and more data is sent over such high speed serial links (e.g., due to increased display resolution, color depth, and/or refresh rate), the interface speed increases accordingly. As speed increases, so does the power and silicon area of the communication receiver of the interface.

The above information in the background section is only for enhancement of understanding of the background of the technology and is therefore not to be construed as an admission that the prior art exists or is relevant.

Disclosure of Invention

This summary is provided to introduce a selection of features and concepts of the embodiments of the disclosure that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. One or more of the described features may be combined with one or more other described features to provide a workable apparatus.

Aspects of example embodiments of the present disclosure relate to Continuous Time Linear Equalization (CTLE) feedback for adjustable DC gain and mid-band correction.

In one or more embodiments, an Analog Front End (AFE) circuit includes: a Continuous Time Linear Equalizer (CTLE) circuit; a transimpedance amplifier (TIA) connected to the CTLE circuit; and a feedback circuit comprising: a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source; a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and a first tunable resistor coupled between the first node and the second node, wherein: a first input of the feedback circuit is connected to a first output of the TIA; a second input of the feedback circuit is connected to a second output of the TIA; a second output of the feedback circuit is connected to a first input of the TIA; and a first output of the feedback circuit is connected to a second input of the TIA.

In one or more embodiments, the first input of the feedback circuit is connected to the gate terminal of the first transistor through a second adjustable resistor; a second input of the feedback circuit is connected to the gate terminal of the second transistor through a third adjustable resistor; the first current source is connected between the first node and ground; and a second current source is connected between the second node and ground.

In one or more embodiments, the feedback circuit further comprises: a first capacitor connected between a gate terminal of the first transistor and ground; and a second capacitor connected between the gate terminal of the second transistor and ground, wherein the second tunable resistor, the third tunable resistor, the first capacitor, and the second capacitor are configured to reduce a feedback factor of the AFE circuit at high frequencies to enhance the maximum peak value.

In one or more embodiments, the first adjustable resistor is between 500 ohms and 3K ohms, and the second and third adjustable resistors are between 500 ohms and 4K ohms. In one or more embodiments, the second and third tunable resistors are configured to equalize a wideband frequency response of the AFE circuit. In one or more embodiments, the second and third tunable resistors are configured to adjust a mid-band frequency response of the AFE circuit by adjusting a zero position in the frequency response of the AFE circuit.

In one or more embodiments, the first adjustable resistor is configured to adjust a DC gain of the AFE circuit. In one or more embodiments, the second input of the TIA is connected to the first output of the CTLE circuit; a first input of the TIA is connected to a second output of the CTLE circuit; the first output of the TIA is connected to the first input of the TIA through a fourth adjustable resistor; and a second output of the TIA is connected to a second input of the TIA through a fifth adjustable resistor.

In one or more embodiments, the fourth and fifth adjustable resistors are configured to achieve the same gain change over all frequencies; a third capacitor connected between the first output of the TIA and ground; and a fourth capacitor is connected between the second output of the TIA and ground.

In one or more embodiments, the CTLE circuit includes: a third transistor connected between the first output of the CTLE circuit and a third node connected to a third current source; a fourth transistor connected between the second output of the CTLE circuit and a fourth node connected to a fourth current source; an adjustable negative feedback resistor coupled between the third node and the fourth node; a negative feedback capacitor coupled between the third node and the fourth node, wherein: a gate terminal of the third transistor and a gate terminal of the fourth transistor are connected to the passive CTLE circuit; a first output of the CTLE circuit is connected to a first output of the feedback circuit and a second input of the TIA; and a second output of the CTLE circuit is connected to a second output of the feedback circuit and a first input of the TIA.

In one or more embodiments, a third current source is connected between the third node and ground; and a fourth current source is connected between the fourth node and ground. In one or more embodiments, the gain and boost of the AFE circuit is controlled by adjusting an adjustable negative feedback resistor and a negative feedback capacitor. In one or more embodiments, the adjustable negative feedback resistor is configured to adjust a low frequency DC gain of the AFE circuit by adjusting a zero position in a frequency response of the AFE circuit, and wherein the negative feedback capacitor is configured to adjust a high frequency gain of the AFE circuit.

In one or more embodiments, the AFE circuit further comprises: a fifth transistor connected between the power supply and the first output of the CTLE circuit; a sixth transistor connected between the power supply and a second output of the CTLE circuit; and a Common Mode Feedback (CMFB) circuit connected to gate terminals of the fifth transistor and the sixth transistor, wherein: an output terminal of the CMFB circuit is connected to gate terminals of the fifth transistor and the sixth transistor, and a first input terminal of the CMFB circuit is connected to a first output of the CTLE circuit; a second input terminal of the CMFB circuit is connected to a second output of the CTLE circuit; and a third input terminal of the CMFB circuit is connected to the reference voltage.

In one or more embodiments, an Analog Front End (AFE) circuit includes: a transimpedance amplifier (TIA); and a feedback circuit comprising: a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source; a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and a first tunable resistor coupled between the first node and the second node, wherein: a first input of the feedback circuit is connected to a first output of the TIA; a second input of the feedback circuit is connected to a second output of the TIA; a second output of the feedback circuit is connected to a first input of the TIA; a first output of the feedback circuit is connected to a second input of the TIA; a first input of the feedback circuit is connected to the gate terminal of the first transistor through a second adjustable resistor; a second input of the feedback circuit is connected to the gate terminal of the second transistor through a third adjustable resistor; the first output of the TIA is connected to the first input of the TIA through a fourth adjustable resistor; and a second output of the TIA is connected to a second input of the TIA through a fifth adjustable resistor.

In one or more embodiments, the feedback circuit further comprises: a first capacitor connected between a gate terminal of the first transistor and ground; and a second capacitor connected between the gate terminal of the second transistor and ground, wherein: the first current source is connected between the first node and ground; the second current source is connected between the second node and ground; and the second tunable resistor, the third tunable resistor, the first capacitor, and the second capacitor are configured to reduce a feedback factor of the AFE circuit at high frequencies to enhance the maximum peak.

In one or more embodiments, the AFE circuit further comprises a Continuous Time Linear Equalizer (CTLE) circuit, the CTLE circuit comprising: a third transistor connected between the first output of the CTLE circuit and a third node connected to a third current source; a fourth transistor connected between the second output of the CTLE circuit and a fourth node connected to a fourth current source; an adjustable negative feedback resistor coupled between the third node and the fourth node; a negative feedback capacitor coupled between the third node and the fourth node, wherein: a gate terminal of the third transistor and a gate terminal of the fourth transistor are connected to the passive CTLE circuit; a first output of the CTLE circuit is connected to a first output of the feedback circuit and a second input of the TIA; a second output of the CTLE circuit is connected to a second output of the feedback circuit and a first input of the TIA; the third current source is connected between the third node and ground; and a fourth current source is connected between the fourth node and ground. In one or more embodiments, a third capacitor is connected between the first output of the TIA and ground; and a fourth capacitor is connected between the second output of the TIA and ground.

In one or more embodiments, the AFE circuit further comprises: a fifth transistor connected between the power supply and the first output of the CTLE circuit; a sixth transistor connected between the power supply and a second output of the CTLE circuit; and a Common Mode Feedback (CMFB) circuit connected to gate terminals of the fifth transistor and the six transistor, wherein: an output terminal of the CMFB circuit is connected to gate terminals of the fifth transistor and the sixth transistor, and a first input terminal of the CMFB circuit is connected to a first output of the CTLE circuit; a second input terminal of the CMFB circuit is connected to a second output of the CTLE circuit; and a third input terminal of the CMFB circuit is connected to the reference voltage.

In one or more embodiments, a communication system includes an Analog Front End (AFE) circuit. The AFE circuit includes: a Continuous Time Linear Equalizer (CTLE) circuit; a transimpedance amplifier (TIA) connected at the output of the CTLE circuit; and a feedback circuit comprising: a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source; a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and a first tunable resistor coupled between the first node and the second node, wherein: a first input of the feedback circuit is connected to a first output of the TIA; a second input of the feedback circuit is connected to a second output of the TIA; a second output of the feedback circuit is connected to a first input of the TIA; a first output of the feedback circuit is connected to a second input of the TIA; a first input of the feedback circuit is connected to the gate terminal of the first transistor through a second adjustable resistor; and a second input of the feedback circuit is connected to the gate terminal of the second transistor through a third adjustable resistor.

Drawings

These and other features of some example embodiments of the present disclosure will be appreciated and understood with reference to the specification, claims, and drawings.

Fig. 1 shows a simple block diagram of a high-speed communication system.

Fig. 2 shows a transimpedance amplifier (TIA) based Analog Front End (AFE) circuit.

Fig. 3A and 3B illustrate the frequency response of the TIA-based AFE circuit of fig. 2.

Fig. 4 shows a TIA-based AFE circuit with feedback.

Fig. 5A and 5B illustrate the frequency response of the TIA-based AFE circuit of fig. 4 with feedback.

Aspects, features, and effects of embodiments of the present disclosure are best understood by referring to the following detailed description. Like reference numerals refer to like elements throughout the drawings and the written description unless otherwise specified, and thus, a description thereof will not be repeated. In the drawings, the relative sizes of elements, layers and regions may be exaggerated for clarity.

Detailed Description

The detailed description set forth below in connection with the appended drawings is considered a description of some example embodiments of a system for continuous-time linear equalization (CTLE) feedback for adjustable Direct Current (DC) gain and mid-band correction provided in accordance with the present disclosure, and is not intended to represent the only form in which the present disclosure may be constructed or utilized. The description sets forth the features of the present disclosure in connection with the illustrated embodiments. However, it is to be understood that the same or equivalent functions and structures may be accomplished by different embodiments that are also intended to be encompassed within the scope of the disclosure. Like reference numerals are intended to indicate like elements or features, as indicated elsewhere herein.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed herein could be termed a second element, component, region, layer or section without departing from the scope of the present disclosure.

Spatially relative terms, such as "under … …," "under … …," "lower," "under … …," "over … …," and "upper" may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below," "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below … …" and "below … …" may encompass both an orientation of above and below. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the terms "substantially," "about," and similar terms are used as approximation terms and not as degree terms, and are intended to illustrate the inherent deviations of measured or calculated values that would be recognized by one of ordinary skill in the art.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When a statement such as "at least one of … …" follows a list of elements, the entire list of elements is modified and the individual elements of the list are not modified. Furthermore, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure. In addition, the term "exemplary" is intended to refer to an example or illustration. As used herein, the term "use" and variants thereof may be considered synonymous with the term "utilization" and variants thereof, respectively.

It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, connected to, coupled to or directly adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present.

Any numerical range recited herein is intended to include all sub-ranges subsumed with the same numerical precision within the recited range. For example, a range of "1.0 to 10.0" is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, subranges having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as for example 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited herein is intended to include all higher numerical limitations subsumed therein.

In some embodiments, one or more outputs of the different embodiments of the methods and systems of the present disclosure may be sent to an electronic device coupled to or having a display device for displaying the one or more outputs of the different embodiments of the methods and systems of the present disclosure or information regarding the one or more outputs.

The electronic or electrical devices and/or any other related devices or components described herein according to embodiments of the present disclosure may be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one Integrated Circuit (IC) chip or on separate IC chips. In addition, various components of these devices may be implemented on a flexible printed circuit film, a Tape Carrier Package (TCP), a Printed Circuit Board (PCB), or formed on one substrate. Further, the various components of these devices may be processes or threads running on one or more processors in one or more computing devices that execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory that may be implemented in a computing device using standard memory devices such as Random Access Memory (RAM) for example. The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM or flash drive. In addition, those skilled in the art will recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or that the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the present disclosure.

High-speed serial links, commonly referred to as serializers/deserializers (SerDes), are widely used as interfaces in electronic devices such as electronic displays. As more and more data is sent over such high speed serial links (e.g., due to increased display resolution, color depth, and/or refresh rate), the interface speed increases accordingly. As speed increases, so does the power and silicon area of the communication receiver of the interface. High speed SerDes may encounter many challenges in terms of high speed operation, equalization methods, power consumption, area, etc. For example, for SerDes applications with hundreds of lines integrated in an Integrated Circuit (IC), power consumption may be an important factor in maintaining high performance.

High-speed digital (HSD) ICs may be used in SerDes circuits defined at high data rates with lossy channels between the transmitter and the receiver. The data received in such SerDes circuits may be distorted and may need to be reconstructed (e.g., equalized) prior to use.

Decision Feedback Equalizer (DFE) circuits may be used in high-speed wireless data communication systems for the purpose of recovering signals distorted during propagation through lossy and dispersive channels.

For example, fig. 1 shows a simple block diagram of a high-speed communication system. The communication system of fig. 1 comprises a transmitter 10, a receiver 20 and a channel 30 for data communication between the transmitter 10 and the receiver 20. The receiver 20 includes an Analog Front End (AFE) 21, a DFE 22, and receiver logic 23.

The Analog Front End (AFE) (e.g., AFE 21) circuit may be a single stage circuit and incorporate both Variable Gain Amplification (VGA) and Linear Equalizer (LEQ) functions therein. The buffer in the AFE drives a DFE (e.g., DFE 22) input stage, and the buffer output is controlled by common mode feedback to control the common mode for the DFE input stage. AFE can play an important role not only in terms of equalization but also in terms of robustness and power. This can be achieved by a simple and minimum of constructional stages. In the case of high speed applications (e.g., 28Gbps or higher), increasing the bias current using a differential pair circuit may not be useful after a particular optimal bias because the output impedance of the differential pair may be degraded by the increased bias current. Thus, even though the transconductance of the differential pair will increase with higher currents, the AFE may not achieve sufficient gain. Bandwidth is also degraded because of the large device size required at low supply voltages.

A high-speed transimpedance amplifier (TIA) circuit may be desirable in high-speed applications to improve high-frequency bandwidth. One or more embodiments of the present disclosure include a single stage TIA-based LEQ with feedback. The AFE may drive a DFE input stage where there are several data and error DFE slicer circuits connected. The TIA decouples the reload capacitance and improves the high frequency response.

Fig. 2 shows a TIA-based AFE circuit. For example, fig. 2 shows a TIA-based AFE circuit 100 (hereinafter, also referred to as an AFE circuit). The AFE circuit 100 of fig. 2 includes: a Common Mode Feedback (CMFB) circuit 110; a passive Continuous Time Linear Equalizer (CTLE) circuit 120; an input stage differential pair 130 (hereinafter, also referred to as a differential pair) including two n-type metal oxide semiconductor (NMOS) transistors 131 and 132; negative feedback resistor (R) _S ) 133 (e.g., variable resistor or adjustable resistor) and a negative feedback capacitor (C _S ) 134; two current sources (I) ₁ ) 135 and 136; two p-type metal oxide semiconductor (PMOS) transistors 141 and 142; a high speed transimpedance amplifier (TIA) 150; two variable (or adjustable) feedback resistors (R _F ) 151 and 152; two capacitors (C _L ) 161 and 162.

In one or more embodiments, the differential pair 130, the passive CTLE circuit 120, the degeneration resistor (R _S ) 133 (e.g., a variable resistor), a negative feedback capacitor (C _S ) 134, a first current source (I ₁ ) 135 and a second current source (I ₁ ) 136 may together be referred to as CTLE circuitry 170.

CTLE circuits can be used to equalize data received at the receiver end of the SerDes circuits. CTLE is a linear filter that may be located at the receiver for attenuating low frequency signal components, amplifying components around the nyquist frequency, and filtering out higher frequencies. CTLE gain can be adjusted to optimize the ratio of low frequency attenuation to high frequency amplification.

The two input terminals of the CMFB circuit 110 can be connected to the two output terminals 137 and 138 of the CTLE circuit 170. Third input of CMFB circuit 110The terminal can receive a reference voltage V _REF . In one or more embodiments, to keep the inverter circuits in the TIA 150 properly biased in process, voltage, and temperature (PVT), the reference voltage V of the CMFB circuit 110 _REF May be generated by a replication bias block. In one or more embodiments, the replica bias block may be a half circuit of the TIA 150, and the input and output may be shorted to generate a reference bias voltage that is optimal over PVT variations. In one or more embodiments, the replica bias block may include a PMOS transistor and an NMOS transistor connected in series between a power supply and a current source. The current source may be further connected to ground. For example, a PMOS transistor may be connected between a power supply and a first electrode of an NMOS transistor, and an NMOS transistor may be connected between a second electrode of the PMOS transistor and a current source. The current source may be connected between the second electrode of the NMOS transistor and ground. The gate electrodes of the PMOS transistor and the NMOS transistor are connected together. In the copy bias block, the input and output may be shorted.

An output terminal of the CMFB circuit 110 can be connected at gate terminals of the two PMOS transistors 141 and 142. PMOS transistors 141 and 142 may be connected between the power supply 140 and output terminals 137 and 138 of CTLE circuit 170. For example, PMOS transistor 141 may be connected between power supply 140 and first output terminal 137 of CTLE circuit 170, and PMOS transistor 142 may be connected between power supply 140 and second output terminal 138 of CTLE circuit 170.

The differential pair 130 includes a first NMOS transistor 131 and a second NMOS transistor 132. A first terminal of the first NMOS transistor 131 may be connected to the first output terminal 137 of the CTLE circuit 170, and a second terminal of the first NMOS transistor 131 may be connected to a first current source (I ₁ ) 135. A first terminal of the second NMOS transistor 132 may be connected to the second output terminal 138 of the CTLE circuit 170, and a second terminal of the second NMOS transistor 132 may be connected to a second current source (I ₁ ) 136. The gate terminals of the NMOS transistors 131 and 132 of the differential pair 130 may be connected to the output terminal of the passive CTLE circuit 120. In one or more embodiments, g _m1 Representing the transconductance of the input stage differential pair 130.

Negative feedback resistor (R) _S ) 133 (e.g., variable resistor or adjustable resistor) and a negative feedback capacitor (C _S ) 134 may be connected between the second terminals of NMOS transistors 131 and 132 of differential pair 130. In one or more embodiments, the gain and boost of AFE circuit 100 can be controlled by adjusting the negative feedback resistor (R _S ) 133 and negative feedback capacitor (C) _S ) 134.

First current source (I ₁ ) 135 may be connected between the second terminal of the first NMOS transistor 131 and ground, and a second current source (I ₁ ) 136 may be connected between the second terminal of the second NMOS transistor 132 and ground.

The output current from the differential pair 130 is fed to the TIA 150. For example, a first input terminal (e.g., a non-inverting input terminal) of the TIA 150 may be connected to the second output terminal 138 of the CTLE circuit 170, and a second input terminal (e.g., an inverting input terminal) of the TIA 150 may be connected to the first output terminal 137 of the CTLE circuit 170. First variable feedback resistor (R _F ) 151 may be connected between a first input terminal (e.g., a non-inverting input terminal) and a first output terminal (e.g., an inverting output terminal) of the TIA 150, and a second variable feedback resistor (R _F ) 152 may be connected between a second input terminal (e.g., an inverting input terminal) and a second output terminal (e.g., a non-inverting output terminal) of TIA 150. First capacitor (C) _L ) 161 may be connected between a first output terminal (e.g., an inverting output terminal) of the TIA 150 and ground, and a second capacitor (C _L ) 162 may be connected between a second output terminal (e.g., a non-inverting output terminal) of TIA 150 and ground. In one or more embodiments, the TIA 150 may be configured by a single stage inverter-based circuit and tail current source to maintain a DC bias.

The TIA-based topology decouples the overload capacitance from the subsequent blocks (e.g., limiters or DFEs), thus improving the high frequency response, and combines both Linear Equalization (LEQ) and Variable Gain Amplification (VGA) functions.

In one or more embodiments, a negative feedback resistor (R _S ) 133 can adjust the low frequency DC gain of the TIA-based AFE circuit 100. First variable feedback resistor (R _F ) 151 and a second variable feedback resistor (R _F ) 152 may implement VGA functionality (e.g., to implement the same gain change over all frequencies).

Fig. 3A and 3B illustrate the frequency response of the TIA-based AFE circuit 100 of fig. 2.

For example, as shown in FIG. 3A, in one or more embodiments, a negative feedback resistor (R _S ) 133 may adjust the DC gain of AFE circuit 100. For example, in one or more embodiments, a negative feedback resistor (R _S ) 133 may change the zero position in the frequency response.

For example, in one or more embodiments, the zero frequency may be represented as:wherein R is _S Is the value of a negative feedback resistor, and C _S Is the value of the negative feedback capacitor. Because of the negative feedback resistor (R _S ) 133 is a variable resistor, so by adjusting the negative feedback resistor (R _S ) 133, the location of zeros in the frequency response of AFE circuit 100 may be changed.

Furthermore, as shown in fig. 3B, in one or more embodiments, the high frequency gain (e.g., maximum peak) of AFE circuit 100 may be achieved by adjusting a variable negative feedback capacitor (C _S ) 134. However, such adjustment of the high frequency gain may also change the high frequency response.

For example, in one or more embodiments, the pole frequency may be represented asWherein C is _S Is the value of a negative feedback capacitor, and g _m1 Representing the transconductance of the input stage differential pair 130. In the negative feedback capacitor (C) _S ) 134 is a variable capacitor, the pole frequency can be controlled by adjusting the negative feedback capacitor (C _S ) 134. By making the transconductance of the input stage differential pair 130 high, the pole frequency shifts higher and the Q factor becomes higher, which in turn improves the high frequency row Is the following.

In one or more embodiments, the pole frequency may correspond to a corner frequency at which the slope of the magnitude curve decreases by 20 dB/frequency-decade, and the zero frequency corresponds to a corner frequency at which the slope increases by 20 dB/frequency-decade.

However, the TIA-based AFE circuit 100 of fig. 2 may not allow for mid-band gain adjustment.

Fig. 4 shows a TIA-based AFE circuit with feedback. For example, fig. 4 shows a TIA-based AFE circuit 300 with feedback, where a feedback circuit 310 is incorporated into the AFE circuit 100 of fig. 2 to allow for increased CTLE control over various types of channels, and to change the mid-band response by zero position adjustment, while keeping the high frequency region of operation unchanged.

For example, in the embodiment of fig. 4, the feedback circuit (or feedback stage) 310 is connected between an input terminal of the TIA150 and an output terminal of the TIA 150.

For example, the input terminals 381 and 382 of the feedback circuit 310 may be connected to the first and second output terminals of the TIA150, respectively. For example, a first input terminal 381 of the feedback circuit 310 may be connected to a first output terminal (e.g., an inverting output terminal) of the TIA150, and a second input terminal 382 of the feedback circuit 310 may be connected to a second output terminal (e.g., a non-inverting output terminal) of the TIA 150. The first output terminal 371 of the feedback circuit 310 may be connected to a second input terminal (e.g., an inverting input terminal) of the TIA150 and a first output terminal 137 of the CTLE circuit 170. The second output terminal 372 of the feedback circuit 310 may be connected to a first input terminal (e.g., a non-inverting input terminal) of the TIA150 and a second output terminal 138 of the CTLE circuit 170.

The feedback circuit 310 includes a feedback differential pair 320, a feedback negative feedback variable resistor (R _S2 ) 330 (e.g., an adjustable resistor), a first feedback current source (I _FB ) 341, a second feedback current source (I _FB ) 342, first feedback variable resistor (R _FB ) 351 (e.g., an adjustable resistor), a second feedback variable resistor (R _FB ) 352 (e.g., an adjustable resistor), a first feedback capacitor (C _FB ) 361 and a second feedback capacitor (C _FB )362。

The feedback differential pair 320 includes a third NMOS transistor 321 and a fourth NMOS transistor 322. A first terminal of the third NMOS transistor 321 may be connected to the first output terminal 371 of the feedback circuit 310, and a second terminal of the third NMOS transistor 321 may be connected to a first feedback current source (I _FB ) 341. A gate terminal of the third NMOS transistor 321 may be connected to a first input terminal 381 of the feedback circuit 310, the first input terminal 381 of the feedback circuit 310 being connected to a first output terminal (e.g., an inverting output terminal) of the TIA 150. The gate terminal of the third NMOS transistor 321 of the feedback circuit 310 may be connected via a first feedback variable resistor (R _FB ) 351 are connected to a first input terminal 381 of the feedback circuit 310. For example, a first feedback variable resistor (R _FB ) 351 may be connected between the gate terminal of the third NMOS transistor 321 and the first input terminal 381 of the feedback circuit 310. In one or more embodiments, a feedback variable resistor (R _FB ) The values (e.g., 351 and 352) may be 500 ohms to 4K ohms.

A first terminal of the fourth NMOS transistor 322 may be connected to the second output terminal 372 of the feedback circuit 310, and a second terminal of the fourth NMOS transistor 322 may be connected to a second feedback current source (I _FB ) 342. The gate terminal of the fourth NMOS transistor 322 may be connected to the second input terminal 382 of the feedback circuit 310, the second input terminal 382 of the feedback circuit 310 being connected to a second output terminal (e.g., a non-inverting output terminal) of the TIA 150. The gate terminal of the fourth NMOS transistor 322 may be connected via a second feedback variable resistor (R _FB ) 352 are connected to the second input terminal 382 of the feedback circuit 310. For example, a second feedback variable resistor (R _FB ) 352 may be connected between the gate terminal of the fourth NMOS transistor 322 and the second input terminal 382 of the feedback circuit 310.

In one or more embodiments, g _mFB Representing the transconductance of the feedback differential pair 320.

First feedback capacitor (C) _FB ) 361 may be connected between the gate terminal of the third NMOS transistor 321 and ground, and a second feedback capacitor (C _FB ) 362 may be connected to the gate terminal of the fourth NMOS transistor 322Between sub and ground.

Feedback negative feedback variable resistor (R) _S2 ) 330 may be connected between the second terminals of NMOS transistors 321 and 322 of feedback differential pair 320. In one or more embodiments, a feedback negative feedback variable resistor (R _S2 ) The value of 330 may be 500 ohms to 3K ohms.

A first feedback current source (I _FB ) 341 may be connected between the second terminal of the third NMOS transistor 321 and ground, and a second feedback current source (I _FB ) 342 may be connected between the second terminal of the fourth NMOS transistor 322 and ground.

The feedback differential pair 320 of the feedback circuit 310 is coupled via a first feedback variable resistor (R _FB ) 351 and a second feedback variable resistor (R _FB ) 352 receives the gate bias from the output terminal of the TIA 150 and the output current from the feedback differential pair 320 is fed to the input terminal of the TIA 150 via the output terminals 371 and 372 of the feedback circuit 310.

The feedback circuit 310 of fig. 4 may also be referred to as a CTLE feedback circuit (or stage).

Fig. 5A and 5B illustrate the frequency response of the TIA-based AFE circuit 300 of fig. 4 with feedback.

The TIA-based AFE circuit 300 with feedback may maintain all of the beneficial features of the TIA-based AFE circuit 100 of fig. 2 while providing additional unique control for various types of channels. For example, when the feedback variable resistor (R _FB ) When used as control knobs (e.g., 351 and 352), can allow wideband frequency equalization. For example, in one or more embodiments, as shown in fig. 5A, the feedback variable resistor (R _FB ) The values of (e.g., 351 and 352), the mid-band frequency response of the TIA-based AFE circuit 300 with feedback may be changed (or adjusted) by a zero adjustment while keeping the high frequency region of operation unchanged.

In addition, in addition to a negative feedback resistor (R _S ) In addition to 133, as shown in fig. 5B, a feedback negative feedback variable resistor (R _S2 ) 330 may also be used for DC gain adjustment of the TIA-based AFE circuit 300 with feedback while maintaining the high frequency response unchanged.

In one or more embodiments, adding feedback circuit 310 to TIA-based AFE circuit 300 with feedback maintains all the useful features of conventional CTLE, as well as providing two key additional control knobs for mid-band frequency response correction and DC gain trimming of TIA-based AFE circuit 300 with feedback (e.g., feedback negative feedback variable resistor (R _S2 ) 330 and feedback variable resistor (R) _FB ) 351 and 352), thereby increasing CTLE control over various types of channels with small power/area overhead.

As shown in fig. 4, the feedback circuit 310 of the TIA-based AFE circuit 300 with feedback includes: low-pass RC filter comprising a feedback variable resistor (R _FB ) (e.g., 351 and 352) and a feedback capacitor (C) _FB ) (e.g., 361 and 362); and a Current Mode Logic (CML) gain circuit (or stage) comprising a feedback differential pair 320 and a feedback negative feedback variable resistor (R _S2 ) 330. At low frequencies, the feedback circuit 310 operates like a wideband amplifier. At high frequencies, the transconductance g of the input stage differential pair 130 in the forward path _m1 Overwhelming the much weaker transconductance g from the feedback differential pair 320 _mFB And the high frequency gain approximates the gain of the forward path including TIA 150. In one or more embodiments, a feedback variable resistor (R _FB ) (e.g., 351 and 352) and a feedback capacitor (C) _FB ) The low pass RC filters (e.g., 361 and 362) reduce the feedback factor at high frequencies, further enhancing the maximum peak. Due to g _mFB <g _m1 And/5, thus includes a feedback differential pair 320 and a feedback negative feedback variable resistor (R _S2 ) The CML gain stage of 330 incurs less power and area overhead.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The embodiments described herein are examples only. Those skilled in the art will recognize various alternative embodiments from those specifically disclosed. Those alternative embodiments are also intended to be within the scope of this disclosure. As such, the embodiments are limited only by the claims and their equivalents.

Claims

1. An analog front end circuit comprising:

a continuous time linear equalizer circuit;

a transimpedance amplifier connected to the continuous-time linear equalizer circuit; and

a feedback circuit, comprising:

a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source;

a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and

a first tunable resistor coupled between the first node and the second node, wherein:

a first input of the feedback circuit is connected to a first output of the transimpedance amplifier;

a second input of the feedback circuit is connected to a second output of the transimpedance amplifier;

the second output of the feedback circuit is connected to a first input of the transimpedance amplifier; and is also provided with

The first output of the feedback circuit is connected to a second input of the transimpedance amplifier.

2. The analog front-end circuit of claim 1, wherein:

the first input of the feedback circuit is connected to a gate terminal of the first transistor through a second adjustable resistor;

the second input of the feedback circuit is connected to the gate terminal of the second transistor through a third adjustable resistor;

the first current source is connected between the first node and ground; and is also provided with

The second current source is connected between the second node and the ground.

3. The analog front end circuit of claim 2, wherein the feedback circuit further comprises:

a first capacitor connected between the gate terminal of the first transistor and the ground; and

a second capacitor connected between the gate terminal of the second transistor and the ground,

wherein the second adjustable resistor, the third adjustable resistor, the first capacitor and the second capacitor are configured to reduce a feedback factor of the analog front-end circuit at high frequencies to enhance a maximum peak.

4. The analog front end circuit of claim 2, wherein the first adjustable resistor is between 500 ohms and 3K ohms and the second and third adjustable resistors are between 500 ohms and 4K ohms.

5. The analog front-end circuit of claim 2, wherein the second and third adjustable resistors are configured to equalize a wideband frequency response of the analog front-end circuit.

6. The analog front-end circuit of claim 2, wherein the second and third adjustable resistors are configured to adjust a mid-band frequency response of the analog front-end circuit by adjusting a zero position in the frequency response of the analog front-end circuit.

7. The analog front-end circuit of any of claims 2 to 6, wherein the first adjustable resistor is configured to adjust a DC gain of the analog front-end circuit.

8. The analog front-end circuit of claim 1, wherein:

the second input of the transimpedance amplifier is connected to a first output of the continuous-time linear equalizer circuit;

the first input of the transimpedance amplifier is connected to a second output of the continuous-time linear equalizer circuit;

the first output of the transimpedance amplifier is connected to the first input of the transimpedance amplifier through a second adjustable resistor; and is also provided with

The second output of the transimpedance amplifier is connected to the second input of the transimpedance amplifier through a third adjustable resistor.

9. The analog front end circuit of claim 8, wherein:

the second and third tunable resistors are configured to achieve the same gain change over all frequencies;

a first capacitor connected between the first output of the transimpedance amplifier and ground; and is also provided with

A second capacitor is connected between the second output of the transimpedance amplifier and the ground.

10. The analog front-end circuit of claim 1, wherein the continuous-time linear equalizer circuit comprises:

a third transistor connected between a first output of the continuous time linear equalizer circuit and a third node connected to a third current source;

a fourth transistor connected between a second output of the continuous-time linear equalizer circuit and a fourth node connected to a fourth current source;

an adjustable negative feedback resistor coupled between the third node and the fourth node;

a negative feedback capacitor coupled between the third node and the fourth node, wherein:

a gate terminal of the third transistor and a gate terminal of the fourth transistor are connected to a passive continuous time linear equalizer circuit;

The first output of the continuous-time linear equalizer circuit is connected to the first output of the feedback circuit and the second input of the transimpedance amplifier; and is also provided with

The second output of the continuous-time linear equalizer circuit is connected to the second output of the feedback circuit and the first input of the transimpedance amplifier.

11. The analog front end circuit of claim 10, wherein:

the third current source is connected between the third node and ground; and is also provided with

The fourth current source is connected between the fourth node and the ground.

12. The analog front end circuit of claim 10, wherein gain and boost of the analog front end circuit are controlled by adjusting the adjustable degeneration resistor and the degeneration capacitor.

13. The analog front end circuit of claim 10, wherein the adjustable negative feedback resistor is configured to adjust a low frequency DC gain of the analog front end circuit by adjusting a zero position in a frequency response of the analog front end circuit, and

wherein the negative feedback capacitor is configured to adjust a high frequency gain of the analog front end circuit.

14. The analog front end circuit of any of claims 10 to 13, further comprising:

a fifth transistor connected between a power supply and the first output of the continuous-time linear equalizer circuit;

a sixth transistor connected between the power supply and the second output of the continuous time linear equalizer circuit; and

a common mode feedback circuit connected to gate terminals of the fifth transistor and the six transistors, wherein:

an output terminal of the common mode feedback circuit is connected to the gate terminals of the fifth transistor and the sixth transistor,

a first input terminal of the common mode feedback circuit is connected to the first output of the continuous time linear equalizer circuit;

a second input terminal of the common mode feedback circuit is connected to the second output of the continuous time linear equalizer circuit; and is also provided with

A third input terminal of the common mode feedback circuit is connected to a reference voltage.

15. An analog front end circuit comprising:

a transimpedance amplifier; and

a feedback circuit, comprising:

the second output of the feedback circuit is connected to a first input of the transimpedance amplifier;

the first output of the feedback circuit is connected to a second input of the transimpedance amplifier;

the first output of the transimpedance amplifier is connected to the first input of the transimpedance amplifier through a fourth adjustable resistor; and is also provided with

The second output of the transimpedance amplifier is connected to the second input of the transimpedance amplifier through a fifth adjustable resistor.

16. The analog front end circuit of claim 15, wherein the feedback circuit further comprises:

a first capacitor connected between the gate terminal of the first transistor and ground; and

a second capacitor connected between the gate terminal of the second transistor and the ground, wherein:

the first current source is connected between the first node and the ground;

the second current source is connected between the second node and the ground; and is also provided with

The second adjustable resistor, the third adjustable resistor, the first capacitor, and the second capacitor are configured to reduce a feedback factor of the analog front-end circuit at high frequencies to enhance a maximum peak.

17. The analog front-end circuit of claim 16, further comprising a continuous-time linear equalizer circuit comprising:

the first output of the continuous-time linear equalizer circuit is connected to the first output of the feedback circuit and the second input of the transimpedance amplifier;

the second output of the continuous-time linear equalizer circuit is connected to the second output of the feedback circuit and the first input of the transimpedance amplifier;

the third current source is connected between the third node and the ground; and is also provided with

The fourth current source is connected between the fourth node and the ground.

18. The analog front end circuit of claim 17, wherein:

a third capacitor connected between the first output of the transimpedance amplifier and the ground; and is also provided with

A fourth capacitor is connected between the second output of the transimpedance amplifier and the ground.

19. The analog front-end circuit of any of claims 17 and 18, further comprising:

20. A communication system comprising an analog front-end circuit, the analog front-end circuit comprising:

a continuous time linear equalizer circuit;

a transimpedance amplifier connected at the output of the continuous time linear equalizer circuit; and

a feedback circuit, comprising:

the first input of the feedback circuit is connected to a gate terminal of the first transistor through a second adjustable resistor; and is also provided with

The second input of the feedback circuit is connected to a gate terminal of the second transistor through a third adjustable resistor.