CN116646404A - Thin film transistor, integrated gate driving circuit and display panel - Google Patents
Thin film transistor, integrated gate driving circuit and display panel Download PDFInfo
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- CN116646404A CN116646404A CN202310621003.6A CN202310621003A CN116646404A CN 116646404 A CN116646404 A CN 116646404A CN 202310621003 A CN202310621003 A CN 202310621003A CN 116646404 A CN116646404 A CN 116646404A
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- 239000010409 thin film Substances 0.000 title claims abstract description 53
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- 239000010410 layer Substances 0.000 claims description 399
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- 229910052757 nitrogen Inorganic materials 0.000 claims description 22
- 239000010408 film Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 10
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
Abstract
The application provides a thin film transistor, an integrated gate driving circuit and a display panel, wherein the thin film transistor comprises an insulating layer, an active layer, a first electrode and a second electrode, the energy gap of the insulating layer is between 4.0ev and 6.7ev, the insulating layer and the active layer are arranged in a layer-by-layer mode, the active layer comprises amorphous silicon, the first electrode and the second electrode are located on one side, away from the insulating layer, of the active layer, the second electrode is arranged at intervals with the first electrode, and the second electrode is communicated with the first electrode through the active layer. The technical scheme of the application can improve the energy gap of the insulating layer in the thin film transistor, thereby reducing the light degradation of the active layer.
Description
Technical Field
The present application relates to the field of electronics, and more particularly, to a thin film transistor, an integrated gate driving circuit, and a display panel.
Background
Currently, an active layer in a thin film transistor undergoes photo-degradation after irradiation, resulting in an increase in surface defects of the active layer. The defect of the active layer can cause the source electrode and the drain electrode to be unable to be normally conducted, which affects the overall working stability of the thin film transistor, and further causes abnormal display of the display panel.
Disclosure of Invention
Embodiments of the present application provide a thin film transistor, an integrated gate driving circuit, and a display panel capable of improving an energy gap of an insulating layer in the thin film transistor, thereby reducing light degradation of an active layer.
In a first aspect, the present application provides a thin film transistor comprising:
an insulating layer having an energy gap between 4.0ev and 6.7 ev;
the insulation layer is arranged on the active layer, and the material of the active layer comprises amorphous silicon; and
The first electrode and the second electrode are positioned on one side of the active layer, which is away from the insulating layer, the second electrode is arranged at intervals with the first electrode, and the second electrode is communicated with the first electrode through the active layer.
It is understood that the energy gap of the insulating layer in the prior art is generally less than 4ev, and after the active layer is irradiated, electrons of the active layer may jump to the insulating layer, thereby generating defects, so that the active layer cannot provide enough carriers to conduct the source and the gate. Eventually causing the display panel to display anomalies. The energy gap of the insulating layer provided by the application is between 4.0ev and 6.7ev (including the end point values of 4.0ev and 6.7 ev), and the improvement of the energy gap of the insulating layer can prevent electrons of the active layer from being injected into the insulating layer, so that the photodegradation of the active layer is effectively reduced.
In one possible implementation manner, the insulating layer is a laminated multilayer structure, the multilayer structure includes at least two of a first layer, a second layer and a third layer, the first layer, the second layer and the third layer are all silicon nitride film layers formed by chemical vapor deposition, the nitrogen content of the first layer is lower than that of the second layer, and the nitrogen content of the second layer is lower than that of the third layer.
In one possible embodiment, the insulating layer includes two second layers and two third layers, and one second layer, one third layer, the other second layer, and the other third layer are stacked in this order in a direction in which the insulating layer faces the active layer.
In a possible embodiment, the insulating layer includes one first layer, one second layer, and two third layers, and one first layer, one third layer, one second layer, and the other third layer are stacked in this order in a direction in which the insulating layer faces the active layer.
In a possible embodiment, the insulating layer includes one first layer, one second layer, and two third layers, and one third layer, one first layer, one second layer, and the other third layer are stacked in this order in a direction in which the insulating layer faces the active layer.
In a possible embodiment, the insulating layer includes one of the first layer, one of the second layer, one of the third layer, and one of the fourth layer, and the material of the fourth layer includes hafnium oxide or silicon oxide;
one of the fourth layers, one of the first layers, one of the third layers, and one of the third layers are sequentially stacked in a direction in which the insulating layer faces the active layer.
In a possible embodiment, the insulating layer includes two of the second layers, one of the third layers, and one of the fourth layers, and the material of the fourth layer includes hafnium oxide or silicon oxide;
one of the second layers, one of the fourth layers, the other of the second layers and one of the third layers are stacked in this order in a direction in which the insulating layer faces the active layer.
In a possible embodiment, the insulating layer has a single-layer structure, and the material of the single-layer structure includes hafnium oxide or silicon oxide.
In a second aspect, the present application also provides an integrated gate drive circuit comprising a plurality of drive units, each of said drive units comprising a thin film transistor as described above.
In a third aspect, the present application further provides a display panel, including a display module and an integrated gate driving circuit as described above, where the integrated gate driving circuit controls the display module to display an image.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained by those skilled in the art without the inventive effort.
Fig. 1 is a schematic structural diagram of a display panel provided in the present application;
fig. 2 is a schematic structural view of a thin film transistor in the display panel shown in fig. 1;
FIG. 3 is a schematic cross-sectional view of a first possible embodiment of the insulating layer provided in FIG. 2;
FIG. 4 is a schematic cross-sectional view of a second possible embodiment of the insulating layer provided in FIG. 2;
FIG. 5 is a schematic cross-sectional view of a third possible embodiment of the insulating layer provided in FIG. 2;
FIG. 6 is a schematic cross-sectional view of a first of the second possible embodiment of the insulating layer provided in FIG. 2;
FIG. 7 is a second cross-sectional schematic view of a second possible embodiment of the insulating layer provided in FIG. 2;
fig. 8 is a schematic cross-sectional view of a fourth possible embodiment of the insulating layer provided in fig. 2.
Reference numerals: the display device includes a display panel 1000, a driving circuit 100, a display module 200, a thin film transistor 101, a substrate 110, a gate electrode 120, an insulating layer 130, a first electrode 140, a second electrode 150, a first conductive layer 160, an active layer 170, a first layer 131, a second layer 132, and a third layer 133.
Detailed Description
For convenience of understanding, terms involved in the embodiments of the present application will be explained first.
And/or: merely one association relationship describing the associated object, the representation may have three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone.
A plurality of: refers to two or more.
And (3) connection: it is to be understood in a broad sense that, for example, a is linked to B either directly or indirectly via an intermediary.
The following description of the embodiments of the present application will be made with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel 1000 provided in the present application. The application provides a display panel 1000. The display panel 1000 includes an integrated gate driving circuit 100 and a display module 200. The integrated gate driving circuit 100 controls the display module 200 to display an image.
The integrated gate driving circuit 100 includes a plurality of driving units (not shown), each of which includes one thin film transistor 101. The thin film transistor 101 may serve as a switch of the integrated gate driving circuit 100.
It is understood that with the development of the technology for manufacturing display panels, requirements for high resolution and narrow frame of display panels are continuously increasing, and more integrated gate driving circuits (Gate Driven on Array, GOA) are applied to the display panels. The integrated grid driving circuit can realize the progressive scanning driving function of the display panel, and the grid driving circuit is integrated on the array substrate of the display panel by utilizing the integrated grid driving circuit technology, so that a grid driving part can be omitted, and the product cost can be reduced in the aspects of raw materials and manufacturing processes.
Currently, an active layer in a thin film transistor undergoes photo-degradation after irradiation, resulting in an increase in surface defects of the active layer. The defect of the active layer can cause the source electrode and the drain electrode to be unable to be normally conducted, which affects the overall working stability of the thin film transistor, and further causes abnormal display of the display panel.
Based on this, the embodiment of the present application provides a thin film transistor 101 capable of improving the energy gap of an insulating layer in the thin film transistor 101, thereby reducing the photodegradation of an active layer.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a thin film transistor 101 in the display panel 1000 shown in fig. 1. The thin film transistor 101 includes a substrate 110, a gate electrode 120, an insulating layer 130, a first electrode 140, a second electrode 150, a first conductive layer 160, and an active layer 170.
It should be noted that fig. 1 is only for schematically describing the connection relationship of the substrate 110, the gate electrode 120, the insulating layer 130, the first electrode 140, the second electrode 150, the first conductive layer 160, and the active layer 170, and is not limited to a specific connection location, a specific structure, and a specific number of devices. The structure illustrated in the embodiment of the present application does not form a specific limitation on the thin film transistor 101. In other embodiments of the application, the thin film transistor 101 may include more or less components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components may be provided. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
The substrate 110 may be a glass substrate, a sapphire substrate, or a silicon wafer substrate, for example. Or the substrate 110 may be a flexible substrate, which may be made of any one or more of the following materials: polyimide, polyethylene terephthalate (Polyethylene terephthalate, PET), polyethylene naphthalate (Polyethylene naphthalate two formic acid glycol ester, PEN), cyclic Olefin Polymer (COP), polycarbonate (PC), polystyrene (PS), polypropylene (PP), polytetrafluoroethylene (PTFE). In other implementations, the substrate 110 may be a ceramic substrate, which is not limited in the present application.
The gate electrode 120 is disposed on the surface of the substrate 110, and the insulating layer 130 covers the gate electrode 120. The active layer 170 may be disposed on a surface of the insulating layer 130 facing away from the substrate 110. The active layer 170 may be disposed opposite to the gate electrode 120. The first conductive layer 160 may be disposed on a surface of the active layer 170 remote from the insulating layer 130. The first electrode 140 and the second electrode 150 are disposed on a side of the insulating layer 130 away from the gate electrode 120, and the first electrode 140 and the second electrode 150 are spaced apart. The first electrode 140 may be a source of the thin film transistor 101, and the second electrode 150 is a drain of the thin film transistor 101. Or the first electrode 140 may be the drain of the thin film transistor 101, and the second electrode 150 is the source of the thin film transistor 101.
The material of the active layer 170 may be amorphous silicon. Amorphous silicon may undergo photodegradation after irradiation, thereby generating defects on the surface. And thus causes leakage of the thin film transistor 101.
The energy gap of the insulating layer 130 provided by the embodiment of the application is higher. The energy gap of the insulating layer 130 is between 4.0ev and 6.7 ev.
It is understood that the energy gap of the insulating layer in the prior art is generally less than 4ev, and after the active layer is irradiated, electrons of the active layer may jump to the insulating layer, thereby generating defects, so that the active layer cannot provide enough carriers to conduct the source and the gate. Eventually causing the display panel to display anomalies. The energy gap of the insulating layer 130 provided by the application is between 4.0ev and 6.7ev (including the end point values of 4.0ev and 6.7 ev), and the improvement of the energy gap of the insulating layer 130 can prevent the electrons of the active layer 170 from being injected into the insulating layer 130, thereby effectively reducing the photo-degradation of the active layer 170.
In addition, the gate electrode in the integrated gate driving circuit generally applies a higher voltage, which makes electrons of the gate electrode easily transition to the insulating layer, and electrons that transition to the insulating layer may be recombined with holes of the active layer, so that structures of the electron layer and the hole layer of the active layer may be damaged, defects are generated in the active layer, and finally, the thin film transistor cannot work normally. In the embodiment provided by the application, after the energy gap of the insulating layer 130 is increased, electrons of the gate electrode 120 are not easy to transition to the insulating layer 130, so that the active layer 170 can work normally.
The insulating layer 130 of the present application includes various structures, and the structure of the insulating layer 130 will be described below by way of example in a number of embodiments. It should be understood that embodiments similar to the following embodiments are also protected by the present application without additional inventive effort by those skilled in the art.
In a first possible embodiment, referring to fig. 3, fig. 3 is a schematic cross-sectional view of a first possible embodiment of the insulating layer 130 provided in fig. 2. The energy gap of the insulating layer 130 is between 4.0ev and 5.1 ev. The insulating layer 130 includes at least two of a first layer 131, a second layer 132, and a third layer 133. The first layer 131, the second layer 132, and the third layer 133 are silicon nitride film layers formed by plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD). Ammonia, silane, and nitrogen may be used as the gas raw materials in the deposition process of silicon nitride. The ratio of ammonia to silane may range between 5 and 15 (inclusive) among others. The ratio of nitrogen to silane may range between 15 and 30 (inclusive of the endpoints 15 and 30). For example, after the silicon oxide deposition is completed, nitrogen and hydrogen may be excited, thereby generating low-temperature plasmas of nitrogen and hydrogen, and further performing atmosphere protection on the silicon nitride film layer just formed.
It will be appreciated that in the chemical vapor deposition of silicon nitride, which is currently in common use, the ratio of ammonia to silane is approximately 9 and the ratio of nitrogen to silane is approximately 3. In the application, the proportion of ammonia to silane and the proportion of nitrogen to silane are improved, so that the nitrogen content in the deposited silicon nitride film layer is improved, the insulativity of silicon nitride is further improved, and the result of improving the energy gap of the insulating layer 130 is finally achieved.
The deposition rate of the first layer 131 is between 10A/s and 15A/s (inclusive). The film thickness of the first layer 131 may be between 300A-1000A (inclusive of the end points 300A and 1000A). The nitrogen content of the first layer 131 is lower than the nitrogen content of the second layer 132.
The deposition rate of the second layer 132 is between 7A/s and 10A/s (inclusive). The film thickness of the second layer 132 may be between 1500A-3800A (inclusive of the endpoints 1500A and 3800A). The nitrogen content of the second layer 132 is lower than the nitrogen content of the third layer 133.
The deposition rate of the third layer 133 is less than 7A/s. The film thickness of the third layer 133 may be between 200A-1500A (inclusive of the end points 200A and 1500A). The third layer 133 may have three kinds, and the deposition rates of the materials of the three kinds of third layers 133 are different. Specifically, the three third layers 133 are a first sub-layer (not shown), a second sub-layer (not shown), and a third sub-layer (not shown), respectively. The deposition rate of the first sub-layer is between 5A/s and 7A/s (inclusive). The film sub-layer thickness of the first sub-layer may be between 500A-1500A (inclusive of the endpoints 500A and 1500A). The nitrogen content of the first sub-layer is lower than the nitrogen content of the second sub-layer. The deposition rate of the second sub-layer is between 3A/s and 5A/s (inclusive). The film sub-layer thickness of the second sub-layer may be between 200A and 500A (inclusive of the end points 200A and 500A). The nitrogen content of the second sub-layer is lower than the nitrogen content of the third sub-layer. The deposition rate of the third sub-layer is less than 3A/s. The film sub-layer thickness of the third sub-layer may be between 200A and 500A (inclusive of the end points 200A and 500A).
It is understood that reducing the film formation rate can effectively increase the nitrogen content of the silicon nitride film. Further, the insulation property of the silicon nitride is improved, and the energy gap of the insulating layer 130 is finally improved.
A first possible example includes a plurality of implementations. In the first embodiment, referring to fig. 3 again, the insulating layer 130 includes a first layer 131, a second layer 132 and two third layers 133, and in the direction of the insulating layer 130 toward the active layer 170, the first layer 131, the third layer 133, the second layer 132 and the third layer 133 are sequentially stacked. One third layer 133 may be a first sub-layer, and the other third layer 133 may be a third sub-layer. That is, one first layer 131, one third sub-layer, one second layer 132, and one first sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170.
In a second embodiment, referring to fig. 4, fig. 4 is a schematic cross-sectional view of a second possible example of the insulating layer 130 provided in fig. 2. The insulating layer 130 includes two second layers 132 and two third layers 133, and one second layer 132, one third layer 133, another second layer 132, and another third layer 133 are sequentially stacked in the direction in which the insulating layer 130 faces the active layer 170. The third layer 133 may be a first sub-layer, a second sub-layer, or a third sub-layer.
Specifically, one second layer 132, one first sub-layer, another second layer 132, and another first sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170. Alternatively, one second layer 132, one second sub-layer, another second layer 132, and another second sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170. Alternatively, one second layer 132, one third sub-layer, another second layer 132, and another third sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170.
In a third embodiment, referring to fig. 5, fig. 5 is a schematic cross-sectional view of a third possible example of the insulating layer 130 provided in fig. 2. The insulating layer 130 includes a first layer 131, a second layer 132, and two third layers 133, and one third layer 133, one first layer 131, one second layer 132, and the other third layer 133 are sequentially stacked in the direction in which the insulating layer 130 faces the active layer 170. The third layer 133 may be a first sub-layer, a second sub-layer, or a third sub-layer.
Specifically, a third sub-layer, a first layer 131, a second layer 132, and a first sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170. Alternatively, one third sub-layer, one first layer 131, one second layer 132, and another third sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170. Alternatively, one second sub-layer, one first layer 131, one second layer 132, and one second sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170.
In a second possible embodiment, referring to fig. 6, fig. 6 is a schematic cross-sectional view of a first embodiment of the insulating layer 130 provided in fig. 2. Unlike the first embodiment, the insulating layer 130 further includes a fourth layer 134, and the material of the fourth layer 134 includes hafnium oxide. Hafnium oxide may be formed by plasma enhanced chemical vapor deposition, with the energy gap of hafnium oxide ranging from 5.5ev to 6.7 ev. The film thickness of the fourth layer 134 may be between 200A-500A.
In a second possible embodiment two implementations are included. In the first embodiment, one fourth layer 134, one first layer 131, one second layer 132, and one third layer 133 are stacked in this order in the direction in which the insulating layer 130 faces the active layer 170. The third layer 133 may be a first sub-layer, a second sub-layer, or a third sub-layer.
In a second embodiment, referring to fig. 7, fig. 7 is a schematic cross-sectional view of a second possible example of the insulating layer 130 provided in fig. 2. The insulating layer 130 includes two second layers 132, a third layer 133, and a fourth layer 134. One second layer 132, one fourth layer 134, another second layer 132, and one third layer 133 are sequentially stacked in the direction in which the insulating layer 130 faces the active layer 170. The third layer 133 may be a first sub-layer, a second sub-layer, or a third sub-layer.
In a third possible embodiment, the material of the fourth layer 134 is silicon oxide, unlike the second possible embodiment.
A third possible example includes two implementations. Referring to fig. 6 again, in the first embodiment, a fourth layer 134, a first layer 131, a third layer 133 and a third layer 133 are sequentially stacked in the direction of the insulating layer 130 toward the active layer 170. The third layer 133 may be a first sub-layer, a second sub-layer, or a third sub-layer.
In a second embodiment, referring again to fig. 7, the insulating layer 130 includes two second layers 132, a third layer 133 and a fourth layer 134. One second layer 132, one fourth layer 134, another second layer 132, and one third layer 133 are sequentially stacked in the direction in which the insulating layer 130 faces the active layer 170. The third layer 133 may be a first sub-layer, a second sub-layer, or a third sub-layer.
In a fourth possible embodiment, referring to fig. 8, fig. 8 is a schematic cross-sectional view of a fourth possible embodiment of the insulating layer 130 provided in fig. 2. Unlike the first three possible embodiments, the insulating layer 130 has a single-layer structure. The material of the single-layer structure includes hafnium oxide or silicon oxide.
The present application also explores the performance of the thin film transistor 101 by the following two formulas.
Equation 1:
I_ds＝W/L*μ_eff*C_ox*[(V_gs-V_th)*V_ds-(V_ds^2)/2]
equation 2:
V_(gs(ob))＝V_GH-V_GL
in formula 1, W/L represents a ratio of a channel width to a channel length of the thin film transistor 101, μ_eff represents electron mobility, c_ox represents a capacitance per unit area of a structure of the gate electrode 120-the insulating layer 130-the active layer 170 in the thin film transistor 101, v_gs represents a voltage difference between the gate electrode 120 and the source electrode, v_th represents a threshold voltage of the thin film transistor 101, and v_ds represents a voltage difference between the source electrode and the drain electrode.
In formula 2, v_gh represents the voltage when the thin film transistor 101 is on, v_gl represents the voltage when the thin film transistor 101 is off, and v_ (gs (on)) represents the voltage difference of the thin film transistor 101.
It is understood that the larger the voltage difference of the thin film transistor 101, the larger the on-state current of the thin film transistor 101. Therefore, the voltage of the thin film transistor 101 in the off state is reduced, and the on-state current of the thin film transistor 101 can be effectively mentioned, so that the working stability of the thin film transistor 101 is improved, and the display abnormality of the display panel 1000 caused by the instability of the driving circuit is avoided.
In addition, in the thin film transistor 101, the energy gap of the insulating layer 130 can be increased to increase the dielectric constant of the insulating layer 130, and further increase the capacitance per unit area (c_ox) of the structure of the gate electrode 120, the insulating layer 130, and the active layer 170 in the thin film transistor 101, so that the current can be increased, and the current can be sufficiently large to drive the display panel 1000 to display a picture.
The foregoing has outlined rather broadly the more detailed description of embodiments of the application, wherein the principles and embodiments of the application are explained in detail using specific examples, the above examples being provided solely to facilitate the understanding of the method and core concepts of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. A thin film transistor, comprising:
an insulating layer having an energy gap between 4.0ev and 6.7 ev;
the insulation layer is arranged on the active layer, and the material of the active layer comprises amorphous silicon; and
The first electrode and the second electrode are positioned on one side of the active layer, which is away from the insulating layer, the second electrode is arranged at intervals with the first electrode, and the second electrode is communicated with the first electrode through the active layer.
2. The thin film transistor according to claim 1, wherein the insulating layer is a stacked multilayer structure, the multilayer structure includes at least two of a first layer, a second layer, and a third layer, the first layer, the second layer, and the third layer are silicon nitride film layers formed by chemical vapor deposition, nitrogen content of the first layer is lower than nitrogen content of the second layer, and nitrogen content of the second layer is lower than nitrogen content of the third layer.
3. The thin film transistor according to claim 2, wherein the insulating layer includes two of the second layers and two of the third layers, and one of the second layers, one of the third layers, the other of the second layers, and the other of the third layers are stacked in this order in a direction in which the insulating layer faces the active layer.
4. The thin film transistor according to claim 2, wherein the insulating layer includes one of the first layer, one of the second layer, and two of the third layer, and one of the first layer, one of the third layer, one of the second layer, and the other of the third layer are stacked in this order in a direction in which the insulating layer faces the active layer.
5. The thin film transistor according to claim 2, wherein the insulating layer includes one of the first layer, one of the second layer, and two of the third layer, and one of the third layer, one of the first layer, one of the second layer, and the other of the third layer are stacked in this order in a direction in which the insulating layer faces the active layer.
6. The thin film transistor according to claim 2, wherein the insulating layer includes one of the first layer, the second layer, the third layer, and a fourth layer, and a material of the fourth layer includes hafnium oxide or silicon oxide;
one of the fourth layers, one of the first layers, one of the third layers, and one of the third layers are sequentially stacked in a direction in which the insulating layer faces the active layer.
7. The thin film transistor according to claim 2, wherein the insulating layer includes two of the second layers, one of the third layers, and one of the fourth layers, and a material of the fourth layer includes hafnium oxide or silicon oxide;
one of the second layers, one of the fourth layers, the other of the second layers and one of the third layers are stacked in this order in a direction in which the insulating layer faces the active layer.
8. The thin film transistor according to claim 1, wherein the insulating layer has a single-layer structure, and a material of the single-layer structure includes hafnium oxide or silicon oxide.
9. An integrated gate drive circuit comprising a plurality of drive units, each of said drive units comprising a thin film transistor according to any one of claims 1-8.
10. A display panel comprising a display module and the integrated gate drive circuit of claim 9, the integrated gate drive circuit controlling the display module to display an image.
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| JPS6215857A (en) * | 1985-07-12 | 1987-01-24 | Matsushita Electric Ind Co Ltd | Active element |
| JPS63117469A (en) * | 1986-11-05 | 1988-05-21 | Sumitomo Metal Ind Ltd | Thin-film semiconductor device |
| JPH0234821A (en) * | 1988-07-25 | 1990-02-05 | Matsushita Electric Ind Co Ltd | Thin film transistor |
| JPH06177382A (en) * | 1992-12-10 | 1994-06-24 | Sharp Corp | Thin film transistor and liquid crystal display panel using it |
| CN103681673A (en) * | 2012-09-14 | 2014-03-26 | 瑞萨电子株式会社 | Semiconductor device and semiconductor device manufacturing method |
| CN114823730A (en) * | 2022-04-20 | 2022-07-29 | 广州华星光电半导体显示技术有限公司 | Display panel and display device |
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|---|---|---|---|---|
| JPS6215857A (en) * | 1985-07-12 | 1987-01-24 | Matsushita Electric Ind Co Ltd | Active element |
| JPS63117469A (en) * | 1986-11-05 | 1988-05-21 | Sumitomo Metal Ind Ltd | Thin-film semiconductor device |
| JPH0234821A (en) * | 1988-07-25 | 1990-02-05 | Matsushita Electric Ind Co Ltd | Thin film transistor |
| JPH06177382A (en) * | 1992-12-10 | 1994-06-24 | Sharp Corp | Thin film transistor and liquid crystal display panel using it |
| CN103681673A (en) * | 2012-09-14 | 2014-03-26 | 瑞萨电子株式会社 | Semiconductor device and semiconductor device manufacturing method |
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