CN116646404A - Thin film transistor, integrated gate driving circuit and display panel - Google Patents

Abstract

The application provides a thin film transistor, an integrated gate driving circuit and a display panel, wherein the thin film transistor comprises an insulating layer, an active layer, a first electrode and a second electrode, the energy gap of the insulating layer is between 4.0ev and 6.7ev, the insulating layer and the active layer are arranged in a layer-by-layer mode, the active layer comprises amorphous silicon, the first electrode and the second electrode are located on one side, away from the insulating layer, of the active layer, the second electrode is arranged at intervals with the first electrode, and the second electrode is communicated with the first electrode through the active layer. The technical scheme of the application can improve the energy gap of the insulating layer in the thin film transistor, thereby reducing the light degradation of the active layer.

Description

Thin film transistor, integrated gate drive circuit and display panel

technical field

The present application relates to the field of electronics, in particular to a thin film transistor, an integrated gate drive circuit and a display panel.

Background technique

At present, the active layer in the thin film transistor will undergo photodegradation after being irradiated with light, resulting in the increase of surface defects in the active layer. Defects in the active layer will lead to the failure of normal conduction between the source and the drain, which will affect the overall stability of the thin film transistor and lead to abnormal display of the display panel.

Contents of the invention

Embodiments of the present application provide a thin film transistor, an integrated gate driving circuit, and a display panel, which can increase the energy gap of an insulating layer in the thin film transistor, thereby reducing photodegradation of an active layer.

In a first aspect, the present application provides a thin film transistor, including:

an insulating layer, the energy gap of the insulating layer is between 4.0ev-6.7ev;

an active layer, the insulating layer is stacked with the active layer, and the material of the active layer includes amorphous silicon; and

A first electrode and a second electrode, the first electrode and the second electrode are located on the side of the active layer away from the insulating layer, the second electrode is spaced apart from the first electrode, the The second electrode communicates with the first electrode through the active layer.

It can be understood that the energy gap of the insulating layer in the prior art is generally less than 4 eV. After the active layer is illuminated, the electrons in the active layer may jump to the insulating layer, thereby generating defects, which cause the active layer to fail to provide sufficient energy. Carriers conduct the source and gate. Ultimately, the display panel displays abnormally. And the energy gap of the insulating layer provided by the present application is between 4.0ev-6.7ev (including the endpoint value 4.0ev and 6.7ev), the improvement of the energy gap of the insulating layer can prevent the electron injection of the active layer into the insulating layer, and then effectively Reduces photodegradation of the active layer.

In a possible implementation manner, the insulating layer is a stacked multi-layer structure, the multi-layer structure includes at least two of the first layer, the second layer and the third layer, the first layer, the Both the second layer and the third layer are silicon nitride film layers formed by chemical vapor deposition, the nitrogen content of the first layer is lower than that of the second layer, and the nitrogen content of the second layer is The nitrogen content is lower than that of the third layer.

In a possible implementation manner, the insulating layer includes two second layers and two third layers, and in the direction that the insulating layer faces the active layer, one second layer , one of the third layer, another of the second layer and another of the third layer are sequentially stacked.

In a possible implementation manner, the insulating layer includes one first layer, one second layer and two third layers, and in the direction where the insulating layer faces the active layer, one of the The first layer, one third layer, one second layer and another third layer are sequentially stacked.

In a possible implementation manner, the insulating layer includes one first layer, one second layer, and two third layers, and in a direction in which the insulating layer faces the active layer, One of the third layer, one of the first layer, one of the second layer and another of the third layer are stacked in sequence.

In a possible implementation manner, the insulating layer includes one of the first layer, one of the second layer, one of the third layer and a fourth layer, and the material of the fourth layer includes hafnium oxide or Silicon oxide;

In a direction in which the insulating layer faces the active layer, one fourth layer, one first layer, one third layer, and one third layer are sequentially stacked.

In a possible implementation manner, the insulating layer includes two second layers, one third layer and one fourth layer, and the material of the fourth layer includes hafnium oxide or silicon oxide;

In the direction in which the insulating layer faces the active layer, one of the second layer, one of the fourth layer, another of the second layer and one of the third layer are stacked in sequence.

In a possible implementation manner, the insulating layer has a single-layer structure, and a material of the single-layer structure includes hafnium oxide or silicon oxide.

In a second aspect, the present application also provides an integrated gate driving circuit, including a plurality of driving units, each of which includes a thin film transistor as described above.

In a third aspect, the present application further provides a display panel, including a display module and the above-mentioned integrated gate driving circuit, and the integrated gate driving circuit controls the display module to display images.

Description of drawings

In order to illustrate the technical solution of the present application more clearly, the accompanying drawings used in the implementation will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some implementations of the application. As far as the skilled person is concerned, on the premise of not paying creative work, other drawings can also be obtained like these drawings.

Fig. 1 is a schematic structural diagram of a display panel provided in this application;

FIG. 2 is a schematic structural diagram of a thin film transistor in the display panel shown in FIG. 1;

Fig. 3 is a schematic cross-sectional view of the first kind in the first possible embodiment of the insulating layer provided in Fig. 2;

Fig. 4 is a second cross-sectional schematic diagram of the first possible embodiment of the insulating layer provided in Fig. 2;

Fig. 5 is a schematic cross-sectional view of a third type in the first possible embodiment of the insulating layer provided in Fig. 2;

Fig. 6 is a schematic cross-sectional view of the first kind in the second possible embodiment of the insulating layer provided in Fig. 2;

FIG. 7 is a second cross-sectional schematic diagram of a second possible embodiment of the insulating layer provided in FIG. 2;

FIG. 8 is a schematic cross-sectional view of a fourth possible embodiment of the insulating layer provided in FIG. 2 .

Reference signs: display panel 1000, drive circuit 100, display module 200, thin film transistor 101, substrate 110, gate 120, insulating layer 130, first electrode 140, second electrode 150, first conductive layer 160, active Layer 170 , first layer 131 , second layer 132 , third layer 133 .

Detailed ways

For ease of understanding, the terms involved in the embodiments of the present application are explained first.

And/or: It is just a relationship describing the associated object, which means that there can be three kinds of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist at the same time, and B exists alone. .

Plurality: Refers to two or more than two.

Connection: It should be understood in a broad sense. For example, the connection between A and B can be directly connected between A and B, or indirectly connected through an intermediary.

The specific implementation manners of the present application will be clearly described below in conjunction with the accompanying drawings.

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a display panel 1000 provided in this application. The present application provides a display panel 1000 . The display panel 1000 includes an integrated gate driving circuit 100 and a display module 200 . The integrated gate driving circuit 100 controls the display module 200 to display images.

The integrated gate driving circuit 100 includes a plurality of driving units (not shown), and each driving unit includes a thin film transistor 101 . The thin film transistor 101 can be used as a switch of the integrated gate driving circuit 100 .

It is understandable that with the continuous development of display panel manufacturing technology, people's requirements for high resolution and narrow frame of the display panel continue to increase, and more and more integrated gate drive circuits (Gate Driven on Array, GOA) are used Applied in the display panel. The integrated gate drive circuit can realize the progressive scan driving function of the display panel. Using the integrated gate drive circuit technology to integrate the gate drive circuit on the array substrate of the display panel can save the gate drive part, so that it can be used in raw materials and The production process reduces the product cost in two aspects.

At present, the active layer in the thin film transistor will undergo photodegradation after being irradiated with light, resulting in the increase of surface defects in the active layer. Defects in the active layer will lead to the failure of normal conduction between the source and the drain, which will affect the overall stability of the thin film transistor and lead to abnormal display of the display panel.

Based on this, the embodiment of the present application provides a thin film transistor 101, which can increase the energy gap of the insulating layer in the thin film transistor 101, thereby reducing the photodegradation of the active layer.

Please refer to FIG. 2 . FIG. 2 is a schematic structural diagram of the thin film transistor 101 in the display panel 1000 shown in FIG. 1 . The thin film transistor 101 includes a substrate 110 , a gate 120 , an insulating layer 130 , a first electrode 140 , a second electrode 150 , a first conductive layer 160 and an active layer 170 .

It should be noted that the purpose of FIG. 1 is only to schematically describe the connection relationship between the substrate 110, the gate 120, the insulating layer 130, the first electrode 140, the second electrode 150, the first conductive layer 160 and the active layer 170, It is not a specific limitation on the connection position, specific structure and quantity of each device. However, the structure shown in the embodiment of the present application does not constitute a specific limitation on the thin film transistor 101 . In other embodiments of the present application, the thin film transistor 101 may include more or fewer components than shown in the figure, or combine certain components, or separate certain components, or arrange different components. The illustrated components can be realized in hardware, software or a combination of software and hardware.

Exemplarily, the substrate 110 may be a glass substrate, a sapphire substrate or a silicon wafer substrate. Or the substrate 110 can be a flexible substrate, and the flexible substrate can be made of any one or more of the following materials: polyimide, polyethylene terephthalate (Polyethylene terephthalate, PET), polyethylene naphthalate Ethylene glycol formate (Polyethylenenaphthalate two formic acid glycol ester, PEN), cyclo-olefin polymer (Cyclo-olefin polymer, COP), polycarbonate (Polycarbonate, PC), polystyrene (Polystyrene, PS), polypropylene (Polypropylene , PP), polytetrafluoroethylene (Polytetrafluoroethylene, PTFE). In other implementation manners, the substrate 110 may also be a ceramic substrate, which is not limited in this application.

The gate 120 is disposed on the surface of the substrate 110 , and the insulating layer 130 covers the gate 120 . The active layer 170 may be disposed on a surface of the insulating layer 130 facing away from the substrate 110 . The active layer 170 may be disposed opposite to the gate 120 . The first conductive layer 160 may be disposed on the surface of the active layer 170 away from the insulating layer 130 . The first electrode 140 and the second electrode 150 are disposed on a side of the insulating layer 130 away from the gate 120 , and the first electrode 140 and the second electrode 150 are disposed at intervals. Wherein, the first electrode 140 may be the source of the thin film transistor 101 , and the second electrode 150 may be the drain of the thin film transistor 101 . Alternatively, the first electrode 140 may be the drain of the thin film transistor 101 , and the second electrode 150 may be the source of the thin film transistor 101 .

The material of the active layer 170 may be amorphous silicon. Amorphous silicon can undergo photodegradation when exposed to light, creating defects on the surface. This further causes leakage of the thin film transistor 101 .

The insulating layer 130 provided by the embodiments of the present application has a relatively high energy gap. The energy gap of the insulating layer 130 is between 4.0ev-6.7ev.

It can be understood that the energy gap of the insulating layer in the prior art is generally less than 4 eV. After the active layer is illuminated, the electrons in the active layer may jump to the insulating layer, thereby generating defects, which cause the active layer to fail to provide sufficient energy. Carriers conduct the source and gate. Ultimately, the display panel displays abnormally. However, the energy gap of the insulating layer 130 provided by the present application is between 4.0ev-6.7ev (including the endpoint value 4.0ev and 6.7ev), and the improvement of the energy gap of the insulating layer 130 can prevent the injection of electrons from the active layer 170 into the insulating layer 130, thereby effectively reducing the photodegradation of the active layer 170.

In addition, a high voltage is generally applied to the gate in the integrated gate drive circuit, which makes it easy for the electrons in the gate to transition to the insulating layer, and the electrons transitioning to the insulating layer may recombine with the holes in the active layer, resulting in The structure of the electron layer and the hole layer of the active layer will be damaged, causing defects in the active layer, and finally causing the thin film transistor to fail to work normally. In the embodiment provided in the present application, when the energy gap of the insulating layer 130 is increased, electrons in the gate 120 are not easy to transition to the insulating layer 130 , thereby ensuring that the active layer 170 can work normally.

The insulating layer 130 of the present application includes various structures, and the structure of the insulating layer 130 will be described as examples in several embodiments below. However, it should be understood that, on the premise that those skilled in the art do not need to pay extra creative work, embodiments similar to the following embodiments are also protected by the present application.

For the first possible embodiment, please refer to FIG. 3 , which is a first cross-sectional schematic view of the first possible embodiment of the insulating layer 130 provided in FIG. 2 . The energy gap of the insulating layer 130 is between 4.0ev˜5.1ev. The insulating layer 130 includes at least two of a first layer 131 , a second layer 132 and a third layer 133 . The first layer 131 , the second layer 132 and the third layer 133 are silicon nitride film layers formed by plasma enhanced chemical vapor deposition (PECVD). During the deposition of silicon nitride, ammonia, silane, and nitrogen can be used as gaseous materials. Wherein, the ratio range of ammonia to silane can be between 5-15 (inclusive of endpoints 5 and 15). The ratio of nitrogen to silane can range from 15-30 (15 and 30 inclusive). Exemplarily, after the deposition of silicon oxide is completed, nitrogen and hydrogen may be excited to generate a low-temperature plasma of nitrogen and hydrogen, and then perform atmosphere protection for the newly formed silicon nitride film.

It can be understood that, in the currently commonly used chemical vapor deposition of silicon nitride, the ratio of ammonia gas to silane is about 9, and the ratio of nitrogen gas to silane is about 3. In this application, the ratio of ammonia gas to silane, and the ratio of nitrogen gas to silane is increased, thereby increasing the nitrogen content in the deposited silicon nitride film layer, thereby improving the insulation of silicon nitride, and finally achieving the lifting of the insulating layer 130. The result of the energy gap.

The deposition rate of the first layer 131 is between 10A/s-15A/s (endpoints 10A/s and 15A/s inclusive). The film thickness of the first layer 131 may be between 300A-1000A (inclusive of endpoint values 300A and 1000A). The nitrogen content of the first layer 131 is lower than that of the second layer 132 .

The deposition rate of the second layer 132 is between 7A/s-10A/s (inclusive). The film layer thickness of the second layer 132 may be between 1500A-3800A (inclusive of endpoint values 1500A and 3800A). The nitrogen content of the second layer 132 is lower than that of the third layer 133 .

The deposition rate of the third layer 133 is less than 7A/s. The film thickness of the third layer 133 may be between 200A-1500A (inclusive of endpoints 200A and 1500A). There may be three types of third layers 133 , and the deposition speeds of the materials of the three types of third layers 133 are different. Specifically, the three types of third layers 133 are respectively a first sub-layer (not shown in the figure), a second sub-layer (not shown in the figure) and a third sub-layer (not shown in the figure). The deposition rate of the first sub-layer is between 5A/s-7A/s (endpoints 5A/s and 7A/s inclusive). The film sublayer thickness of the first sublayer may be between 500A and 1500A inclusive. The nitrogen content of the first sublayer is lower than that of the second sublayer. The deposition rate of the second sublayer is between 3A/s-5A/s (endpoints 3A/s and 5A/s inclusive). The film sublayer thickness of the second sublayer may be between 200A and 500A (inclusive). The nitrogen content of the second sublayer is lower than that of the third sublayer. The deposition rate of the third sublayer is less than 3A/s. The film sublayer thickness of the third sublayer may be between 200A and 500A (inclusive).

It can be understood that reducing the film forming rate can effectively increase the nitrogen content in the silicon nitride film layer. Further, the insulating property of the silicon nitride is improved, and finally the energy gap of the insulating layer 130 is increased.

Multiple implementations are included in the first possible embodiment. In the first implementation mode, please refer to FIG. 3 again. The insulating layer 130 includes a first layer 131, a second layer 132 and two third layers 133. In the direction where the insulating layer 130 faces the active layer 170, one The first layer 131 , a third layer 133 , a second layer 132 and another third layer 133 are stacked in sequence. Wherein, one third layer 133 may be the first sub-layer, and the other third layer 133 may be the third sub-layer. That is, a first layer 131 , a third sub-layer, a second layer 132 and a first sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170 .

For the second implementation manner, please refer to FIG. 4 , which is a second cross-sectional schematic diagram of the first possible embodiment of the insulating layer 130 provided in FIG. 2 . The insulating layer 130 includes two second layers 132 and two third layers 133, in the direction of the insulating layer 130 towards the active layer 170, one second layer 132, one third layer 133, another second layer 132 and Another third layer 133 is stacked in sequence. Wherein, the third layer 133 may be the first sub-layer, the second sub-layer or the third sub-layer.

Specifically, one second layer 132 , one first sub-layer, another second layer 132 and another first sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170 . Alternatively, one second layer 132 , one second sub-layer, another second layer 132 and another second sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170 . Alternatively, a second layer 132 , a third sub-layer, another second layer 132 and another third sub-layer are sequentially stacked on the surface of the substrate 110 facing the active layer 170 .

For the third implementation manner, please refer to FIG. 5 , which is a third cross-sectional schematic diagram of the first possible embodiment of the insulating layer 130 provided in FIG. 2 . The insulating layer 130 includes a first layer 131, a second layer 132 and two third layers 133. In the direction of the insulating layer 130 towards the active layer 170, a third layer 133, a first layer 131, a first layer 133 The second layer 132 and another third layer 133 are stacked in sequence. Wherein, the third layer 133 may be the first sub-layer, the second sub-layer or the third sub-layer.

Specifically, a third sublayer, a first layer 131 , a second layer 132 and a first sublayer are sequentially stacked on the surface of the substrate 110 facing the active layer 170 . Alternatively, a third sublayer, a first layer 131 , a second layer 132 and another third sublayer are sequentially stacked on the surface of the substrate 110 facing the active layer 170 . Alternatively, a second sublayer, a first layer 131 , a second layer 132 and a second sublayer are sequentially stacked on the surface of the substrate 110 facing the active layer 170 .

For the second possible embodiment, please refer to FIG. 6 . FIG. 6 is a schematic cross-sectional view of the first kind in the second possible embodiment of the insulating layer 130 provided in FIG. 2 . Different from the first embodiment, the insulating layer 130 further includes a fourth layer 134, and the material of the fourth layer 134 includes hafnium oxide. Hafnium oxide can be formed by plasma enhanced chemical vapor deposition, and the energy gap range of hafnium oxide is between 5.5ev-6.7ev. The film thickness of the fourth layer 134 may be between 200A-500A.

In a second possible embodiment two implementations are included. In the first implementation manner, a fourth layer 134 , a first layer 131 , a second layer 132 and a third layer 133 are sequentially stacked in a direction in which the insulating layer 130 faces the active layer 170 . Wherein, the third layer 133 may be the first sub-layer, the second sub-layer or the third sub-layer.

For the second implementation manner, please refer to FIG. 7 , which is a second cross-sectional schematic diagram of a second possible embodiment of the insulating layer 130 provided in FIG. 2 . The insulating layer 130 includes two second layers 132 , one third layer 133 and one fourth layer 134 . In the direction from the insulating layer 130 to the active layer 170 , a second layer 132 , a fourth layer 134 , another second layer 132 and a third layer 133 are stacked in sequence. Wherein, the third layer 133 may be the first sub-layer, the second sub-layer or the third sub-layer.

In the third possible embodiment, different from the second possible embodiment, the material of the fourth layer 134 is silicon oxide.

The third possible embodiment includes two implementation manners. Please refer to FIG. 6 again. In the first implementation manner, in the direction of the insulating layer 130 towards the active layer 170, a fourth layer 134, a first layer 131, a third layer 133 and a third layer 133 are sequentially Cascading settings. Wherein, the third layer 133 may be the first sub-layer, the second sub-layer or the third sub-layer.

In the second implementation manner, please refer to FIG. 7 again, the insulating layer 130 includes two second layers 132 , one third layer 133 and one fourth layer 134 . In the direction from the insulating layer 130 to the active layer 170 , a second layer 132 , a fourth layer 134 , another second layer 132 and a third layer 133 are stacked in sequence. Wherein, the third layer 133 may be the first sub-layer, the second sub-layer or the third sub-layer.

For a fourth possible embodiment, please refer to FIG. 8 , which is a schematic cross-sectional view of a fourth possible embodiment of the insulating layer 130 provided in FIG. 2 . Different from the previous three possible embodiments, the insulating layer 130 is a single-layer structure. Materials for the single-layer structure include hafnium oxide or silicon oxide.

The present application also explores the performance of the thin film transistor 101 through the following two formulas.

Formula 1:

I_ds=W/L*μ_eff*C_ox*[(V_gs-V_th)*V_ds-(V_ds^2)/2]

Formula 2:

V_(gs(ob))=V_GH-V_GL

In Formula 1, W/L represents the ratio of the channel width to the channel length of the thin film transistor 101, μ_eff represents the electron mobility, and C_ox represents the unit of the structure of the gate 120-insulating layer 130-active layer 170 in the thin film transistor 101 For area capacitance, V_gs represents the voltage difference between the gate 120 and the source, V_th represents the threshold voltage of the TFT 101 , and V_ds represents the voltage difference between the source and the drain.

In Equation 2, V_GH represents the voltage of the thin film transistor 101 when it is on, V_GL represents the voltage when the thin film transistor 101 is off, and V_(gs(on)) represents the voltage difference of the thin film transistor 101 .

It can be understood that, the larger the voltage difference of the thin film transistor 101 is, the larger the on-state current of the thin film transistor 101 is. Therefore, reducing the off-state voltage of the thin film transistor 101 can effectively increase the on-state current of the thin film transistor 101 , thereby improving the working stability of the thin film transistor 101 , thereby avoiding abnormal display of the display panel 1000 due to an unstable driving circuit.

In addition, in the thin film transistor 101, increasing the energy gap of the insulating layer 130 can increase the dielectric constant of the insulating layer 130, thereby increasing the capacitance per unit area of the gate 120-insulating layer 130-active layer 170 structure in the thin film transistor 101. (C_ox), so that the current can be increased to make the current sufficient to drive the display panel 1000 to display images.

The embodiments of the present application have been introduced in detail above, and specific examples have been used in this paper to illustrate the principles and implementation methods of the present application. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application; meanwhile, for Those skilled in the art will have changes in specific implementation methods and application scopes based on the ideas of the present application. In summary, the contents of this specification should not be construed as limiting the present application.

Claims (10)

1. A thin film transistor, comprising:

an insulating layer having an energy gap between 4.0ev and 6.7 ev;

the insulation layer is arranged on the active layer, and the material of the active layer comprises amorphous silicon; and

The first electrode and the second electrode are positioned on one side of the active layer, which is away from the insulating layer, the second electrode is arranged at intervals with the first electrode, and the second electrode is communicated with the first electrode through the active layer.

2. The thin film transistor according to claim 1, wherein the insulating layer is a stacked multilayer structure, the multilayer structure includes at least two of a first layer, a second layer, and a third layer, the first layer, the second layer, and the third layer are silicon nitride film layers formed by chemical vapor deposition, nitrogen content of the first layer is lower than nitrogen content of the second layer, and nitrogen content of the second layer is lower than nitrogen content of the third layer.

3. The thin film transistor according to claim 2, wherein the insulating layer includes two of the second layers and two of the third layers, and one of the second layers, one of the third layers, the other of the second layers, and the other of the third layers are stacked in this order in a direction in which the insulating layer faces the active layer.

4. The thin film transistor according to claim 2, wherein the insulating layer includes one of the first layer, one of the second layer, and two of the third layer, and one of the first layer, one of the third layer, one of the second layer, and the other of the third layer are stacked in this order in a direction in which the insulating layer faces the active layer.

5. The thin film transistor according to claim 2, wherein the insulating layer includes one of the first layer, one of the second layer, and two of the third layer, and one of the third layer, one of the first layer, one of the second layer, and the other of the third layer are stacked in this order in a direction in which the insulating layer faces the active layer.

6. The thin film transistor according to claim 2, wherein the insulating layer includes one of the first layer, the second layer, the third layer, and a fourth layer, and a material of the fourth layer includes hafnium oxide or silicon oxide;

one of the fourth layers, one of the first layers, one of the third layers, and one of the third layers are sequentially stacked in a direction in which the insulating layer faces the active layer.

7. The thin film transistor according to claim 2, wherein the insulating layer includes two of the second layers, one of the third layers, and one of the fourth layers, and a material of the fourth layer includes hafnium oxide or silicon oxide;

one of the second layers, one of the fourth layers, the other of the second layers and one of the third layers are stacked in this order in a direction in which the insulating layer faces the active layer.

8. The thin film transistor according to claim 1, wherein the insulating layer has a single-layer structure, and a material of the single-layer structure includes hafnium oxide or silicon oxide.

9. An integrated gate drive circuit comprising a plurality of drive units, each of said drive units comprising a thin film transistor according to any one of claims 1-8.

10. A display panel comprising a display module and the integrated gate drive circuit of claim 9, the integrated gate drive circuit controlling the display module to display an image.