CN116646308A - Integrated circuit and method of forming the same - Google Patents
Integrated circuit and method of forming the same Download PDFInfo
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- CN116646308A CN116646308A CN202310347052.5A CN202310347052A CN116646308A CN 116646308 A CN116646308 A CN 116646308A CN 202310347052 A CN202310347052 A CN 202310347052A CN 116646308 A CN116646308 A CN 116646308A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A method of processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reverse tone patterning process to selectively drive dipoles into the gate dielectric of some transistors while preventing the dipoles from entering the gate dielectric of other transistors. This process can be repeated to produce a plurality of transistors, each having a different threshold voltage. The embodiment of the application also discloses an integrated circuit and a forming method thereof.
Description
Technical Field
Embodiments of the application relate to integrated circuits and methods of forming the same.
Background
There is an increasing demand for computing for electronic devices, including smartphones, tablets, desktops, notebooks, and many other types of electronic devices. Integrated circuits provide computing power for these electronic devices. One way to increase the computational power of an integrated circuit is to include transistors with different threshold voltages.
The formation of integrated circuits including multiple transistors with different threshold voltages can be challenging. For 3D transistors such as FinFET transistors and GAA (gate-all-around) transistors, patterning processes to define different regions of an integrated circuit may be difficult. The high-K gate dielectric structure and the channel region may be damaged due to the patterning process. As a result, the threshold voltages of the various device regions may not meet design specifications. This may result in a transistor that does not function properly, a low wafer yield, and an electronic device that does not function properly. The threshold voltage of the resulting device region may not meet design requirements.
Disclosure of Invention
According to an aspect of an embodiment of the present application, there is provided a method of forming an integrated circuit, comprising: forming a first high-K dielectric layer over the first interfacial dielectric layer over the first channel region of the first transistor; forming a second high-K dielectric layer over the second interfacial dielectric layer over the second channel region of the second transistor; depositing a first hard mask layer over the first high-K dielectric layer and over the second high-K dielectric layer; patterning the first hard mask layer to expose the first high-K dielectric layer; depositing a first dipole induction layer on the first high-K dielectric layer and on the first hard mask layer over the second channel region; and performing a first thermal annealing process when the first dipole induction layer is located on the first high-K dielectric layer and on the first hard mask layer over the second channel region.
According to another aspect of an embodiment of the present application, there is provided a method of forming an integrated circuit, comprising: forming a first high-K dielectric layer over a first channel region of a first transistor; forming a second high-K dielectric layer over a second channel region of the second transistor; driving atoms from the first dipole induction layer into the first high-K dielectric layer by performing a first thermal annealing process when the first hard mask layer covers the second high-K dielectric layer and does not cover the first high-K dielectric layer; and driving atoms from the second dipole induction layer into the first high-K dielectric layer by performing a second thermal annealing process when the second dipole induction layer covers the first high-K dielectric layer and is not present over the second high-K dielectric layer.
According to yet another aspect of an embodiment of the present application, there is provided an integrated circuit including: a first transistor having a first threshold voltage and comprising: a plurality of stacked first channel regions; and a first high-K dielectric layer surrounding each of the first channel regions, wherein the first high-K dielectric layer is thinner on a top side of the uppermost first channel region than on a bottom side of the uppermost first channel region; a second transistor having a second threshold voltage different from the first threshold voltage and including: a plurality of stacked second channel regions; and a second high-K dielectric layer surrounding each of the second channel regions, wherein a thickness of the second high-K dielectric layer on a top side of the uppermost second channel region is the same as on a bottom side of the uppermost second channel region, wherein a thickness of the second high-K dielectric layer on the top side of the uppermost second channel region is greater than a thickness of the first high-K dielectric layer on the bottom side of the uppermost first channel region.
Drawings
The various aspects of the disclosure are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A-1J are cross-sectional views of an integrated circuit at different stages of a process according to some embodiments.
Fig. 2 is a cross-sectional view of an integrated circuit according to some embodiments.
Fig. 3A and 3B are cross-sectional views of integrated circuits according to some embodiments.
Fig. 4 is a cross-sectional view of an integrated circuit according to some embodiments.
Fig. 5A-5C are cross-sectional views of integrated circuits according to some embodiments.
Fig. 6A-6C are cross-sectional views of integrated circuits according to some embodiments.
Fig. 7 is a cross-sectional view of an integrated circuit according to some embodiments.
Fig. 8 is a flow chart of a method of processing an integrated circuit according to some embodiments.
Fig. 9 is a flow chart of a method of processing an integrated circuit according to some embodiments.
Detailed Description
In the following description, numerous thicknesses and materials of different layers and structures within an integrated circuit chip are described. Specific dimensions and materials are given by way of example for various embodiments. Those of skill in the art will recognize in light of the present disclosure that other dimensions and materials may be used in many cases without departing from the scope of the present disclosure.
The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, for ease of description, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly.
In the following description, certain specific details are set forth in order to provide a thorough understanding of the various embodiments disclosed. However, it will be understood by those skilled in the art that the present disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and fabrication techniques have not been described in detail so as not to unnecessarily obscure the description of the embodiments of the disclosure.
Throughout the specification and in the following disclosure, unless the context requires otherwise, the word "comprise" and variations such as "comprises" and "comprising" will be interpreted in an open, inclusive sense as "including but not limited to".
The use of ordinal numbers, such as first, second and third, does not necessarily imply a sequential sense, but rather may merely distinguish between multiple instances of an action or structure.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular component, structure, or feature described in connection with the embodiment is included in at least some embodiments. Thus, appearances of the phrases "in one embodiment," "in an embodiment," or "in some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular components, structures, or features may be combined in any suitable manner in one or more embodiments.
As used in this specification and this disclosure, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" generally includes "and/or" in its sense unless the content clearly dictates otherwise.
Embodiments of the present disclosure provide an integrated circuit having a plurality of transistor regions formed with different threshold voltages. In particular, embodiments of the present disclosure utilize inverse tone (inverted tone) patterning to perform dipole driving safely and efficiently in a process without significantly damaging the high-K gate dielectric layer. Embodiments of the present disclosure may utilize a combination of reverse tone and forward tone patterning to form multiple threshold voltage regions. The result is an efficient and effective formation of multiple threshold voltage regions within the tolerances specified by the Falcon programming language. This results in a properly functioning integrated circuit, higher wafer throughput, and better functioning electronic device.
As used herein, a dipole-driven inverse tone patterning process may include forming a hard mask layer prior to depositing a dipole-inducing layer. Specifically, a patterned hard mask is formed prior to depositing the dipole induction layer. Patterning of the hard mask exposes the high-K gate dielectric layer at the locations where the hard mask is removed. A dipole inducing layer is then deposited over the hard mask and exposed high-K gate dielectric layer. Subsequently, the drive-in process drives the dipoles to those locations where no hard mask remains.
In one example, the positive tone patterning process may include forming a dipole induction layer on the high-K gate dielectric, and then forming a hard mask on the dipole induction layer. The hard mask layer is then patterned. The dipole induction layer is removed at the location where the hard mask layer is removed. The dipole induction layer remains only under the remaining portion of the hard mask layer. A drive-in process is then performed to drive the dipole in the location where the hard mask (and dipole induction layer) remains.
Fig. 1A is a cross-sectional view of an integrated circuit 100 at an intermediate stage of processing according to some embodiments. In fig. 1A, transistors T1 and T2 are in an intermediate stage of the process. As will be explained in more detail below, the process of forming integrated circuit 100 results in transistors T1 and T2 having different threshold voltages.
Transistors T1 and T2 may correspond to full-gate-all-around transistors. The full-gate-all-around transistor structure may be patterned by any suitable method. For example, one or more photolithographic processes (including double patterning or multiple patterning processes) may be used to pattern the structures. Typically, a double pattern or multiple pattern process combines a lithographic and a self-aligned process, which allows for creating patterns with a smaller pitch than, for example, that obtained using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can then be used as a mask to pattern the full-ring gate structure. Further, the full-gate-all-around transistors may each include a plurality of semiconductor nanostructures corresponding to channel regions of the transistors. The semiconductor nanostructures may include nanoplatelets, nanowires, or other types of nanostructures. Full-gate-all-around transistors may also be referred to as nanostructure transistors.
Transistors T1 and T2 are formed in the same integrated circuit 100, although they may be located in different areas of the integrated circuit 100. As will be explained in more detail below, transistor T1 will incorporate dipole driving, while transistor T2 will not incorporate dipole driving. This results in transistors T1 and T2 having different threshold voltages.
The integrated circuit 100 includes a semiconductor substrate 102. In one embodiment, the semiconductor substrate 102 includes a single crystal semiconductor layer on at least a surface portion. The substrate 102 may comprise single crystal semiconductor materials such as, but not limited to, si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gasbs, and InP. The substrate 102 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). For example, the dopant is boron (e.g., BF 2 ) And phosphorus for p-type transistors.
The integrated circuit 100 may include one or more insulating components such as shallow trench isolation 103 separating the transistor T1 from the transistor T2 or separating the transistors T1 from each other and the transistors T2 from each other. Shallow trench isolation 103 may be used to separate groups of transistor structures formed in conjunction with semiconductor substrate 102. The shallow trench isolation 103 may comprise a dielectric material. The dielectric material for the shallow trench isolation 103 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), siOCN, siCN, fluorosilicate glass (FSG), or low K dielectric material formed by LPCVD (low pressure chemical vapor deposition), plasma enhanced CVD, or flowable CVD. Other materials and structures may be used for the shallow trench isolation 103 without departing from the scope of the present disclosure.
Transistors T1 and T2 comprise many of the same types of structures and materials. Thus, if both transistors T1 and T2 contain structures of the same name, the corresponding reference number for transistor T1 will contain the suffix "a" and the corresponding reference number for transistor T2 will contain the suffix "b".
Transistors T1 and T2 each include a plurality of channel regions 108a/108b. The channel regions 108a/108b correspond to the channel regions of transistors T1 and T2. Although not shown in FIG. 1A, after transistors T1 and T2 are completed, each channel region 108a/108b of transistors T1 and T2 will extend between the source/drain regions of transistors T1 or T2. In FIG. 1A, transistors T1 and T2 each include two vertically stacked channel regions 108a/108b. In practice, however, transistors T1 and T2 may each include more than two vertically stacked channel regions 108a/108b. The channel regions 108a/108b may correspond to semiconductor nanostructures. The semiconductor nanostructures may include semiconductor nanoplatelets, semiconductor nanowires, or other types of semiconductor nanostructures.
Channel regions 108a/108b are formed over substrate 102. The channel region 108a/108b may include one or more layers of Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb, or InP. In one embodiment, the channel regions 108a/108b are the same semiconductor material as the substrate 102. Other semiconductor materials may be used for the channel regions 108a/108b without departing from the scope of the present disclosure.
The width of the channel regions 108a/108b may be between 5nm and 25 nm. The channel regions 108a/108b may be between 4nm and 8nm thick. The distance D between the channel regions 108a/108b may be between 6nm and 15 nm. Other thicknesses and dimensions may be used for the channel regions 108a/108b without departing from the scope of this disclosure.
In FIG. 1A, each channel region 108a/108b of transistors T1 and T2 is covered by an interfacial dielectric layer 110a/110 b. Interfacial dielectric layers 110a/110b may be used to create a good interface between channel regions 108a/108b and a subsequent dielectric layer, as described in more detail below. The interfacial dielectric layers 110a/110b may help suppress mobility degradation of charge carriers in the channel regions 108a/108b that serve as channel regions for transistors T1 and T2.
Interfacial dielectric layer 110a/110b may comprise a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric material. The interfacial dielectric layer 110a/110b may comprise a low-K dielectric that is opposite a high-K dielectric (such as hafnium oxide or other high-K dielectric material) that is opposite the gate dielectric of the transistor. The high-K dielectric may comprise a dielectric material having a dielectric constant that is higher than the dielectric constant of silicon oxide. In the example of fig. 1A, interfacial dielectric layer 110a/110b is silicon dioxide, although other materials may be used without departing from the scope of the present disclosure.
The interfacial dielectric layers 110a/110b may be formed by a thermal oxidation process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process. The interfacial dielectric layer 110a/110b may have a thickness between 0.5nm and 1.5 nm. One factor to consider when selecting the thickness of interfacial dielectric layer 110a/110b is to leave sufficient space between channel regions 108a/108b to deposit and etch various materials, as will be explained in more detail below. Other materials, deposition processes, and thicknesses may be used for interfacial dielectric layer 110a/110b without departing from the scope of this disclosure.
Transistors T1 and T2 each include a high-K dielectric layer 112a/112b. high-K dielectric layers 112a/112b are located over interfacial dielectric layers 110a/110b. Interfacial dielectric layers 110a/110b separate high-K gate dielectric layers 112a/112b from channel regions 108a/108 b. high-K dielectric layers 112a/112b and interfacial dielectric layers 110a/110b together form the gate dielectric of transistors T1 and T2. The high-K dielectric layers 112a/112b and the interfacial dielectric layers 110a/110b physically separate the channel regions 108a/108b from the gate metal that will be deposited in a later step. The high-K dielectric layers 112a/112b and the interfacial dielectric layers 110a/110b isolate the gate metal from the channel regions 108a/108b, which correspond to the channel regions of the transistors.
The high-K dielectric layer 112a/112b includes one or more layers of dielectric material, such as HfO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zirconia, alumina, titania, hafnia-alumina (HfO 2 -Al 2 O 3 ) Alloys, other suitable high-K dielectric materials, and/orA combination thereof. The high-K dielectric layers 112a/112b may be formed by CVD, ALD, or any suitable method. In one embodiment, high-K dielectric layers 112a and 112b are formed using a highly conformal deposition process (such as ALD) to ensure that the formation of the gate dielectric layer around each channel region 108a and 108b has a uniform thickness. In one embodiment, the thickness of high-K dielectric layers 112a and 112b is in the range of about 1nm to about 2 nm. Other thicknesses, deposition processes, and materials may be used for the high-K dielectric layers 112a/112b without departing from the scope of the present disclosure.
In FIG. 1B, a hard mask layer 114 is deposited over the high K dielectric layers 112a/112B of transistor T1 and transistor T2. The hard mask layer 144 may include SiO x (wherein x represents the concentration of oxygen), alO x 、ZrO 2 、SiN、TiN、TiO x 、ZrO x One or more of AlN, tiSiN, or other suitable material. The hard mask layer 114 may have a thickness between 1nm and 5 nm. Although the hard mask layer 114 shown in FIG. 1B completely fills the gap between the channel regions 108a/108B of transistors T1 and T2, in practice, the thickness of the hard mask layer 144 may be selected to ensure that the gap remains between the channel regions 108a/108B of transistors T1 and T2. This helps ensure that the hard mask layer 114 can be reliably removed from between the channel regions 108a/108b at the appropriate time. The hard mask layer 114 may be deposited by a PVD process, an ALD process, a CVD process, or other suitable deposition process. The hard mask layer 114 may have other thicknesses, materials, and deposition processes without departing from the scope of the present disclosure.
In fig. 1C, a layer of photoresist 116 is deposited. A photoresist 116 is deposited on the hard mask layer 114. The layer of photoresist 116 may include a multi-layer photoresist including a bottom layer and a top layer. The layer of photoresist 116 may be deposited by standard photoresist deposition techniques including vapor deposition, diffusion deposition, spin-on coating, or other suitable processes.
In fig. 1D, a layer of photoresist 116 is patterned. The layer of photoresist 116 is patterned to expose the hard mask layer 114 of transistor T1. The hard mask layer 114 of transistor T2 is covered by a layer of photoresist 116. The layer of photoresist 116 may be patterned by exposing the layer of photoresist 116 to light through a photolithographic mask. Thus, a layer of photoresist 116 may be deposited and patterned using standard photolithographic techniques. The material of hard mask 114 is selected to enable photoresist 116 to adhere to hard mask 144.
In fig. 1E, an etching process is performed on the integrated circuit 100. Specifically, an etching process is performed on portions of integrated circuit 100 not covered by photoresist 116. The etching process etches the hard mask layer 114 from the transistor T1. The etching process may be selected to selectively etch the hard mask layer 114 relative to the high-K dielectric layer 112a/112 b. This ensures that hard mask layer 114 is removed at the location of transistor T1 without etching or damaging high-K dielectric layer 112a. The etching process may include wet etching, dry etching, atomic Layer Etching (ALE) process, timed etching, or other suitable etching techniques. Because transistor T2 is still covered by photoresist 116, the etching process does not remove hard mask layer 114 at the region of transistor T2.
In fig. 1F, photoresist layer 116 is removed. Photoresist layer 116 may be removed by an ashing process. The ashing process completely removes photoresist layer 116. The etching process may also have an effect on the hard mask layer 114 at transistor T2 and the high K dielectric layer 112a at transistor T1. Other suitable methods for photoresist removal may be used without departing from the scope of the present disclosure.
In fig. 1F, a dipole induction layer 118 is deposited at the regions of transistors T1 and T2. The dipole induction layer 118 is deposited directly on the high-K dielectric layer 112a at the transistor T1. The dipole induction layer 118 is deposited directly on the hard mask layer 114 of transistor T2. Although fig. 1F shows that there is no dipole induction layer 118 between the channel regions 108b of transistor T2, the hard mask layer 114 does not fill the entire space between the channel regions 108b, as described previously in some embodiments. In these embodiments, dipole induction layer 118 will be located on hard mask layer 114 between channel regions 108b of transistor T2.
The dipole induction layer 118 may include one or more of La, Y, al, sr, er, sc, ti or Nb. The material of dipole induction layer 118 may be selected to have a high etch selectivity relative to high-K dielectric layers 112a/112b. Thus, during removal of dipole induction layer 118, little or no high-K dielectric layer 112a/112b is removed. The thickness of the dipole induction layer 118 may be between 0.5nm and 1.5 nm. A dipole induction layer of less than 1.5nm may be advantageous to keep the total thickness of the gate dielectric low. The dipole induction layer 118 may be deposited by a Physical Vapor Deposition (PVD) process, an ALD process, a CVD process, or other suitable deposition process. Other thicknesses, materials, and deposition processes may be used for dipole induction layer 118 without departing from the scope of this disclosure.
One purpose of the dipole induction layer 118 is to adjust the threshold of the transistor T1 according to the threshold voltage of the transistor T2. The dipole induction layer 118 will be used to create a dipole layer on the transistor T1 interface dielectric layers 110a/110 b. The dipole layer generated from the dipole induction layer 118 has a dipole effect that increases or decreases the influence of the voltage applied to the gate electrode when the transistor T1 is turned on or off. The dipole dopants in the dipole induction layer 118 are driven into the adjacent dielectric layers to modulate the effective work function of the transistor, thereby increasing or decreasing the threshold voltage of the transistor T1. In some embodiments, the materials of dipole induction layer 118, high-K dielectric layers 112a/112b, and interfacial dielectric layers 110a/110b are selected to result in a dipole layer that lowers the threshold voltage of transistor T1. As will be explained in more detail below, the process of creating a dipole layer from dipole induction layer 118 results in substantially no dipole layer on interface layer 110b of transistor T2.
In fig. 1G, a thermal annealing process is performed on the integrated circuit 100. The thermal annealing process may include exposing the integrated circuit 100 to an elevated temperature for a selected duration. For example, the thermal annealing process may include exposing the integrated circuit to a temperature between 400 ℃ and 1000 ℃. The duration of the thermal annealing process may be between 0.5 seconds and 30 seconds. Other durations and temperatures may be used without departing from the scope of the present disclosure.
The thermal annealing process bonds atoms from the dipole induction layer to at least one of the interfacial dielectric layer 110a and the high-K dielectric layer 112a in a manner that creates a dipole layer. The dipole layer may be generated by at least one of the polarized dipole induction layer 118, the interfacial dielectric layer 110a, and the high-K dielectric layer 112 a. In an example where interfacial dielectric layer 110a is silicon dioxide, the dipole layer may be a dipole oxide. The dipole oxide is composed of an oxide of the material of the dipole induction layer 118. Depending on the material of dipole induction layer 118, the dipole oxide may include an oxide of Y, la, al, sr, er, sc, nb or other material.
The presence of the dipole layer in transistor T1 results in a difference in threshold voltage between transistor T1 and transistor T2. The threshold voltage of transistor T1 may be 300mV lower than the threshold of transistor T2, although other threshold voltage variations may occur without departing from the scope of the present disclosure. In other embodiments, the threshold voltage of transistor T1 may be higher than the threshold voltage of transistor T2.
Because hard mask layer 114 is present at transistor T2, particularly between dipole induction layer 118 and high-K dielectric layer 112b, the dipole is not driven into high-K dielectric layer 112b at transistor T2. Instead, the dipoles are driven into the hard mask layer 144. Thus, high-K dielectric layer 112b and interfacial dielectric layer 110b of transistor T2 do not receive dipoles. The result is that the threshold voltage of transistor T2 is unchanged.
In fig. 1H, an etching process is performed on the integrated circuit 100. The etching process etches the dipole induction layer 118 from the transistors T1 and T2. Specifically, the etching process removes the dipole induction layer 118 from the hard mask layer 114 of the transistor T2. The etching process removes dipole induction layer 118 from over high-K dielectric layer 112a of transistor T1. The etching process also removes the hard mask layer 114 from over the transistor T2. The result is to expose both of the high-K dielectric layers 112a/112b of transistors T1 and T2. The etching process may include an isotropic etching process that etches the hard mask layer 114 and the dipole induction layer 118 uniformly in all directions. The duration of the etching process is selected to completely remove the hard mask layer 114 and the dipole induction layer 118 from the channel region 108b of the transistor T2. The etching process may include wet etching, dry etching, ALE process, timed etching, or other suitable etching process. The etching process may include a plurality of etching steps. For example, a first etching step may be performed to remove the dipole induction layer 118. A second etching step may be performed to remove the hard mask layer 114. Other types of etching processes may be used without departing from the scope of this disclosure.
As will be set forth in more detail below, by repeating the processes described with respect to fig. 1A-1H, more than two different threshold voltages may be provided using the inverse tone patterning process described with respect to fig. 1A-1H. For example, if four transistors of different threshold voltages are required, the process in FIGS. 1A-1H is performed to drive dipoles into transistors 1 and 2, while transistors 3 and 4 are protected by hard mask layer 114. This will change the threshold voltages of transistors 1 and 2 by a first amount. The hard mask layer and the dipole induction layer are removed from all transistors. This process is then performed again with the dipole inducing material or parameter to drive the dipoles to transistors 1 and 3, while transistors 2 and 4 are protected by hard mask layer 114. This will change the threshold voltages of transistor 1 and transistor 3 by a second amount different from the first amount. As a result, all transistors now have different threshold voltages by using the inverse tone patterning process twice. As will be explained in more detail below, more than four different threshold voltages may be obtained.
The process described in fig. 1A-1H has some advantages over alternative processes that may form a dipole layer at transistor T1. Specifically, the process described with respect to fig. 1A-1H utilizes a reverse tone patterning process to form a dipole in transistor T1. An alternative process is a positive tone patterning process. In the positive tone patterning process, a dipole layer is first deposited directly on the high-K dielectric layers 112a/112b of both transistor T1 and transistor T2. A hard mask layer is then deposited, followed by a photoresist. The photoresist is patterned to expose the hard mask at transistor T2. The hard mask and dipole induction layer are then removed from transistor T2, while the dipole induction layer and hard mask layer at transistor T1 are protected by photoresist. Then, the photoresist on the hard mask layer is removed from the transistor T1 using an etching process and an ashing process. This exposes the dipole induction layer at the transistor T1. Then a drive-in process is performed. Since the dipole induction layer exists only at the transistor T1, a dipole is formed only at the transistor T1, thereby changing the threshold voltage of the transistor T1.
However, the positive tone patterning process may cause several problems. For example, during the etching process and ashing process, the positive tone patterning causes damage to the high K dielectric layer at transistor T2. For example, in a positive tone patterning process, a dipole inducing layer may be first deposited on a high-K gate dielectric layer. A hard mask layer may then be deposited on the dipole induction layer. A layer of photoresist may then be deposited over the hard mask. The layer of photoresist may then be patterned by a photolithographic process. Then, the etching process removes the hard mask layer and the dipole induction layer according to the pattern of the photoresist layer. An ashing process may then be performed to remove the remaining photoresist. Such etching and ashing processes may damage the high-K dielectric layer at the transistor T1 and reduce the thickness of the high-K dielectric layer at the transistor T1. Such damage may include thickness loss, increased roughness, oxygen vacancy generation, and other potential problems. This may result in equivalent oxide thickness changes and variations, thereby negatively affecting the threshold voltage. Damage and thickness loss of the high-K dielectric layer results in unexpected variations in the threshold voltage of transistor T1. If more than two different threshold voltages are required and two positive tone patterning processes are used, the damage to the high K dielectric layer is even greater, while the threshold voltage variation of transistors that were not intended to have threshold voltage variation is even greater.
The inverse tone patterning process described with respect to fig. 1A-1H avoids the disadvantages of the positive tone patterning process. In particular, the high-K dielectric layer of the transistor T2, which is not expected to change the threshold voltage, is hardly damaged. This is because the etching process is mainly performed in a region where the threshold voltage needs to be changed. In the example of a P-type transistor with an N-type dipole, a very low threshold voltage may be specified for a high performance device. For such P-type transistors, it may be highly desirable to have a set of transistors with unchanged threshold voltages. The back tone process is capable of providing such ultra low threshold voltage P-type transistors, wherein a high K dielectric layer with good thickness quality is utilized to provide a high P-type work function close to the bandgap voltage. Degradation of the high-K dielectric layer lowers the P-type work function, thereby increasing the threshold voltage. N-type transistors with P-type dipoles have similar advantages. The processes described herein may be utilized for both P-type and N-type transistors with P-dipoles or N-dipoles.
In some embodiments, the inverse tone patterning process may be combined with the positive tone patterning process. This is used in cases where more than two different threshold voltages are required. In some cases, it may be acceptable to suffer from a single positive tone patterning process. In these cases, a back tone process may be used for the first dipole driving process. The positive tone patterning process may then be used for the second dipole driving process. More details regarding the combination of the reverse tone and positive tone patterning processes will be provided below.
In fig. 1I, a gate metal 120 is deposited around the channel regions 108a/108b of transistors T1 and T2. Gate metal 120 is separated from channel regions 108a/108b by interfacial dielectric layers 110a/110b and high-K dielectric layers 112a/112 b. In the view of fig. 1I, gate metal 120 is shown as a single gate metal. In practice, however, the gate metal 120 may comprise a plurality of separate metal layers. For example, gate metal 120 may include a relatively thin glue layer, barrier layer, or work function layer initially deposited on high-K dielectric layer 112a/112 b. These initial gate metal layers may include one or more of titanium nitride, tantalum nitride, tungsten nitride, tantalum, or other materials. After depositing the initial gate metal layer, a gate fill material may be deposited. The gate fill material may include tungsten, titanium, tantalum, cobalt, aluminum, or copper. The initial gate metal layer and the gate fill material together comprise gate metal 120. The various layers of gate metal 120 may be deposited by one or more deposition processes, including PVD, CVD, ALD or other suitable deposition processes. Other materials, layer types, and deposition processes may be used for the gate metal 120 without departing from the scope of the present disclosure.
Fig. 1J is a cross-sectional view of an integrated circuit 100 according to one embodiment. The view of fig. 1J is taken along section line 1J of fig. 1I. The view of fig. 1J more fully shows the overall structure of transistor T1. The structure of transistor T2 will be substantially similar to transistor T1.
Fig. 1J shows a dielectric barrier 140 between the semiconductor substrate 102 and the source/drain regions 128. The dielectric barrier 140 may be used to electrically isolate the source/drain regions 128 from the semiconductor substrate. The dielectric material for the dielectric barrier layer 140 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), siOCN, siCN, fluorosilicate glass (FSG), or low K dielectric material formed by Low Pressure CVD (LPCVD), plasma CVD, or flowable CVD. Other materials and structures may be used for the dielectric barrier 140 without departing from the scope of the present disclosure.
The integrated circuit 100 includes source/drain regions 128. Source/drain regions 128 comprise a semiconductor material. Source/drain regions 128 may be epitaxially grown from channel region 108 a. Source/drain regions 128 may be epitaxially grown from channel region 108 or from substrate 102 prior to forming channel region 108 a. In the case of an N-type transistor, the source/drain regions 128 may be doped with N-type dopant species. In the case of a P-type transistor, the source/drain regions 128 may be doped with a P-type dopant species.
Channel region 108a extends between source/drain regions 128. As previously described, the channel region 108a corresponds to the channel region of the transistor T1. By applying a selected voltage to the gate metal 120 and the source/drain regions 128, current flows through the channel region 108a between the source/drain regions 128.
Fig. 1J also shows an internal spacer 138 located between the source/drain regions 128 and the gate metal 120. More specifically, the inner spacers 138 are located between the high-K dielectric layer 112a and the source/drain regions 128. The inner spacer 138 may comprise one or more dielectric materials including silicon nitride, siON, siOCN, siCN, silicon oxide, or other dielectric materials. Other dielectric materials may be used for the inner spacer 138 without departing from the scope of the present disclosure.
The view of fig. 1J shows interfacial dielectric layer 110a in contact with channel region 108a. high-K dielectric layer 112a is in contact with interfacial dielectric layer 110a. Gate metal 120 is in contact with high K dielectric layer 112 a.
The integrated circuit 100 includes an interlayer dielectric layer 132 located over the source/drain regions 128. The interlayer dielectric layer 132 may include one or more of silicon oxide, silicon nitride, siCOH, siOC, or an organic polymer. Other types of dielectric materials may be used for interlayer dielectric layer 132 without departing from the scope of the present disclosure.
The integrated circuit 100 includes silicide regions 130 formed in the source/drain regions 128. Silicide regions 130 may comprise titanium silicide, cobalt silicide, or other types of silicides. A contact plug 134 is formed in the interlayer dielectric layer 132. The contact plug 134 may include cobalt or other suitable conductive material. The contact plug 134 may be used to apply a voltage to the source/drain region 128 of the transistor T1. The contact plug 134 may be surrounded by a titanium nitride glue layer.
Gate metal 120 is deposited in a trench formed in interlayer dielectric layer 132. Gate metal 120 also surrounds channel region 108a as shown in fig. 1I. Sidewall spacers 136 are located in trenches in the interlayer dielectric layer 132 and surround the gate metal 120. Sidewall spacers 136 may comprise a plurality of dielectric layers including one or more of silicon nitride, silicon oxide, silicon carbide, or other suitable dielectric materials. high-K dielectric layer 112a is also located on the sidewalls of the trench between sidewall spacers 136 and gate metal 120. Other materials, structures, and features may be included in the full-gate-all-around transistor T1 and, correspondingly, the full-gate-all-around transistor T2 without departing from the scope of this disclosure.
In some embodiments, the process of forming the full-gate-all-around transistors T1 and T2 of fig. 1A-1J may include forming alternating stacks of first and second epitaxial semiconductor layers over the substrate 102. The process may include patterning the semiconductor stack to form a fin, and forming a shallow trench isolation region around the fin. A dummy gate structure comprising polysilicon material may then be formed across the fin. Then, a gate spacer 136 may be formed on sidewalls of the dummy gate. The fin may be patterned to form recesses for source/drain regions 128. The first epitaxial layer may then be recessed to have a deformed gap in which the inner spacers 138 are formed. Source/drain regions 128 are then formed. An interlayer dielectric layer 132 may then be formed. The dummy gate structure and the first epitaxial layer are then removed to define a channel region 108a from the second epitaxial layer. An interlayer dielectric layer 110a and a high-K dielectric layer 112a are then deposited over the channel region 108a. A reverse tone patterning process may then be performed to generate a plurality of threshold voltages. Gate metal 120 may then be deposited around channel region 108a. Various other processes may be utilized to form a full-gate-all-around transistor without departing from the scope of the present disclosure.
Fig. 2 is a cross-sectional view of a portion of a second transistor T2 and a first transistor T1, in accordance with some embodiments. Specifically, fig. 2 shows one channel region 108a of the transistor T1 and one channel region 108b of the transistor T2. In some embodiments, the processes described with respect to fig. 1A-1H may result in certain characteristics of the channel region 108a of the transistor T1 performing dipole driving and the channel region 108a of the transistor T2 not performing dipole driving. For example, for transistor T1, there may be a thickness difference in the thickness Tht of high-K dielectric layer 112a on top of channel region 108a as compared to the thickness Thb of high-K dielectric layer 112a on the bottom of channel region 108 a. Specifically, the thickness Tht of the transistor T1 is smaller than the thickness Thb of the transistor T1. In some embodiments, this thickness difference between the top and bottom may occur only in the highest channel region 108a of transistor T1. Thus, in some embodiments, the top channel region 108a of transistor T1 has a difference between the thickness of the high-K dielectric layer 112a on the top side and the thickness of the high-K dielectric layer 112a on the bottom side, while the lower channel region 108a of transistor T1 has no difference between the thickness of the high-K dielectric layer 112a on the top side and the thickness of the high-K dielectric layer 112a on the bottom side.
In some embodiments, for transistor T2, there is no difference between thickness Tht and thickness Thb for any channel region 108b due to the presence of hard mask layer 114 between high-K dielectric layer 112b and dipole induction layer 118. Further, the thickness Tht and thickness Thb of all the channel regions 108b of the transistor T2 may be greater than the thickness Tht and thickness Thb of all the channel regions 108a of the transistor T1. The thickness difference between high-K dielectric layer 112b of transistor T2 and high-K dielectric layer 112a of transistor T1 may beTo->Between them.
In some embodiments, there may be some intermixing of the hard mask layer 114 and the high-K dielectric layer 112b at the channel region 108b of the transistor T2. This may be due to the presence of the hard mask layer 114 on the high-K dielectric layer 112b during the thermal annealing process driving in the dipole. The thermal annealing process may form a thin hybrid layer 122 on the surface of the high-K dielectric layer 112b of transistor T2. The hybrid layer will include a trace (trace) of the material of high-K dielectric layer 112b and the material of hard mask layer 114. After depositing gate metal 120, hybrid layer 122 may still be present between high-K dielectric layer 112b at transistor T2 and gate metal 120. The thickness of the hybrid layer 122 may be at To->Between them. Alternatively, the hybrid layer may be partially or completely removed before forming the gate metal 120.
As previously described, if only a positive tone patterning process is used, no desired change in the threshold voltage of the transistor will result in a significant reduction in the thickness of the high K dielectric layer. In some embodiments, this does not occur for a reverse tone patterning process.
Fig. 3A and 3B are cross-sectional views of integrated circuit 100 at intermediate stages of a process according to some embodiments. Fig. 3A and 3B illustrate a formation process of transistors each having a different threshold voltage. Fig. 3A and 3B utilize the inverse tone patterning principles described with respect to fig. 1A-1I.
Fig. 3A shows an integrated circuit 100 comprising four transistors T1-T4. In practice, the integrated circuit 100 will include a plurality of transistors T1, a plurality of transistors T2, a plurality of transistors T3, and a plurality of transistors T4. One of each type of transistor is shown in fig. 3A. The cross-sectional view of fig. 3A is simplified to show only a portion of the channel regions 108a-108d of each transistor. Interfacial dielectric layers 110a-110d are located over channel regions 108a-108d, respectively. high-K dielectric layers 112a-112d are respectively located on interfacial dielectric layers 110a-110 d. Furthermore, while embodiments herein describe transistors that include semiconductor nanostructures, in practice the principles of the present disclosure extend to other types of transistors.
Fig. 3A shows a process stage corresponding to fig. 1G. Specifically, the inverse tone patterning process is performed such that the dipole induction layer 118 is located on the high-K dielectric layers 112a/112b of the transistors T1 and T2. A hard mask layer 114 is located over the high K dielectric layers 112c/112d of transistors T3 and T4. The dipole induction layer 118 is located on the hard mask layer 114 at transistors T3 and T4. The thermal annealing process described with respect to fig. 1G is performed to drive dipoles into the high-K dielectric layer 112a/112b and the interfacial dielectric layer 110a/110b at transistors T1 and T2. At the same time, hard mask layer 114 protects high-K dielectric layers 112c/112d at transistors T3 and T4 from receiving dipoles. Thus, in fig. 3A, transistors T1 and T2 receive the first dipole-driving process, while transistors T3 and T4 remain unchanged. After the thermal annealing process, dipole induction layer 118 is removed from all transistors and hard mask layer 114 is removed from transistors T3 and T4.
In fig. 3B, the process steps of fig. 1A-1H are again performed, except that the photolithographic mask is patterned such that transistors T2 and T4 are still covered by hard mask layer 114. The dipole induction layer 118 is deposited directly on the high-K dielectric layers 112a/112c at transistors T1 and T3. A dipole induction layer 118 is deposited on the hard mask layer 114 of transistors T2 and T4. A thermal annealing process is performed to drive dipoles into the high-K dielectric layers 112a/112c and the interfacial dielectric layers 110a/110c of transistors T1 and T3. Due to the presence of the hard mask layer 114, the high-K dielectric layers 112b/112d of the transistors T2 and T4 are protected from the dipole driving process. The hard mask layer 114 and dipole induction layer 118 may then be removed, and a gate metal 120 may be deposited over all transistors T1-T4.
As a result of the process described with respect to fig. 3A and 3B, each transistor T1-T4 has a different threshold voltage. It should be noted that the first dipole-driving process (fig. 3A) results in a first change in the threshold voltage of the transistor receiving the first dipole-driving process. The second dipole-driving process (fig. 3B) results in a second change in the threshold voltage of the transistor receiving the second dipole-driving process. The first and second variations of the threshold voltage are different from each other. Such differences may be based on the use of different materials for the dipole induction layer 118 in fig. 3B, different lengths of time or temperature for the thermal annealing process, and even different thicknesses for the dipole induction layer 118 than the dipole induction layer 118 in fig. 3B. The result is that the transistor T1 receives both the first and second dipole-driving processes and has a threshold voltage Vt1. The second transistor T2 receives only the first dipole driving process and has a threshold voltage Vt2. The transistor T3 receives only the second dipole driving process and has a threshold voltage Vt3.
The transistor T4 does not receive any dipole driving-in process and has a threshold voltage Vt4. Since transistor T4 is protected by hard mask layer 114 during each dipole driving process, transistor T4 may receive less damage to high-K dielectric layer 112 d. This may enable the transistor T4 to be used as a high performance device.
Fig. 4 is a cross-sectional view of integrated circuit 100 according to some embodiments. Fig. 4 shows portions of transistors T1-T8. As shown in fig. 3A and 3B, portions of channel regions 108a-108h, interfacial dielectric layers 110a-110h, and high-K dielectric layers 112a-112h are shown for each transistor T1-T8. In fig. 4, three dipole driving-in processes are performed using three inverse tone patterning processes. In other words, although fig. 3A and 3B illustrate two inverse tone patterning and dipole-driving processes, in fig. 4, a third dipole-driving process is performed to provide different threshold voltages for eight transistors.
Transistors T1-T4 receive the first dipole driving process, while transistors T5-T8 are protected by hard mask layer 114. Transistors T1, T2, T5, and T6 receive the second dipole-driving process, while transistors T3, T4, T7, and T8 are protected by hard mask layer 144. Transistors T1, T3, T5, and T7 receive the third dipole-driving process, while transistors T2, T4, T6, and T8 are protected by hard mask layer 114. As previously described, each of the dipole driving processes provides a different threshold voltage variation. The transistor T1 receives all three dipole driving processes and has a threshold voltage Vt1. The transistor T2 receives the first and second dipole driving processes and has a threshold voltage Vt2. The transistor T3 receives the first and third dipole driving processes and has a threshold voltage Vt3. The transistor T4 receives the first dipole driving process and has a threshold voltage Vt4. The transistor T5 receives the second and third dipole driving processes and has a threshold voltage Vt5. The transistor T6 receives the second dipole driving process and has a threshold voltage Vt6. The transistor T7 receives the third dipole driving process and has a threshold voltage Vt7. The transistor T8 does not receive any dipole driving process and has a threshold voltage Vt8. Each of the transistors T1-T8 has a different threshold voltage from each other.
Fig. 5A-5C are cross-sectional views of integrated circuit 100 at intermediate stages of processing according to some embodiments. Fig. 5A-5C illustrate a process of providing transistors (or transistor regions thereof) T1-T4 having different threshold voltages using a combination of positive tone patterning and negative tone patterning. Fig. 5A and 5B illustrate a positive tone patterned dipole driving-in process. Fig. 5C illustrates a reverse tone patterned dipole driving-in process.
In fig. 5A, the positive tone patterning process begins with the direct deposition of a dipole induction layer 118 on the surface of the high-K dielectric layers 112a-112d of all four transistors T1-T4. The dipole induction layer 118 may be deposited using the materials and deposition processes described with respect to fig. 1F. A hard mask layer 114 is then deposited over the dipole induction layer 118 of all transistors T1-T4 using the processes and materials described with respect to fig. 1B. A layer of photoresist 116 is then deposited over the hard mask layer 114 in the process described with respect to fig. 1C. The layer of photoresist 116 is then patterned using the process described with respect to fig. 1D to expose hard mask layer 114 at transistors T3 and T4. The hard mask layer 114 is then etched in the presence of the patterned photoresist, as described with respect to fig. 1E. The result is that hard mask layer 114 is removed at transistors T3 and T4, exposing dipole induction layer 118 of transistors T3 and T4. These steps produce the structure shown in fig. 5A.
In fig. 5B, an etching process is performed in the presence of the hard mask layer 114 and the photoresist layer 116 to completely remove the dipole induction layer 118 of the transistors T3 and T4. An ashing process is then performed, followed by an etching process to remove the remaining photoresist layer 114 and the remaining hard mask layer 114 of the transistors T1 and T2. This leaves the structure shown in fig. 5B. In practice, the removal of the dipole induction layer 118 from the transistors T3 and T4 may occur in the same etching step that removes the hard mask layer 114 from the transistors T3 and T4. A thermal annealing process is then performed to drive the dipoles into the high-K dielectric layers 112a/112b of transistors T1 and T2. The thermal annealing process may be substantially as described with respect to fig. 1G.
The steps shown in fig. 5A and 5B help illustrate that the dipole induction layer 118 is initially deposited directly on the high-K dielectrics 112a-112d of all transistors T1-T4. In addition, etching and ashing processes that remove photoresist 116 and hard mask layer 114 prior to the thermal annealing process may cause damage to high-K dielectric layers 112c/112d of transistors T3 and T4. While this may be undesirable in some cases, in some embodiments, damage from a single such positive tone patterning process may result in an amount of damage to high K dielectric layer 112d that is sufficiently small to be acceptable. Since the subsequent dipole induction process is a reverse tone patterning process that is damage-free to the high K dielectric layer 112d, the combination of the positive tone and reverse tone patterning processes may result in different threshold voltages with acceptable amounts of damage.
In fig. 5C, a reverse tone patterning process as described with respect to fig. 3B is performed. This results in the dipole induction layer 118 being formed directly on the surface of the high-K dielectric layers 112a/112c of transistors T1 and T3 and the hard mask layer 114 of transistors T2 and T4. A thermal annealing process is then performed to drive dipoles into the high-K dielectric layers 112a/110c and the interfacial dielectric layers 110a/110c of transistors T1 and T3.
In fig. 5A-5C, the transistor T1 receives both the first and second dipole induction processes and has a threshold voltage Vt1. The transistor T2 receives only the first dipole induction process and has a threshold voltage Vt2. The transistor T3 receives only the second dipole induction process and has a threshold voltage Vt3. Transistor T4 does not receive any dipole induction process and has a threshold voltage Vt4.
Fig. 6A-6C are cross-sectional views of intermediate process stages of an integrated circuit 100 according to some embodiments. Fig. 6A and 6B illustrate the formation of transistors T1-T4 each having a different threshold voltage. The process of fig. 6A and 6B is similar to the process of fig. 5A-5C except that the inverse tone patterning process is performed first, followed by the positive tone patterning process.
In fig. 6A, a reverse tone patterning process is performed substantially as described with respect to fig. 3A. The dipole induction layer 118 is located directly on the surface of the high-K dielectric layers 112a/112b of transistors T1 and T2. The hard mask layer 114 is located between the high-K dielectric layers 112c/112d and the dipole induction layer 118 of transistors T3 and T4. A thermal annealing process is performed to drive the dipoles into the high-K dielectric layers 112a/112b and the interfacial dielectric layers 110a/110b at the transistors T1 and T2, while the hard mask layer 114 protects the high-K dielectric layers 112c/112d at the transistors T3 and T4 from the dipole driving process.
In fig. 6B, a positive tone patterning process is performed as described with respect to fig. 5A and 5B. Dipole induction layer 118 is located on high-K dielectric layers 112a/112c of transistors T1 and T3. The dipole induction layer 118 at transistors T2 and T4 is removed. A thermal annealing process is then performed to drive dipoles into the high-K dielectric layers 112a/112c and the interfacial dielectric layers 110a/110c at transistors T1 and T3. The result of the process of fig. 6A and 6B is that transistor T1 has a threshold voltage Vt1, transistor T2 has a threshold voltage Vt2, transistor T3 has a threshold voltage Vt3, and transistor T4 has a threshold voltage Vt4.
Fig. 6C shows an embodiment of depositing gate metal 120, wherein dipole induction layer 118 is still present at transistors T1 and T3. The gate metal 120 may have the materials and deposition processes described with respect to fig. 1I. In embodiments where the final patterning process is a positive tone patterning process, the gate metal 120 may be deposited directly on the dipole induction layer 118, as the hard mask layer 114 is no longer present in any transistor. Thus, gate metal 120 is in direct contact with dipole induction layer 118 of transistors T1 and T3, and with high-K dielectric layers 112b/112d at transistors T2 and T4. Alternatively, the dipole induction layer 118 may be removed from all transistors prior to depositing the gate metal 120.
A combination of positive tone patterning and reverse tone patterning processes may be used to produce transistors T1-T8 having different threshold voltages. In some embodiments, the first dipole driving process may include a positive tone patterning process, and the second and third dipole driving processes may each include a negative tone patterning process. In some embodiments, the first and third dipole driving processes may each include a reverse tone patterning process, while the second dipole driving process includes a positive tone patterning process. In some embodiments, the first and second dipole driving processes may include a reverse tone patterning process, and the final dipole driving process may include a positive tone patterning process. In some embodiments, two positive tone patterning processes and a single negative tone patterning process may be utilized.
Fig. 7 is a cross-sectional view of an integrated circuit 100 according to some embodiments. The integrated circuit 100 includes four FinFET transistors T1-T4 in an intermediate processing stage. Each FinFET transistor T1-T4 includes a channel region 108a-108d. The channel regions 108a-108d may include the materials described with respect to the channel regions 108a-108b of fig. 1A. Interfacial dielectric layers 110a-110d are located on the sides and top surfaces of the channel regions 108a-108d of each transistor. high-K dielectric layers 112a-112d are located over interfacial dielectric layers 110a-110 d. The substrate 102 is located below the channel regions 108a-108d. Shallow trench isolation regions 103 are also present.
The process stage shown in fig. 7 corresponds to the process stage shown in fig. 1G. Specifically, a reverse tone patterning process is performed. A dipole induction layer 118 is located on the high K dielectric layers 112a/112b of transistors T1 and T2. A hard mask layer 114 is located over the high K dielectric layers 112c/112d of transistors T3 and T4. The dipole induction layer 118 is located on the hard mask layer 144 of transistors T3 and T4. A thermal annealing process is performed to drive dipoles into the high-K dielectric layers 112a/112b and the interfacial dielectric layers 110a/110b of the transistors T1 and T2, thereby changing the threshold voltages of the transistors T1 and T2. The threshold voltages of transistors T3 and T4 remain unchanged due to the presence of hard mask layer 114.
Although not shown, the second inverse tone patterning process and the dipole-driving process in fig. 3B may be performed to drive dipoles into the high-K dielectric layers 112a/112c and the interfacial dielectric layers 110a/110c of the transistors T1 and T3, resulting in different threshold voltages for each transistor T1-T4. In some embodiments, for the second dipole driving process, a positive tone patterning process may be performed on the FinFET transistor. In some embodiments, the positive tone patterning process may be performed first, followed by the negative tone patterning process. Various combinations of the processes described herein may be used to pattern the FinFET transistor in fig. 7. After all dipole driving processes are completed, gate metal 120 may be deposited on the FinFET transistor.
The process of forming the FinFET transistor may include patterning the semiconductor substrate 102 to form a semiconductor fin. Shallow trench isolation regions 103 are then formed around the fins. Dummy gate structures and gate spacers 136 are then formed across the fin. Source/drain recesses are then formed in the fin. Source/drain regions 128 are then formed in the recesses. An interlayer dielectric layer may then be deposited and then the dummy gate is removed to form a gate trench. Interface dielectric layers 110a-110d and high-K dielectric layers 112a-112d corresponding to channel regions 108a-108d are then formed on the exposed portions of the fins. To create different threshold voltages in FinFET transistors, dipoles may be driven in using an inverse tone patterning process. In some embodiments, the positive tone patterning process may also be used in combination with the negative tone patterning process. Gate metal 120 is then deposited over high-K dielectric layers 112a-112d. Various other processes may be used to form FinFET transistors without departing from the scope of the present disclosure.
Fig. 8 is a flow chart of a method 800 of processing an integrated circuit according to some embodiments. The method 800 may utilize the processes, components, and systems described with respect to fig. 1A-7. At 802, method 800 includes forming a first high-K dielectric layer on a first interfacial dielectric layer of a first channel region of a first transistor. One example of a first transistor is transistor T1 of fig. 1A. One example of a first channel region is channel region 108a of fig. 1A. One example of a first interfacial dielectric layer is interfacial dielectric layer 110a of fig. 1A. One example of a first high-K dielectric layer is high-K dielectric layer 112a of fig. 1A.
At 804, method 800 includes forming a second high-K dielectric layer on the second interfacial dielectric layer over the second channel region of the second transistor. One example of a second transistor is transistor T2 in fig. 1A. One example of a second channel region is channel region 108a of fig. 1A. One example of a second interfacial dielectric layer is interfacial dielectric layer 110b of fig. 1A. One example of a second high-K dielectric layer is high-K dielectric layer 112b of fig. 1A.
At 806, method 800 includes depositing a first hard mask layer over the first high-K dielectric layer and the second high-K dielectric layer. One example of a first hard mask layer is hard mask layer 114 of FIG. 1B.
At 808, the method 800 includes patterning the first hard mask layer to expose the first high-K dielectric layer.
At 810, method 800 includes depositing a first dipole induction layer on a first hard mask layer over a first high-K dielectric layer and a second channel region. One example of a first dipole induction layer is the first dipole induction layer 118 of fig. 1F. At 812, the method 800 includes performing a first thermal annealing process while the first dipole induction layer is located on the first high-K dielectric layer and on the first hard mask layer over the second channel region.
Fig. 9 is a flow chart of a method 900 of processing an integrated circuit according to some embodiments. The method 900 may utilize the processes, components, and systems described with respect to fig. 1A-8. At 902, method 900 includes forming a first high-K dielectric layer over a first channel region of a first transistor. One example of a first transistor is transistor T1 of fig. 1A. One example of a first channel region is channel region 108a of fig. 1A. One example of a first high-K dielectric layer is high-K dielectric layer 112a of fig. 1A.
At 904, method 900 includes forming a second high-K dielectric layer over a second channel region of a second transistor. One example of a second transistor is transistor T2 of fig. 1A. One example of a second channel region is channel region 108a of fig. 1A. One example of a second high-K dielectric layer is high-K dielectric layer 112b of fig. 1A.
At 906, the method 900 includes driving atoms from the first dipole induction layer into the first high-K dielectric layer by performing a first thermal annealing process while the first hard mask layer overlies the second high-K dielectric layer and does not overlie the first high-K dielectric layer. One example of a first hard mask layer is hard mask layer 114 of FIG. 1B. One example of a first dipole induction layer is dipole induction layer 118 of fig. 1F. At 908, the method 900 includes driving atoms from the second dipole induction layer into the first high-K dielectric layer by performing a second thermal annealing process while the second dipole induction layer covers the first high-K dielectric layer and is not present over the second high-K dielectric layer. One example of a second dipole induction layer is dipole induction layer 118 of fig. 5A.
Embodiments of the present disclosure provide an integrated circuit having multiple regions formed with transistors of different threshold voltages. In particular, embodiments of the present disclosure utilize inverse tone patterning to safely and efficiently perform a dipole driving-in process that does not significantly damage the high-K gate dielectric layer. Embodiments of the present disclosure may utilize a combination of reverse tone and forward tone patterning to form multiple threshold voltage regions. The result is an efficient and effective formation of multiple threshold voltage regions within the tolerances specified by the Falcon programming language. Thus, an integrated circuit capable of operating properly, a higher wafer yield, and an electronic device with better functions are obtained.
In some embodiments, a method of forming an integrated circuit includes: forming a first high-K dielectric layer over the first interfacial dielectric layer over the first channel region of the first transistor; forming a second high-K dielectric layer over the second interfacial dielectric layer over the second channel region of the second transistor; depositing a first hard mask layer over the first high-K dielectric layer and over the second high-K dielectric layer; patterning the first hard mask layer to expose the first high-K dielectric layer; depositing a first dipole induction layer on the first high-K dielectric layer and on the first hard mask layer over the second channel region; and performing a first thermal annealing process when the first dipole induction layer is located on the first high-K dielectric layer and on the first hard mask layer over the second channel region.
In some embodiments, the method includes adjusting a threshold voltage of the first transistor by performing a first thermal annealing process.
In some embodiments, the first thermal annealing process does not adjust the threshold voltage of the second transistor.
In some embodiments, a method comprises: removing the remaining portions of the first dipole induction layer and the first hard mask layer; and depositing a gate metal on the first high-K dielectric layer and on the second high-K dielectric layer.
In some embodiments, a method comprises: forming a third high-K dielectric layer on the third interfacial dielectric layer on the third channel region of the third transistor prior to depositing the first hard mask layer; forming a fourth high-K dielectric layer on the fourth interfacial dielectric layer on the fourth channel region of the fourth transistor prior to depositing the first hard mask layer; wherein depositing the first hard mask layer comprises depositing the first hard mask layer on the third high-K dielectric layer and on the fourth high-K dielectric layer; wherein patterning the first hard mask layer includes exposing the third high-K dielectric layer; wherein depositing the first dipole induction layer comprises depositing the first dipole induction layer on the third high-K dielectric layer and on the first hard mask layer over the fourth high-K dielectric layer; and wherein performing the first thermal annealing process includes performing the first thermal annealing process while the first dipole induction layer is located on the third high-K dielectric layer and on the first hard mask layer over the fourth channel region.
In some embodiments, a method comprises: removing the first hard mask layer and the first dipole induction layer; depositing a second hard mask layer over the first high-K dielectric layer, the second high-K dielectric layer, the third high-K dielectric layer, and the fourth high-K dielectric layer; exposing the first high-K dielectric layer and the fourth high-K dielectric layer by patterning the second hard mask layer; depositing a second dipole induction layer on the first high-K dielectric layer and the fourth high-K dielectric layer and on the second hard mask layer over the second channel region and the fourth channel region; and performing a second thermal annealing process when the second dipole induction layer is located on the first high-K dielectric layer and the fourth high-K dielectric layer.
In some embodiments, the first thermal annealing process and the second thermal annealing process are performed, resulting in the first transistor, the second transistor, the third transistor, and the fourth transistor each having a different threshold voltage.
In some embodiments, the first thermal annealing process and the second thermal annealing process do not change the threshold voltage of the second transistor.
In some embodiments, a method comprises: removing the first hard mask layer and the first dipole induction layer; depositing a second dipole induction layer on the first high-K dielectric layer, the second high-K dielectric layer, the third high-K dielectric layer and the fourth high-K dielectric layer; depositing a second hard mask layer over the second dipole induction layer over the first high-K dielectric layer, the second high-K dielectric layer, the third high-K dielectric layer and the fourth high-K dielectric layer; exposing the second dipole induction layer over the second high-K dielectric layer and the third high-K dielectric layer by patterning the second hard mask layer; removing the second dipole induction layer from the second high-K dielectric layer and the third high-K dielectric layer when the second hard mask is on the second dipole induction layer on the first high-K dielectric layer and the fourth high-K dielectric layer; and performing a second thermal annealing process after removing the second dipole induction layer from the second high-K dielectric layer and the third high-K dielectric layer and while the second dipole induction layer is located on the first high-K dielectric layer and the fourth high-K dielectric layer.
In some embodiments, the first thermal annealing process and the second thermal annealing process do not change the threshold voltage of the second transistor.
In some embodiments, a method of forming an integrated circuit includes: forming a first high-K dielectric layer over a first channel region of a first transistor; forming a second high-K dielectric layer over a second channel region of the second transistor; driving atoms from the first dipole induction layer into the first high-K dielectric layer by performing a first thermal annealing process when the first hard mask layer covers the second high-K dielectric layer and does not cover the first high-K dielectric layer; and driving atoms from the second dipole induction layer into the first high-K dielectric layer by performing a second thermal annealing process when the second dipole induction layer covers the first high-K dielectric layer and is not present over the second high-K dielectric layer.
In some embodiments, the threshold voltage of the first transistor is changed by a first thermal annealing process and is changed by a second thermal annealing process, wherein the threshold voltage of the second transistor is not changed by the first thermal annealing process and is not changed by the second thermal annealing process.
In some embodiments, a method comprises: the first thermal annealing process is performed after the second thermal annealing process is performed.
In some embodiments, a method comprises: the second thermal annealing process is performed after the first thermal annealing process is performed.
In some embodiments, a method comprises: forming a third high-K dielectric layer on the third interfacial dielectric layer on the third channel region of the third transistor before performing the first thermal annealing process and before performing the second thermal annealing process; forming a fourth high-K dielectric layer on the fourth interfacial dielectric layer on the fourth channel region of the fourth transistor before performing the first thermal annealing process and before performing the second thermal annealing process; driving atoms from the first dipole induction layer into the third high-K dielectric layer by performing a first thermal annealing process when the first hard mask layer covers the fourth high-K dielectric layer and does not cover the third high-K dielectric layer; and driving atoms from the second dipole induction layer into the fourth high-K dielectric layer by performing a second thermal annealing process when the second dipole induction layer is not present over the second high-K dielectric layer.
In some embodiments, during the first thermal annealing process, the first dipole induction layer is located on the first hard mask layer over the second high-K dielectric layer and the fourth high-K dielectric layer.
In some embodiments, during the second thermal annealing process, the second dipole induction layer is not present on the third high-K dielectric layer.
In some embodiments, an integrated circuit includes: a first transistor having a first threshold voltage. The first transistor includes a plurality of stacked first channel regions and a first high-K dielectric layer surrounding each of the first channel regions, wherein the first high-K dielectric layer is thinner on a top side of a highest first channel region than on a bottom side of the highest first channel region. The integrated circuit includes a second transistor having a second threshold voltage different from the first threshold voltage. The second transistor includes a plurality of stacked second channel regions and a second high-K dielectric layer surrounding each of the second channel regions. The second high-K dielectric layer has the same thickness on the top side of the uppermost second channel region as on the bottom side of the uppermost second channel region. The thickness of the second high-K dielectric layer on the top side of the uppermost second channel region is greater than the thickness of the first high-K dielectric layer on the bottom side of the uppermost first channel region.
In some embodiments, an integrated circuit includes: a gate metal surrounding the second channel region, wherein a second high-K dielectric layer is located between the gate metal and the second channel region; and a hybrid layer on the second high-K dielectric layer in contact with the gate metal, wherein the hybrid layer includes material from the second high-K dielectric layer and the hard mask layer.
In some embodiments, the first high-K dielectric layer has a different dipole concentration than the second high-K dielectric layer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (10)
1. A method of forming an integrated circuit, comprising:
forming a first high-K dielectric layer over the first interfacial dielectric layer over the first channel region of the first transistor;
forming a second high-K dielectric layer over the second interfacial dielectric layer over the second channel region of the second transistor;
depositing a first hard mask layer over the first high-K dielectric layer and over the second high-K dielectric layer;
patterning the first hard mask layer to expose the first high-K dielectric layer;
Depositing a first dipole induction layer on the first high-K dielectric layer and on the first hard mask layer over the second channel region; and
a first thermal annealing process is performed when the first dipole induction layer is located on the first high-K dielectric layer and on the first hard mask layer over the second channel region.
2. The method of claim 1, comprising adjusting a threshold voltage of the first transistor by performing the first thermal annealing process.
3. The method of claim 2, wherein the first thermal annealing process does not adjust a threshold voltage of the second transistor.
4. The method according to claim 1, comprising:
removing the remaining portions of the first dipole induction layer and the first hard mask layer; and
a gate metal is deposited on the first high-K dielectric layer and on the second high-K dielectric layer.
5. The method according to claim 2, comprising:
forming a third high-K dielectric layer on the third interfacial dielectric layer on the third channel region of the third transistor prior to depositing the first hard mask layer;
forming a fourth high-K dielectric layer on the fourth interfacial dielectric layer on the fourth channel region of the fourth transistor prior to depositing the first hard mask layer;
Wherein depositing the first hard mask layer comprises depositing the first hard mask layer on the third high-K dielectric layer and on the fourth high-K dielectric layer;
wherein patterning the first hard mask layer comprises exposing the third high-K dielectric layer;
wherein depositing the first dipole induction layer comprises depositing the first dipole induction layer on the third high-K dielectric layer and on the first hard mask layer over the fourth high-K dielectric layer; and is also provided with
Wherein performing the first thermal annealing process includes performing the first thermal annealing process when the first dipole induction layer is located on the third high-K dielectric layer and on the first hard mask layer over the fourth channel region.
6. The method of claim 5, comprising:
removing the first hard mask layer and the first dipole induction layer;
depositing a second hard mask layer over the first high-K dielectric layer, the second high-K dielectric layer, the third high-K dielectric layer, and the fourth high-K dielectric layer;
exposing the first high-K dielectric layer and the fourth high-K dielectric layer by patterning the second hard mask layer;
depositing a second dipole induction layer on the first high-K dielectric layer and the fourth high-K dielectric layer and on the second hard mask layer over the second channel region and the fourth channel region; and
A second thermal annealing process is performed when the second dipole induction layer is located on the first high-K dielectric layer and the fourth high-K dielectric layer.
7. The method of claim 6, wherein performing the first thermal annealing process and the second thermal annealing process results in the first transistor, the second transistor, the third transistor, and the fourth transistor each having different threshold voltages from one another.
8. The method of claim 7, wherein the first thermal annealing process and the second thermal annealing process do not change a threshold voltage of the second transistor.
9. A method of forming an integrated circuit, comprising:
forming a first high-K dielectric layer over a first channel region of a first transistor;
forming a second high-K dielectric layer over a second channel region of the second transistor;
driving atoms from a first dipole induction layer into the first high-K dielectric layer by performing a first thermal annealing process when a first hard mask layer covers the second high-K dielectric layer and does not cover the first high-K dielectric layer; and
atoms are driven from the second dipole induction layer into the first high-K dielectric layer by performing a second thermal annealing process when the second dipole induction layer covers the first high-K dielectric layer and is not present over the second high-K dielectric layer.
10. An integrated circuit, comprising:
a first transistor having a first threshold voltage and comprising:
a plurality of stacked first channel regions; and
a first high-K dielectric layer surrounding each of the first channel regions, wherein the first high-K dielectric layer is thinner on a top side of a highest first channel region than on a bottom side of the highest first channel region;
a second transistor having a second threshold voltage different from the first threshold voltage and including:
a plurality of stacked second channel regions; and
a second high-K dielectric layer surrounding each of the second channel regions, wherein the second high-K dielectric layer has the same thickness on a top side of a highest second channel region as on a bottom side of the highest second channel region, wherein a thickness of the second high-K dielectric layer on the top side of the highest second channel region is greater than a thickness of the first high-K dielectric layer on the bottom side of the highest first channel region.
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| US17/890,980 US11996298B2 (en) | 2022-05-03 | 2022-08-18 | Reversed tone patterning method for dipole incorporation for multiple threshold voltages |
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