CN116644414A

CN116644414A - Processing method, processing system, electronic system and storage medium

Info

Publication number: CN116644414A
Application number: CN202310633393.9A
Authority: CN
Inventors: 曹鎏
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2023-05-31
Filing date: 2023-05-31
Publication date: 2023-08-25

Abstract

At least one embodiment of the present disclosure provides a processing method, system, electronic system, and storage medium. The processing method comprises the following steps: providing a first execution domain in the system, wherein the first execution domain operates in a first mode, and as an operating environment for the security monitor, the first mode being a machine mode in a non-extended situation; and creating at least one second execution domain in the system, wherein each second execution domain runs based on the first execution domain and runs in a correspondingly set second mode, wherein the second mode has a lower authority than the machine mode. The processing method can provide rich privilege modes for the execution domain, thereby facilitating the construction of flexible and rich security business models.

Description

Processing method, processing system, electronic system and storage medium

Technical Field

The present disclosure relates to the field of integrated circuits, and more particularly, to processing methods, systems, electronic systems, and storage media.

Background

The trusted computing consortium (Confidential Computing Consortium, CCC) defines a trusted execution environment (Trusted Execution Environment, TEE) for building a Data in Use (Data in Use) secure execution environment, ensuring confidentiality, integrity and usability of Data at the Use stage. There are various CCC solutions in the industry, such as Intel SGX, ARM Trust-zone, etc.

Disclosure of Invention

At least one embodiment of the present disclosure provides a processing method, including: providing a first execution domain in the system, wherein the first execution domain operates in a first mode, and as an operating environment for the security monitor, the first mode being a machine mode in a non-extended situation; and creating at least one second execution domain in the system, wherein each second execution domain runs based on the first execution domain and runs in a correspondingly set second mode, wherein the second mode has a lower authority than the machine mode.

At least one embodiment of the present disclosure provides a system comprising: a first execution domain, wherein the first execution domain operates in a first mode and is a machine mode in a non-extended situation as an operating environment for the security monitor; and at least one second execution domain, wherein each second execution domain runs based on the first execution domain and runs in a correspondingly set second mode, wherein the authority of the second mode is lower than the authority of the machine mode.

At least one embodiment of the present disclosure provides an electronic device, including: a processor; a memory including one or more computer program modules; wherein one or more computer program modules are stored in the memory and configured to be executed by the processor to implement the processing methods as described above.

At least one embodiment of the present disclosure provides a non-transitory readable storage medium having stored thereon computer-executable instructions, wherein the computer-executable instructions, when executed by a processor, implement a processing method as described above.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure will be briefly described below. It is apparent that the figures in the following description relate only to some embodiments of the present disclosure and are not limiting of the present disclosure.

FIG. 1 illustrates a schematic diagram showing an exemplary isolation and context switch;

FIG. 2 illustrates a schematic diagram of a processor-level system architecture in accordance with at least one embodiment of the present disclosure;

FIG. 3 illustrates a schematic diagram of performing domain switching in accordance with at least one embodiment of the present disclosure;

FIG. 4 illustrates a data object diagram of a control status register setting in accordance with at least one embodiment of the present disclosure;

FIG. 5 illustrates a schematic diagram of interrupt isolation in accordance with at least one embodiment of the present disclosure;

FIG. 6 illustrates a schematic diagram of data cache isolation in accordance with at least one embodiment of the present disclosure;

FIG. 7A illustrates a flow chart of a processing method in accordance with at least one embodiment of the present disclosure;

FIG. 7B illustrates a schematic diagram of a system in accordance with at least one embodiment of the present disclosure;

FIG. 8A illustrates a flow diagram of a method of interrupt processing in accordance with at least one embodiment of the present disclosure;

FIG. 8B illustrates a schematic diagram of an interrupt controller in accordance with at least one embodiment of the present disclosure;

FIG. 9A illustrates a flow diagram of a method of operating a cache in accordance with at least one embodiment of the present disclosure;

FIG. 9B illustrates a schematic diagram of a cache controller in accordance with at least one embodiment of the present disclosure;

FIG. 10A illustrates a flow diagram of a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure;

FIG. 10B illustrates a schematic diagram of a translation look-aside buffer controller in accordance with at least one embodiment of the present disclosure;

FIG. 11 illustrates a schematic diagram of an electronic device in accordance with at least one embodiment of the present disclosure;

FIG. 12 illustrates a schematic diagram of a non-transitory readable storage medium in accordance with at least one embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosure to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims. It should be noted that the method operations described herein may be implemented by any functional block or arrangement of functions, and that any functional block or arrangement of functions may be implemented as a physical entity or a logical entity, or a combination of both.

In order that those skilled in the art will better understand the present disclosure, the present disclosure will be described in further detail below with reference to the accompanying drawings and detailed description.

Note that the examples to be presented below are only specific examples and are not intended to limit the embodiments of the present disclosure to the particular shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc., shown and described. Those skilled in the art can, upon reading the present specification, utilize the concepts of the present disclosure to construct additional embodiments not described in the present specification.

The terms used in the present disclosure are those general terms that are currently widely used in the art in view of the functions of the present disclosure, but may vary according to the intention, precedent, or new technology in the art of the person of ordinary skill in the art. Furthermore, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Accordingly, the terms used in the specification should not be construed as simple names, but rather based on the meanings of the terms and the general description of the present disclosure.

A flowchart is used in this disclosure to describe the operations performed by a system according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in order precisely. Rather, the various steps may be processed in reverse order or simultaneously, as desired. Also, other operations may be added to or removed from these processes.

The processor Core (or CPU Core) is a Core that can independently perform the steps of the Central Processing Unit (CPU) operation. For example, a Central Processing Unit (CPU) may contain one or more CPU cores, and depending on how many CPU cores are included, the CPU may be a single-Core Processor (CPU) or a multi-Core Processor (CPU). One or more levels of cache may be included in the CPU, e.g., the CPU core typically includes a first level cache, while the second level cache and the third level cache are located outside the CPU core.

In addition, for ease of description, such as in the exemplary RISC-V architecture, the Core, hart, CPU/CPU core or processor/processor core described herein may be semantically indistinguishable and may indicate the same object. It will be appreciated that while the above terms may refer to different objects in various architectures, aspects of the present disclosure may be applied in such architectures, with or without modification, without departing from the scope of the present disclosure.

Processors increase instruction execution efficiency through pipelining, including, for example, branch prediction, instruction fetching, decoding, register renaming, launching, execution, retirement, and the like. To further increase instruction execution efficiency, the processor may also provide multiple parallel pipelines (multiple hardware threads) that may share some components (e.g., cache queues, etc.).

When the operating system allocates memory to a process, the virtual address used needs to be mapped to a physical address (i.e., address translation), which is the actual physical memory access address. Address translation is a very time-consuming process. To save address translation time, improve computer system performance, a translation look-aside buffer (Translation Lookaside Buffer, TLB) is provided to store page table entries PTEs of a previously used first stage page table. For example, when an instruction or a piece of data needs to be read from the memory, a virtual address adopted in the read instruction needs to be translated into a physical address, that is, an address translation request is generated, at this time, the virtual address needing to be translated is firstly used for querying the TLB, if the TLB is hit, the corresponding physical address can be immediately obtained, otherwise, the page table is further queried step by step to obtain the corresponding physical address.

Currently, in computer systems, physical memory protection/enhanced physical memory protection (PMP/ePMP) is a hardware-level memory protection mechanism for isolating physical memory intervals. For example, processor chips based on RISC-V architecture, etc., may support PMP/ePMP. There are various PMP-based Enclave schemes to implement TEE, such as Berkeley keystone, hex-Five Multi-zone, etc.

However, PMP-based schemes do not provide a richer execution domain with a flexible level of operation; fine-grained hardware-level memory protection cannot solve isolation problems such as context switches/interrupts, caches/Translation Lookaside Buffers (TLB), etc. among multiple enclaves.

Fig. 1 shows a schematic diagram of an exemplary isolation and context switch.

The focus of trusted computing security solutions is on the isolation mechanism and context switching. There are a number of ways of isolation that logically depend on the Privilege Mode (privile Mode). For example, the isolation and context switching mechanism of the lower privilege mode (Lower Privilege Mode) is provided by the higher privilege mode (Higher Privilege Mode).

For example, referring to FIG. 1 (where isolation is identified by dashed lines), the Kernel of the operating system (e.g., the Linux Kernel, kernel for short) operates in super mode (SuperVisor mode), providing an inter-Process isolation and context switching mechanism that runs in User mode (User mode); a virtual machine manager (e.g., VMM) operates in a high super Mode (HS Mode) and provides isolation and context switching mechanisms between virtual machines (e.g., guest operating systems); a Security Monitor (Security Monitor) operates in Machine mode (Machine mode) and provides a mechanism for isolation and context switching between execution domains (hereinafter simply referred to as domains or domains). In addition, isolation and context switching mechanisms may also be provided at the hardware level (e.g., hardware primitives). The Hardware levels may include RISC-V cores (e.g., RISC-Vcore), PMP/ePMPs, security monitor extensions (Security Monitor Extension), hardware-supported handover extensions (Hardware-backed Switching Extension), and so on.

These isolation approaches differ securely in the trusted computing base (Trusted Computing Base, TCB): the complexity of the TCB determines the security level, with the more complex TCBs having lower security levels; at the same time, the TCB can read all data of the context, which can cause traffic data leakage.

Meanwhile, various isolation modes also have a large difference in the privilege modes provided for the service. For example, privileged modes provided to the business to be operable in a register block may include from user mode to machine mode, while the isolation of Linux kernels only provides the level of operation of the business user mode. Thus, in some aspects, how to provide a richer level of operation for a service is critical to building a flexible and secure service system.

The inventors of the present disclosure realized that in the above-described embodiments, the processor architecture, for example, is unable to meet trusted computing requirements, and is unable to truly fall to the product; too high a complexity of the TCB can present more potential safety hazards; and business systems require rich privilege modes to meet business needs.

At least one embodiment of the invention provides a processor-level system architecture (isolation model), for example involving one or more of the following: providing a richer execution domain with flexible operation level; fine-grained hardware-level memory protection, such as solving isolation problems of context switches/interrupts, cache/translation look-aside buffers, etc. among multiple enclaves. In this way, at least one embodiment of the present disclosure provides a processor-level system architecture (isolation model), for example, that can support multiple execution domains to meet trusted computing security requirements; simplifying and optimizing context switching, and reducing performance overhead caused by the context switching; and providing a security monitor implementation in machine mode, providing supermode and user mode to support secure business models, and the like.

The following describes an exemplary architecture or model of the present disclosure, it being understood that such descriptions are merely exemplary and are not exhaustive of the various aspects of the exemplary architecture or model, and that various aspects of such descriptions and aspects of other embodiments may be mutually referenced without departing from the scope of the present disclosure.

An exemplary isolation model is described below.

Fig. 2 illustrates a schematic diagram of a processor-level system architecture in accordance with at least one embodiment of the present disclosure. In this system architecture, isolation of execution domains may be achieved, and thus the system architecture described with reference to FIG. 2 and related embodiments is also referred to as an isolation model.

Referring to FIG. 2, a processor Core (Core) running an instruction set or a hardware thread (Hart) in a multithreaded processor Core (both of which may be intermixed) is logically partitioned into a plurality of execution domains, including, for example, execution domain 0, execution domain X, execution domain Y, and execution domain Z. For example, execution domain 0 acts as the running environment for the security monitor, while extending to, for example, supermodes as required by the service as a special security execution domain. Privilege functions (Privileged function) and an execution domain context manager (Domain Context Manager) may also be run in execution domain 0. The switching and interrupt operations and the like of the execution domain X, the execution domain Y, and the execution domain Z are controlled by the execution domain 0, and the execution domain X, the execution domain Y, and the execution domain Z can provide, for example, a high super mode, a user mode, and the like, respectively.

The processes and tasks may each run in a user mode of the execution domain. For example, processes PA, PB, and PC may run in user mode in execution domain X, and task a, task B may run in user mode in execution domain Y.

The kernel, the REE/TEE operating system, trusted services may run in a supermode in any execution domain. As shown in FIG. 2, the system kernel may run in a supermode of execution domain X, the real-time operating system (RTOS) may run in a supermode of execution domain Y, and the trusted service may run in a supermode of execution domain Z.

As shown in fig. 2, the execution domain X, the execution domain Y, and the execution domain Z may not have a special distinction in security level, and the service may make a REE/TEE or other semantic distinction according to the operating system being run. In a multi-core environment inside a CPU cluster (cluster), each Hart can autonomously do context switching according to traffic or interrupts.

The software system architecture can be flexibly designed according to business requirements, and supports simultaneous deployment of a plurality of software operating systems such as Linux/Android, RTOS, bare-Metal. Isolation between execution domains may be implemented using, for example, PMP/ePMP. When the execution domain is switched, the context of the execution domain which is currently running is saved, and the context of the execution domain which is about to run is restored.

Execution domain 0, execution domain X, execution domain Y, and execution domain Z control and operate based on processor cores (e.g., core 0, core 1, core 2, core 3). For example, the processor core may perform switching and interrupt operations on the execution domain, and so on. For example, the interrupt controllers may include a core local interrupt controller (actint), a Platform Level Interrupt Controller (PLIC), etc., where actint may initiate an interrupt request to a processor core. The PLIC may receive interrupt requests from devices external to the processor and distribute those requests to the processor cores for processing.

Execution domain X, execution domain Y, and execution domain Z may be scheduled simultaneously using, for example, a STimer mechanism. Under the multi-core system, the security monitor can do inter-core scheduling of the execution domain X, the execution domain Y and the execution domain Z according to the MTimer interrupt. This will be described in detail below in connection with fig. 3.

Fig. 3 illustrates a schematic diagram of performing domain switching in accordance with at least one embodiment of the present disclosure.

In the example shown in fig. 3, execution domain X is the executing execution domain or the currently running execution domain and is identified as the currently running execution domain, and execution domain Y and execution domain Z are non-currently running execution domains.

The switching of execution domain X, execution domain Y, and execution domain Z includes a variety of trigger conditions, such as ECALL, MTimer interrupt, MSWI/MEI, MEXG, WFI, etc., which are described in detail below.

ECALL: from low privilege mode trap (trap) to machine mode, the security monitor switches to the corresponding service according to the current register data.

MTimer interrupt: the security monitor may implement various scheduling mechanisms, such as time slice fair scheduling, preemptive scheduling, etc. And judging whether to perform domain context switching according to the MTimer interrupt. If only the execution Domain X uses MTimer for Intra-Domain (Intra-Domain) scheduling, the execution Domain X can be directly allowed to process Timer interrupts in a delegate manner.

MSWI/MEI: after the safety monitor processes the interrupt, the safety monitor determines to switch to the execution domain X, the execution domain Y and the execution domain Z according to a scheduling mechanism.

MEXG: acLINT and PLIC determine whether to trigger MEXG based on interrupt Pending (Pending) status in supermode, and the security monitor determines to switch to the corresponding execution domain based on ACLINT and PLIC registers when processing MEXG. For example, MEXG has the lowest priority and is automatically cleared after all ACLINT/PLIC pending interrupts have been processed. Additional aspects regarding MEXG will be described in detail below.

WFI: when the WFI is used in the super mode by the execution domain, illegal instruction exception is triggered, and the MStatus TW is forcedly set to 1 after SME is enabled and cannot be modified by referring to RISC-V Privileged Spec, 3.3.3. The security monitor judges whether to schedule or enter the WFI state according to the current requirements of the execution domain X, the execution domain Y and the execution domain Z. WFI in execution Domain 0 machine mode is defined along the RISC-V standard.

It should be noted that SSWI/SEI does not trigger execution domain X, execution domain Y, and execution domain Z switching directly, and if SSWI/SEI interrupts occur in the currently running execution domain (e.g., execution domain X), processing is performed directly in super mode. If the SSWI/SEI interrupt occurs in a non-currently running execution domain (e.g., execution domain Y and execution domain Z), then post-scheduling processing is performed according to the MEXG interrupt. After context save and restore is completed, the mret instruction is used to switch to the target execution domain. Exemplary additional aspects regarding MEXG interrupts are described in detail below in the interrupt isolation section.

An exemplary MDID CSR definition is described below.

mdid is a Control Status Register (CSR) in machine mode, comprising mdid. DID and mdid. NS for configuring an execution domain identifier (execution domain ID or DID) and/or non-secure identification information (NS), respectively, of length XLEN bits, where XLEN may refer to the number of bits or the length of the control status register or a data object set by the control status register.

It is noted that throughout the various embodiments of the present disclosure, mdid (e.g., execution domain state information that may correspond to a context, and may include DID and NS information) is typically associated with a current execution domain, and with a target execution domain when a context switch of the execution domain is made.

FIG. 4 illustrates a data object diagram of a control status register setting in accordance with at least one embodiment of the present disclosure. Referring to FIG. 4, the data object is XLEN bits in length, where mdid. DID is, for example, a 4-bit write random read method (WARL) field that identifies the execution domain that is to be executed after Hart executes the mret instruction.

Here, the mret instruction is a machine instruction to return from machine mode to a previous privilege mode, which can only be used when the privilege level is machine mode. The mret instruction functions to restore the Program Counter (PC) and privilege level (MPP) in machine mode to previously saved values and to set the current privilege level to the previously saved privilege level.

Referring to fig. 4, mdid.ns is, for example, a 1-bit write random read legal (WARL) field that is used to identify whether the current state of Hart is non-secure (non-secure) or secure (secure). For example, a secure state is indicated when the NS field is 0, and an unsecure state is indicated when the NS field is 1. In some embodiments, the reset or initial value of the NS field is 0.

The lengths of the bytes of mdid.did and mdid.ns herein are merely exemplary, and embodiments of the present disclosure are not limited thereto.

In addition, referring to fig. 4, mdid may also include a write reserved read ignore (WPRI) field of length XLEN-5 bits, for example, to hold other information associated with traffic.

Setting mdid in machine mode may immediately cause an interrupt controller (e.g., PLIC/actlin) state update, but does not cause a change in system access unit (LSU) and finger fetch unit (IFU) transactions DID/NS. For example, the setting will only take effect after execution of the mret instruction. Interruption and ECALL in machine mode will not cause mdid values to change, so interrupt controllers will not undergo state updates, but access unit (LSU) and Instruction Fetch Unit (IFU) transactions DID/NS will switch to execution domain 0 state according to the current machine mode.

Interrupt isolation, cache isolation, translation look-aside buffer isolation, etc., as exemplarily described below, may be performed based on the execution domain identifier and/or the unsecure identification information.

Exemplary interrupt isolation is described below.

The interrupt controller (ACLINT/PLIC) standard, such as RISC-V, defines that the interrupt controller trigger SSWI/MSWI/STIMER/MTIMER/SEI/MEI for each Hart. On this basis, the actint and PLIC need to be extended to support the execution domain and privileged mode states, and in addition, MEXG interrupt signals can be added simultaneously to trigger the execution domain context switch. After Hart is interrupted by MEXG interrupt signals, software respectively inquires ACLINT and PLIC MEXGx registers according to service requirements to obtain an execution domain identifier of a target execution domain to be switched to.

FIG. 5 illustrates a schematic diagram of interrupt isolation in accordance with at least one embodiment of the present disclosure.

As shown in fig. 5, the CPU cores (e.g., core 0, core 1, core M, core N, etc.) need to send Privilege Mode (privile Mode) and execution domain identifier (execution domain ID) information of the current Hart to interrupt controllers actin and PLIC, and update in real time according to changes in ECALL/xRET (e.g., sret/mret) and execution domain ID. For example, machine mode has full read and write rights to ACLINT and PLIC.

For example, actint and PLIC trigger only interrupts for machine mode and the currently running execution domain (e.g., execution domain X), processing is performed in the security monitor and the operating system kernel (e.g., linux kernel), respectively, according to the set state of interrupts based on interrupt signals. For example, a supermode interrupt of a non-currently running execution domain (e.g., execution domain Y and execution domain Z) may be suppressed by actint and PLIC, and the transition to a MEXG interrupt requires the security monitor to perform an execution domain switch, and the supermode interrupt of the currently running execution domain may be triggered when the corresponding execution domain switches to the running state.

For example, the interrupt controller (e.g., PLIC) may receive an interrupt request signal from the outside by comparing whether the execution domain corresponding to the interrupt request signal coincides with the current execution domain ID. If the signals are consistent, a signal corresponding to the interrupt request signal or the direct transparent interrupt request signal can be generated, so that the interrupt controller performs interrupt operation; if not, a MEXG interrupt signal may be generated and the interrupt controller may be caused to perform an execution domain switching based on the MEXG interrupt signal, and after the execution domain switching (at which time the current execution domain ID will become consistent with the execution domain corresponding to the interrupt request signal), a signal corresponding to the interrupt request signal or a transparent interrupt request signal may be generated.

An exemplary cache isolation is described below.

Processor cores such as RISC-V typically support multiple levels of caches, such as first level instruction Cache (I-Cache)/first level data Cache (D-Cache)/second level Cache (L2 Cache)/Last Level Cache (LLC), and so forth. Cache isolation may increase DID/NS support for I-Cache/D-Cache/L2Cache/LLC, etc., such as enabling DID/NS signals on the bus when Flush (Flush) and eviction (Evict) are made, such as causing data to be stored into or read from the Cache with corresponding DID/NS information.

For example, DID extensions require that the minimum granularity allowed by the PMP region be kept consistent with the length of the Cache line (Cache line), so that one DID/NS can be assigned to each Cache line. Of course, the disclosure is not limited thereto, for example, the DID extension requires that the minimum granularity allowed by the PMP region be kept consistent with the length of a Cache Set (Cache Set) or a Cache region in the Cache adopting the Set associative mapping manner, so that a plurality of Cache lines may correspond to one DID/NS.

In the case where the DID extension requires that the minimum granularity allowed by the PMP region remain consistent with the length of the cache line, each cache line of the cache may add additional space to record the DID/NS field to extend the cache.

FIG. 6 illustrates a schematic diagram of data Cache (D-Cache) isolation in accordance with at least one embodiment of the present disclosure. In fig. 6, a data cache is described as an example, and caches for other levels may be implemented in the same or similar manner.

Referring to fig. 6, each cache line of the data cache records the DID field and the NS field through additional space in addition to a general data storage section, a Tag (Tag) field, a valid bit (not shown) to associate the stored data with the DID and NS fields. As such, referring to fig. 6, each cache line may include DID and NS fields, a Tag (Tag), and corresponding Data (Data). Of course, embodiments of the present disclosure are not limited thereto. For example, in the case where only secure access and non-secure access need to be considered, the NS field may be recorded through additional space. For another example, in case that only the execution domain is needed, the DID field may be recorded through additional space.

Referring to fig. 6, the cache may be operated based on DID information (DID/NS).

For example, when a fill cache line issues a Load (Load) request to the bus, the CPU core and/or cache may send DID and NS signals to the external bus, for example. When a load or Store (Store) request is issued by the CPU core, the DID and NS may be sent to the cache along with other signals such as tags, indexes, etc. of the request. The DID and NS fields attached to the signal are not used for matching the cache line, and the matching rule is still performed in the original manner, for example, matching is performed through a tag and an index in the Physical Address (PA), and the corresponding address is summarized by searching the cache line through an Offset (Offset) in the physical address, so as to perform a read-write operation.

For example, when data is read from a data source (e.g., memory) into a cache data cache for filling in the event of a data cache miss (miss), the DID and NS fields carried by the signal are written into the cache line to be filled. The DID and NS fields of the cache line are not updated when the data cache hits (hit). If the corresponding address changes in the DID at run-time, the software may perform active Clean-up (Clean) and invalidate (Invalid) operations to refill the cache line with the new DID.

When the data cache performs a flush operation due to a CMO instruction or eviction, the DID and NS fields carried by the cache line are sent together to the external bus.

An exemplary translation look-aside buffer isolation is described below.

The RISC-V Privilege Specification (RISC-V Privilege Spec) defines supervisor address translation and protection registers (SATP) and Page Table Entries (PTEs). The translation look-aside buffer (TLB) may record the DID field with additional space, e.g., a tag extension that adds a DID to a portion of the translation look-aside buffer. Thus, the translation look-aside buffer can be operated based on the DID field.

For example, the DID and Address Space Identifier (ASID) are saved in the translation look-aside buffer as tags for its Entry (Entry), and the Entry of the translation look-aside buffer is hit only if the DID and ASID match. In other words, upon matching to the DID and ASID, the hit continues to query the translation look-aside buffer to determine if the entry in the translation look-aside buffer matches. In addition, a memory barrier instruction (MFENCE. VMA instruction) may be introduced simultaneously to ensure that PTE operations are completed before completion, while controlling translation look aside buffer flushing. For example, the MFENCE.VMA instruction can only execute in machine mode, with instruction exceptions occurring when other privileged modes execute.

Based on the above description of the exemplary system architecture, at least one embodiment of the present disclosure provides a processor-level secure execution domain.

Fig. 7A illustrates a flow chart of a processing method 700 in accordance with at least one embodiment of the present disclosure. The processing method 700 may be implemented, for example, in the isolation model described with reference to fig. 2 or in other suitable processor system architecture. Referring to fig. 7A, the processing method 700 includes steps S710 to S720.

In step S710, a first execution domain is provided in the system, wherein the first execution domain operates in a first mode and is an operating environment for the security monitor, wherein the first mode is a machine mode in a non-extended situation.

In step S720, at least one second execution domain is created in the system, wherein each second execution domain runs based on the first execution domain and runs in a correspondingly set second mode, wherein the rights of the second mode are lower than the rights of the first machine mode.

The above-described system may be part or all of a RISV-C processor system architecture or other suitable processor system, such as described with reference to fig. 2. The first execution domain may correspond to execution domain 0 above and the second execution domain may correspond to execution domain X, execution domain Y, and execution domain Z above. The first mode may be a high super mode, super mode or user mode when the non-extended situation is a machine mode.

As such, a processing method in accordance with at least one embodiment of the present disclosure may provide an execution domain with a rich privilege mode, thereby facilitating the construction of a flexible and rich secure business model.

Some exemplary additional aspects of processing methods according to at least one embodiment of the present disclosure are described below.

For example, according to a processing method of at least one embodiment of the present disclosure, the first mode may be extended to, for example, a high super mode, a super mode, or the like. For example, referring to fig. 2, the first mode may be extended to, for example, a high super mode, a super mode, etc. In some examples, the first mode may extend from machine mode to super mode, depending on the traffic needs. As such, a processing method in accordance with at least one embodiment of the present disclosure may further provide rich privilege modes, thereby facilitating the construction of flexible and rich security business models.

For example, according to a processing method of at least one embodiment of the present disclosure, the at least one second execution domain includes a plurality of second execution domains, and the plurality of second execution domains are not distinguished in a security level. For example, referring to fig. 2, the execution domain X, the execution domain Y, and the execution domain Z are not distinguished in the security level. As such, a processing method in accordance with at least one embodiment of the present disclosure may provide a flexible execution domain for having various security levels.

For example, according to a processing method of at least one embodiment of the present disclosure, isolation between a first execution domain and at least one second execution domain, and between each of a plurality of second execution domains, is achieved by physical memory protection/enhanced physical memory protection. For example, referring to fig. 2, isolation between execution domain 0 and execution domain X, execution domain Y, and execution domain Z may be achieved by PMP/ePMP, and isolation between execution domain X, execution domain Y, and execution domain Z may be achieved by PMP/ePMP. Thus, the processing method according to at least one embodiment of the present disclosure can realize isolation of the execution domain through specific memory protection, so as to ensure security of data in the execution domain.

For example, a processing method according to at least one embodiment of the present disclosure further includes: and switching between the current running execution domain and the target execution domain based on an execution domain identifier, wherein the execution domain identifier is used for identifying the target execution domain when the execution domain is switched, the current execution domain and the target execution domain are selected from a group comprising a first execution domain and at least one second execution domain, and the current execution domain and the target execution domain are different. For example, the current execution domain may be execution domain 0 and the target execution domain may be execution domain X. For another example, referring to fig. 5, the current execution domain may be an execution domain X and the target execution domain may be an execution domain Y. For example, referring to the embodiment of fig. 5, upon performing an execution domain switch, e.g., from execution domain X to execution domain Y, execution domain X may be switched to execution domain Y based on an execution domain identifier identifying execution domain Y, e.g., via an interrupt operation, protecting the current context of execution domain X and restoring the context of execution domain Y, etc. As such, a processing method according to at least one embodiment of the present disclosure may perform an execution domain or context switch based on an execution domain identifier.

For example, in accordance with a processing method of at least one embodiment of the present disclosure, a target execution domain is switched to a running execution domain after a processor core executes a privileged mode deauth instruction. For example, a privileged mode deauth instruction may be used to return to a previous privileged level mode when moving from, for example, machine mode. For example, in the RISC-V architecture, the privilege mode release instruction may be an mret instruction, although embodiments of the disclosure are not so limited, and in other architectures, other privilege mode release instructions may exist. For example, in the process of switching from the execution domain X to the execution domain Y, the execution domain X is the currently running execution domain, the execution domain Y is the target execution domain, and after the Hart executes the mret instruction, the switching from the execution domain X to the execution domain Y is completed, and the currently running execution domain will be the execution domain Y. That is, hart completes executing the mret instruction as a point in time when the execution domain switch is complete.

For example, in accordance with a processing method of at least one embodiment of the present disclosure, a control status register is provided to set and record an execution domain identifier. For example, referring to fig. 4, a status register may be controlled to set and record the execution domain identifier DID. As such, a processing method in accordance with at least one embodiment of the present disclosure may facilitate performing the setting and recording of domain identifiers by setting corresponding registers within a processor. The processing speed of the processor can be increased compared to executing the domain identifier by processing an external input.

Here, at the time of performing domain switching, the execution domain identifier set and recorded by the Control Status Register (CSR) is an execution domain identifier of the target execution domain (for example, an execution domain identifier of the execution domain Y in the execution domain switching process from the execution domain X to the execution domain Y). Of course, at the completion of the execution domain switching, since the target execution domain has become the current execution domain (e.g., the execution domain X has become the execution domain Y, and thus the current execution domain is the execution domain Y), the execution domain identifier set and recorded by the control status register is the execution domain identifier of the current execution domain (i.e., the execution domain identifier of the execution domain Y). That is, the execution domain identifier set and recorded by the control status register is the execution domain identifier of the target execution domain at the time of execution domain switching, and the execution domain identifier set and recorded by the Control Status Register (CSR) is the execution domain identifier of the current execution domain without switching.

For example, according to a processing method of at least one embodiment of the present disclosure, at least one second execution domain includes a plurality of second execution domains, and the plurality of second execution domains are distinguished based on a general execution environment/trusted execution environment (REE/TEE) semantic. For example, referring to fig. 2, the execution domain X, the execution domain Y, and the execution domain Z may be REEs or TEEs. For example, the execution domain X, the execution domain Y may be REE, and the execution domain Z may be TEE. Thus, part of the execution domains in the second execution domain may be REEs and may run or execute general traffic thereon, while other part of the execution domains in the second execution domain are TEEs and may run or execute trusted traffic thereon. As such, a processing method according to at least one embodiment of the present disclosure may provide a re/TEE environment that facilitates execution of various services on a system.

For example, according to a processing method of at least one embodiment of the present disclosure, the system runs on a hardware device that includes at least one processor core and a system bus, the processing method further comprising: the execution domain identifier is transmitted in a pipeline and a system bus of at least one processor core. For example, referring to FIG. 2, a processor system may run on hardware devices such as a processor Core, LLC, and interrupt controller, and may transmit an execution domain identifier in a processor pipeline and system bus. As such, a processing method in accordance with at least one embodiment of the present disclosure may facilitate the transmission of an execution domain identifier in, for example, a processor system architecture for further processing based on the execution domain identifier.

In other additional aspects, non-secure identification information may also be transmitted in the processor pipeline and system bus. For example, bits of NS information may be mapped to AXI bus AxPROT [1] for transmission of NS information. For example, a value of 0 for AxPROT [1] may indicate a secure access, and a value of 1 for AxPROT [1] may indicate an unsecure access.

For example, a processing method according to at least one embodiment of the present disclosure further includes: an interrupt operation is performed based on the execution domain identifier. For example, as described above with reference to fig. 5 regarding the interrupt operation, the interrupt operation may be performed via the interrupt controller based on the execution domain identifier DID. As such, a processing method according to at least one embodiment of the present disclosure may enable secure and efficient interrupt processing based on an execution domain.

For example, a processing method according to at least one embodiment of the present disclosure further includes: the cache is operated on based on the execution domain identifier. For example, as described above with respect to the cache of fig. 6, the cache may be operated based on the execution domain identifier DID and NS information. As such, a processing method according to at least one embodiment of the present disclosure may enable secure and efficient cache operations based on execution domains. For example, fine-grained operations based on execution domains may be implemented, enabling fine-grained hardware-level memory protection.

For example, a processing method according to at least one embodiment of the present disclosure further includes: the translation look-aside buffer is operated on the basis of the execution domain identifier. For example, as described above with respect to the translation look-aside buffer, the translation look-aside buffer may be operated based on the execution domain identifier DID and NS information. As such, a processing method in accordance with at least one embodiment of the present disclosure may enable secure and efficient address translation operations based on an execution domain. For example, fine-grained operations based on execution domains may be implemented, enabling fine-grained hardware-level memory protection.

Corresponding to the above-described processing method according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure provides a system, see fig. 7B. In other aspects, the system corresponds to, for example, the isolation model described with reference to fig. 2.

Fig. 7B shows a schematic diagram of a system 750 in accordance with at least one embodiment of the present disclosure.

Referring to fig. 7B, a system 750 includes a first execution domain 760 and at least one second execution domain 770.

The first execution domain 760 operates in a first mode, which in the non-extended case is machine mode, and acts as an operating environment for the security monitor.

Each of the at least one second execution domain 770 operates based on the first execution domain 760 and operates in a corresponding set second mode, wherein the second mode has a lower authority than the machine mode.

As such, a system in accordance with at least one embodiment of the present disclosure may provide rich privilege modes for execution domains, thereby facilitating the construction of flexible and rich secure business models.

Some exemplary additional aspects of systems in accordance with at least one embodiment of the present disclosure are described below.

For example, in accordance with a system of at least one embodiment of the present disclosure, at least one second execution domain includes a plurality of second execution domains that are not differentiated at a security level or are differentiated based on common execution environment/trusted execution environment semantics.

For example, in accordance with a system of at least one embodiment of the present disclosure, isolation between a first execution domain and at least one second execution domain, and between each of a plurality of second execution domains, is achieved by physical memory protection/enhanced physical memory protection.

For example, a system according to at least one embodiment of the present disclosure, further comprising: and an execution domain switching unit configured to switch between a current execution domain and a target execution domain based on an execution domain identifier, wherein the execution domain identifier is used for identifying the target execution domain when the execution domain is switched, the current execution domain and the target execution domain are selected from a group comprising a first execution domain and at least one second execution domain, and the current execution domain and the target execution domain are different.

For example, in accordance with a system of at least one embodiment of the present disclosure, a target execution domain is switched to a running execution domain after a processor core executes a privileged mode dea instruction.

For example, a system according to at least one embodiment of the present disclosure, further comprising: a control status register configured to set and record an execution domain identifier.

For example, a system according to at least one embodiment of the present disclosure operates on a hardware device that includes at least one processor core and a system bus, and an execution domain identifier is transmitted in the pipeline and system bus of the at least one processor core.

For example, a system according to at least one embodiment of the present disclosure further includes an interrupt controller configured to perform an interrupt operation based on the execution domain identifier; a cache controller configured to operate the cache based on the execution domain identifier; or a translation look-aside buffer controller configured to operate the translation look-aside buffer based on the execution domain identifier.

The additional aspects of the system 750 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the processing method 700 according to at least one embodiment of the present disclosure, and thus technical effects of the additional aspects of the processing method 700 according to at least one embodiment of the present disclosure may also be mapped to the additional aspects of the system 750 according to at least one embodiment of the present disclosure, which are not described herein.

In addition, the additional aspects of the systems described above in accordance with at least one embodiment of the present disclosure are merely exemplary, and may be implemented by other architectures and can refer to or incorporate the various aspects as described above in connection with fig. 2, for example.

FIG. 8A illustrates a flow diagram of an interrupt processing method in accordance with at least one embodiment of the present disclosure. The interrupt handling method may be implemented, for example, in aspects described with reference to fig. 2, 3, 5, or other suitable processor system architecture. Illustratively, the interrupt handling method may be performed by an interrupt controller (core local interrupt controller/platform level interrupt controller) described with reference to fig. 2 or 5. Referring to fig. 8A, the interrupt processing method includes steps S810 to S820.

In step S810, an execution domain identifier is received, wherein the execution domain identifier identifies a target execution domain of the interrupt process.

In step S820, an interrupt operation is performed based on the execution domain identifier.

For example, the execution domain identifier may identify the target execution domain upon an interrupt operation involving a switch from the currently running execution domain to the target execution domain. Further, the interrupt controller may trigger the processor core to perform an interrupt operation based on the execution domain identifier to perform a switch from the currently running execution domain to the target execution domain. For example, referring to fig. 5, in an interrupt operation of a handover from a currently running execution domain (execution domain X) to a target execution domain (execution domain Y), an interrupt controller (actlingt/PLIC) may receive an execution domain identifier (e.g., DID Y) of the target execution domain (execution domain Y), and the interrupt controller (actlingt/PLIC) may control a processor core (e.g., linux kernel/security monitor) to perform the interrupt operation based on the execution domain identifier (DID Y).

In this manner, the interrupt processing method according to at least one embodiment of the present disclosure may perform an interrupt operation based on the execution domain identifier, and may implement safe and efficient interrupt processing based on the execution domain.

Some exemplary additional aspects of interrupt handling methods in accordance with at least one embodiment of the present disclosure are described below.

For example, according to an interrupt processing method of at least one embodiment of the present disclosure, performing an interrupt operation based on an execution domain identifier includes: an interrupt signal is generated based on the execution domain identifier. Here, the interrupt signal may be transmitted to, for example, a processor core for further operation. For example, referring to fig. 5, in some cases, the interrupt controller PLIC may receive an interrupt signal SEI/MEI generated based on the execution domain identifier to trigger and control interrupt operations such as the security monitor and Linux kernel.

As such, an interrupt processing method according to at least one embodiment of the present disclosure may implement a corresponding interrupt operation based on an execution domain identifier.

For example, according to an interrupt processing method of at least one embodiment of the present disclosure, interrupt operations involve only triggering interrupts of a machine mode and a currently running execution domain, and are processed in a security monitor and an operating system kernel, respectively, according to a set state of interrupts based on an interrupt signal. For example, referring to fig. 5, if the currently running execution domain is execution domain X, the interrupt controller PLIC triggers only the machine mode and the interrupts of execution domain X, the interrupt signal MEI and possibly MEXG are processed in the security monitor and the interrupt signal SEI is processed in the operating system kernel (e.g. Linux kernel) according to the set state of the interrupts based on the interrupt signal. As such, the interrupt processing method according to at least one embodiment of the present disclosure may ensure the security of the interrupt operation.

For example, an interrupt processing method according to at least one embodiment of the present disclosure, generating an interrupt signal based on an execution domain identifier, includes: in response to determining that the currently running execution domain is inconsistent with the execution domain corresponding to the interrupt request signal based on the execution domain identifier, generating a context switch interrupt signal for triggering a switch from the currently running execution domain to the execution domain corresponding to the interrupt request signal; and generating an interrupt signal corresponding to the signal of the interrupt request as an interrupt signal in response to a switch from the currently running execution domain to the execution domain corresponding to the interrupt request signal. For example, the context switch interrupt signal may be the MEXG interrupt signal described with reference to fig. 5. For example, the MEXG interrupt signal may be used to trigger a switch from the currently running execution domain to the execution domain corresponding to the interrupt request signal via, for example, a processor core.

For example, upon an interrupt operation involving a switch from a current running execution domain to a target execution domain, the execution domain identifier may identify the target execution domain, and if the current execution domain is inconsistent with the target execution domain, the interrupt may be considered abnormal. At this point, the interrupt controller may generate a MEXG interrupt signal to control the processor core to trigger a switch from the currently running execution domain to the target execution domain. Then, the execution domain which is switched and is running is the latest currently running execution domain, and normal interrupt operation can be performed thereafter.

For example, referring to FIG. 3, the currently running execution domain may be execution domain X and the target execution domain may be execution domain Y.

As such, the interrupt processing method according to at least one embodiment of the present disclosure may perform switching of execution domains when an interrupt is abnormal to facilitate an interrupt operation.

For example, an interrupt processing method according to at least one embodiment of the present disclosure further includes: after the processor core is interrupted by the context switch interrupt signal, an execution domain identifier of the target execution domain is provided. For example, referring to fig. 3, after the processor core is interrupted by the MEXG interrupt signal, a context switch register (e.g., MEXGx register or other suitable register) of the interrupt controller (actlin/PLIC) may store an execution domain identifier of the target execution domain, and the context switch register of the interrupt controller (actlin/PLIC) may be queried by software according to service needs, respectively, to obtain the execution domain identifier of the target execution domain to which switching is required (e.g., see execution domain Y of fig. 3).

As such, an interrupt handling method according to at least one embodiment of the present disclosure may acquire an execution domain identifier through a register of an interrupt controller when an interrupt is abnormal. Of course, the disclosure is not limited in this regard, and the above-described retrieval of the execution domain identifier may be accomplished, for example, by an external input, a processor core resending, or looking up other suitable registers.

For example, an interrupt processing method according to at least one embodiment of the present disclosure, generating an interrupt signal based on an execution domain identifier, includes: in response to determining that the target execution domain coincides with the execution domain corresponding to the interrupt request signal based on the execution domain identifier, an interrupt signal corresponding to the signal of the interrupt request is generated as the interrupt signal. For example, in an interrupt operation involving a switch from a first execution domain to a second execution domain, the execution domain identifier may identify the second execution domain and the currently running execution domain is the second execution domain, at which point an interrupt exception may be deemed to be absent, and the interrupt controller may directly generate an interrupt signal to cause the processor core to perform interrupt processing.

For example, an interrupt processing method according to at least one embodiment of the present disclosure further includes: the privilege mode and execution domain identifier of the current processor core sent by the processor are received and updated in real-time according to changes in the privilege mode trapping/releasing instructions and execution domain identifiers to perform an interrupt operation based on the update. For example, a privileged mode trapping instruction may be used to trap from a low privileged mode to a machine mode. For example, in the RISC-V architecture, the privilege mode trapping/privilege mode relieving instruction may be ECALL/xRET (sret/mret), although embodiments of the present disclosure are not so limited, and in other architectures, other privilege mode trapping/privilege mode relieving instructions may exist. The processor directs the current Hart's privilege mode and execution domain identifier to the interrupt controller and updates in real time based on changes in ECALL/xRET (sret/mret) and execution domain identifier, and the interrupt controller triggers an interrupt based on these updated information. As such, an interrupt processing method in accordance with at least one embodiment of the present disclosure may update respective privilege modes and execution domain identifiers in real-time to facilitate interrupt operations via an interrupt controller.

Corresponding to the above-described processing method according to at least one embodiment of the present disclosure, at least one embodiment of the present disclosure provides an interrupt controller, see fig. 8B. In other aspects, the interrupt controller corresponds to, for example, the interrupt controller described with reference to fig. 2, 5 (e.g., a core local interrupt controller/platform level interrupt controller).

Fig. 8B illustrates a schematic diagram of an interrupt controller 850 in accordance with at least one embodiment of the present disclosure.

Referring to fig. 8B, the interrupt controller 850 includes a receiving unit 860 and an interrupt operation unit 870.

The receiving unit 860 is configured to receive an execution domain identifier, wherein the execution domain identifier identifies a target execution domain of the interrupt process.

The interrupt operation unit 870 is configured to perform an interrupt operation based on the execution domain identifier.

In this manner, an interrupt processor in accordance with at least one embodiment of the present disclosure may perform interrupt operations based on an execution domain identifier, and may implement secure and efficient interrupt processing based on an execution domain.

For example, according to an interrupt controller of at least one embodiment of the present disclosure, the interrupt operation unit is further configured to generate an interrupt signal based on the execution domain identifier.

For example, according to an interrupt controller of at least one embodiment of the present disclosure, the interrupt operation unit is further configured to trigger only the machine mode and the interrupt of the currently running execution domain, and to process in the security monitor and the operating system kernel, respectively, according to the setting state of the interrupt based on the interrupt signal.

For example, according to the interrupt controller of at least one embodiment of the present disclosure, the interrupt operation unit is further configured to: in response to determining that the currently running execution domain is inconsistent with the execution domain corresponding to the interrupt request signal based on the execution domain identifier, generating a context switch interrupt signal for triggering a switch from the currently running execution domain to the execution domain corresponding to the interrupt request signal; and generating an interrupt signal corresponding to the signal of the interrupt request as an interrupt signal in response to a switch from the currently running execution domain to the execution domain corresponding to the interrupt request signal.

For example, an interrupt controller according to at least one embodiment of the present disclosure further comprises a context switch register, and the interrupt operation unit is further configured to, after the processor core is interrupted by the context switch interrupt signal, query the context switch register to provide an execution domain identifier of the target execution domain.

For example, according to the interrupt controller of at least one embodiment of the present disclosure, the interrupt operation unit is further configured to generate an interrupt signal corresponding to the signal of the interrupt request as the interrupt signal in response to determining that the target execution domain coincides with the execution domain corresponding to the interrupt request signal based on the execution domain identifier.

For example, according to the interrupt controller of at least one embodiment of the present disclosure, the receiving unit is further configured to receive the privilege mode and the execution domain identifier of the current processor core transmitted by the processor, and the interrupt operation unit is further configured to update in real time according to the change of the privilege mode trapping instruction/privilege mode releasing instruction and the execution domain identifier to perform the interrupt operation based on the update.

The additional aspects of the interrupt controller 850 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the interrupt processing method 800 according to at least one embodiment of the present disclosure, and thus technical effects of the additional aspects of the interrupt processing method 800 according to at least one embodiment of the present disclosure may also be mapped to the additional aspects of the interrupt controller 850 according to at least one embodiment of the present disclosure, which will not be described again herein.

In addition, the additional aspects of the interrupt controller described above in accordance with at least one embodiment of the present disclosure are merely exemplary, and may be implemented by other architectures and may refer to or incorporate various aspects such as those described above in connection with fig. 2, 5.

Fig. 9A illustrates a flow diagram of a method of operating a cache in accordance with at least one embodiment of the present disclosure. The method of operating a cache may be implemented, for example, in the isolation model described with reference to FIG. 2, in the cache described with reference to FIG. 6, or in other suitable processor system architecture. Referring to fig. 9A, the method of operating a cache includes steps S910 to S920.

In step S910, execution domain state information of a transaction accessing a cache is received, wherein the execution domain state information is associated with an execution domain of the transaction. For example, the execution domain state information may be associated with an execution domain to which the target address space of the transaction belongs or with an execution domain to which the transaction belongs. For example, the execution domain status information herein may include an execution domain identifier and/or non-secure identification information. The execution domain identifier is used to identify the execution domain, and the non-secure identification information may identify whether the execution domain is secure or trusted. For example, referring to FIG. 6, execution domain state information for a transaction accessing a data cache may be received, and the transaction may involve a read, write, eviction, etc. operation of the data cache.

In step S920, the cache is operated based on the execution domain-state information. For example, different caching schemes may be employed accordingly for transactions from different execution domains, such as disabling or allowing access operations, caching in different storage locations of the cache, and so forth. For example, referring to FIG. 6, the cache may be operated based on DID and NS information to enable cache load and store operations, and the like.

As such, a method of operating a cache according to at least one embodiment of the present disclosure may operate the cache based on an execution domain identifier, and may enable safe and efficient cache operations based on an execution domain. For example, fine-grained operations based on execution domains may be implemented, enabling fine-grained hardware-level memory protection.

Some exemplary additional aspects of methods of operating a cache in accordance with at least one embodiment of the present disclosure are described below.

For example, a method of operating a cache in accordance with at least one embodiment of the present disclosure, operating the cache based on execution domain-state information, includes: data or instructions of a transaction are cached in a cache and execution domain state information of the data or instructions is recorded. For example, referring to fig. 6, data and corresponding DID and NS information may be cached in a data cache.

As such, a method of operating a cache in accordance with at least one embodiment of the present disclosure may implement fine-grained cache for an execution domain. A method of operating a cache in accordance with at least one embodiment of the present disclosure may provide space in the cache for recording execution domain state information of data or instructions. However, the embodiment is not limited thereto, and the execution domain state information of the data or instructions may also be recorded through an external space.

For example, a method of operating a cache according to at least one embodiment of the present disclosure, caching data or instructions of a transaction in the cache and recording execution domain state information of the data or instructions, includes: a space for recording execution domain state information is provided for a cache line of cache data or instructions in the cache and corresponding execution domain state information of the data or instructions is recorded in the space. For example, referring to fig. 6, a space may be provided for each cache line in the data cache, and corresponding DID and NS information may be recorded in the space.

As such, a method of operating a cache in accordance with at least one embodiment of the present disclosure may provide a fine-grained execution domain identifier and/or non-secure identification information based cache for cache behavior objects.

For example, a method of operating a cache according to at least one embodiment of the present disclosure, providing a space for recording execution domain state information for a cache line of cache data or instructions in the cache and recording corresponding execution domain state information of the data or instructions in the space, includes: when a cache line is filled and a load request is issued by the cache to the bus, the cache is enabled to send out execution domain state information to the bus. For example, referring to FIG. 6, when a cache line is filled and a load request is issued by the data cache to the bus, the cache is enabled, e.g., by the cache controller, to send DID and NS information to the bus.

As such, a method of operating a cache in accordance with at least one embodiment of the present disclosure may facilitate filling of cache lines including DID and NS information.

For example, a method of operating a cache according to at least one embodiment of the present disclosure, providing a space for recording execution domain state information for a cache line of cache data or instructions in the cache and recording corresponding execution domain state information of the data or instructions in the space, includes: when a processor issues a load request or a store request for a cache line of a cache, the cache is enabled to receive a signal comprising execution domain state information and tag information (and optionally information such as an index), wherein the execution domain state information is not used for matching the cache line. For example, referring to FIG. 6, when a processor issues a load request or a store request for a cache line of a data cache, the cache is enabled, e.g., by a cache controller, to receive signals including DID, NS information, tags (tags), and optionally index (index) information to effect read and write operations to the data cache. For example, the DID and NS fields attached to the signal may not be used for cache line matching, and the matching rules may still proceed as they were. For example, the DID and NS fields may not be checked when making a cache hit, i.e., the DID and NS field information may not be involved as a tag in the hit operation when matching.

For example, a method of operating a cache according to at least one embodiment of the present disclosure, providing a space for recording execution domain state information for a cache line of cache data or instructions in the cache and recording corresponding execution domain state information of the data or instructions in the space, includes: when the cache misses and fills, writing the execution domain state information into a cache line to be filled; when the cache hits, the execution domain state information of the cache line is not updated, and when the corresponding address has a change in the execution domain state information at run-time, the clearing and invalidating operations are performed, and the cache line is refilled according to the changed execution domain state information. For example, referring to fig. 6, when the data cache misses to be filled, the DID and NS information may be written into a cache line to be filled to facilitate storage of the corresponding DID and NS information. For another example, upon a data cache hit, the DID and NS information of the cache line may not be updated, and in response to a change in the corresponding address at runtime that there is DID and NS information, a cleanup and invalidation operation is performed, and the cache line is refilled with changed DID and NS information.

As such, a method of operating a cache in accordance with at least one embodiment of the present disclosure may provide a specific way for the cache to record execution domain state information.

For example, a method of operating a cache according to at least one embodiment of the present disclosure, providing a space for recording execution domain state information for a cache line of cache data or instructions in the cache and recording corresponding execution domain state information of the data or instructions in the space, includes: the execution domain identifier corresponding to the last cache line is used when the cache is enabled to initiate a prefetch operation. For example, referring to FIG. 6, the execution domain identifier corresponding to the last cache line may be used when a prefetch operation is initiated by the data cache.

As such, a method of operating a cache in accordance with at least one embodiment of the present disclosure may facilitate a fast hit of corresponding data.

For example, a method of operating a cache in accordance with at least one embodiment of the present disclosure, further comprises: when the cache performs a flush or eviction operation, the execution domain state information carried by the cache line is sent out together. For example, referring to FIG. 6, when a cache performs a flush or eviction operation, the DID and NS information carried by the cache line may be sent out together, e.g., to a bus, for writing to memory. For example, at this time, data in the cache needs to be written into the memory, and since a bus operation is required, the DID is required here, and thus the execution domain status information here includes the DID and NS information. However, embodiments are not limited thereto, and DID may not be necessary when only a simple system architecture of one execution domain is involved.

As such, a method of operating a cache in accordance with at least one embodiment of the present disclosure may result in data with execution domain state information such that other components further operate on the data based on the execution domain state information.

For example, in accordance with a method of operating a cache in accordance with at least one embodiment of the present disclosure, the cache includes an instruction cache, a data cache, a second level cache, and a Last Level Cache (LLC).

As such, a method of operating a cache in accordance with at least one embodiment of the present disclosure may be applicable to a wide range of cache systems.

The embodiments described above in connection with cache lines relate, for example, to operating a cache line of a cache based on execution domain-state information. However, embodiments are not limited thereto, e.g., in some embodiments, providing space in a cache for recording execution domain state information of data or instructions, including: space is provided for recording execution domain state information for a cache set in a cache for caching data or instructions, and the cache set is operated on based on an execution domain identifier. The cache set here includes a plurality of cache lines. In some examples, cache sets corresponding to the same execution domain state information may be dedicated to the same execution domain. For example, referring to fig. 6, one DID and NS information may be shared by data of a plurality of cache lines. In this way, the efficiency of the memory to store data or instructions may be improved.

In correspondence with the above-described method of operating a cache in accordance with at least one embodiment of the present disclosure, at least one embodiment of the present disclosure provides a cache controller, see fig. 9B. In other aspects, the cache controller is used, for example, to facilitate implementing various aspects of the cache described with reference to FIG. 6.

Fig. 9B shows a schematic diagram of a cache controller 950 in accordance with at least one embodiment of the present disclosure.

Referring to fig. 9B, the cache controller 950 includes a receiving unit 960 and a cache operating unit 970.

The receiving unit 960 is configured to receive execution domain state information of a transaction accessing the cache, wherein the execution domain state information is associated with an execution domain of the transaction.

The cache operation unit 970 is configured to operate the cache based on the execution domain status information.

As such, a cache controller in accordance with at least one embodiment of the present disclosure may operate a cache based on an execution domain identifier, and may implement secure and efficient cache operations based on an execution domain. For example, fine-grained operations based on execution domains may be implemented, enabling fine-grained hardware-level memory protection.

Some exemplary additional aspects of cache controllers in accordance with at least one embodiment of the present disclosure are described below.

For example, a cache controller according to at least one embodiment of the present disclosure, the cache operation unit is further configured to: data or instructions of a transaction are cached in a cache and execution domain state information of the data or instructions is recorded.

For example, a cache controller according to at least one embodiment of the present disclosure, the cache operation unit is further configured to: a space for recording execution domain state information is provided for a cache line of cache data or instructions in the cache and corresponding execution domain state information of the data or instructions is recorded in the space.

For example, a cache controller according to at least one embodiment of the present disclosure, the cache operation unit is further configured to: when a cache line is filled and a load request is issued by the cache to the bus, the cache is enabled to send out execution domain state information to the bus.

For example, a cache controller according to at least one embodiment of the present disclosure, the cache operation unit is further configured to: when a processor issues a load request or a store request to a cache, the enabling cache receives a signal comprising execution domain state information and tag information, wherein the execution domain state information is not used for matching of the cache line.

For example, a cache controller according to at least one embodiment of the present disclosure, the cache operation unit is further configured to: when the cache misses and fills, writing the execution domain state information into a cache line to be filled; when the cache hits, the execution domain state information of the cache line is not updated; and when the corresponding address has the change of the execution domain state information in the running process, cleaning and invalidating operation is carried out, and the cache line is filled again according to the changed execution domain state information.

For example, a cache controller according to at least one embodiment of the present disclosure, the cache operation unit is further configured to: the execution domain identifier corresponding to the last cache line is used when the cache is enabled to initiate a prefetch operation.

For example, a cache controller according to at least one embodiment of the present disclosure, the cache operation unit is further configured to: when the cache performs a flush or eviction operation, the execution domain state information carried by the cache line is sent out together.

For example, a cache controller in accordance with at least one embodiment of the present disclosure, the cache includes an instruction cache, a data cache, a second level cache, and a last level cache.

The additional aspects of the cache controller 950 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the method 900 of operating a cache according to at least one embodiment of the present disclosure, and thus technical effects of the additional aspects of the method 900 of operating a cache according to at least one embodiment of the present disclosure may also be mapped to the additional aspects of the cache controller 950 according to at least one embodiment of the present disclosure, which are not repeated herein.

In addition, the additional aspects of the interrupt controller described above in accordance with at least one embodiment of the present disclosure are merely exemplary, and the additional aspects of the cache controller described above may be implemented by other architectures and may refer to or incorporate various aspects such as those described above in connection with fig. 2, 6.

FIG. 10A illustrates a flow diagram of a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure. This operational translation look-aside buffer may be implemented, for example, in the isolation model described with reference to FIG. 2, with reference to the translation look-aside buffer described above, or in other suitable processor system architecture. Referring to fig. 10A, the method of operating the translation look-aside buffer includes steps S1010 to S1020.

In step S1010, execution domain state information of a transaction accessing a translation look aside buffer is received, wherein the execution domain state information is associated with an execution domain of the transaction. For example, the execution domain state information may be associated with an execution domain to which the target address space of the transaction belongs or with an execution domain to which the transaction belongs. For example, the execution domain status information herein may include an execution domain identifier and/or non-secure identification information. The execution domain identifier is used to identify the execution domain, and the non-secure identification information may identify whether the execution domain is secure or trusted.

In step S1020, a translation look-aside buffer is operated based on the execution domain-state information. For example, the translation look-aside buffer may be operated accordingly for transactions from different execution domains.

As such, a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure may operate the translation look-aside buffer based on an execution domain identifier, and may enable safe and efficient address translation operations based on an execution domain. For example, fine-grained operations based on execution domains may be implemented, enabling fine-grained hardware-level memory protection.

Some exemplary additional aspects of methods of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure are described below.

For example, a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure operates the translation look-aside buffer based on execution domain-state information, comprising: the execution domain state information of the transaction is recorded in an operation translation look-aside buffer. Of course, embodiments of the present disclosure are not limited in this regard and may be implemented by recording the execution domain state information of the transaction outside of the translation look-aside buffer.

As such, a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure may enable storage of execution domain state information within the translation look-aside buffer to facilitate subsequent query operations based on the execution domain state information.

For example, a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure, recording execution domain state information of a transaction in the operation translation look-aside buffer, comprising: space is provided in the translation look-aside buffer for recording execution domain state information. For example, as described above, a Translation Lookaside Buffer (TLB) may record the DID field with additional space. However, the embodiment is not limited thereto, and the execution domain-state information may be recorded through an external space.

As such, a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure may facilitate recording execution domain state information of a transaction in the operation translation look-aside buffer.

For example, a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure provides space in the translation look-aside buffer for recording execution domain state information, comprising: a tag or part of a tag for holding execution domain state information and an address space identifier as entries of the translation look-aside buffer is provided in the translation look-aside buffer. For example, as described above, the DID information and address space identifier may be saved in the translation look-aside buffer as tags for its entries.

As such, a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure provides a specific manner to facilitate recording execution domain state information of transactions in the operation translation look-aside buffer.

For example, a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure operates the translation look-aside buffer based on execution domain-state information, comprising: upon matching the execution domain state information and the address space identifier, the translation look-aside buffer is continued to be queried to determine if an entry in the translation look-aside buffer matches. For example, as described above, the DID information and the address space identifier may be saved in the translation look-aside buffer as tags for its entries, and the entries of the translation look-aside buffer may be hit only if the DID information and ASID match.

As such, a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure increases DID information and ASID as one of the hit conditions, and conventional TLB query hits may remain unchanged, facilitating address translation operations based on execution domain-state information with less modification to the translation look-aside buffer.

For example, a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure further comprises: using memory barrier instructions, it is ensured that Page Table Entry (PTE) operations are completed before completion, as well as control of translation look-aside buffer cleanup operations. For example, as described above, a memory barrier instruction (MFENCE. VMA instruction) may be introduced simultaneously to ensure that PTE operations are completed before completion while controlling translation look aside buffer flushing.

In this way, the method for operating the translation look-aside buffer according to at least one embodiment of the present disclosure can ensure that the corresponding address translation operation is completed smoothly.

For example, in accordance with a method of operating a translation look-aside buffer in accordance with at least one embodiment of the present disclosure, memory barrier instructions execute in machine mode and instruction exceptions occur when other privileged modes execute.

As such, a method of operating a translation look-aside buffer according to at least one embodiment of the present disclosure may ensure system security because it is performed only in machine mode.

In correspondence with the method of operating a translation look-aside buffer described above in accordance with at least one embodiment of the present disclosure, at least one embodiment of the present disclosure provides a translation look-aside buffer controller, see FIG. 10B. In other aspects, the translation look-aside buffer controller is used, for example, to facilitate implementing various aspects of the translation look-aside buffers described above.

FIG. 10B illustrates a schematic diagram of a translation look-aside buffer controller 1050 in accordance with at least one embodiment of the present disclosure.

Referring to fig. 10B, the translation look-aside buffer controller 1050 includes a receiving unit 1060 and a translation look-aside buffer controller operating unit 1070.

The receiving unit 1060 is configured to receive execution domain state information of a transaction accessing a translation look aside buffer, wherein the execution domain state information is associated with an execution domain of the transaction.

The translation look-aside buffer controller operation unit 1070 is configured to operate the translation look-aside buffer based on the execution domain state information.

As such, a translation look-aside buffer controller in accordance with at least one embodiment of the present disclosure may operate a translation look-aside buffer based on an execution domain identifier, and may implement secure and efficient address translation operations based on an execution domain. For example, fine-grained operations based on execution domains may be implemented, enabling fine-grained hardware-level memory protection.

For example, a translation look-aside buffer controller in accordance with at least one embodiment of the present disclosure, the translation look-aside buffer controller operating unit is further configured to: the execution domain state information of the transaction is recorded in an operation translation look-aside buffer.

For example, a translation look-aside buffer controller operation unit in accordance with at least one embodiment of the present disclosure is further configured to: the tag or part of a tag holding the execution domain state information and the address space identifier is provided in the translation look-aside buffer as an entry of the translation look-aside buffer.

For example, a translation look-aside buffer controller in accordance with at least one embodiment of the present disclosure, the translation look-aside buffer controller operating unit is further configured to: upon matching the execution domain state information and the address space identifier, the translation look-aside buffer is continued to be queried to determine if an entry in the translation look-aside buffer matches.

For example, a translation look-aside buffer controller in accordance with at least one embodiment of the present disclosure, the translation look-aside buffer controller operating unit is further configured to: using a memory barrier instruction, it is ensured that page table entry operations before completion, as well as control of translation look-aside buffer cleanup operations.

For example, a translation look aside buffer controller in accordance with at least one embodiment of the present disclosure, memory barrier instructions execute in machine mode and instruction exceptions occur when executing in other privileged modes.

For example, a translation look-aside buffer controller in accordance with at least one embodiment of the present disclosure, the execution domain state information includes at least one of an execution domain identifier and non-secure identification information.

The additional aspects of the translation look-aside buffer controller 1050 according to at least one embodiment of the present disclosure may correspond to the additional aspects of the method 1000 of operating a translation look-aside buffer according to at least one embodiment of the present disclosure, and thus the technical effects of the additional aspects of the method 1000 of operating a translation look-aside buffer according to at least one embodiment of the present disclosure may also be mapped to the additional aspects of the translation look-aside buffer controller 1050 according to at least one embodiment of the present disclosure, which are not repeated herein.

In addition, the additional aspects of the interrupt controller described above in accordance with at least one embodiment of the present disclosure are merely exemplary, and the additional aspects of the translation look-aside buffer controller described above may be implemented by other architectures and may refer to or incorporate various aspects of the translation look-aside buffer as described above.

Fig. 11 shows a schematic diagram of an electronic device 1100 in accordance with at least one embodiment of the present disclosure.

As shown in fig. 11, the electronic device 1100 includes a processor 1110 and a memory 1120. Memory 1120 includes one or more computer program modules 1121. One or more computer program modules 1121 are stored in the memory 1120 and configured to be executed by the processor 1110, the one or more computer program modules 1121 comprising instructions for performing the various methods described above in accordance with at least one embodiment of the present disclosure, which when executed by the processor 1110, can perform one or more steps of the various methods described above and additional aspects thereof in accordance with at least one embodiment of the present disclosure. The memory 1120 and the processor 1110 may be interconnected by a bus system and/or other forms of connection mechanisms (not shown). For example, the bus may be a peripheral component interconnect standard (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus may be classified as an address bus, a data bus, a control bus, or the like.

Illustratively, the processor 1110 may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), or other form of processing unit having data processing and/or program execution capabilities, such as a Field Programmable Gate Array (FPGA) or the like; for example, the Central Processing Unit (CPU) may be a RISC-V architecture or other suitable type of architecture, etc. The processor 1110 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 1100 to perform desired functions.

By way of example, memory 1120 may comprise any combination of one or more computer program products, which may comprise various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules 1121 may be stored on the computer-readable storage medium, and the processor 1110 may execute the one or more computer program modules 1121 to implement the various functions of the electronic device 1100. Various applications and various data, as well as various data used and/or generated by the applications, etc., may also be stored in the computer readable storage medium.

For example, the electronic device 1100 may also include input devices such as a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; including output devices such as liquid crystal displays, speakers, vibrators, etc.; including storage devices such as magnetic tape, hard disk (HDD or SDD); for example, communication devices such as LAN cards, modems and the like may also be included. The communication apparatus may allow the electronic apparatus 1100 to perform wireless or wired communication with other devices to exchange data, performing communication processing via a network such as the internet. The drive is connected to the I/O interface as needed. A removable storage medium such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive as needed so that a computer program read therefrom is installed into the storage device as needed.

For example, the electronic device 1100 may further include a peripheral interface (not shown), and the like. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning (lighting) interface, etc. The communication means may communicate with networks and other devices by way of wireless communication, such as the internet, intranets and/or wireless networks such as cellular telephone networks, wireless Local Area Networks (LANs) and/or Metropolitan Area Networks (MANs). The wireless communication may use any of a variety of communication standards, protocols, and technologies including, but not limited to, global System for Mobile communications (GSM), enhanced Data GSM Environment (EDGE), wideband code division multiple Access (W-CDMA), code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), bluetooth, wi-Fi (e.g., based on the IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and/or IEEE 802.11n standards), voice over Internet protocol (VoIP), wi-MAX, protocols for email, instant messaging, and/or Short Message Service (SMS), or any other suitable communication protocol.

The electronic device 1100 may be, for example, a system on a chip (SOC) or a device including the SOC, for example, any device such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a game console, a television, a digital photo frame, a navigator, a home appliance, a communication base station, an industrial controller, a server, or any combination of data processing devices and hardware, which is not limited in the embodiments of the present disclosure. Specific functions and technical effects of the electronic device 1100 may be referred to the above description of the various methods for a reduced instruction set computer processor and additional aspects thereof according to at least one embodiment of the present disclosure, and are not repeated herein.

Fig. 12 illustrates a schematic diagram of a non-transitory readable storage medium 1200 in accordance with at least one embodiment of the present disclosure.

As shown in fig. 12, a non-transitory readable storage medium 1200 has stored thereon computer instructions 1210 that when executed by a processor perform one or more steps of the various methods and additional aspects thereof described above.

Illustratively, the non-transitory readable storage medium 1200 may be any combination of one or more computer readable storage media, e.g., a computer readable storage medium containing program code for performing the various methods described above.

Illustratively, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium to perform one or more steps of the various methods described above and additional aspects thereof, for example, in accordance with at least one embodiment of the present disclosure.

By way of example, the non-transitory readable storage medium may include a memory card of a smart phone, a memory component of a tablet computer, a hard disk of a personal computer, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, and other non-transitory readable storage media or any combination thereof.

At least some embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, so long as identical and similar parts between the various embodiments are mutually referred to.

It is noted that in this document, relational terms such as first, second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may further include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

For the purposes of this disclosure, the following points are also noted:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely exemplary embodiments of the present disclosure and is not intended to limit the scope of the disclosure, which is defined by the appended claims.

Claims

1. A method of processing, comprising:

providing a first execution domain in a system, wherein the first execution domain operates in a first mode and is an operating environment of a security monitor, the first mode being a machine mode in a non-extended situation; and

at least one second execution domain is created in the system, wherein each second execution domain runs based on the first execution domain and runs in a correspondingly set second mode, wherein the second mode has a lower authority than the machine mode.

2. The processing method of claim 1, wherein the at least one second execution domain comprises a plurality of second execution domains that are not differentiated in a security level.

3. The processing method of claim 2, wherein isolation between the first execution domain and the at least one second execution domain, and between each of the plurality of second execution domains, is achieved by physical memory protection/enhanced physical memory protection.

4. The processing method according to claim 1 or 2, further comprising:

and switching between a current running execution domain and a target execution domain based on an execution domain identifier, wherein the execution domain identifier is used for identifying the target execution domain when the execution domain is switched, the current running execution domain and the target execution domain are selected from a group comprising the first execution domain and the at least one second execution domain, and the current running execution domain and the target execution domain are different.

5. The processing method of claim 4, wherein the target execution domain is switched to a running execution domain after the processor core executes the privileged mode dea instruction.

6. The processing method of claim 4, further comprising:

a control status register is provided to set and record the execution domain identifier.

7. The processing method of claim 1, wherein the at least one second execution domain comprises a plurality of second execution domains that are differentiated based on common execution environment/trusted execution environment semantics.

8. The processing method of claim 4, wherein the system is run on a hardware device comprising at least one processor and a system bus, the processing method further comprising:

the execution domain identifier is transmitted in a pipeline of the at least one processor and the system bus.

9. The processing method of claim 4, further comprising:

and performing interrupt operation based on the execution domain identifier.

10. The processing method of claim 4, further comprising:

the cache is operated on the basis of the execution domain identifier.

11. The processing method of claim 4, further comprising:

and operating a translation look-aside buffer based on the execution domain identifier.

12. A system, comprising:

a first execution domain, wherein the first execution domain operates in a first mode and is an operating environment for a security monitor, the first mode being a machine mode in a non-extended situation; and

at least one second execution domain, wherein each second execution domain runs based on the first execution domain and runs in a correspondingly set second mode, wherein the second mode has a lower authority than the machine mode.

13. The system of claim 12, wherein the at least one second execution domain comprises a plurality of second execution domains that are not differentiated at a security level or are differentiated between the plurality of second execution domains based on common execution environment/trusted execution environment semantics.

14. The system of claim 13, wherein isolation between the first execution domain and the at least one second execution domain, and between each of the plurality of second execution domains, is achieved by physical memory protection/enhanced physical memory protection.

15. The system of claim 13 or 14, further comprising:

an execution domain switching unit configured to switch between a current running execution domain and a target execution domain based on an execution domain identifier, wherein the execution domain identifier is used to identify the target execution domain at the time of execution domain switching, the current running execution domain and the target execution domain are selected from a group including the first execution domain and the at least one second execution domain, and the current running execution domain and the target execution domain are different.

16. The system of claim 15, wherein the target execution domain is switched to a running execution domain after the processor core executes the privileged mode dea instruction.

17. The system of claim 15, further comprising:

a control status register configured to set and record the execution domain identifier.

18. The system of claim 15, wherein the system is run on a hardware device comprising at least one processor and a system bus, and the execution domain identifier is transmitted in the pipeline of the at least one processor and the system bus.

19. The system of claim 15, further comprising:

an interrupt controller configured to perform an interrupt operation based on the execution domain identifier;

a cache controller configured to operate the cache based on the execution domain identifier; or alternatively

A translation look-aside buffer controller configured to operate the translation look-aside buffer based on the execution domain identifier.

20. An electronic device, comprising:

a processor;

a memory including one or more computer program modules;

wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor to implement the processing method of any of claims 1-11.

21. A non-transitory readable storage medium having stored thereon computer-executable instructions,

wherein the computer executable instructions, when executed by a processor, implement the processing method according to any of claims 1-11.