CN116644009A - Instruction structure configuration method, controller and computer readable storage medium - Google Patents

Instruction structure configuration method, controller and computer readable storage medium Download PDF

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Publication number
CN116644009A
CN116644009A CN202310564804.3A CN202310564804A CN116644009A CN 116644009 A CN116644009 A CN 116644009A CN 202310564804 A CN202310564804 A CN 202310564804A CN 116644009 A CN116644009 A CN 116644009A
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Prior art keywords
instruction
state
controller
instruction structure
bit
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魏天博
黄杨国
湛厚超
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Rockchip Electronics Co Ltd
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Rockchip Electronics Co Ltd
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Priority to CN202310564804.3A priority Critical patent/CN116644009A/en
Publication of CN116644009A publication Critical patent/CN116644009A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

The present disclosure provides instruction structure configuration methods, controllers, and computer-readable storage media. The instruction structure configuration method comprises the following steps: acquiring a device instruction structure of the interaction device; determining at least one status instruction based on timing requirements of the interaction device; and adapting an instruction structure of the interaction device based on the device instruction structure and the status instruction configuration. The invention can flexibly adapt to the interactive equipment with various instruction structures and enrich the type selection requirements of the interactive equipment.

Description

Instruction structure configuration method, controller and computer readable storage medium
Technical Field
The disclosure relates to a method for configuring an instruction structure, a controller and a computer readable storage medium.
Background
The FLASH memory and the PSRAM pseudo-static random access memory are mostly based on interactive protocols such as xSPI and Hyperbus, but the interactive protocols provided by various manufacturers are different in detail, and even if the interactive protocols are the xSPI protocols, the instruction structures are different.
Because the interactive protocol of the FLASH memory is too complicated, the instruction structure of the single-design controller cannot be compatible with most FLASH memories.
Disclosure of Invention
The disclosure provides an instruction structure configuration method, a controller and a computer readable storage medium, which are used for solving the technical problem that an instruction structure of a controller cannot be adapted to various devices in the prior art.
In a first aspect, an embodiment of the present disclosure provides an instruction structure configuration method. The instruction structure configuration method comprises the following steps: acquiring a device instruction structure of the interaction device; determining at least one status instruction based on timing requirements of the interaction device; and adapting an instruction structure of the interaction device based on the device instruction structure and the status instruction configuration.
In an implementation manner of the first aspect, the acquiring a device instruction structure of the interaction device includes: the method comprises the steps of obtaining any combination of a controller working state instruction bit, a command operation code instruction bit, a target address sending instruction bit, a continuous reading instruction bit, an interface direction conversion instruction bit and a data transmission instruction bit.
In an implementation manner of the first aspect, the determining at least one status instruction based on a timing requirement of the interaction device includes: and determining a first state instruction for starting the data synchronous clock after delaying the first preset time after the moment that the controller enters the working state from the non-working state based on the first preset time of the interval between the moment that the controller enters the working state from the non-working state and the starting moment of the data synchronous clock.
In an implementation manner of the first aspect, adapting the instruction structure of the interaction device based on the device instruction structure and the status instruction configuration includes: and configuring instruction bits corresponding to the first state instruction between the controller working state instruction bits and the command operation code instruction bits.
In one implementation form of the first aspect, determining at least one status instruction based on timing requirements of the interaction device comprises: and converting the output interface state into the input interface state based on the condition that the second preset time is required to execute the read operation, and determining a second state instruction for converting the output interface state into the input interface state at the second preset time during the read operation.
In an implementation manner of the first aspect, adapting the instruction structure of the interaction device based on the device instruction structure and the status instruction configuration includes: and when the device instruction structure of the interactive device does not have an interface direction conversion instruction bit, configuring the instruction bit corresponding to the second state instruction between the data transmission instruction bit and a target address sending instruction bit.
In one implementation form of the first aspect, determining at least one status instruction based on timing requirements of the interaction device comprises: and determining a third state instruction for the controller to enter the non-working state from the working state after delaying the third preset time after the data transmission completion time based on the third preset time of the interval between the data transmission completion time and the time when the controller enters the non-working state from the working state.
In an implementation manner of the first aspect, adapting the instruction structure of the interaction device based on the device instruction structure and the status instruction configuration includes: and configuring instruction bits corresponding to the third state instruction between the data transmission instruction bits and the controller working state instruction bits.
In an implementation manner of the first aspect, adapting the instruction structure of the interaction device based on the device instruction structure and the status instruction configuration includes: the instruction thread, shan Shuangyan sample, and instruction length of each instruction bit are configured.
In one implementation of the first aspect, the interaction device includes a memory coupled with a controller, and adapting the instruction structure of the interaction device based on the device instruction structure and the status instruction configuration includes: an instruction structure adapted to the memory is configured in a register of the controller.
In a second aspect, embodiments of the present disclosure provide a controller. The controller comprises a processor and a register, the processor being configured to configure an instruction structure for the interaction device in the register according to the instruction structure configuration method of the second aspect of the present disclosure.
In a third aspect, the disclosed embodiments provide a computer-readable storage medium having stored thereon a computer program that is executed to implement the instruction structure configuration method according to the second aspect of the disclosure.
In the instruction structure configuration method provided by the embodiment of the disclosure, the state instruction is determined based on the time sequence requirement of the interactive equipment, and the instruction structure of the interactive equipment is adapted based on the equipment instruction structure and the state instruction configuration of the interactive equipment, so that the interactive equipment with various instruction structures can be flexibly adapted, and the type selection requirement of the interactive equipment is enriched.
Drawings
Fig. 1 is a flow chart illustrating a method for configuring an instruction structure according to an embodiment of the disclosure.
Fig. 2 is a schematic diagram showing an interval between a time when a time sequence requirement of an interactive device is a controller enters an operating state from a non-operating state and a starting time of a data synchronization clock in the configuration method of a command structure in the embodiment of the present disclosure.
Fig. 3 is a schematic diagram showing that the timing requirement of the interactive device in the command structure configuration method in the embodiment of the disclosure is to switch the output interface state to the input interface state when the second preset time is required to perform the read operation.
Fig. 4 is a schematic diagram showing a third preset time interval between a time when data transmission is completed and a time when a controller enters a non-working state from a working state in the time when the time sequence requirement of the interaction device in the command structure configuration method in the embodiment of the disclosure.
FIG. 5 is a diagram showing an example of an instruction structure in the instruction structure configuration method according to the embodiment of the disclosure.
Fig. 6 shows an exemplary diagram of a device instruction structure of an interactive device in the instruction structure configuration method in the embodiment of the present disclosure.
Fig. 7 is a schematic diagram of a schematic structure of a controller according to an embodiment of the disclosure.
Detailed Description
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The existing memories have various interactive protocols and different corresponding instruction structures, so that the controller cannot be compatible with various memories at the same time.
In view of the foregoing, embodiments of the present disclosure provide an instruction structure configuration method. In the instruction structure configuration method, a state instruction is determined according to the time sequence requirement of the interactive equipment such as a memory, and the instruction structure in a register is configured according to the equipment instruction structure and the state instruction of the interactive equipment so as to adapt to the corresponding interactive equipment, thereby achieving the purpose of flexibly adapting to the interactive equipment with various instruction structures. The instruction structure configuration method of the present embodiment is described in detail below.
Fig. 1 is a flow diagram illustrating an instruction structure configuration method provided according to an embodiment of the present disclosure. The instruction structure configuration method of the present embodiment may be applied to, but not limited to, a controller. As shown in fig. 1, the instruction structure configuration method provided by the embodiment of the present disclosure includes the following steps S100 to S300.
In step S100, a device instruction structure of the interactive device is acquired.
In some embodiments, the interactive devices include, but are not limited to, devices that communicate based on the xSPI protocol and the Hyperbus protocol. In some embodiments, the interactive device includes, but is not limited to, FLASH memory, PSRAM pseudo-static random access memory.
In some embodiments, the instruction corresponding to the instruction structure is an instruction sent by the controller to the FLASH memory or the PSRAM pseudo-static random access memory. The instructions include control instructions and data instructions. The control instruction is used for controlling the command of the FLASH memory or the PSRAM pseudo-static random access memory. The data instruction is used for data transmission, and the data instruction is divided into a read instruction and a write instruction.
At step S200, at least one status instruction is determined based on timing requirements of the interactive device.
In step S300, an instruction structure of the interaction device is adapted based on the device instruction structure and the status instruction configuration.
In some possible implementations, an instruction structure adapted to the interaction device is configured in a register of the controller, where the interaction device is a memory of the controller. That is, parameters of the instruction structures of the respective communication phases are configured by the configuration registers, thereby configuring the instruction structures to adapt the instruction structures of the various interactive devices.
The instruction structure may be different under different communication interaction protocols, for example the instruction structure is different in the xSPI protocol and the Hyperbus protocol. The Hyperbus protocol uses 3bit command bits+45 bit address bits with Reserved bits (Reserved bits) among others. There are also many variations of the xSPI protocol, such as 16bit command bits and 8bit command bits.
In this embodiment, the device instruction structure of the interaction device is determined based on the instruction features of the communication interaction protocol.
In particular, in some possible implementations, obtaining a device instruction structure of the interaction device may include: the controller is any combination of working state instruction bits, command operation code instruction bits, target address sending instruction bits, continuous reading instruction bits, interface direction conversion instruction bits and data transmission instruction bits.
For convenience of description, this embodiment will describe the instruction structure of the apparatus according to this embodiment by using common markers in the instruction for each instruction bit.
The command corresponding to the controller working state command bit is a controller working state command idle_st, and the command is used for indicating the non-working state of the controller, and at this time, the chip select signal CSn is at a high level.
The command operation code command bit corresponds to a command operation code command cmd_st, and in the command phase, the command is used to send a command operation code of the interactive device (e.g., FLASH memory). The command phase is the opcode portion of the entire instruction to indicate what operations the interactive device specifically is to do.
The instruction corresponding to the destination address sending instruction bit is a destination address sending instruction addr_st, and in the address stage, the instruction is used for sending the destination address.
The instruction corresponding to the continuous reading instruction bit is a continuous reading instruction AX_ST, the instruction is used for supporting the behavior characteristic of continuous reading, and part of interaction equipment supports no command when continuously reading data, and continuous reading behavior is marked by an address+AX instruction signal, so that an instruction structure is optimized under a specific scene, protocol overhead is saved, and reading efficiency is improved.
The continuous read command ax_st is an 8-bit complementary signal, and is transmitted after the destination address transmission command addr_st. When the first instruction is a read instruction, the continuous read instruction ax_st is equal to a specific value, and then the next read instruction can skip the command phase and directly start from the address phase. After the value of the continuous read command ax_st changes, the mode of such an omit command is exited. This is an optimization of protocol overhead, and some interactive devices have this design, and the specific continuous read command ax_st value is set differently by different manufacturers.
The command corresponding to the interface direction conversion command bit is an interface direction conversion command dumm_st, and when the command is read, the controller usually firstly sends out a command and an address and then receives data, so that conversion of the IO interface direction can be involved. The interface direction switching command dumm_st is equivalent to providing a buffer time for switching the IO driving direction, avoiding the occurrence of a multi-drive scenario, and requiring a short time to process the command after the command is received by part of the interaction, and also requiring an increase in the buffer time.
The command corresponding to the DATA transmission command bit is a DATA transmission command data_st for receiving and transmitting DATA to be transmitted in the DATA transmission stage.
In this embodiment, the device instruction structure is a combination of a controller working state instruction bit, a command operation code instruction bit, a target address sending instruction bit, a continuous reading instruction bit, an interface direction conversion instruction bit, and a data transmission instruction bit according to different actual interaction devices.
For example, some interactive devices do not have device instruction structures such as controller operating state instruction bits, command opcode instruction bits, target address send instruction bits, interface direction switch instruction bits, and data transfer instruction bits, and do not have continuous read instruction bits.
In order to improve transmission time sequence, so as to adapt more interactive devices and meet time sequence requirements of different interactive devices and different frequencies, in the embodiment, at least one state instruction is determined based on the time sequence requirements of the interactive devices, and then the instruction structure of the interactive devices is adapted based on the device instruction structure and the state instruction configuration of the interactive devices, so that the purposes of flexibly adapting the interactive devices with various instruction structures and enriching the model selection requirements of the interactive devices are achieved.
In some possible implementations, determining at least one status instruction based on timing requirements of the interaction device may include: and determining a first state instruction for starting the data synchronous clock after delaying the first preset time after the moment that the controller enters the working state from the non-working state based on the first preset time of the interval between the moment that the controller enters the working state from the non-working state and the starting moment of the data synchronous clock.
Fig. 2 is a schematic diagram showing an interval between a time when a time sequence requirement of an interactive device is a controller enters an operating state from a non-operating state and a starting time of a data synchronization clock in the configuration method of a command structure in the embodiment of the present disclosure. As shown in fig. 2, when the controller enters the working state from the non-working state, that is, when the chip select signal CSn is pulled down to be low level, a state is inserted between the time when the chip select signal CSn is pulled down to be low level and the transmission starting time of the external data synchronization clock SCLK, and a first preset time is prolonged to meet the time sequence requirement of the interactive device at the stage, and is shown in fig. 2.
During the state corresponding to the first instruction state, that is, during the first preset time, the controller, the FLASH memory or the PSRAM memory does not perform an operation, which is equivalent to inserting a delay interval between the time when the chip select signal CSn is pulled down to a low level and the time when the external data synchronization clock SCLK starts to transmit.
For whether the interactive device needs to wait for a period of time between the moment when the chip select signal CSn is pulled down to be low level and the moment when the external data synchronization clock SCLK starts to transmit, the timing parameters and the running frequency of the interactive device are specifically considered. For example, some flash memories need to wait for a period of time after the chip select signal CSn is pulled low to be low and then output the data synchronization clock SCLK, otherwise, the flash memories cannot operate. Therefore, the embodiment solves the compatibility of the flash memory by configuring the first state instruction for starting the data synchronous clock after the first preset time after the moment that the controller enters the working state from the non-working state.
The length of the first preset time is related to the time sequence requirement of the interactive device, and the length of the first preset time can be obtained from an equipment manual of the interactive device.
In some possible implementations, adapting the instruction structure of the interaction device based on the device instruction structure and the status instruction configuration may include: and configuring instruction bits corresponding to the first state instruction between the controller working state instruction bits and the command operation code instruction bits.
As shown in fig. 5, the first status instruction is denoted as csst, and in the instruction structure, the csst instruction bit is disposed between the controller operation status instruction bit idle_st and the command operation code instruction bit cmd_st.
In some possible implementations, determining at least one status instruction based on timing requirements of the interaction device may include: and converting the output interface state into the input interface state based on the condition that the second preset time is required to execute the read operation, and determining a second state instruction for converting the output interface state into the input interface state at the second preset time during the read operation.
Fig. 3 is a schematic diagram showing that the timing requirement of the interactive device in the command structure configuration method in the embodiment of the disclosure is to switch the output interface state to the input interface state when the second preset time is required to perform the read operation. As shown in fig. 3, when performing a read command operation, the interface needs to be converted from an output state to an input state, and a state is inserted in this stage to ensure that the conversion is successfully performed, so as to avoid the situation of multiple drives generated during the conversion.
In some possible implementations, adapting the instruction structure of the interaction device based on the device instruction structure and the status instruction configuration may include: and when the device instruction structure of the interactive device does not have an interface direction conversion instruction bit, configuring the instruction bit corresponding to the second state instruction between the data transmission instruction bit and a target address sending instruction bit.
As shown in fig. 5, the second state instruction is denoted as o2i_st, and in the instruction structure, the o2i_st instruction bit is arranged between the DATA transfer instruction bit data_st and the destination address transmission instruction bit addr_st.
The second state command o2_st is only used when the interaction protocol of the interaction device has no interface direction switch command dumm_st, and the interaction device having the interface direction switch command dumm_st is generally switched in the DUMM phase, as shown in fig. 3.
For the interactive device with the interface direction conversion instruction dumm_st, the o2i_st is not added, and the interactive device with the DUMM stage generally completes the conversion from the output interface to the input interface in the DUMM stage, and at this time, the second state instruction o2i_st may not be required.
During the state corresponding to the second state instruction, that is, during the second preset time, the controller needs to switch the IO interface from the output state to the input state in this period.
For whether the interactive device has an interface direction conversion instruction dumm_st, there is a dumm_st phase, reference may be made to whether the device manual of the interactive device has a need to set the DUMM phase.
The length of the second preset time is related to the time sequence requirement of the interactive device, and the time sequence requirement of the interactive device can be obtained according to the device manual of the interactive device. For example, the device manual of the FLASH memory knows that the FLASH memory does not specifically set aside the DUMM stage to change the IO interface direction, so that in order to avoid multiple driving when reading data, only the frequency can be reduced, and through the second state instruction in this embodiment, the output interface state is converted into the input interface state at a second preset time during the reading operation, that is, a buffer time can be provided for converting the output interface state into the input interface state, the IO conversion can be performed at the buffer time, the data synchronization clock SCLK of the state cannot be turned over, no data needs to be output, and the time period is only used for changing the directional configuration of the IO interface.
In some possible implementations, determining at least one status instruction based on timing requirements of the interaction device may include: and determining a third state instruction for the controller to enter the non-working state from the working state after delaying the third preset time after the data transmission completion time based on the third preset time of the interval between the data transmission completion time and the time when the controller enters the non-working state from the working state.
Fig. 4 is a schematic diagram showing a third preset time interval between a time when data transmission is completed and a time when a controller enters a non-working state from a working state in the time when the time sequence requirement of the interaction device in the command structure configuration method in the embodiment of the disclosure. As shown in fig. 4, a third preset time is spaced between the time when the data transmission is completed and the time when the controller enters the non-working state from the working state, that is, a state is inserted between the time when the data transmission is completed and the IDLE state (non-working state) of the controller, and the third preset time is prolonged to meet the time sequence requirement of the interactive device at this stage, and is shown in fig. 4.
During the state corresponding to the third instruction state, that is, during the third preset time, the controller, the FLASH memory or the PSRAM memory does not perform an operation, which is equivalent to inserting a delay interval between the time when the chip select signal CSn is pulled high to the high level at the time of completion of data transmission, that is, waiting for a period of time before the completion of data transmission and the state of the controller IDLE.
For whether the interactive device needs to wait for a period of time between the time when the data transmission is completed and the time when the controller enters the non-working state from the working state, the time sequence parameters and the running frequency of the interactive device are specifically seen.
The length of the third preset time is related to the time sequence requirement of the interactive device, and the length of the third preset time can be obtained from an equipment manual of the interactive device.
In some possible implementations, adapting the instruction structure of the interaction device based on the device instruction structure and the status instruction configuration may include: and configuring instruction bits corresponding to the third state instruction between the data transmission instruction bits and the controller working state instruction bits.
As shown in fig. 5, the third state instruction is denoted as tcsh_st, and in the instruction structure, the tcsh_st instruction bit is disposed between the DATA transfer instruction bit data_st and the operation state instruction bit idle_st of the controller.
In some possible implementations, the interaction device includes a memory coupled with the controller, and adapting the instruction structure of the interaction device based on the device instruction structure and the status instruction configuration may include: an instruction structure adapted to the memory is configured in a register of the controller.
It should be noted that, according to the actual time sequence requirement of the interaction device, a specific instruction structure of each stage and whether the stage is experienced or not are agreed through a configuration register, and finally, an instruction structure adapting to the interaction device is formed.
In the instruction structure of fig. 5, there are no instruction bits that have to be added, specifically, whether to add the instruction bit css_st corresponding to the first state instruction, the instruction bit o2i_st corresponding to the second state instruction, and the instruction bit tcsh_st corresponding to the third state instruction, which are determined according to the device instruction structure and the timing requirement of the interaction device. For example, when a WREN command is issued, only the command opcode command CMD_ST is required, and when a read DATA command is issued, there is CMD_ST+ADDR_ST+DUMM_ST+DATA_ST. And if the time sequence does not meet the time sequence requirement of the interactive equipment, then adjusting the time sequence of the interactive equipment according to the instruction bit corresponding to the joining state instruction.
Taking FLASH as an example, WREN/ERASE has only commands of CMD_ST, continuous reading has only commands of ADDR_ST+AX_ST+DUMM_ST+DATA_ST, RDID has commands of CMD_ST+DUMM_ST+DATA_ST, and the like. Because of the complex combination of instruction structures, the configuration method of the instruction structures according to the embodiment can flexibly adapt to the combination forms of various instruction structures and flexibly adapt to the time sequence demands of FLASH of different instruction structures.
In an example of configuring an instruction structure through a configuration register, adapting an instruction structure of the interaction device based on the device instruction structure and the status instruction configuration may include: the instruction thread, shan Shuangyan sample, and instruction length of each instruction bit are configured.
The agreed instructions in the interaction protocol can use 1 thread, 2 thread, 4 thread, 8 thread or 16 thread to carry out single-delay sampling transmission or double-delay sampling transmission.
The general protocol is agreed to describe the number of threads in each phase in the form of a-B-C. A represents the number of threads used by CMD_ST and Shan Shuangyan samples, B represents the number of threads used by ADDR_ST and Shan Shuangyan samples, and C represents the number of threads used by DATA_ST and Shan Shuangyan samples.
For example, 1S-4S-4S represents the command transmission of CMD_ST using 1-line single-delay sampling, the first 4S representing ADDT_ST using 4-line single-delay sampling, and the second 4S representing DATA_ST using 4-line single-delay sampling. The transition state of dumm_st is not included in this expression.
Forming a complete instruction structure also requires length information, such as how many bytes of data to send, and what bytes of instructions to compose. A common xSPI protocol instruction is a 1byte, with a small portion of the xSPI instructions using a 2byte instruction. The instruction of the hyperbus protocol is 3 bits.
Fig. 6 shows an exemplary diagram of a device instruction structure of an interactive device in the instruction structure configuration method in the embodiment of the present disclosure. As shown in FIG. 6, the device instruction structure of the interactive device is a 1S-4S-4S structure. The register informs that the IP is currently 1S-4S-4S, the command operation code command CMD_ST is 1byte, the target address sending command ADDT_ST is 3byte, the AX_ST command exists, the interface direction conversion command DUMM_ST is 4 DATA synchronous clocks in length, and the DATA transmission command DATA_ST is 3byte.
Therefore, each instruction bit in the instruction structure needs to be configured according to the thread, single-double delay sampling and the number of bits sent, so as to form the required instruction structure. The method for configuring the instruction structure of the embodiment can enable the controller to be compatible with most FLASH memories based on protocols such as xSPI and hyperbus or variant protocols in the prior art.
The present disclosure also provides a computer-readable storage medium having stored thereon a computer program that is executed to implement the instruction structure configuration method provided by any of the embodiments of the present disclosure.
In some possible implementations, any combination of one or more storage media may be employed. The storage medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a RAM, a ROM, an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The embodiment of the disclosure also provides a controller. Fig. 7 is a schematic diagram of the principle structure of the controller 101 according to some embodiments of the disclosure. As shown in fig. 7, the controller 101 includes a memory 1001, a processor 1002, and a register 1003. The processor 1002 is configured to configure an instruction structure for the interactive apparatus in the register 1003 according to the instruction structure configuration method disclosed in the present embodiment.
In some embodiments, memory 1001 may be FLASH memory, PSRAM pseudo-static random access memory, random Access Memory (RAM), and/or cache memory, among others. In some embodiments, the processor 1002 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), and the like. In other embodiments, the processor 1002 may also be a digital signal processor (Digital Signal Processor, DSP for short), application specific integrated circuit (Application Specific Integrated Circuit, ASIC for short), field programmable gate array (Field Programmable Gate Array, FPGA for short), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.
In summary, in the instruction structure configuration method provided by the embodiment of the present disclosure, the status instruction is determined based on the time sequence requirement of the interaction device, and the instruction structure of the interaction device is adapted based on the device instruction structure and the status instruction configuration of the interaction device, so that the interaction device with various instruction structures can be flexibly adapted, and the type selection requirement of the interaction device is enriched. Therefore, the method overcomes various defects in the prior art and has a high application prospect.
The above embodiments are merely illustrative of the principles of the present disclosure and its efficacy, and are not intended to limit the disclosure. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present disclosure. Accordingly, it is intended that all equivalent modifications and variations which a person having ordinary skill in the art would accomplish without departing from the spirit and technical spirit of the present disclosure be covered by the claims of the present disclosure.

Claims (12)

1. A method for configuring an instruction structure, comprising:
acquiring a device instruction structure of the interaction device;
determining at least one status instruction based on timing requirements of the interaction device; and
adapting an instruction structure of the interaction device based on the device instruction structure and the status instruction configuration.
2. The instruction structure configuration method according to claim 1, wherein acquiring the device instruction structure of the interaction device includes:
the method comprises the steps of obtaining any combination of a controller working state instruction bit, a command operation code instruction bit, a target address sending instruction bit, a continuous reading instruction bit, an interface direction conversion instruction bit and a data transmission instruction bit.
3. The instruction structure configuration method of claim 2, wherein determining at least one status instruction based on timing requirements of the interaction device comprises:
and determining a first state instruction for starting the data synchronous clock after delaying the first preset time after the moment that the controller enters the working state from the non-working state based on the first preset time of the interval between the moment that the controller enters the working state from the non-working state and the starting moment of the data synchronous clock.
4. A method of configuring an instruction structure according to claim 3, wherein adapting the instruction structure of the interactive device based on the device instruction structure and the status instruction configuration comprises:
and configuring instruction bits corresponding to the first state instruction between the controller working state instruction bits and the command operation code instruction bits.
5. The instruction structure configuration method of claim 2, wherein determining at least one status instruction based on timing requirements of the interaction device comprises:
and converting the output interface state into the input interface state based on the condition that the second preset time is required to execute the read operation, and determining a second state instruction for converting the output interface state into the input interface state at the second preset time during the read operation.
6. The instruction structure configuration method of claim 5, wherein adapting the instruction structure of the interactive device based on the device instruction structure and the status instruction configuration comprises:
and when the device instruction structure of the interactive device does not have an interface direction conversion instruction bit, configuring the instruction bit corresponding to the second state instruction between the data transmission instruction bit and a target address sending instruction bit.
7. The instruction structure configuration method of claim 2, wherein determining at least one status instruction based on timing requirements of the interaction device comprises:
and determining a third state instruction for the controller to enter the non-working state from the working state after delaying the third preset time after the data transmission completion time based on the third preset time of the interval between the data transmission completion time and the time when the controller enters the non-working state from the working state.
8. The instruction structure configuration method of claim 7, wherein adapting the instruction structure of the interactive device based on the device instruction structure and the status instruction configuration comprises:
and configuring instruction bits corresponding to the third state instruction between the data transmission instruction bits and the controller working state instruction bits.
9. The instruction structure configuration method according to any one of claims 1 to 8, characterized in that adapting an instruction structure of the interactive device based on the device instruction structure and the status instruction configuration comprises:
the instruction thread, shan Shuangyan sample, and instruction length of each instruction bit are configured.
10. The instruction structure configuration method of claim 1, wherein the interactive device comprises a memory coupled to a controller, and adapting the instruction structure of the interactive device based on the device instruction structure and the status instruction configuration comprises:
an instruction structure adapted to the memory is configured in a register of the controller.
11. A controller comprising a processor and a register, the processor being configured to configure an instruction structure for the interaction device in the register according to the instruction structure configuration method of any one of claims 1 to 10.
12. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program is executed to implement the instruction structure configuring method according to any one of claims 1 to 10.
CN202310564804.3A 2023-05-18 2023-05-18 Instruction structure configuration method, controller and computer readable storage medium Pending CN116644009A (en)

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