CN116633379A - Communication device and method for compensating frequency response distortion of communication device - Google Patents
Communication device and method for compensating frequency response distortion of communication device Download PDFInfo
- Publication number
- CN116633379A CN116633379A CN202210124930.2A CN202210124930A CN116633379A CN 116633379 A CN116633379 A CN 116633379A CN 202210124930 A CN202210124930 A CN 202210124930A CN 116633379 A CN116633379 A CN 116633379A
- Authority
- CN
- China
- Prior art keywords
- predistortion
- circuit
- coefficients
- communication device
- equalizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004044 response Effects 0.000 title claims abstract description 55
- 238000004891 communication Methods 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000005540 biological transmission Effects 0.000 claims abstract description 32
- 238000012360 testing method Methods 0.000 claims abstract description 26
- 238000012937 correction Methods 0.000 claims abstract description 18
- 238000006243 chemical reaction Methods 0.000 claims description 16
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000003993 interaction Effects 0.000 description 3
- 238000007781 pre-processing Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
Abstract
The invention provides a communication device and a method for compensating frequency response distortion of the communication device. The communication device includes a transmission path, a reception path, a memory predistortion circuit, a pre-equalizer and a pre-equalizer calculation circuit. The transmitting path and the receiving path are used for generating a feedback signal according to a predistortion test signal, wherein a group of predistortion coefficients of the memory predistortion circuit are corrected according to the feedback signal. After the correction of the predistortion coefficients is completed, the predistortion coefficient set is calculated by the predistortion calculation circuit to generate a calculation result for correcting the predistorter. After the correction of the pre-equalizer is completed, the transmission signal is processed by the pre-equalizer and the memory pre-distortion circuit and then output to the outside of the communication device through the transmission path.
Description
Technical Field
The present invention relates to signal preprocessing of a communication device, and more particularly, to a communication device and a method for compensating frequency response distortion of the communication device.
Background
In the conventional wireless broadband communication apparatus, various signal processing methods are used to improve linearity. However, these signal processing techniques have certain problems. For example, when some signal in a wireless broadband communication device is preprocessed by these signal processing methods for improving linearity, the frequency response of the wireless broadband communication device is distorted due to the preprocessing.
Accordingly, there is a need for a novel approach and related architecture to address the problems of the related art without or with less side effects.
Disclosure of Invention
An object of the present invention is to provide a communication device and a method for compensating for frequency response distortion of the communication device, so as to improve linearity of the communication device without causing or being less likely to cause frequency response distortion.
At least one embodiment of the present invention provides a communication device. The communication device comprises a transmission path, a receiving path, a memory predistortion (pre-distortion) circuit, a pre-equalizer and a pre-equalizer calculation circuit, wherein the memory predistortion circuit and the pre-equalizer are both positioned at the front end of the transmission path, and the pre-equalizer calculation circuit is coupled to the pre-equalizer. The transmitting path is used for generating an output test signal according to a predistortion test signal, and the receiving path is used for generating a feedback signal according to the output test signal, wherein a group of predistortion coefficients of the memory predistortion circuit are corrected according to the feedback signal. In addition, after the correction of the predistortion coefficients of the memory predistortion circuit is completed, the predistortion calculation circuit receives the predistortion coefficients to calculate the predistortion coefficients to generate a calculation result, and the pre-equalizer is corrected according to the calculation result, especially after the correction of the pre-equalizer is completed, a transmission signal is processed by the pre-equalizer and the memory predistortion circuit and then is output to the outside of the communication device through the transmission path.
At least one embodiment of the present invention provides a method for compensating for frequency response distortion of a communication device, wherein the method comprises: generating an output test signal according to a predistortion test signal by using a transmission path of the communication device; generating a feedback signal according to the output test signal by using a receiving path of the communication device; correcting a set of predistortion coefficients of a memory predistortion circuit of the communication device according to the feedback signal; after the correction of the group of predistortion coefficients of the memory predistortion circuit is completed, receiving the group of predistortion coefficients by using a predistortion calculation circuit of the communication device so as to calculate the group of predistortion coefficients to generate a calculation result; a pre-equalizer (pre-equalizer) of the communication device is calibrated according to the calculation result. In addition, after the calibration of the pre-equalizer is completed, a transmission signal is processed by the pre-equalizer and the memory pre-distortion circuit and then outputted to the outside of the communication device through the transmission path.
According to the communication device and the method provided by the embodiment of the invention, the pre-equalizer can compensate the frequency response distortion caused by pre-distortion processing on the path comprising the low-pass filter. In addition, embodiments of the present invention do not add significant additional cost. Accordingly, the present invention can solve the problems of the related art without side effects or with less side effects.
Drawings
FIG. 1 is a diagram of estimating a memory digital predistortion coefficient in a communication device in accordance with an embodiment of the present invention.
Fig. 2 is a flowchart of a method for compensating for frequency response distortion of the communication device of fig. 1 in accordance with one embodiment of the present invention.
FIG. 3 is a schematic diagram of a digital predistortion circuit in the communication device of FIG. 1 according to one embodiment of the present invention.
FIG. 4 illustrates the operation of a digital predistortion circuit and a digital predistortion pre-equalizer in the communication device of FIG. 1 after calibration in accordance with one embodiment of the present invention.
FIG. 5 shows some implementation details of a digital predistortion pre-equalization calculation circuit in accordance with an embodiment of the present invention.
Detailed Description
Fig. 1 is a diagram of estimating Memory Digital Predistortion (MDPD) coefficients in a communication device, such as transceiver 10, in accordance with one embodiment of the present invention. As shown in fig. 1, transceiver 10 may include a transmit path 110TX, a receive path 110RX, an MDPD circuit 120, an MDPD pre-equalizer (pre-equalizer) 130. In the present embodiment, the transmission path 110TX may include a digital-to-analog converter 111TX (DAC), a transmission filter 112TX, a mixer 113TX and a power amplifier 114TX, and the reception path 110RX may include an analog-to-digital converter 111RX (ADC), a reception filter 112RX, a mixer 113RX and an attenuator 114RX. In this embodiment, the transceiver 10 may further include an MDPD calculation circuit 140 and an MDPD pre-equalizer calculation circuit 150, wherein the transceiver 10 may use the MDPD calculation circuit 140 to calibrate the MDPD circuit 120 (e.g. to calibrate a set of predistortion coefficients of the MDPD circuit 120), and then use the MDPD pre-equalizer calculation circuit 150 to calibrate the MDPD pre-equalizer 130 according to the set of predistortion coefficients. Specifically, the MDPD circuit 120 may be used to compensate for the nonlinear distortion of the power amplifier 114TX in the transmit path 110TX after correction is complete, and the MDPD pre-equalizer 130 may be used to compensate for the frequency response distortion generated by the MDPD circuit 120 after correction if either of the transmit path 110TX and the receive path 110RX includes a filter (e.g., the transmit filter 112TX and/or the receive filter 112 RX) after correction is complete. For example, when the transmit path 110TX and/or the receive path 110RX include any filter, the MDPD circuit 120 generates a frequency response distortion according to the frequency response of the filter after being corrected, and the frequency response distortion can be compensated/cancelled by the frequency response of the MDPD pre-equalizer 130. In addition, the MDPD circuit 120 and the MDPD pre-equalizer 130 are located at the front end of the transmission path 110TX, and after the calibration of the MDPD circuit 120 and the MDPD pre-equalizer 130 is completed, a transmission signal may be processed by the MDPD pre-equalizer 130 and the MDPD circuit 120 and then output to the outside of the transceiver 10 through the transmission path 110TX (e.g., through an antenna coupled to the transmission path 110 TX). In this embodiment, the transceiver 10 may utilize multiplexers (multiplexers) 160 and 170 (labeled "MUX" in the figure for simplicity) therein to control the correction signal paths of the MDPD circuit 120 and the MDPD pre-equalizer 130 (e.g., a controller therein generates a plurality of control signals for controlling the multiplexers 160 and 170 to enable one of the upper and lower paths thereof, respectively), and details about the correction of the MDPD circuit 120 and the MDPD pre-equalizer 130 will be described in the following paragraphs. In some embodiments, the multiplexer 170 may be omitted and the input of the MDPD circuit 120 may be coupled to the output of the MDPD pre-equalizer 130, but the invention is not limited thereto.
Fig. 2 is a flowchart of a method for compensating for distortion in the frequency response of a communication device, such as transceiver 10 shown in fig. 1, in accordance with one embodiment of the present invention. It should be noted that the workflow shown in fig. 2 is for illustration purposes only and is not a limitation of the present invention. In particular, one or more steps may be added, deleted, or modified in the workflow shown in FIG. 2. Furthermore, these steps need not be performed in the exact order shown in FIG. 2, so long as the overall result is not hindered.
In step S210, the communication device generates an output test signal according to a predistortion test signal by using a transmission path therein.
In step S220, the communication device generates a feedback signal according to the output test signal by using a receiving path therein.
In step S230, the communication device corrects a set of predistortion coefficients of a memory predistortion circuit therein according to the feedback signal.
To facilitate understanding of the operations of steps S210 to S230, please refer to fig. 3. The transceiver 10 (e.g., a controller therein) may control the multiplexer 160 to enable (enable) its upper path and disable (disable) its lower path to bypass (bypass) the MDPD pre-equalizer 130 and the MDPD circuit 120 such that a pre-distortion TEST signal TEST is generated MDPD Is input to the transmission path 110TX without the MDPD pre-equalizer 130 and the MDPD circuit 120, and sequentially processed by the DAC 111TX, the transmission filter 112TX, the mixer 113TX and the power amplifier 114TX to generate an output TEST signal TEST OUT . Output TEST signal TEST OUT Can then be transmitted to the receiving path 110RX and sequentially through the attenuator 114RX, the mixer 113RX, and thenThe receiving filter 112RX and the analog-to-digital converter 111RX generate a feedback signal FB1. The MDPD calculating circuit 140 can calculate the feedback signal FB1 and the predistortion TEST signal TEST MDPD A comparison is made to estimate the nonlinear distortion caused by the power amplifier 114TX and a set of predistortion coefficients { a } is calculated therefrom mp As coefficients of filters within the MDPD circuit 120, so that the MDPD circuit 120 can pre-distortion process the transmit signal to compensate for non-linear distortion caused by the power amplifier 114 TX.
Since the transmit path 110TX includes the transmit filter 112TX and the receive path 110RX includes the receive filter 112RX, the frequency response of the MDPD circuit 120 is distorted after the transceiver 10 corrects the MDPD circuit 120 with the signal path shown in fig. 3. For example, when the transmission filter 112TX and the reception filter 112RX are both low-pass filters, the amplitude response of the low-pass filters is suppressed down in the high frequency band, so that equalization compensation by the corrected MDPD circuit 120 causes the amplitude response to be raised up in the high frequency band. Therefore, the present invention can perform the pre-equalization processing according to the corrected frequency response of the MDPD circuit 120 in the subsequent steps to solve the above-mentioned problem of frequency response distortion.
In step S240, after the correction of the set of predistortion coefficients of the memory predistortion circuit is completed, the communication device receives the set of predistortion coefficients by using a pre-equalization calculation circuit therein to calculate the set of predistortion coefficients to generate a calculation result.
In step S250, the communication device corrects a pre-equalizer therein according to the calculation result.
When the memory depth of the MDPD circuit 120 is M, the MDPD circuit 120 may determine the input signal at the current time point, such as the signal x (n) (which may represent the nth input sample received by the MDPD circuit 120), the input signals at the first M time points at the current time point, such as the signals x (n-1), x (n-2), x (n-3), …, and x (n-M) (which may represent the (n-1) th input sample, the (n-2) th input sample, the (n-3) th input sample, …, and the (n-M) th input sample received by the MDPD circuit 120), and the set of predistortion coefficients (e.g., { a } mp }) yield ofAn output signal (e.g., the nth output sample) is generated for the current time point, wherein M, n is a positive integer. In particular, the set of predistortion coefficients (e.g. { a mp (m+1) first-order coefficients may be included, and the (m+1) first-order coefficients correspond to (m+1) weights (weights) of the input signal at the current time point and the input signal at the first M time points, respectively.
For example, the output signal of the MDPD circuit 120 may be described by a generic memory polynomial (Generalized Memory Polynomial, GMP) model as follows:
wherein y is GMP (n) represents the nth output sample, C, of MDPD circuit 120 lead Representing the maximum length of the leading interaction term (lead cross-term), C lag Representing the maximum length of the lag cross-term, and x (n-m) represents the (n-m) th input sample of the MDPD circuit 120. Thus, the set of predistortion coefficients (e.g., { a } mp }、{b mpc { c } mpc After correction of (a)), MDPD pre-equalization calculation circuit 150 may perform a correction on the set of predistortion coefficients (e.g., { a } mp }、{b mpc { c } mpc }) to obtain the frequency response distortion generated by the MDPD circuit 120, and to correct the MDPD pre-equalization circuit 130 accordingly so that the frequency response of the MDPD pre-equalization circuit 130 cancels/compensates for the frequency response distortion generated by the MDPD circuit 120.
As shown in fig. 4, after the MDPD circuit 120 and the MDPD pre-equalizer 130 are calibrated, the transceiver 10 (e.g., a controller therein) may control the multiplexer 160 to enable its lower path and disable its upper path, and control the multiplexer 170 to enable its lower path and disable its upper path, so that a transmission signal TXDATA may be sequentially processed by the MDPD pre-equalizer 130 and the MDPD circuit 120 and then output to the outside of the transceiver 10 through the transmission path 110 TX.
FIG. 5 is a diagram of an MDPD pre-equalization calculation circuit 150 according to an embodiment of the inventionSome implementation details. As shown in fig. 5, the MDPD pre-equalization calculation circuit 150 may include a time-to-frequency domain conversion circuit such as a discrete fourier transform (Discrete Fourier Transform, DFT) circuit 151 (labeled "DFT" in fig. 5 for simplicity), a channel estimator (channel estimator) such as an absolute value calculation circuit 152 (labeled "amplitude= |response|" in fig. 5 for ease of understanding), a reciprocal calculation circuit 153 (labeled "1/amplitude" in fig. 5 for ease of understanding), and an inverse discrete fourier transform (Inverse Discrete Fourier Transform, IDFT) circuit 154 (labeled "IDFT" in fig. 5 for simplicity). It should be noted that, to simplify the design of the MDPD pre-equalization calculation circuit 150 to reduce its hardware cost and calculation time, the MDPD pre-equalization calculation circuit 150 is not necessarily based on the set of predistortion coefficients (e.g., { a } mp }、{b mpc { c } mpc All of which) calculates the frequency response of MDPD circuit 120. In this embodiment, the coefficients { b } of the leading and trailing interaction terms mpc { c } mpc And can be ignored. In addition, the MDPD pre-equalization calculation circuit 150 may further include a selection circuit 155 (labeled "first-order coefficient selection" in FIG. 5 for ease of understanding) for selecting the predistortion coefficients { a } mp The first order coefficients are discarded, and the predistortion coefficients other than the first order coefficients are discarded, thereby further reducing the hardware cost and calculation time of subsequent processing.
For example, assume that the output signal y (n) of the MDPD circuit 120 is described as follows by a general memory polynomial model with an order of 5, a memory depth of 3, and a maximum length of 1 of the lag cross-terms (lag cross-term) after completion of the correction:
y(n)＝w(1)·x(n)+w(2)·x(n)·|x(n)| 2 +w(3)·x(n)·|x(n)| 4
+w(4)·x(n–1)+w(5)·x(n–1)·|x(n–1)| 2 +w(6)·x(n–1)·|x(n–1)| 4
+w(7)·x(n–2)+w(8)·x(n–2)·|x(n–2)| 2 +w(9)·x(n–2)·|x(n–2)| 4
+w(10)·x(n–3)+w(11)·x(n–3)·|x(n–3)| 2 +w(12)·x(n–3)·|x(n–3)| 4
+w(13)·x(n)·|x(n–1)| 2 +w(14)·x(n)·|x(n–1)| 4
+w(15)·x(n–1)·|x(n–2)| 2 +w(16)·x(n–1)·|x(n–2)| 4
+w(17)·x(n–2)·|x(n–3)| 2 +w(18)·x(n–2)·|x(n–3)| 4
+w(19)·x(n–3)·|x(n–4)| 2 +w(20)·x(n–3)·|x(n–4)| 4
wherein w (13) to w (20) are lag interaction term coefficients { b } mpc Examples of }, w (2), w (5), w (8) and w (11) are predistortion coefficients { a } mp Examples of third order term coefficients in the case of }, and w (3), w (6), w (9), and w (12) are predistortion coefficients { a } mp Examples of fifth order term coefficients in. Thus, the selection circuit 155 may apply the predistortion coefficients { a } mp Discarding coefficients other than the first-order coefficients w (1), w (4), w (7) and w (10) in the second order to reduce the output signal y (n) to y SIMP (n) =w (1) ·x (n) +w (4) ·x (n-1) +w (7) ·x (n-2) +w (10) ·x (n-3), but the present invention is not limited thereto. Since the frequency response of the MDPD circuit 120 is typically dominated by first order coefficients, even though the present embodiment greatly simplifies the computation of the set of predistortion coefficients, correcting the MDPD pre-equalizer 130 with the simplified computation described above still enables the MDPD pre-equalizer 130 to effectively compensate/equalize the frequency response of the MDPD circuit 120.
In this embodiment, the selection circuit 155 may select a predetermined value from the set of predistortion coefficients (e.g., { a mp (m+1) first order term coefficients { a) selected from them 01 ,a 11 ,a 21 ,…,a M1 And sequentially arranging and outputting { d [0] as memory depth corresponding to each first-order term coefficient],d[1],d[2],…,d[M]The following are set forth:
next, the discrete fourier transform circuit 151 may perform a time-domain to frequency-domain transform such as a discrete fourier transform (which may be implemented in practice with a fast fourier transform (Fast Fourier Transform, FFT)) on the (m+1) first-order term coefficients { D [0], D [1], D [2], …, D [ M ] } output by the selection circuit 155 to obtain (m+1) frequency-domain transform results { D [ k ] } corresponding to the (m+1) frequencies, respectively, as follows:
and any one of the (m+1) frequency domain conversion results D [ k ] may be expressed as follows:
where k=0, 1, 2, …, M (corresponding to the (m+1) frequencies, respectively), "e" may represent You La numbers (Euler's numbers), "pi" may represent the circumference ratio, and "j" may represent the circumference ratioThen, the absolute value calculation circuit 152 can calculate the (M+1) frequency domain conversion results { Dk }, respectively]Absolute value calculation is performed to obtain (M+1) amplitude response values { |D [ k ] corresponding to the (M+1) frequencies respectively]I. Due to the frequency domain conversion result Dk obtained via discrete Fourier conversion]Is complex number, so the (M+1) amplitude response values { |D [ k ]]Any amplitude response value |d [ k ]]The calculation of i is as follows:
wherein real (D [ k ]]) Representing the frequency domain conversion result Dk]Real part of (D), while imag (D [ k)]) Representing the frequency domain conversion result Dk]Imaginary part (imaginary part). Then, the inverse calculation circuit 153 may calculate the (M+1) amplitude response values { |Dk]Reciprocal calculation is performed to obtain (M+1) compensation gains { S } corresponding to the (M+1) frequencies, respectively PreEQ_freq [k]And the (M+1) compensation gains { S }, respectively PreEQ_freq [k]Any compensation gain S PreEQ_freq [k]Is calculated as follows:
then, the inverse discrete Fourier transform circuit 154 can compensate the gain { S } for the (M+1) pieces respectively PreEQ_freq [k]Frequency-domain to time-domain conversion such as an inverse discrete fourier transform (which may be implemented in practice with an inverse fast fourier transform (Inverse Fast Fourier Transform, IFFT)) to obtain (m+1) pre-equalization coefficients { S PreEQ_time [r]As the calculation result, wherein the (M+1) pre-equalization coefficients { S } are PreEQ_time [r]Any pre-equalization coefficient S in } PreEQ_time [r]Is calculated as follows:
where r=0, 1, 2, …, M, and the (m+1) pre-equalization coefficients { S PreEQ_time [r]The frequency response of MDPD pre-equalizer 130 is made to correspond to the (M+1) compensation gains { S }, respectively PreEQ_freq [k]A frequency response constructed to cancel/compensate for frequency response distortion generated by MDPD circuit 120.
In some embodiments, the MDPD pre-equalizer 130 may include a filter (e.g., a finite impulse response (finite impulse response, FIR) filter or an infinite impulse response (infinite impulse response, IIR) filter) with the (M+1) pre-equalization coefficients { S } PreEQ_time [r]The coefficients of the filter (e.g., (M+1) coefficients corresponding to (M+1) taps, respectively, in the filter) may be used to match a frequency response of the filter to the (M+1) compensation gains S PreEQ_freq [k]The frequency response constituted by }, but the invention is not limited thereto.
It should be noted that each sub-circuit (e.g., discrete fourier transform circuit 151, absolute value calculation circuit 152, inverse discrete fourier transform circuit 153, and inverse discrete fourier transform circuit 154) within the MDPD pre-equalization calculation circuit 150 may be implemented with a calculation circuit dedicated to the above calculations, respectively. In some embodiments, some of the more complex computations (e.g., discrete fourier transform circuits and/or inverse discrete fourier transforms) within the MDPD pre-equalization computation circuit 150 may use proprietary computation circuits, while some of the simpler computations (e.g., absolute value computations and/or inverse computation) may be performed by existing computation circuits within the discrete fourier transform circuit 151 and/or the inverse discrete fourier transform circuit 154, or by existing computation circuits external to the MDPD pre-equalization computation circuit 150, although the invention is not limited in this respect.
In summary, the present invention utilizes MDPD circuitry 120 to pre-distortion the input signal to compensate for the non-linear distortion of the power amplifier 114 TX. Since the filter characteristics in the signal path may be involved in correcting the MDPD circuit 120, resulting in distortion (e.g., having a high pass filter characteristic) of the frequency response of the MDPD circuit 120 after correction, the present invention utilizes the MDPD pre-equalizer 130 to provide a frequency response (e.g., a low pass filter characteristic) that is offset from the frequency response distortion of the MDPD circuit 120 to compensate for the frequency response distortion generated by the MDPD circuit 120. In addition, embodiments of the present invention do not add significant additional cost. Accordingly, the present invention can solve the problems of the related art without side effects or with less side effects.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
[ symbolic description ]
10 transceiver
110TX transmission path
111TX digital-to-analog converter
112TX transmit filter
113TX mixer
114TX power amplifier
110RX receiving path
111RX analog-to-digital converter
112RX receiving filter
113RX mixer
114RX attenuator
120 memory digital predistortion circuit
130 memory digital predistortion pre-equalizer
140 memory digital predistortion calculation circuit
150 memory digital predistortion pre-equalization calculation circuit
160,170 multiplexer
S210-S250 steps
TEST MDPD Predistortion test signal
FB1 feedback Signal
TXDATA transmission signal
151 discrete Fourier transform circuit
152 absolute value calculating circuit
153 reciprocal calculating circuit
154 inverse discrete Fourier transform circuit
155 selection circuitry.
Claims (10)
1. A communication device, comprising:
a transmission path for generating an output test signal according to a predistortion test signal;
a receiving path for generating a feedback signal according to the output test signal;
a memory predistortion circuit located at the front end of the transmission path, wherein a set of predistortion coefficients of the memory predistortion circuit are corrected according to the feedback signal;
a pre-equalizer located at the front end of the transmission path; and
a pre-equalizer circuit coupled to the pre-equalizer, wherein after the correction of the set of predistortion coefficients of the memory predistortion circuit is completed, the pre-equalizer circuit receives the set of predistortion coefficients to calculate the set of predistortion coefficients to generate a calculation result, and the pre-equalizer is corrected according to the calculation result;
after the calibration of the pre-equalizer is completed, a transmission signal is processed by the pre-equalizer and the memory pre-distortion circuit and then outputted to the outside of the communication device through the transmission path.
2. The communication device of claim 1, wherein a memory depth of the memory predistortion circuit is M, the memory predistortion circuit generates an output signal at a current time point based on an input signal at the current time point, the input signals at the previous M time points at the current time point, and the set of predistortion coefficients, wherein M is a positive integer.
3. The communication device of claim 2, wherein the set of predistortion coefficients includes m+1 first order coefficients, and each of the m+1 first order coefficients corresponds to one of m+1 weights, the m+1 weights including one weight of the input signal at the current time point and M weights of the input signal at the first M time points.
4. The communication device of claim 3, wherein the computing of the set of predistortion coefficients by the pre-equalization calculation circuit comprises:
the pre-equalization calculation circuit performs time domain to frequency domain conversion on the M+1 first order coefficients to obtain M+1 frequency domain conversion results each corresponding to one of the M+1 frequencies;
the pre-equalization calculation circuit respectively calculates absolute values of the M+1 frequency domain conversion results to obtain M+1 amplitude response values corresponding to one of the M+1 frequencies;
the pre-equalization calculation circuit respectively performs reciprocal calculation on the M+1 amplitude response values to obtain M+1 compensation gains corresponding to one of the M+1 frequencies; and
the pre-equalization calculation circuit performs frequency domain to time domain conversion on the M+1 compensation gains to obtain M+1 pre-equalization coefficients as the calculation result, wherein the M+1 pre-equalization coefficients enable a frequency response of the pre-equalizer to correspond to a frequency response formed by the M+1 compensation gains.
5. The communication device of claim 1, wherein the memory predistortion circuit is configured to compensate for nonlinear distortion of a power amplifier in the transmit path.
6. The communication device of claim 1 wherein the pre-equalizer is configured to compensate for frequency response distortion generated by the memory pre-distortion circuit after correction if either of the transmit path and the receive path includes a filter.
7. A method for compensating for frequency response distortion of a communication device, comprising:
generating an output test signal according to a predistortion test signal by using a transmission path of the communication device;
generating a feedback signal according to the output test signal by using a receiving path of the communication device;
correcting a set of predistortion coefficients of a memory predistortion circuit of the communication device according to the feedback signal;
after the correction of the group of predistortion coefficients of the memory predistortion circuit is completed, receiving the group of predistortion coefficients by using a predistortion calculation circuit of the communication device so as to calculate the group of predistortion coefficients to generate a calculation result; and
correcting a pre-equalizer of the communication device according to the calculation result;
after the calibration of the pre-equalizer is completed, a transmission signal is processed by the pre-equalizer and the memory pre-distortion circuit and then outputted to the outside of the communication device through the transmission path.
8. The method of claim 7, wherein a memory depth of the memory predistortion circuit is M, and the memory predistortion circuit generates an output signal at a current time point based on an input signal at the current time point, the input signals at the previous M time points at the current time point, and the set of predistortion coefficients, wherein M is a positive integer.
9. The method of claim 8, wherein the set of predistortion coefficients includes m+1 first order coefficients, and each of the m+1 first order coefficients corresponds to one of m+1 weights, the m+1 weights including one weight of the input signal at the current time point and M weights of the input signal at the first M time points.
10. The method of claim 9, wherein calculating the set of predistortion coefficients to produce the calculation comprises:
performing time domain to frequency domain conversion on the m+1 first order coefficients to obtain m+1 frequency domain conversion results each corresponding to one of the m+1 frequencies;
respectively carrying out absolute value calculation on the M+1 frequency domain conversion results to obtain M+1 amplitude response values corresponding to one of the M+1 frequencies;
performing reciprocal computation on the m+1 amplitude response values to obtain m+1 compensation gains each corresponding to one of the m+1 frequencies; and
frequency domain-to-time conversion is performed on the M+1 compensation gains respectively to obtain M+1 pre-equalization coefficients as the calculation result;
wherein the M+1 pre-equalization coefficients are such that a frequency response of the pre-equalizer corresponds to a frequency response of the M+1 compensation gains.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210124930.2A CN116633379A (en) | 2022-02-10 | 2022-02-10 | Communication device and method for compensating frequency response distortion of communication device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210124930.2A CN116633379A (en) | 2022-02-10 | 2022-02-10 | Communication device and method for compensating frequency response distortion of communication device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116633379A true CN116633379A (en) | 2023-08-22 |
Family
ID=87640455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210124930.2A Pending CN116633379A (en) | 2022-02-10 | 2022-02-10 | Communication device and method for compensating frequency response distortion of communication device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116633379A (en) |
-
2022
- 2022-02-10 CN CN202210124930.2A patent/CN116633379A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2202879B1 (en) | A predistortion apparatus and predistortion method | |
| EP1446871B1 (en) | Digital linearization circuit | |
| EP3054590B1 (en) | System linearization | |
| EP2859655B1 (en) | Modeling digital predistorter | |
| EP1560329B1 (en) | Digital predistorter using power series model | |
| KR101098134B1 (en) | Distortion compensation controller and distortion compensation control method | |
| US20020193087A1 (en) | Method and apparatus for modeling and estimating the characteristics of a power amplifier | |
| US20060133536A1 (en) | Power amplifier pre-distortion | |
| US10756682B1 (en) | Compensating for transmitter nonlinearities | |
| US7412469B2 (en) | Power amplifier pre-distorter training | |
| CN101662821A (en) | Signal processing method and communication system | |
| US6498529B1 (en) | Method and apparatus for calculating the predistortion function from a power amplifier | |
| US8712345B2 (en) | Distortion compensation device, distortion compensation method, and radio transmitter | |
| CN116633379A (en) | Communication device and method for compensating frequency response distortion of communication device | |
| EP0942525A1 (en) | Adaptive joint linearization, equalization and delay alignment for a wide-band power amplifier | |
| TWI819476B (en) | Communications device and method for compensating frequency response distortion of communication device | |
| CN113328845B (en) | Method and device for compensating flatness of downlink carrier | |
| CN116667863A (en) | Communication device and method for compensating frequency response distortion of communication device | |
| KR100762218B1 (en) | Apparatus for calibrating transmitters and receivers in array antenna system | |
| TW202333448A (en) | Communications device and method for compensating frequency response distortion of communication device | |
| US20100097137A1 (en) | Lookup table generation method and related device for a predistorter | |
| CN110868264B (en) | Time division duplex transceiver, calibration method thereof and readable storage medium | |
| CN113676156B (en) | LMS-based arbitrary amplitude-frequency response FIR filter design method | |
| KR100625445B1 (en) | Prediction apparatus with a varying order and its control method | |
| US11626897B2 (en) | Transmitter circuit, compensation value calibration device and method for calibrating IQ imbalance compensation values |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |