CN116633343A - Differential complementary arbiter PUF circuit suitable for FPGA platform - Google Patents
Differential complementary arbiter PUF circuit suitable for FPGA platform Download PDFInfo
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- CN116633343A CN116633343A CN202310557371.9A CN202310557371A CN116633343A CN 116633343 A CN116633343 A CN 116633343A CN 202310557371 A CN202310557371 A CN 202310557371A CN 116633343 A CN116633343 A CN 116633343A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a differential complementary arbiter PUF circuit suitable for an FPGA platform, which is used for generating output response and auxiliary information related to response stability by carrying out differential comparison on two complementary arbiter PUFs with the same layout and wiring characteristics. The complementary arbiter PUF circuit consists of a pulse synchronous circuit, a complementary delay circuit, an arbiter group and the like; the arbiter PUF circuit structure with good symmetry can be realized on an FPGA platform, and the response uniqueness is good. The differential structure can eliminate the influence of factors such as ambient temperature, power supply voltage and the like, so that the PUF response has good stability. The differential processing result of the two arbiter groups can embody response stability, and is convenient for subsequent processing to further improve response stability. The circuit has high response generation rate, and can quickly generate a large amount of responses at a higher clock frequency because cyclic bias adjustment is not needed.
Description
Technical Field
The invention belongs to the field of physical unclonable functions, and particularly relates to a differential complementary arbiter PUF circuit suitable for an FPGA platform.
Background
The Physical Unclonable Function (PUF) is a novel hardware security technology, and is used for extracting hardware fingerprints from uncontrollable process deviations in the manufacturing process of integrated circuit chips and applied to key generation, hardware security authentication and the like. Because the process deviation has uncontrollable and random characteristics, the hardware fingerprint extracted from different chips by using the PUF technology has unique and physical unclonable characteristics, and the security of the hardware system can be enhanced.
Arbiter PUF is a lightweight PUF circuit consisting of a configurable delay circuit and an arbiter, as shown in fig. 1. The configurable delay circuit is formed by cascading n switch modules into two configurable signal transmission paths, and is provided with n-bit excitation input ports, two signal input ports and two signal output ports. Each switch module consists of two selectors, and is controlled by the same excitation bit Ci to form two parallel and crossed transmission paths. The input pulse is input into the configurable delay circuit from the upper path and the lower path respectively, and reaches the arbiter through two different transmission paths. The arbiter is typically formed of flip-flops that arbitrate the two-way signal propagation delays to generate a 1-bit response R output. One stimulus signal C and one bit response R constitute a set of stimulus-response pairs. The number of stimulus responses of an arbiter PUF consisting of n-stage switch modules is 2 n . The exponential stimulus response number enables the arbiter PUF to generate a large amount of response data with a small hardware resource overhead, suitable for various lightweight security solutions.
In an ideal arbiter PUF, the two configurable delay paths should have the same nominal propagation delay, and random process variations in the manufacturing process cause the two paths in different PUF entities to differ in delay, and thus the resulting responses to be different. This requires symmetrical placement and routing of the delay path of the arbiter PUF circuit between the pulse input to the input of the arbiter. The overall delay path of the arbiter PUF can be divided into four parts, namely a pulse input end, a parallel transmission path of the switch modules, a cross transmission path of the switch modules, and an output end of the switch module of the last stage, to an input end of the arbiter. According to the characteristics of the FPGA device, symmetrical wiring is simple on parallel transmission paths of the switch module, and other partial circuits are difficult to realize symmetrical wiring, so that the uniqueness of PUF response is poor.
Even if strict wiring delay constraint is adopted, so that the upper and lower delays are approximately equal, the influence of the change of the ambient temperature and the supply voltage is difficult to cope with. FPGA wiring resources which are passed by upper and lower transmission paths of asymmetric wiring are different, so that the FPGA wiring resources are affected differently by the change of the ambient temperature and the power supply voltage, the response uniformity of the arbiter PUF can be greatly fluctuated, and the stability of coping with the change of the ambient temperature and the power supply voltage is poor.
Disclosure of Invention
The invention aims to solve the technical problems in the background art and provides a differential complementary arbiter PUF circuit suitable for an FPGA platform.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a differential complementary arbiter PUF circuit suitable for use in an FPGA platform, comprising: two complementary arbiter PUF circuits with identical place and route characteristics;
the input end of the complementary arbiter PUF circuit is input with a pulse and is driven by the same clock; differential comparison of the complementary arbiter PUF circuits generates an output response and side information related to response stability.
Further, the complementary arbiter PUF circuit includes: a pulse synchronization circuit, a complementary delay circuit, and an arbiter set;
the arbiter set is responsive to the complementary delay circuit, which is responsive to the pulse synchronization circuit.
Further, the pulse synchronization circuit comprises two D flip-flops, and the data input ports of the two D flip-flops receive the input pulse of the PUF circuit and output the synchronization pulse under the drive of the same clock.
Further, for n-bit input excitation signals, the complementary delay circuit comprises 2n+3 stages of switch modules, a first stage of switch module is used as a buffer, a control signal is fixed to be 0, parallel output is carried out on the input signals, and the output delay of the input synchronous pulse signals after passing through two parallel paths of the first stage of switch module is ensured to be equal through symmetrical layout wiring control;
the other 2n+2 switch modules are divided into two identical groups, each group contains n+1 switch modules, and the signals [ C 0 ...C n ]Performing control; from C n The controlled switch module is called a switch exchange module, whose control signal C n Can be activated by input 0 ...C n-1 ]The calculation results are that:
wherein, the liquid crystal display device comprises a liquid crystal display device,representing an exclusive or operation.
Further, the switch module is configured to ensure that the input uplink and downlink pulse signals are output from the downlink and uplink of the switch module after passing through the switch module group, that is, the uplink and downlink signal exchange transmission paths; after passing through the two switch module groups, the transmission paths of the upper and lower signals are complementary, and the two switch module groups have the same layout wiring characteristics through layout wiring control, so that the same delay can be ensured when the upper and lower signal transmission paths reach the output ports of the complementary delay circuits.
Further, the upper pulse signal and the lower pulse signal output by the complementary delay circuit are respectively connected to the data input port and the clock input port of the D trigger for arbitration; the arbiter group comprises m D triggers, the data and clock inputs of the arbiter group are respectively connected to the data input port and the clock input port of each D trigger, m-bit data formed by the output of the m D triggers is used as an arbitration result of the arbiter group, the delay difference of the data input port and the clock input port of the arbiter group is approximately and uniformly distributed by taking 0 as the center through layout wiring control, when the delay difference of the input end of the D triggers changes due to the change of the ambient temperature and the supply voltage, the quantity of 0 and 1 in the m-bit arbitration result fluctuates along with the delay difference of the input end of the D triggers, if PUF response is generated by directly using the arbitration result, the response is easily influenced by temperature and supply voltage fluctuation, the stability is poor, and the influence of the temperature and the supply voltage fluctuation is eliminated by the aid of differential logic.
Further, two complementary arbiter PUF circuits with the same layout and wiring structure form a differential structure, the Hamming weights of the output results A0 and A1 of the two arbiter groups are subtracted, if the difference value is more than or equal to 0, the output response is 1, otherwise, the output response is 0; the absolute value of the Hamming weight difference value shows the stability of output response, and is used as auxiliary information for output, the larger the absolute value of the difference value is, the better the response stability is, and the worse the stability is otherwise.
Further, since the two complementary arbiter PUF circuits have the same layout and wiring structure, the symmetry will make the corresponding delay paths in the two arbiter groups, especially the delay paths of the input ends of the D flip-flops relatively consistent under the influence of temperature and supply voltage fluctuations; the final PUF response is generated by carrying out differential comparison on the arbitration results of the two complementary arbiters PUF, so that the influence of temperature and power supply voltage fluctuation can be eliminated, and the difference value of the arbitration results is output as auxiliary information, thereby providing convenience for the subsequent stability screening and error correction processing process of the response.
Compared with the prior art, the invention has the advantages that:
1. the arbiter PUF circuit structure with good symmetry can be realized on the FPGA platform, and the response uniqueness is good;
2. the differential structure can eliminate the influence of factors such as ambient temperature, power supply voltage and the like, so that PUF response has good stability;
3. the differential processing result of the two arbiter groups can embody response stability, and is convenient for subsequent processing to further improve response stability;
4. the response generation rate is high, and a large number of responses can be quickly generated at a higher clock frequency because cyclic bias adjustment is not needed.
Drawings
FIG. 1, arbiter PUF typical circuit configuration;
FIG. 2, differential complementary arbiter PUF circuit structure;
FIG. 3, pulse synchronization circuit;
FIG. 4, complementary delay circuit;
fig. 5, arbiter set.
Detailed Description
The following describes specific embodiments of the present invention with reference to examples:
it should be noted that the structures, proportions, sizes and the like illustrated in the present specification are used for being understood and read by those skilled in the art in combination with the disclosure of the present invention, and are not intended to limit the applicable limitations of the present invention, and any structural modifications, proportional changes or size adjustments should still fall within the scope of the disclosure of the present invention without affecting the efficacy and achievement of the present invention.
Also, the terms such as "upper," "lower," "left," "right," "middle," and "a" and the like recited in the present specification are merely for descriptive purposes and are not intended to limit the scope of the invention, but are intended to provide relative positional changes or modifications without materially altering the technical context in which the invention may be practiced.
Example 1:
the embodiment discloses a differential complementary arbiter PUF circuit structure suitable for an FPGA platform, as shown in fig. 2, and the output response and the auxiliary information related to response stability are generated by performing differential comparison on two complementary arbiter PUFs with the same layout and wiring characteristics. The complementary arbiter PUF circuit is composed of a pulse synchronous circuit, a complementary delay circuit, an arbiter group and the like.
1. Pulse synchronization circuit
The pulse synchronization circuit consists of two D flip-flops as shown in fig. 3. The data input ports of the two D flip-flops receive input pulses of the PUF circuit and output synchronous pulses under the drive of the same clock. Due to the wiring delay difference, the time when the pulse input signal arrives at the data input ports of the two D flip-flops is not synchronous. After buffering by the D triggers, the clock structure of the FPGA ensures that the signals at the output ends of the two D triggers are synchronous.
2. Complementary delay circuit
For an n-bit input excitation signal, the complementary delay circuit consists of 2n+3 stages of switch modules, as shown in fig. 4. The first-stage switch module is used as a buffer, the control signal of the first-stage switch module is fixed to be 0, and input signals are output in parallel. Through symmetrical layout wiring control, output delay is equal after the input synchronous pulse signal passes through two parallel paths of the first-stage switch module.
The other 2n+2 switch modules are divided into two identical groups, each group contains n+1 switch modules, and the signals [ C 0 ...C n ]And controlling. From C n The controlled switch module is called a switch exchange module, whose control signal C n Can be activated by input 0 ...C n-1 ]The calculation results are that:
wherein, the liquid crystal display device comprises a liquid crystal display device,representing an exclusive or operation.
The switch module is used for ensuring that the input upper path and lower path pulse signals are respectively output from the lower path and the upper path of the switch module after passing through the switch module group, namely an upper path and a lower path of signal exchange transmission paths. After passing through the two switch module groups, transmission paths through which the upper and lower signals pass are complementary. Through layout wiring control, the two switch module groups have the same layout wiring characteristics, and the same delay can be ensured when the upper signal transmission path and the lower signal transmission path reach the output port of the complementary delay circuit.
3. Arbitrator set
The upper pulse signal and the lower pulse signal output by the complementary delay circuit are respectively connected to the data input port and the clock input port of the D trigger for arbitration. Ideally, the data input port and the clock input port should be symmetrically routed to ensure the same delay, so as to avoid serious bias of output response. On an FPGA platform, the data input port and the clock input port of the D flip-flop are difficult to implement symmetric wiring. Even though design delays of the data input port and the clock input port are relatively close by strict wiring screening, path delay changes are different when the ambient temperature and the supply voltage change due to the different switching devices through which the wiring paths pass, resulting in an increase in delay offset. The differential logic based on the arbiter group can effectively solve the problem of delay offset caused by asymmetric wiring of the arbiter on the FPGA platform.
The arbiter set consists of m D flip-flops as shown in fig. 5. The data and clock inputs of the arbiter set are connected to the data input and the clock input of each D flip-flop, respectively. The m-bit data composed of m D flip-flop outputs is used as an arbitration result of the arbiter group. The delay difference between the data input port and the clock input port of the arbiter group is approximately uniformly distributed centering around 0 by the control of the layout and the wiring. The number of 0 s and 1 s in the m-bit arbitration result will fluctuate as the delay difference at the D flip-flop input varies due to ambient temperature and supply voltage variations. If PUF response is directly generated by the arbitration result, the response is easily affected by temperature and supply voltage fluctuation, and the stability is poor. It is also necessary to supplement differential logic to eliminate temperature and supply voltage ripple effects.
4. Differential output logic
To cope with ambient temperature and supply voltage variations, a differential structure is formed by two complementary arbiter PUF circuits with the same layout wiring structure. The Hamming weights of the output results A0 and A1 of the two arbiter groups are subtracted, if the difference value is more than or equal to 0, the output response is 1, otherwise, the output response is 0. The absolute value of the hamming weight difference represents the stability of the output response and is output as auxiliary information. The larger the absolute value of the difference, the better the response stability, and conversely the worse the stability.
Since the two complementary arbiter PUF circuits have the same layout and wiring structure, this symmetry will make the corresponding D flip-flops in the two arbiter groups relatively uniform from temperature and supply voltage fluctuations. The final PUF response is generated by differential comparison of the PUF arbitration results of the two complementary arbiters, which largely eliminates the temperature and supply voltage ripple effects. And the difference value of the arbitration result is used as auxiliary information to be output, so that convenience is brought to the subsequent processing procedures of stability screening, error correction and the like of the response.
While the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes may be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.
Many other changes and modifications may be made without departing from the spirit and scope of the invention. It is to be understood that the invention is not to be limited to the specific embodiments, but only by the scope of the appended claims.
Claims (8)
1. A differential complementary arbiter PUF circuit suitable for use in an FPGA platform, comprising: two complementary arbiter PUF circuits with identical place and route characteristics;
the input end of the complementary arbiter PUF circuit is input with a pulse and is driven by the same clock; differential comparison of the complementary arbiter PUF circuits generates an output response and side information related to response stability.
2. A differential complementary arbiter PUF circuit suitable for use in an FPGA platform according to claim 1, comprising: a pulse synchronization circuit, a complementary delay circuit, and an arbiter set;
the arbiter set is responsive to the complementary delay circuit, which is responsive to the pulse synchronization circuit.
3. A differential complementary arbiter PUF circuit for use in an FPGA platform according to claim 2, wherein the pulse synchronization circuit comprises two D flip-flops, the data input ports of which receive the input pulses of the PUF circuit and output synchronization pulses driven by the same clock.
4. A differential complementary arbiter PUF circuit suitable for FPGA platform according to claim 3, wherein for n-bit input excitation signals, the complementary delay circuit comprises 2n+3 stages of switch modules, the first stage of switch module is used as a buffer, the control signal is fixed to 0, the input signals are output in parallel, and the output delay of the input synchronous pulse signals after passing through two parallel paths of the first stage of switch module is ensured to be equal by symmetrical layout wiring control;
the other 2n+2 switch modules are divided into two identical groups, each group contains n+1 switch modules, and the signals [ C 0 ...C n ]Performing control; from C n The controlled switch module is called a switch exchange module, whose control signal C n Can be activated by input 0 ...C n-1 ]The calculation results are that:
C n ＝1⊕C 0 ⊕C 1 ⊕...⊕C n-1 ；
where ∈ represents an exclusive or operation.
5. The PUF circuit of a differential complementary arbiter suitable for FPGA platform according to claim 4, wherein the switch module is configured to ensure that the input up and down pulse signals are output from the down and up of the switch module respectively, i.e. up and down signal exchange transmission paths after passing through the switch module group; after passing through the two switch module groups, the transmission paths of the upper and lower signals are complementary, and the two switch module groups have the same layout wiring characteristics through layout wiring control, so that the same delay can be ensured when the upper and lower signal transmission paths reach the output ports of the complementary delay circuits.
6. The PUF circuit of a differential complementary arbiter suitable for FPGA platform according to claim 5, wherein the upper and lower pulse signals output by the complementary delay circuit are respectively connected to the data input port and the clock input port of the D flip-flop for arbitration; the arbiter group comprises m D triggers, the data and clock inputs of the arbiter group are respectively connected to the data input port and the clock input port of each D trigger, m-bit data formed by the output of the m D triggers is used as an arbitration result of the arbiter group, the delay difference of the data input port and the clock input port of the arbiter group is approximately and uniformly distributed by taking 0 as the center through layout wiring control, when the delay difference of the input end of the D triggers changes due to the change of the ambient temperature and the supply voltage, the quantity of 0 and 1 in the m-bit arbitration result fluctuates along with the delay difference of the input end of the D triggers, if PUF response is generated by directly using the arbitration result, the response is easily influenced by temperature and supply voltage fluctuation, the stability is poor, and the influence of the temperature and the supply voltage fluctuation is eliminated by the aid of differential logic.
7. The differential complementary arbiter PUF circuit suitable for FPGA platform according to claim 6, wherein two complementary arbiter PUF circuits having the same layout and wiring structure form a differential structure, the hamming weights of the output results A0 and A1 of the two arbiter groups are subtracted, if the difference is greater than or equal to 0, the output response is 1, otherwise the output response is 0; the absolute value of the Hamming weight difference value shows the stability of output response, and is used as auxiliary information for output, the larger the absolute value of the difference value is, the better the response stability is, and the worse the stability is otherwise.
8. A differential complementary arbiter PUF circuit for FPGA platform according to claim 7, characterized in that, since the two complementary arbiter PUF circuits have the same layout and wiring structure, this symmetry will make the corresponding delay paths in the two arbiter groups, especially the D flip-flop input delay paths, relatively consistent under the influence of temperature and supply voltage fluctuations; the final PUF response is generated by carrying out differential comparison on the arbitration results of the two complementary arbiters PUF, so that the influence of temperature and power supply voltage fluctuation can be eliminated, and the difference value of the arbitration results is output as auxiliary information, thereby providing convenience for the subsequent stability screening and error correction processing process of the response.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110239002A1 (en) * | 2010-03-25 | 2011-09-29 | Empire Technology Development Llc | Differential uncloneable variability-based cryptography |
| CN107276761A (en) * | 2016-04-08 | 2017-10-20 | 智能Ic卡公司 | Apparatus and method for testing the unclonable function of physics |
| CN110048858A (en) * | 2019-04-30 | 2019-07-23 | 东南大学 | A kind of high-performance APUF circuit structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110239002A1 (en) * | 2010-03-25 | 2011-09-29 | Empire Technology Development Llc | Differential uncloneable variability-based cryptography |
| CN107276761A (en) * | 2016-04-08 | 2017-10-20 | 智能Ic卡公司 | Apparatus and method for testing the unclonable function of physics |
| CN110048858A (en) * | 2019-04-30 | 2019-07-23 | 东南大学 | A kind of high-performance APUF circuit structure |
Non-Patent Citations (2)
| Title |
|---|
| TAKANORI MACHIDA等: "A New Arbiter PUF for Enhancing Unpredictability on FPGA", THE SCIENTIFIC WORLD JOURNAL, pages 3 - 5 * |
| 刘海龙: "基于PUF的密钥生成关键技术及FPGA实现研究", 中国博士学位论文全文数据库 信息科技辑, pages 46 * |
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