CN116632048A - Bottom dielectric isolation and method for forming same in field effect transistor - Google Patents

Bottom dielectric isolation and method for forming same in field effect transistor Download PDF

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Publication number
CN116632048A
CN116632048A CN202310196130.6A CN202310196130A CN116632048A CN 116632048 A CN116632048 A CN 116632048A CN 202310196130 A CN202310196130 A CN 202310196130A CN 116632048 A CN116632048 A CN 116632048A
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layer
substrate
source
sige layer
sige
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Inventor
陈佳政
邓运桢
陈亮吟
杨育佳
何彩蓉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/833,440 external-priority patent/US20230282751A1/en
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Publication of CN116632048A publication Critical patent/CN116632048A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure relates to bottom dielectric isolation and methods of forming the same in field effect transistors. The semiconductor structure includes a substrate and a stacked structure including a channel layer interleaved with a metal gate structure. The semiconductor structure further includes an isolation feature disposed between the stacked structure and the substrate, wherein a bottommost portion of the metal gate structure directly contacts the isolation feature. The semiconductor structure further includes source/drain features disposed adjacent the stacked structure and an internal spacer disposed between the metal gate structure and the source/drain features.

Description

Bottom dielectric isolation and method for forming same in field effect transistor
Technical Field
The present disclosure relates to bottom dielectric isolation and methods of forming the same in field effect transistors.
Background
The semiconductor industry has experienced a rapid growth. Technological advances in semiconductor materials and design have resulted in several generations of semiconductor devices, where each generation of circuitry is smaller and more complex than the previous generation. During the evolution of Integrated Circuits (ICs), the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such a scaled down process generally provides ease of use by improving production efficiency and reducing associated costs. But these advances have also increased the complexity of handling and manufacturing semiconductor devices.
Multiple gate transistors, such as Gate All Around (GAA) Field Effect Transistors (FETs), have been incorporated into various memory and core devices to reduce IC chip footprint while maintaining reasonable processing margins. In existing implementations, the isolation structures in the FET may be formed from doped layers within the device substrate to prevent punch-through of leakage currents, which is often sufficient. Sub-channel leakage control, however, remains a challenge for GAA FETs, especially in advanced devices with scalable architecture. Thus, for at least this reason, there is a need for improved methods of forming isolation structures to mitigate sub-channel leakage problems in GAA FETs.
Disclosure of Invention
According to an aspect of the present disclosure, there is provided a semiconductor structure including: a substrate; a plurality of semiconductor layers disposed over the substrate; a gate structure disposed on and surrounding each of the semiconductor layers; source/drain features disposed over the substrate and adjacent to the gate structure; and a dielectric layer disposed between a bottommost surface of the gate structure and the substrate.
According to an aspect of the present disclosure, there is provided a semiconductor structure including: a substrate; a stacked structure including a channel layer interleaved with the metal gate structure; an isolation feature disposed between the stacked structure and the substrate, wherein a bottommost portion of the metal gate structure directly contacts the isolation feature; source/drain features disposed adjacent the stacked structure; and an internal spacer disposed between the metal gate structure and the source/drain feature.
According to an aspect of the present disclosure, there is provided a method of forming a semiconductor structure, comprising: forming a fin protruding from a substrate, wherein the fin comprises a first SiGe layer and a stacked structure located above the first SiGe layer, wherein the stacked structure comprises alternating second SiGe layers and Si layers, and wherein the first SiGe layer comprises more Ge than each of the second SiGe layers; forming a dummy gate stack over a channel region of the fin; replacing the first SiGe layer with a dielectric layer to form an isolation feature; removing a portion of the fin to form a source/drain recess adjacent the dummy gate stack; forming an internal spacer on sidewalls of the second SiGe layer exposed to the source/drain recess; forming source/drain features over the internal spacers; and forming a metal gate structure adjacent to the source/drain feature in place of the dummy gate stack and the second SiGe layer such that a bottommost portion of the metal gate structure directly contacts the isolation feature.
Drawings
The disclosure is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale, but are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A and 1B illustrate a flowchart of an example method for fabricating a semiconductor device, according to various embodiments of the disclosure.
Fig. 2 is a three-dimensional perspective view of an example semiconductor device according to various embodiments of the present disclosure.
Fig. 3A, 4A, 5A, 7A, 8A, 9A, 11A, 15A, 16A, 18A, 19A, and 22A are three-dimensional perspective views of the semiconductor device shown in fig. 2 at an intermediate stage of the example method of fig. 1A and/or 1B according to various embodiments of the present disclosure.
Fig. 6A, 17A and 23A are top plan views of the semiconductor device shown in fig. 2 at intermediate stages of the example methods of fig. 1A and/or 1B in accordance with various embodiments of the present disclosure.
Fig. 3B, 4B, 5B, 7B, 8B, 9B, 10A, 10B, 10C, 11B, 11C, 12A, 12B, 12C, 13, 14A, 14B, 15B, 16B, 18B, 19B, 20A, 20B, 20C, 21, 22B, 24A, 24B, 25, 26, 27, 28 and 29 are cross-sectional views of the semiconductor device shown in fig. 2 taken along line BB' of the example methods of fig. 1A and/or 1B at intermediate stages of the example methods according to various embodiments of the present disclosure.
Fig. 6B, 17B, and 23B are cross-sectional views of the semiconductor device shown in fig. 2, taken along line CC' at an intermediate stage of the example method of fig. 1A and/or 1B, in accordance with various embodiments of the present disclosure.
Fig. 6C is a schematic diagram of a relationship between etch selectivity and Ge content for embodiments of semiconductor devices etched using different etchants in accordance with various embodiments of the disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following disclosure, the formation of one feature over, connected to, and/or coupled to another feature may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed between the features such that the features may not be in direct contact. Furthermore, spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "below," "upper," "lower," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.), are used to facilitate the relationship of one feature to another feature of the present disclosure. Spatially relative terms are intended to encompass different orientations of the device in which the feature is included.
Furthermore, when "about," "approximately," etc. are used to describe a number or range of numbers, the term is intended to encompass numbers within a reasonable range including the number described, for example within +/-10% of the number described or other values as understood by one of skill in the art. For example, the term "about 5nm" encompasses a size range from 4.5nm to 5.5 nm. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The present disclosure relates generally to structures and methods of forming a multi-gate metal oxide semiconductor field effect transistor (MOSFET or FET in the present disclosure), such as a gate-all-around (GAA) FET. More particularly, the present disclosure relates to structures and methods of forming multi-layer channel regions in n-channel or n-type GAA FETs (GAA NFETs) and p-channel or p-type GAA FETs (GAA PFETs) that together form a Complement MOSFET (CMOSFET). The GAA FETs provided herein may be nanoplatelet-based FETs, nanowire-based FETs, and/or nanorod-based FETs. In other words, the present disclosure does not limit GAA FETs to have a particular configuration.
Typically, the channel region of the GAA NFET and the channel region of the GAA PFET each include a stack of silicon-based channel layers (Si layers) interleaved with metal gate structures. While such structures are generally adequate to maintain the performance of GAA devices, they are not entirely satisfactory in all respects. For example, in existing implementations, the isolation structures in the FET may be formed by a punch-through stop implant, which is generally sufficient. Sub-channel leakage control, however, remains a challenge for GAA FETs, especially in advanced devices with scalable architecture. The present embodiments provide a method of forming a bottom dielectric isolation structure under the channel and/or source/drain regions of a GAA FET to mitigate sub-channel leakage problems.
Referring now to fig. 1A and 1B, a flowchart of a method 100 and a method 140 of forming a semiconductor device (hereinafter device) 200 is shown, in accordance with various aspects of the present disclosure. Methods 100 and 140 are merely examples and are not intended to limit the present disclosure to that explicitly recited in the claims. Additional operations may be provided before, during, and after methods 100 and 140, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of each method. Methods 100 and 140 are described below in connection with fig. 1-28. Specifically, fig. 2, 3A, 4A, 5A, 7A, 8A, 9A, 11A, 15A, 16A, 18A, 19A, and 22A are three-dimensional perspective views of device 200 at intermediate stages of methods 100 and/or 140; fig. 6A, 17A, and 23A are top plan views of device 200 at intermediate stages of methods 100 and/or 140. Fig. 3B, 4B, 5B, 7B, 8B, 9B, 10A, 10B, 10C, 11B, 11C, 12A, 12B, 12C, 13, 14A, 14B, 15B, 16B, 18B, 19B, 20A, 20B, 20C, 21, 22B, 24A, 24B, 25, 26, 27, 28 and 29 are cross-sectional views of the device 200 shown in fig. 2 taken along line BB' at intermediate stages of the method 100 and/or 140; fig. 6B, 17B, and 23B are cross-sectional views of device 200 shown in fig. 2, taken along line CC' at intermediate stages of methods 100 and/or 140.
The device 200 may be an intermediate device fabricated during processing of the IC or a portion thereof, which may include Static Random Access Memory (SRAM) and/or other logic circuitry, passive components such as resistors, capacitors, and inductors, active components such as GAA FETs, finFET, MOSFET, CMOSFET, bipolar transistors, high voltage transistors, high frequency transistors, and/or other transistors. The present disclosure is not limited to any particular number of devices or device regions, or to any particular device configuration. Additional features may be added to the device 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the device 200.
Referring to fig. 1A, 2 and 3A, the method 100 provides a semiconductor substrate (hereinafter "substrate") 202 and then forms a multi-layer structure (ML) thereon at operation 102. The substrate 202 may comprise an elemental (i.e., having a single element) semiconductor, such as silicon (Si), germanium (Ge), or other suitable material; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, other suitable materials, or combinations thereof; an alloy semiconductor, such as SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, other suitable materials, or combinations thereof. The substrate 202 may be a single layer of material having a uniform composition. Alternatively, the substrate 202 may comprise multiple layers of material having similar or different compositions suitable for fabricating the device 200.
In some examples where the substrate 202 includes FETs, various doped regions may be provided in the substrate 202 or on the substrate 202. The doped region may be doped with an n-type dopant (e.g., phosphorus or arsenic) and/or a p-type dopant (e.g., boron or BF 2 ) Depending on the design requirements. The doped regions may be formed directly on the substrate 202, in a p-well structure, in an n-well structure, in a double-well structure, or in a raised structure. The doped regions may be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques. Of course, these examples are for illustration purposes only and are not intended to be limiting.
In this embodiment, the ML includes alternating layers of silicon germanium (SiGe) and silicon (Si) arranged in a vertical stack along the Z-axis and is configured to provide a channel region suitable for forming a GAA FET (e.g., GAA NFET or GAA PFET). In the illustrated embodiment, the bottommost layer of the ML is the SiGe layer 203, and subsequent layers of the ML include alternating SiGe layers 207 and Si layers 205, with the Si layers 205 configured as channel layers of the GAA FET and the SiGe layers 207 considered as non-channel layers replaced with metal gate structures. In this embodiment, the ML includes the same number of Si layers 205 as SiGe layers 207. In some examples, ML may include three to ten Si layers 205, and thus three to ten SiGe layers 207. In this embodiment, the ML includes only one SiGe layer 203 at the very bottom of the ML.
In this embodiment, each Si layer 205 comprises elemental Si and is substantially free of Ge, while SiGe layer 203 and each SiGe layer 207 both substantially comprise Si and Ge, although the amount of Ge in SiGe layer 203 is greater than the amount of Ge in each SiGe layer 207. In this embodiment, the SiGe layer 207 has a composition which may be expressed as Si 1-x Ge x Wherein x (or the amount of Ge) is at least about 0.15 (15%) but less than about 0.3 (30%), and thus (1-x) is at least about 0.7 (70%) but less than about 0.85 (85%). On the other hand, the SiGe layer 203 has a chemical composition which may be expressed as Si 1-y Ge y Wherein y (or the amount of Ge) is generally greater than x. In this embodiment, y is at least about 0.3 (30%) but not more than about 0.6 (60%). In contrast, the amount of Si in each Si layer 205 is at least about 0.95 (95%).
For Si layer 205, when forming a GAA FET, a minimum amount of Ge of about 15% in SiGe layers 203 and 207 provides sufficient selectivity to remove or release the channel layer, i.e., si layer 205, during the etching process. In other words, if the amount of Ge in the SiGe layer 207 (and 203) is less than about 15%, the Si layer 205 may be unintentionally damaged during the channel (or slice) release process. On the other hand, according to some embodiments, the difference in the amount of Ge between SiGe layers 203 and 207 provides selectivity during the etching process to selectively remove SiGe layer 203 relative to SiGe layer 207 to form a bottom (or buried) dielectric isolation structure (BDI) under ML. In other words, if the amount of Ge in the SiGe layer 203 is similar to the amount of Ge in the SiGe layer 207, the SiGe layer 207 may be unintentionally damaged when forming the BDI. Because SiGe layer 207 is configured to be replaced with a metal gate structure and an internal spacer, the etch selectivity between SiGe layer 203 and SiGe layer 207 may vary based on the desired thickness of the resulting internal spacer. In some embodiments, adjusting the etch selectivity between SiGe layer 203 and SiGe layer 207 may affect the structure of the resulting BDI, as discussed in detail below.
In this embodiment, forming the ML includes alternately growing the SiGe layer (i.e., siGe layer 203 or SiGe layer 207) and the Si layer (i.e., si layer 205) in a series of epitaxial growth processes, molecular beam epitaxy, other suitable Selective Epitaxial Growth (SEG) processes, or combinations thereof, which implement Chemical Vapor Deposition (CVD) techniques (e.g., vapor Phase Epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low pressure CVD (LP-CVD), and/or plasma enhanced CVD (PE-CVD)). The epitaxial process may use gaseous and/or liquid precursors that interact with the composition of the underlying substrate. For example, the substrate 202 including Si may interact with a Ge-containing precursor to form the SiGe layer 203 and the SiGe layer 207. In some examples, siGe layer 203, si layer 205, and SiGe layer 207 may form nanoplatelets, nanowires, or nanorods.
In some embodiments, referring to fig. 3a, siGe layer 203 forms a thickness T measured along the Z-axis that is greater than the thicknesses of Si layer 205 and SiGe layer 207. In some embodiments, the thickness T is similar to the thickness of the Si layer 205 and SiGe layer 207. In some embodiments, siGe layer 203, si layer 205, and SiGe layer 207 form a width W measured along the Y-axis s Wherein W is s No more than about 40nm. In some examples, width W s Less than or equal to about 30nm.
In this embodiment, the Si layer 205 is configured as a channel layer for forming the FET of the device 200, while the SiGe layer 207 is considered a non-channel layer. After forming the epitaxial source/drain (S/D) features, a sheet (or line) release process may be performed, for example, to form a plurality of openings between the channel layers, and then a metal gate structure is formed in the openings to complete the fabrication of the FET. In addition, the SiGe layer 203 is configured to form a placeholder (or dummy) layer of BDI over the channel region and/or S/D region of the FET. The source/drain may be referred to individually or collectively as a source or drain, depending on the context.
Still referring to fig. 1A, 2, and 3A, the method 100 forms a fin 204 extending from a substrate 202 at operation 104. In the depicted embodiment, fin 204 is oriented longitudinally along the X-axis. Depending on the conductivity type of the resulting FET, fin 204 may be formed in a region of substrate 202 doped with p-type dopants (i.e., a p-well structure) to form an NFET or in a region of substrate 202 doped with n-type dopants (i.e., an n-well structure) to form a PFET. Note that embodiments of device 200 may include additional fins (semiconductor fins) disposed over substrate 202, the additional fins configured to provide one or more NFETs and/or PFETs.
In this embodiment, each fin 204 includes ML disposed over a base fin 204', where the base fin 204' protrudes from the substrate 202. Fin 204 may be fabricated using suitable processes including photolithography and etching processes. The photolithographic process may include forming a mask element having one or more hard mask layers (not depicted), a photoresist layer (or resist; not depicted) over the hard mask layers, patterning the photoresist layer, and patterning the hard mask layer using the patterned photoresist layer as an etch mask, thereby forming a patterned mask element. The patterned mask element is then used to etch grooves into the ML and portions of the substrate 202, leaving the fins 204 including ML and base fins 204' protruding from the substrate 202. The hard mask layer may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, other suitable materials, or combinations thereof. The etching process may include dry etching, wet etching, reactive Ion Etching (RIE), other suitable processes, or combinations thereof.
Many other embodiments of methods for forming fin 204 may be suitable. For example, fin 204 may be patterned using a double patterning or multiple patterning process. Typically, a double patterning or multiple patterning process combines lithography and self-aligned processes, allowing creation of patterns with smaller pitches, for example, than those obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed beside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and then the remaining spacers or mandrels may be used to pattern fin 204.
Still referring to fig. 1A, 2, and 3A, the method 100 forms an isolation structure 208 over the substrate 202 and around a bottom portion of the fin 204 at operation 104. Isolation structures 208 may include silicon oxide, fluorosilicate glass (FSG), low-k dielectric materials, other suitable materials, or combinations thereof. In this embodiment, the isolation structures 208 include Shallow Trench Isolation (STI) features. In some embodiments, isolation structures 208 are formed by: a dielectric layer is deposited over the substrate 202, filling the trenches between adjacent fins 204, and then recessed such that the top surfaces of the isolation structures 208 are below the top surfaces of the fins 204. Other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), other suitable structures, or combinations thereof, may also be implemented as isolation structures 208. In some embodiments, isolation structure 208 may comprise, for example, a multi-layer structure having one or more thermal oxide liner layers. The isolation structures 208 may be deposited by any suitable method, such as CVD, flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof.
Referring to fig. 1A and 2-3B, the method 100 forms a dummy gate stack (i.e., a placeholder gate) 210 over the channel region of each fin 204 at operation 106. In this embodiment, the portion of the dummy gate stack 210 comprising polysilicon is replaced with a high-k (referring to a dielectric material having a dielectric constant greater than that of silicon oxide, which has a dielectric constant of about 3.9) (hereinafter referred to as a metal gate structure) after forming other elements (e.g., epitaxial S/D features) of the device 200. The dummy gate stack 210 may be formed by a series of deposition and patterning processes. For example, the dummy gate stack 210 may be formed by depositing a polysilicon layer over the fin 204 and then performing an anisotropic etching process (e.g., a dry etching process) that leaves a portion of the polysilicon over the channel region of the fin 204. The dummy gate stack 210 may also include an interfacial layer (not separately depicted) and a gate dielectric layer (not separately depicted).
In this embodiment, the method 100 first forms a dummy oxide layer 209 over the substrate 202 at operation 106, and then forms a dummy gate stack 210. The dummy oxide layer 209 may include a suitable oxide material, such as silicon oxide, and may be formed by a suitable method, such as thermal oxidation, chemical oxidation, other suitable methods, or a combination thereof.
Subsequently, the method 100 forms various isolation structures in the device 200 at operation 108. The various isolation structures include, for example, BDI (e.g., BDI 224, BDI 226, or BDI 276), top gate spacers (e.g., top gate spacers 212), and interior spacers (e.g., interior spacers 240 or interior spacers 242). In this embodiment, operation 108 is implemented by method 140 as shown in FIG. 1B. In some embodiments, the method 140 may form the BDI prior to forming the S/D grooves (e.g., S/D grooves 230 or S/D grooves 232) in the pre-BDI process illustrated in connection with operations 144-156 of FIGS. 4A-12C. Alternatively, the method 140 may form the BDI after forming the S/D grooves in the post-BDI process shown in connection with operations 143-157 of FIGS. 15A-24B.
Referring now to fig. 1B and 4A-4B, method 140 removes portions of dummy oxide layer 209 from portions of device 200 not covered by dummy gate stack 210 at operation 142. The method 140 may implement an etch process that selectively removes exposed portions of the oxide layer 209 without removing or substantially removing other features of the device 200, including, for example, the dummy gate stack 210, the ML, and the isolation structures 208. The selective etching process may be a dry etching process, a wet etching process, a Reactive Ion Etching (RIE) process, other suitable processes, or a combination thereof.
Referring to fig. 1B and 5A-6B, the method 140 selectively removes the SiGe layer 203 relative to the Si layer 205 and the SiGe layer 207 in an etching process 302 at operation 144 to form an opening 211 between the bottom surface of the ML and the substrate 202.
In this embodiment, referring to fig. 5A and 6A, the etching process 302 is configured to isotropically remove the SiGe layer 203 along the Y-axis from two opposite directions ED. In other words, the SiGe layer 203 is removed from both sides of the ML. In this regard, referring to FIGS. 6A-6B, the width C1 of the opening 211 is approximately the width W of ML measured along the Y-axis s Half (i.e. W s /2). In some embodiments, the etching process 302 may unintentionally remove (although not significantly) portions of the SiGe layer 207 and the Si layer 205. As shown in fig. 6B, the amount removed from SiGe layer 207 may be defined by a width A1, and the amount removed from Si layer 205 may be defined by a width B1, wherein width A1 is less than width B1. Thus, it includes Si 1-x Ge x The etch selectivity S1 between SiGe layer 207 and Si layer 205 is defined by the ratio B1/A1 and comprises Si 1-y Ge y The etch selectivity S2 between SiGe layer 203 and SiGe layer 207 is defined by the ratio C1/B1.
In this embodiment, the etch selectivity Sl is configured to be about 8 to about 100 for x values of about 0.15 to about 0.3 to ensure that the SiGe layer 207 is substantially removed relative to the Si layer (channel layer) 205 during a subsequent wafer release process. If the etch selectivity S1 is less than about 8, the Si layer 205 may be unintentionally etched during the wafer release process because the amount of Si in the SiGe layer 207 is close to the amount of Si in the Si layer 205. If the etch selectivity S1 is greater than about 100, the etch selectivity S2 may be unintentionally reduced because the amount of Ge in the SiGe layer 207 may be close to the amount of Ge of the SiGe layer 203, i.e., the value of x may be close to the value of y.
In some embodiments, width W s Can be less than or equal to about 40nm, the length L of ML along the X-axis s May be less than about 40nm, the spacing between adjacent fins 204 may be about 70nm, the gate length L of the dummy gate stack 210 g May be less than or equal to about 14nm, and the spacing between adjacent dummy gate stacks 210 may be about 44nm. As a result, the width C1 may be less than or equal to about 20nm. In some examples, the width B1 is less than or equal to about 1nm.
In a further embodiment, the etch selectivity S2 is at least about 15 for y values of about 0.3 to about 0.6 assuming a width B1 of less than or equal to about 1nm. This level of selectivity ensures that SiGe layer 203 is substantially etched during etch process 302 and SiGe layer 207 is not etched. If the etch selectivity S2 is less than about 15, the SiGe layer 207 may be unintentionally damaged during the etching process 302.
The etching process 302 may be implemented using a dry etchant, a wet etchant, or a combination thereof. Examples of dry etchants include halogen-containing (e.g., fluorine-containing and/or chlorine-containing) gaseous species, such as HF, F 2 、CF 4 、CH x F y (wherein x and y are both positive integers and wherein y=3x), clF 3 、NF 3 、SF 6 、Cl 2 HCl and BCl 3 Other gaseous substances, e.g. H 2 、O 2 He, ar and N 2 Other suitable gaseous materials, or combinations thereof. An example dry etchant may be at any suitable temperature (e.g., at room temperature to less than about 800 ℃) and at any suitable pressure (e.g., at about 10) -3 Torr to about atmospheric pressure).
Examples of wet etchants include those containing ammonium hydroxide (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) Alkaline solution containing tetramethylammonium hydroxide (TMAH) and H 2 O 2 Is alkaline solution containing hydrofluoric acid (HF) and H 2 O 2 And acetic acid (CH) 3 COOH) acidic solution containing HF and HNO 3 Other suitable solutions, or combinations thereof. In some casesIn an example, in an example wet etchant, H 2 O 2 May be completely or partially replaced by ozone water. The example wet etchant may be applied at any suitable temperature (e.g., at room temperature to less than about 200 ℃) and at any suitable pressure (e.g., at atmospheric pressure).
In the present embodiment, for a target range of etch selectivity S2, the choice (S) of etchant (S) for the etch process 302 varies depending on the Ge content in the SiGe layer 203 and the SiGe layer 207, respectively. Table 1 below details an example etchant configured to provide a target range (e.g., at least about 15) of etch selectivity S2 at various amounts of Ge in SiGe layer 203. Specifically, etchant 1 comprises 1:1 (28% NH 4 OH)：(31％ H 2 O 2 ) Etchant 2 comprises 1:2:3 (20% -50% hf): (30% H) 2 O 2 ):(99.5％ CH 3 COOH), etchant 3 comprises plasma-free ClF 3 And etchant 4 comprises gaseous HCl. The symbol "×" in table 1 indicates that the example etchant is suitable for selectively etching SiGe layer 203 at a given composition. For example, etchant 3 and etchant 4 may be used alone or in combination to etch SiGe layer 203 having at least 50% ge. It is noted that the present disclosure is not limited by the contents of table 1, the contents of table 1 being provided for illustrative purposes only.
TABLE 1
Fig. 6C is a schematic diagram of the etch selectivity S1 plotted against the amount of Ge in the SiGe layer 207. The differently shaped data points correspond to the different example etchants provided in table 1, and the enclosed data points in the ellipses represent an etch selectivity S1 in the range of about 8 to about 100 when the amount of Ge in the SiGe layer 207 is about 15% (0.15) to about 30% (0.3). In other words, the example etchants provided in table 1 may each be adapted to achieve a target value of etch selectivity S1 for a given range of Ge content in SiGe layer 207.
Referring to fig. 1B and 7A-7B, method 140 forms a dielectric layer 220 over device 200 at operation 146. In this embodiment, a dielectric layer 220 is conformally deposited over the device 200, wherein a portion of the dielectric layer 220 fills the opening 211. Dielectric layer 220 may comprise any suitable material, such as silicon oxide, silicon nitride, carbon-containing silicon nitride (SiCN), carbon-containing silicon oxide (SiOC), silicon oxynitride (SiON), carbon and oxygen doped silicon nitride (SiOCN), a low-k dielectric material, other suitable dielectric material, or a combination thereof.
The method 140 may deposit the dielectric layer 220 by any suitable process, such as an Atomic Layer Deposition (ALD) process, a CVD process, other suitable process, or a combination thereof. In this embodiment, the dielectric layer 220 is deposited by an ALD process. In some embodiments, forming dielectric layer 220 in opening 211 using an ALD process results in a seam or air gap 222 extending across the width of dielectric layer 220 (i.e., along the Y-axis) and along the length of fin 204 (i.e., along the X-axis) in opening 211. In this embodiment, the seam 222 is substantially horizontal, i.e., substantially along the X-axis. However, in some embodiments, the seam 222 does not necessarily occur as a result of the deposition process of operation 146.
Subsequently, referring to fig. 1B and 8A-8B, the method 140 removes the excess portion of the dielectric layer 220 formed over the dummy gate stack 210 and over the exposed surfaces of the fins 204, leaving only the portion formed in the opening 211 at operation 148. The method 140 may remove the excess portion of the dielectric layer 220 by an anisotropic etching process (e.g., a dry etching process).
Referring to fig. 1B and 9A-9B, the method 140 forms top gate spacers 212 on sidewalls of the dummy gate stack 210 at operation 150. The top gate spacer 212 may be a single layer structure or a multi-layer structure and may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride (SiON), carbon-containing silicon oxide (SiOC), other suitable materials, or combinations thereof. Each spacer layer of top gate spacers 212 may be formed by: a dielectric layer is first deposited over the dummy gate stack 210 and then portions of the dielectric layer are removed in an anisotropic etching process (e.g., a dry etching process), leaving portions of the dielectric layer on the sidewalls of the dummy gate stack 210 as top gate spacers 212.
Still referring to fig. 1B and 9A-9B, method 140 forms S/D grooves 230 adjacent to top gate spacers 212 in the S/D regions of fin 204 at operation 152. In this embodiment, the method 100 removes portions of ML in the S/D regions of the fin 204 by an etching process 304, the etching process 304 may be a dry etching process, a wet etching process, RIE, or a combination thereof. A cleaning process may then be performed to remove any etching residues in the S/D grooves 230 with HF and/or other suitable solvents. In this embodiment, referring to fig. 9b, the S/D recess 230 exposes a portion of the dielectric layer 220 to form a BDI 224, which BDI 224 extends over the channel region and S/D region of the fin 204. In other words, a first portion a of the BDI 224, is formed over the channel region of the fin 204 (i.e., between the bottommost surface of the subsequently formed metal gate structure and the substrate 202), and a second portion B of the BDI 224 is formed over the S/D region of the fin 204 (i.e., between the bottommost surface of the subsequently formed S/D feature and the substrate 202). Thus, in this embodiment, the BDI 224 is considered to be "full BDI". In some embodiments, the method 140 implements an etchant configured to remove the Si layer 205 and the SiGe layer 207 without removing or substantially without removing the dielectric layer 220 at operation 152. In this regard, the S/D grooves 230 may expose the top surface of the BDI 224 and do not extend beyond the seam 222, as shown in fig. 9B.
In some embodiments, referring to fig. 1B and 10A-10C, the method 140 proceeds from operation 152 to operation 156 to form an internal spacer 240 on the sidewalls of the SiGe layer 207 (i.e., the non-channel layer) exposed in the S/D recess 230. Referring to fig. 10A, the method 140 selectively removes portions of the SiGe layer 207 exposed in the S/D recesses 230 in an etching process 306 to form recesses 234. In this embodiment, the etching process 306 is selective to Ge having a content of at least about 15% (i.e., x is at least about 0.15) such that the SiGe layer 207 is etched at a significantly higher rate than the Si layer 205 that is substantially free of Ge. In addition, the etch process 306 is also selective to Ge relative to the dielectric layer 220 (i.e., BDI 224). In some embodiments, the etching process 306 is to implement H 2 O 2 Hydroxides (e.g. NH) 4 OH, TMAH, etc.), CH 3 COOH, other suitable etchants, or combinations thereof. In some embodimentsIn an example, the etching process 306 is a dry etching process that implements the fluorine-containing gaseous species provided herein. In this embodiment, the duration of the etching process 306 is controlled to ensure that only a portion of each SiGe layer 207 is etched to form a recess 234, wherein the width T of the recess 234 along the X-axis s Defining the thickness of the inner spacers 240 and the gate length L of the corresponding subsequently formed metal gate structure g 。
Subsequently, referring to fig. 10B, method 140 deposits a dielectric layer 236 in recess 234 by any suitable deposition process, such as ALD, CVD, other suitable methods, or combinations thereof. In this embodiment, a dielectric layer 236 is conformally deposited over the device 200 such that the dielectric layer 236 is formed on the exposed surfaces of the fins 204 and BDI 224, filling the recess 234. Referring to fig. 10C, the method 140 then performs one or more etching processes to remove portions of the dielectric layer 236 from the sidewalls of the dummy gate stack 210, the top gate spacers 212, and the sidewalls of the S/D recesses 230, leaving the internal spacers 240 in the recesses 234. As shown in fig. 10C, the S/D grooves 230 expose portions of the BDI 224.
The internal spacers 240 (i.e., the dielectric layer 236) may comprise any suitable dielectric material including silicon, carbon, oxygen, nitrogen, other elements, or combinations thereof. For example, the dielectric layer 236 may include silicon nitride, silicon carbide, silicon oxide, carbon-containing silicon nitride (SiCN), carbon-containing silicon oxide (SiOC), silicon oxynitride (SiON), carbon and oxygen doped silicon nitride (SiOCN), low-k dielectric materials, tetraethyl orthosilicate (TEOS), doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluorine doped silicate glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), etc.), air, other suitable dielectric materials, or combinations thereof. The internal spacers 240 may be configured as a single layer structure or as a multi-layer structure comprising a combination of dielectric materials as provided herein. In some embodiments, the inner spacers 240 have a different composition than the top gate spacers 212. In some embodiments, the inner spacers 240 and the top gate spacers 212 have the same composition. Further, the internal spacers 240 and the BDI 224 may have different compositions.
In some embodiments, referring to fig. 1B and 11A-11C and prior to forming the internal spacers 240, the method 140 may further remove portions of the dielectric layer 220 in the S/D regions of the fins 204 in an etching process 308 at operation 154. In some embodiments, referring to fig. 11B, the etch process 308 removes the entire dielectric layer 220 from the S/D regions such that the portion of the dielectric layer 220 that remains below the channel region of the fin 204 forms the BDI 226. Thus, the BDI 226 is considered to be a "partial BDI" as compared to the BDI 224 depicted in FIGS. 9A-10C. In some embodiments, referring to fig. 11C, the etch process 308 removes portions of the dielectric layer 220 such that portions of the dielectric layer 220 remain over the S/D regions to form the BDI 224, i.e., a "full BDI," similar to that depicted in fig. 9A-10C. In other words, the S/D grooves 230 may extend above (not depicted) or below the seams 222 (e.g., as shown in fig. 11C) without exposing the fins 204 in the S/D regions. Similar to the embodiment shown in fig. 9B, the BDI 224 may include a first portion a over the S/D region of the fin 204 and a second portion B over the channel region of the fin 204. In some embodiments, operation 154 may be omitted and BDI 224 remains over the channel region and S/D regions of fin 204.
The etch process 308 differs from the etch process 304 in that the etch process 308 selectively removes the dielectric layer 220 and is not configured to remove or substantially remove the Si layer 205, the SiGe layer 207, or other components of the device 200. In some embodiments, the etch process 308 is an anisotropic etch process, such as a dry etch process, and may be controlled by etch duration or by endpoint detection. For example, with respect to forming the BDI 226 as shown in FIG. 11B, the etch process 308 is controlled such that the S/D grooves 230 extend along the Z-axis to expose the substrate 202 (or base fin 204') in the S/D grooves 232. With respect to forming the BDI 224 as shown in FIG. 11C, the etch process 308 is controlled such that the S/D grooves 230 only partially penetrate the dielectric layer 220 to stop between the seam 222 and the substrate 202.
Subsequently, referring to fig. 1B and 12A-12C, the method 140 forms an internal spacer 240 on the exposed sidewalls of the SiGe layer 207 in a series of processes similar to those depicted in fig. 10A-10C at operation 156. Notably, due to the "partial" structure of the BDI 226, the S/D grooves 232 expose portions of the substrate 202, rather than the BDI 224 as shown in FIG. 10C.
Thereafter, referring to fig. 1A and 13-14, the method 100 proceeds from operation 108 to operation 110 to form epitaxial S/D features in the S/D grooves. Fig. 13 depicts an embodiment of a device 200 including a BDI 224 or full BDI disposed below an epitaxial S/D feature 250, and fig. 14 depicts an embodiment of a device including a BDI 226 or partial BDI disposed adjacent to an epitaxial S/D feature 252. Epitaxial S/D features 250 and 252 may each be configured as n-type epitaxial S/D features or p-type epitaxial S/D features for forming NFETs or PFETs, depending on the specific design requirements. Epitaxial S/D features 250 and 252 may each include one or more epitaxial layers of silicon (epi Si) or silicon carbide (epi SiC) doped with n-type dopants (e.g., arsenic, phosphorous, other n-type dopants, or combinations thereof) to form n-type epitaxial S/D features. Alternatively, the epitaxial S/D features 250 and 252 may each include one or more silicon germanium (epi SiGe) epitaxial layers doped with p-type dopants (e.g., boron, germanium, indium, other p-type dopants, or combinations thereof) to form p-type epitaxial S/D features.
The method 100 may form the epitaxial S/D features 250 and 252 by performing an epitaxial growth process as discussed above with respect to forming the various layers of ML. In some embodiments, the epitaxial material is doped in situ by adding dopants to the source material during the epitaxial growth process. In some embodiments, the epitaxial material is doped by an ion implantation process after the deposition process is performed. In some embodiments, an annealing process is then performed to activate the dopants in the epitaxial S/D features 250 and 252.
Still referring to fig. 1A and 13-14B, the method 100 removes the dummy gate stack 210 and the SiGe layer 207 at operation 112. Fig. 13 corresponds to the embodiment depicted in SIP in fig. 9A-10C, fig. 14A corresponds to the embodiment depicted in fig. 11A, 11B, and 12A-12C, and fig. 14B corresponds to the embodiment depicted in fig. 11C. Prior to removing the dummy gate stack 210, the method 100 forms an inter-layer dielectric (ILD) layer 216 over the epitaxial S/D features 250 (or 252), which may include silicon oxide, low-k dielectric material, TEOS, doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or a combination thereof. In some embodiments, the method 100 may form an Etch Stop Layer (ESL) over the epitaxial S/D feature 250 (or 252) prior to forming the ILD layer 216. The ESL may include silicon nitride, silicon carbide, carbon-containing silicon nitride (SiCN), silicon oxynitride (SiON), carbon and oxygen doped silicon nitride (SiOCN), aluminum nitride, high-k dielectric materials, other suitable materials, or combinations thereof. ILD layer 216 and ESL may each be formed by CVD, FCVD, ALD, PVD, other suitable methods, or a combination thereof. After planarizing the ESL and ILD layer 216 in one or more CMP processes, at least a portion of the dummy gate stack 210 is removed from the device 200 by any suitable etching process, such as a dry etching process, to form a gate trench (not depicted). In some embodiments, the dummy oxide layer 209 is removed from the gate trench and replaced with an interfacial layer (not depicted) prior to forming the metal gate structure in the gate trench.
Subsequently, the method 100 performs a wafer release process at operation 112 to form openings (not depicted) between the Si layers 205 in the fins 204. The sheet release process may be implemented by an etching process that does not remove or substantially does not remove the Si layer 205 and other surrounding dielectric features of the device 200. As discussed in detail above, a minimum Ge content of about 15% ensures a sufficient etch selectivity S1 (e.g., about 8 to about 100 as discussed in detail above) for removing the SiGe layer 207 without damaging the Si layer 205. The etching process may be a dry etching process or a wet etching process selective to Ge contained in the SiGe layer 207. The resulting openings provide room for forming a metal gate structure between the channel layer, i.e., si layer 205. In this regard, the terms "channel layer 205" and "Si layer 205" are interchangeable in the following discussion.
Exemplary dry and wet etchants that may be used to selectively etch the SiGe layer 207 relative to the Si layer 205 are discussed in detail above (see, e.g., table 1). For dry etchants, halogen-containing (e.g., fluorine-and/or chlorine-containing) gas species may react preferentially with Si-Ge bonds rather than Si-Si bonds to form Si-F bonds, ge-F bonds, and reactive dangling bonds, which may further facilitate reactions with additional halogen atoms to completely remove SiGe layer 207. Regarding the base wet etchant, although both the Si layer 205 and the SiGe layer 207 may be oxidized (e.g., H 2 O 2 、HNO 3 And ozone water) to form Si (OH) respectively 2 And Ge (OH) 2 2+ ，Si(OH) 2 And Ge (OH) 2 2+ By hydroxy OH - The rate of ion dissolution may be adjusted to achieve a target range of etch selectivity S1. Similarly, since both the Si layer 205 and the SiGe layer 207 can be oxidized by an oxidizing agent and then dissolved by an acid (e.g., HF) in an acid-based wet etchant, the etch selectivity S1 can be adjusted by adjusting the ratio of oxidizing agent to acid (by weight or by volume).
Thereafter, still referring to fig. 1A and 13-14, the method 100 forms a metal gate structure 260 in the gate trench and opening to replace the dummy gate stack 210 and the SiGe layer 207, respectively, at operation 114. As a result, portions of the metal gate structure 260 surround and engage each channel layer 205 to form a stacked structure ML'. In this embodiment, the metal gate structure 260 includes at least a high-k dielectric layer 262 disposed over the channel layer 205 and surrounding the channel layer 205, and a metal gate electrode 264 disposed over the high-k dielectric layer 262. In this embodiment, the high-k dielectric layer 262 comprises any suitable high-k dielectric material, such as hafnium oxide, lanthanum oxide, other suitable materials, or combinations thereof. In this embodiment, metal gate electrode 264 includes at least a Work Function Metal (WFM) layer 264a disposed over high-k dielectric layer 262 and a conductive layer (or metal fill layer) 264b disposed over the WFM layer. WFM layer 264a may be a single layer structure or a multi-layer structure including at least a p-type WFM layer, an n-type WFM layer, or a combination thereof. Conductive layer 264b may comprise Cu, W, al, co, ru, other suitable materials, or a combination thereof. The metal gate structure 260 may also include other layers (not depicted), such as capping layers, barrier layers, other suitable layers, or combinations thereof. The various layers of the metal gate structure 260 may be formed by any suitable method, such as chemical oxidation, thermal oxidation, ALD, CVD, PVD, electroplating, other suitable methods, or combinations thereof.
As an alternative to the example pre-BDI process discussed above with respect to fig. 5A-12C, the method 140 may implement a post-BDI process during which BDI is formed after S/D grooves are formed. In some embodiments, a portion of the BDI (i.e., BDI 226) is formed separately from the inner spacer (i.e., inner spacer 240), as shown by operations 147, 149, and 151 in fig. 15A-20C. In some embodiments, a portion of the BDI is formed with the internal spacers, as shown in operations 153, 155, and 157 in fig. 15A-15B and 22A-24B.
Referring to fig. 1B and 15A-15B, after operation 142 removes portions of the dummy oxide layer 209 from the device 200, the method 140 forms top gate spacers 212 on sidewalls of the dummy gate stack 210 at operation 143, the process of which is similar to the process of operation 150 discussed above with respect to fig. 9A-9B.
Still referring to fig. 1B and 15A-15B, the method 140 performs an etching process 310 to form S/D grooves 232 in the fins 204 at operation 145, wherein the S/D grooves 232 expose the substrate 202 (or base fins 204'). In this embodiment, the etching process 310 differs from the etching processes 304 and 308 in that the etching process 310 is configured to remove the SiGe layer 203, the Si layer 205, and the SiGe layer 207. In contrast, the etch process 304 is configured to selectively remove the Si layer 205 and the SiGe layer 207 without removing or substantially without removing the dielectric layer 220, and the etch process 308 is configured to substantially remove only the dielectric layer 220.
Referring to fig. 1B and 16A-16B, the method 140 selectively removes the SiGe layer 203 in an etching process 312 to form an opening 211 between the ML and the base fin 204' at operation 147. In this embodiment, the etching process 312 is configured to remove the SiGe layer 203 without removing or substantially without removing the Si layer 205 and the SiGe layer 207. In other words, the etching process 312 removes the SiGe layer 203 at a higher rate than the Si layer 205 and the SiGe layer 207. In some embodiments, the etching process 312 is performed with one or more etchants similar to those used in the etching process 302 (see table 1 for details).
In the present embodiment, referring to fig. 16A and 17A, the etching process 312 is configured to isotropically remove the SiGe layer 203 from two opposite directions ED along the X-axis. In other words, siGe layer 203 is removed from both sides of dummy gate stack 210 (and top gate spacer 212). In this regard, referring to fig. 17A-17B, the width C2 of the opening 211 is the gate length L g About half of and a width W measured along the X-axis p Sum of (i.e., (L) g /2+W p ))。In addition, the etching process 312 may unintentionally remove (although not significantly) portions of the SiGe layer 207 and the Si layer 205. As shown in fig. 17B, the amount removed from SiGe layer 207 can be defined by width A2, and the amount removed from Si layer 205 can be defined by width B2, wherein widths A2 and B2 are similar to (or substantially the same as) widths A1 and B1, respectively. In some embodiments, the width B2 is less than or equal to about 1nm. Thus, the etch selectivity between the Si layer 205 and the SiGe layer 207 is defined by the ratio B2/A2, and may be similar to the etch selectivity S1, and the etch selectivity S3 between the SiGe layer 203 and the SiGe layer 207 is defined by the ratio C2/B2. In a non-limiting example, because W s And/2 may be greater than (L) g /2+W p ) The etch selectivity S2 may be greater than the etch selectivity S3 when the widths B1 and B2 are substantially the same (e.g., both less than or equal to about 1 nm).
Referring now to fig. 1B and 18A-19B, the method 140 forms the BDI 226 in the opening 211 at operation 149. The method 140 forms the BDI 226 in a series of processes similar to those discussed above with respect to operations 146 and 148. For example, referring to fig. 18A-18B, method 140 first deposits a dielectric layer 220 over device 200 such that dielectric layer 220 is formed over top gate spacers 212, along the sidewalls and bottom surfaces of S/D recess 232, and in opening 211. The composition and method of forming the dielectric layer 220 is discussed in detail above. In some embodiments, as depicted herein, the seam 222 may be formed as a result of forming the dielectric layer 220 using, for example, an ALD process, although the seam 222 may not necessarily be present. In the depicted embodiment in fig. 18A-19B, seam 222 extends in a substantially horizontal direction along the X-axis.
Subsequently, referring to fig. 19A-19B, the method 140 performs an etching process 314 to remove portions of the dielectric layer 220, leaving the BDI 226 in the opening 211. In this embodiment, the etch process 314 is configured to remove portions of the dielectric layer 220 from the sidewalls of the dummy gate stack 210, the top gate spacers 212, and the sidewalls of the S/D recesses 232, leaving portions of the dielectric layer 220 in the openings 211 to form the BDIs 226. In some embodiments, the etching process 314 is performed in an anisotropic or directional manner. Because the formation of the S/D recess 232 at operation 145 removes the portion of the SiGe layer 203 disposed over the S/D region of the fin 204, the resulting BDI 226 is considered a "partial" BDI for the same reasons described above.
Referring to fig. 20A-20C, the method 140 forms an internal spacer 240 on sidewalls of the SiGe layer 207 exposed in the S/D recess 232 in operation 151. In this embodiment, method 140 performs an etch process 316 (which may be similar to etch process 306) to form recess 234, deposits dielectric layer 236 over device 200, and removes portions of dielectric layer 236 to form internal spacers 240 in recess 234, similar to those processes discussed above with respect to operation 156.
Thereafter, referring to fig. 1A and 21, the method 100 continues with forming an epitaxial S/D feature 252 in the S/D recess 232 at operation 110, and then forming a metal gate structure 260 at operations 112 and 114, as discussed in detail above with respect to fig. 13 and 14. It is noted that the embodiment of the device 200 depicted in fig. 21 is similar to the embodiment of the device depicted in fig. 14, in that the internal spacers 240 and BDI 226 are formed by separate processes and may (but need not) comprise different materials.
As an alternative to operation 147, referring to fig. 22A-23B, the method 140 removes portions of the SiGe layer 203 and the SiGe layer 207 in an etching process 318 at operation 153 to form openings 211 and recesses 234, wherein the recesses 234 are configured to form internal spacers in subsequent operations. Similar to the embodiment shown in fig. 17A, referring to fig. 23A, the etching process 318 removes the SiGe layer 203A distance substantially equal to the gate length L g About half of the width W of the top gate spacer 212 p The sum (i.e., (L) g /2+W p ))。
In this embodiment, the etching process 318 is configured to completely remove the SiGe layer 203 while also partially removing the SiGe layer 207. In contrast, the etching processes 302 and 312, which are performed at operations 144 and 147, respectively, are configured to completely remove the SiGe layer 203 without removing or substantially without removing the SiGe layer 207. In other words, the etch selectivity S4 between SiGe layer 203 and SiGe layer 207 configured for etch process 318 is less than the etch selectivities S2 and S3 configured for etch processes 302 and 312, respectively. In this regard, instead of separately forming openings for BDIs and recesses for internal spacers (e.g., by etching processes 312 and 316), method 140 may do so in operation 153 in a one-step etching process using the same etchant(s). This reduced etch selectivity reduces the requirement for the amount of Ge in the SiGe layer 203 relative to the SiGe layer 207, resulting in fewer structural defects (e.g., lattice mismatch at the interface between the SiGe layer 203 and the bottommost SiGe layer 207) during epitaxial formation of ML. In some embodiments, the etching process 318 may be performed isotropically and may include a dry etching process, a wet etching process, a RIE process, other suitable processes, or a combination thereof.
Still referring to fig. 22B and 23B, the opening 211 may be defined by a width C3 along the X-axis and a height Z1 along the Z-axis, and the recess 234 may be defined by a width B3 along the X-axis, wherein the width B3 is also considered a lateral loss of the bottommost SiGe layer 207 during the etching process 318. Thus, the etch selectivity S4 between the SiGe layer 203 and the SiGe layer 207 can be expressed as a ratio C3/B3. In some embodiments, the particular value of etch selectivity S4 depends on the value of width B3, which determines the thickness of the inner spacer 242 formed in the recess 234. In this embodiment, the width B3 is configured to be greater than about 1nm to about 5nm. This is in contrast to etch processes 302 and 312, where the lateral loss defined by widths B1 and B2, respectively, may be equal to or less than about 1nm. If the width B3 is less than about 1nm, the resulting internal spacers (i.e., internal spacers 242) may be too thin to provide insulation between the metal gate structure (i.e., metal gate structure 260) and the epitaxial S/D features (i.e., epitaxial S/D features 252). If the width B3 is greater than about 5nm, the resulting gate length L g May be too small to meet the design requirements of a functional FET. In this embodiment, the etch selectivity S4 is about 2.4 to about 12 for a width B3 between about 1nm to about 5nm, which is lower than the foregoing etch selectivity S2 and etch selectivity S3. In some embodiments, the etch selectivity S4 is about 6 to about 12.
In the present embodiment, the relatively low value of the etch selectivity S4 is responsible for the vertical overetching of the bottommost SiGe layer 207 of the tapered opening 270 as shown in fig. 22B and 23B. The tapered opening 270 may be defined by a width D, which is the difference between the width C3 and the width B3. In addition, the height H of the tapered opening 270 (also known as the height loss of the bottommost SiGe layer 207) may be defined by the difference between the height Z2 and the height Z1, the height Z2 being the distance measured from the top surface of the tapered opening 270 to the bottom surface of the opening 211. In this regard, the slope R of the tapered opening 270 that slopes downward and away from the S/D groove 232 may be defined by the ratio H/D. In some embodiments, the height H is similar to the width B3, which is greater than about 1nm but no more than about 5nm. In contrast, vertical overetching of SiGe layer 207 along the Z-axis during etching processes 302 and 312 is insignificant compared to the isotropic etching of SiGe layer 203. For example, although not depicted, the height loss caused by the etching processes 302 and 312 depicted in fig. 5B and 16B is at most about 1nm. In some non-limiting examples, referring to fig. 22B, the width B3 may be about half of the height Z2, and the portion of the S/D groove 232 extending into the base fin 204' may be defined by a height of about half of the height Z2.
In the present embodiment, the consideration of the etch selectivity S4 between the SiGe layer 203 and the SiGe layer 207 for adjusting the etching process 318 is twofold. First, the etch selectivity S4 should be high enough to ensure that SiGe layer 203 is etched much more than SiGe layer 207. Second, the etch selectivity S4 should not exceed a threshold to ensure that the resulting internal spacers (i.e., internal spacers 242 shown in fig. 24B) are formed to a sufficient thickness for providing insulation in the device 200.
In some embodiments, adjusting the etch selectivity S4 may be achieved by using a different etchant than that used for the etch processes 302 and 312. Alternatively or additionally, adjusting the etch selectivity S4 may be achieved by reducing the Si of the SiGe layer 203 1-y Ge y The amount y of Ge in (a) is achieved, while the value of y remains greater than the value of x but less than about 0.6 (60%), as discussed in detail above.
Referring to table 2 below, the same example etchants for etching process 302 as listed in table 1, namely, the applicability of etchant 1, etchant 2, etchant 3, and etchant 4, are provided. The symbol "#" indicates that the use of the example etchant is not suitable for achieving the target range of etch selectivity S4, in accordance with the considerations described above. For example, when the amount of Ge in SiGe layer 203 exceeds about 30%, etchant 1, which is suitable for producing a relatively high etch selectivity (i.e., etch selectivity S2) for etch process 302, may not sufficiently etch SiGe layer 203 and SiGe layer 207 during etch process 318. In contrast, when the amount of Ge in SiGe layer 203 exceeds about 30%, etchant 3 and etchant 4, alone or in combination, are suitable for achieving the desired range of etch selectivity S4. It is noted that the present disclosure is not limited by the contents of table 2, the contents of table 2 are provided for illustrative purposes only.
TABLE 2
Subsequently, referring to fig. 1B and 24A, method 140 deposits a dielectric layer 272 over device 200 at operation 155, filling S/D grooves 232, openings 211, tapered openings 270, and grooves 234. Dielectric layer 272 may be substantially similar or different from dielectric layer 220 discussed above and may include any suitable material, such as silicon oxide, silicon nitride, carbon-containing silicon nitride (SiCN), carbon-containing silicon oxide (SiOC), silicon oxynitride (SiON), carbon and oxygen doped silicon nitride (SiOCN), low-k dielectric materials, other suitable dielectric materials, or combinations thereof. Dielectric layer 272 may be deposited by any suitable method, such as ALD, CVD, other suitable methods, or combinations thereof. In this embodiment, the dielectric layer 272 is deposited by an ALD process.
In some embodiments, forming the dielectric layer 272 in the opening 211 using an ALD process results in a seam or air gap 274a extending longitudinally along the X-axis. Seam 274a differs from seam 222 in that seam 274 is configured to have a slope equal to or less than the slope R of tapered opening 270 shown in fig. 22B and 23B. Referring to fig. 24A, forming dielectric layer 272 may result in additional seams 274b and 274c, wherein seam 274 extends generally along the Z-axis and seam 274c each extends away from seam 274b along the X-axis. In some embodiments, the height of seam 274c measured along the Z-axis tapers in a direction away from seam 274b and along the X-axis. In some examples, the portion of the dielectric layer 272 formed on each side of the seam 274b may be defined by a thickness of about half the height Z2 as shown in fig. 24A. In some embodiments, one or more of the seams 274a-274c are not present in the device 200 after the deposition process of operation 155. Note that after trimming dielectric layer 272 in a subsequent etching process, seams 274b and 274c (if present) are removed from device 200.
Referring to fig. 1B and 24B, the method 140 performs an etching (or trimming) process to remove portions of the dielectric layer 272 formed in the S/D grooves 232, leaving portions of the dielectric layer 272 in the openings 211 and the tapered openings 270 to form BDIs 276 and leaving portions of the dielectric layer 272 in the grooves 234 to form the interior spacers 242 at operation 157. Notably, after removing portions of the dielectric layer 272, portions of the seam 274a remain in the BDI 276. In some embodiments, the etching process is similar to etching process 314 discussed in detail above with respect to operation 148. The resulting BDI276 includes a tapered upper surface 277 extending downwardly and away from the S/D groove 232.
Referring to fig. 1A and 25, the method 100 continues at operation 110 to form epitaxial S/D features 252 in the S/D recesses 232 and then replaces the dummy gate stack 210 and the remainder of the SiGe layer 207 with a metal gate structure 260 at operations 112 and 114, as discussed in detail above with respect to fig. 13 and 14.
In the present embodiment, the difference between the device 200 depicted in fig. 25 and the device 200 depicted in fig. 13 and 14 (or fig. 21) is twofold. First, the internal spacers 242 and BDI276 depicted in fig. 25 are formed by a common etching and deposition process so that they can be formed to have the same composition. In contrast, the internal spacers 240 and BDI 226 depicted in fig. 13 and 14 may be formed to have different compositions because they are formed in separate processes. Second, the common etching process used to form the internal spacers 242 and the BDI276 results in overetching in the bottommost SiGe layer 207 of the ML, resulting in the BDI276 having a downwardly tapered upper surface 277 that interfaces with the bottommost SiGe layer 207. In this embodiment, tapered upper surface 277 also meets the bottommost portion of metal gate structure 260. In contrast, the upper surfaces of the BDIs 224 and 226 depicted in FIGS. 13 and 14 are substantially horizontal along the X-axis. In this embodiment, the seam 274a is also defined by a downward slope, which may be less than or equal to the slope R of the tapered upper surface 277 of the BDI 276.
In some embodiments, referring to fig. 26-29 (corresponding to fig. 13, 14A, 14B, and 25, respectively), BDIs 224 (fig. 26 and 27), 226 (fig. 28), and 276 (fig. 29) are configured with multiple layers of different dielectric materials. For example, the BDI 224 may include a layer 224b disposed over the layer 224a, the BDI 226 may include a layer 226b over the layer 226a, and the BDI 276 may include a layer 276b over the layer 276 a. In some embodiments, referring to fig. 26, the inner spacer 240 may include a single layer structure, and the BDI 224 may include a multi-layer structure. In some embodiments, referring to fig. 27 and 28, the internal spacers 240 include a layer 240b disposed over a layer 240a in a multi-layer structure, wherein the layers 240a and 240b may be the same as or different from the layers 226a and 226b, respectively. In some embodiments, referring to fig. 29, the interior spacer 242 includes a layer 242b disposed over the layer 242a in a multi-layer structure, wherein the layers 242a and 242b are identical to the layers 276a and 276b, respectively. Examples of dielectric materials included in layers 224a, 224b, 226a, 226b, 240a, 240b, 242a, 242b, 276a, and 276b are discussed above with respect to dielectric layer 220 and internal spacers 240.
Thereafter, the method 100 may perform additional processing steps on the device 200 at operation 116. For example, the method 100 may form S/D contacts (not depicted) over the epitaxial S/D features 250 (or 252). Each S/D contact may comprise any suitable conductive material, such as Co, W, ru, cu, al, ti, ni, au, pt, pd, other suitable conductive materials, or a combination thereof. The method 100 may form S/D contact openings in the ILD layer 216 through a series of patterning and etching processes and then deposit conductive material in the S/D contact openings using any suitable method (e.g., CVD, ALD, PVD, electroplating, other suitable process, or a combination thereof). In some embodiments, a silicide layer (not depicted) is formed between the epitaxial S/D features 250 (or 252) and their respective S/D contacts. The silicide layer may comprise nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, other suitable silicides, or combinations thereof. A silicide layer may be formed over the device 200 by a deposition process such as CVD, ALD, PVD or a combination thereof. Subsequently, although not depicted, the method 100 may form additional features over the device 200, such as additional ESL and ILD layers, gate contacts over the metal gate structure 260, vertical interconnect features (e.g., vias), horizontal interconnect features (e.g., wires), additional intermetal dielectric layers (e.g., ESL and ILD layers), other suitable features, or a combination thereof.
Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor devices and their formation. For example, the present disclosure provides methods of forming GAA FETs that include a bottom (or buried) dielectric isolation structure (BDI) that may extend under the channel region or under the channel region and S/D regions of the GAA FETs. In this embodiment, forming the BDI includes forming a dummy SiGe layer and then replacing it with a dielectric layer to form the BDI. In some embodiments, the BDI is formed in an advanced BDI process prior to forming the S/D grooves. Alternatively, the BDI is formed in a post BDI process after the S/D grooves are formed. In some embodiments, the BDI and internal spacers of the GAA FET are formed together in a series of etching and deposition processes. In some embodiments, the BDI is formed to include a tapered top surface that interfaces with the bottommost portion of the gate structure of the GAA FET. Embodiments of the present disclosure may be adapted to improve control of sub-channel leakage by incorporating a buried dielectric layer below the channel region and/or S/D region of the GAA FET.
In one aspect, the present disclosure provides a semiconductor structure that includes a substrate and a plurality of semiconductor layers disposed over the substrate. The semiconductor structure further includes a gate structure disposed on and surrounding each semiconductor layer and source/drain features disposed over the substrate and adjacent to the gate structure. The semiconductor structure further includes a dielectric layer disposed between the bottommost surface of the gate structure and the substrate.
In another aspect, the present disclosure provides a semiconductor structure that includes a substrate and a stacked structure including channel layers interleaved with metal gate structures. The semiconductor structure further includes an isolation feature disposed between the stacked structure and the substrate, wherein a bottommost portion of the metal gate structure directly contacts the isolation feature. The semiconductor structure further includes source/drain features disposed adjacent the stacked structure and an internal spacer disposed between the metal gate structure and the source/drain features.
In yet another aspect, the present disclosure provides a method comprising forming a fin protruding from a substrate, wherein the fin comprises a first SiGe layer and a stacked structure located above the first SiGe layer, wherein the stacked structure comprises alternating second SiGe layers and Si layers, and wherein the first SiGe layer comprises more Ge than each of the second SiGe layers; forming a dummy gate stack over a channel region of the fin; replacing the first SiGe layer with a dielectric layer to form an isolation feature; removing a portion of the fin to form a source/drain recess adjacent the dummy gate stack; forming an internal spacer on sidewalls of the second SiGe layer exposed to the source/drain recess; forming source/drain features over the inner spacers; and forming a metal gate structure adjacent the source/drain feature to replace the dummy gate stack and the second SiGe layer such that a bottommost portion of the metal gate structure directly contacts the isolation feature.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Example 1. A semiconductor structure, comprising:
a substrate;
a plurality of semiconductor layers disposed over the substrate;
a gate structure disposed on and surrounding each of the semiconductor layers;
source/drain features disposed over the substrate and adjacent to the gate structure; and
and a dielectric layer disposed between the bottommost surface of the gate structure and the substrate.
Example 2 the semiconductor structure of example 1, wherein the dielectric layer includes a first portion disposed between a bottommost surface of the gate structure and the substrate and a second portion disposed between the source/drain feature and the substrate.
Example 3 the semiconductor structure of example 1, wherein the dielectric layer includes a seam embedded therein.
Example 4 the semiconductor structure of example 3, wherein the source/drain features extend below the seam but above the substrate.
Example 5 the semiconductor structure of example 1, wherein the dielectric layer includes a tapered top surface extending downward from the source/drain feature.
Example 6 the semiconductor structure of example 5, wherein the dielectric layer includes a seam embedded therein, and wherein the seam is tapered.
Example 7. The semiconductor structure of example 1, further comprising an internal spacer between the gate structure and the source/drain feature, wherein the internal spacer and the dielectric layer have the same composition.
Example 8. A semiconductor structure, comprising:
a substrate;
a stacked structure including a channel layer interleaved with the metal gate structure;
an isolation feature disposed between the stacked structure and the substrate, wherein a bottommost portion of the metal gate structure directly contacts the isolation feature;
source/drain features disposed adjacent the stacked structure; and
An internal spacer is disposed between the metal gate structure and the source/drain feature.
Example 9 the semiconductor structure of example 8, wherein the source/drain features extend through the isolation features to contact the substrate.
Example 10 the semiconductor structure of example 8, wherein a bottom surface of the source/drain feature directly contacts the isolation feature.
Example 11 the semiconductor structure of example 8, wherein an interface between the bottommost portion of the metal gate structure and the isolation feature is sloped downward.
Example 12 the semiconductor structure of example 8, wherein the internal spacer and the isolation feature have the same composition.
Example 13 the semiconductor structure of example 8, wherein the isolation feature surrounds an air gap.
Example 14. A method, comprising:
forming a fin protruding from a substrate, wherein the fin comprises a first SiGe layer and a stacked structure located above the first SiGe layer, wherein the stacked structure comprises alternating second SiGe layers and Si layers, and wherein the first SiGe layer comprises more Ge than each of the second SiGe layers;
forming a dummy gate stack over a channel region of the fin;
Replacing the first SiGe layer with a dielectric layer to form an isolation feature;
removing a portion of the fin to form a source/drain recess adjacent the dummy gate stack;
forming an internal spacer on sidewalls of the second SiGe layer exposed to the source/drain recess;
forming source/drain features over the internal spacers; and
a metal gate structure adjacent to the source/drain features is formed in place of the dummy gate stack and the second SiGe layer such that a bottommost portion of the metal gate structure directly contacts the isolation features.
Example 15. The method of example 14, wherein the source/drain recesses are formed after the isolation features are formed.
Example 16 the method of example 15, further comprising, after forming the source/drain recesses, removing a portion of the isolation features in the source/drain recesses to expose the substrate such that bottom surfaces of the source/drain features are formed in direct contact with the substrate.
Example 17 the method of example 15, wherein forming the source/drain recess exposes a portion of the isolation feature in the source/drain recess such that a bottom surface of the source/drain feature is formed to directly contact the isolation feature.
Example 18 the method of example 14, wherein forming the source/drain recesses is performed prior to forming the isolation features, and wherein forming the internal spacers is performed after forming the isolation features.
Example 19 the method of example 14, wherein forming the source/drain recesses is performed prior to forming the isolation features, and wherein replacing the first SiGe layer comprises forming the isolation features and forming the internal spacers together.
Example 20. The method of example 14, wherein replacing the first SiGe layer comprises:
selectively removing the first SiGe layer relative to the second SiGe layer and the Si layer to form an opening;
depositing the dielectric layer over the substrate, thereby filling the opening; and
an anisotropic etch process is performed to remove a portion of the dielectric layer, leaving the isolation features in the openings.

Claims (10)

1. A semiconductor structure, comprising:
a substrate;
a plurality of semiconductor layers disposed over the substrate;
a gate structure disposed on and surrounding each of the semiconductor layers;
source/drain features disposed over the substrate and adjacent to the gate structure; and
And a dielectric layer disposed between the bottommost surface of the gate structure and the substrate.
2. The semiconductor structure of claim 1, wherein the dielectric layer comprises a first portion disposed between a bottommost surface of the gate structure and the substrate and a second portion disposed between the source/drain feature and the substrate.
3. The semiconductor structure of claim 1, wherein the dielectric layer comprises a seam embedded therein.
4. The semiconductor structure of claim 3 wherein the source/drain features extend below the seam but above the substrate.
5. The semiconductor structure of claim 1 wherein the dielectric layer comprises a tapered top surface extending downward from the source/drain feature.
6. The semiconductor structure of claim 5, wherein the dielectric layer comprises a seam embedded therein, and wherein the seam is tapered.
7. The semiconductor structure of claim 1, further comprising an internal spacer between the gate structure and the source/drain feature, wherein the internal spacer and the dielectric layer have the same composition.
8. A semiconductor structure, comprising:
a substrate;
a stacked structure including a channel layer interleaved with the metal gate structure;
an isolation feature disposed between the stacked structure and the substrate, wherein a bottommost portion of the metal gate structure directly contacts the isolation feature;
source/drain features disposed adjacent the stacked structure; and
an internal spacer is disposed between the metal gate structure and the source/drain feature.
9. The semiconductor structure of claim 8, wherein the source/drain features extend through the isolation features to contact the substrate.
10. A method of forming a semiconductor structure, comprising:
forming a fin protruding from a substrate, wherein the fin comprises a first SiGe layer and a stacked structure located above the first SiGe layer, wherein the stacked structure comprises alternating second SiGe layers and Si layers, and wherein the first SiGe layer comprises more Ge than each of the second SiGe layers;
forming a dummy gate stack over a channel region of the fin;
replacing the first SiGe layer with a dielectric layer to form an isolation feature;
removing a portion of the fin to form a source/drain recess adjacent the dummy gate stack;
Forming an internal spacer on sidewalls of the second SiGe layer exposed to the source/drain recess;
forming source/drain features over the internal spacers; and
a metal gate structure adjacent to the source/drain features is formed in place of the dummy gate stack and the second SiGe layer such that a bottommost portion of the metal gate structure directly contacts the isolation features.
CN202310196130.6A 2022-03-03 2023-03-03 Bottom dielectric isolation and method for forming same in field effect transistor Pending CN116632048A (en)

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US17/833,440 US20230282751A1 (en) 2022-03-03 2022-06-06 Bottom dielectric isolation and methods of forming the same in field-effect transistors

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