CN116632005A

CN116632005A - Semiconductor device structure and forming method thereof

Info

Publication number: CN116632005A
Application number: CN202310306045.0A
Authority: CN
Inventors: 张正伟; 沙哈吉·B·摩尔; 周其雨; 白岳青
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-04-29
Filing date: 2023-03-27
Publication date: 2023-08-22

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes one or more semiconductor layers, an interface layer surrounding at least one of the one or more semiconductor layers, a work function metal disposed over the interface layer, and a high-K (HK) dielectric layer disposed between the interface layer and the work function metal. The HK dielectric layer includes a first dopant region adjacent to a first interface of the HK dielectric layer and the interface layer, wherein the first dopant region includes a first dopant having a first polarity. The HK dielectric layer also includes a second dopant region adjacent to the second interface of the HK dielectric layer and the work function metal, wherein the second dopant region includes a second dopant having a second polarity opposite the first polarity. Embodiments of the present application also relate to methods for forming semiconductor device structures.

Description

Semiconductor device structure and forming method thereof

Technical Field

Embodiments of the present application relate to semiconductor device structures and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. This scaling down presents new challenges.

Challenges from manufacturing and design issues have created the development of three-dimensional designs, such as multi-gate Field Effect Transistors (FETs), including nanoflake FETs, in pursuit of higher device density, higher performance, and lower cost. In a nanoflake FET, all sides of the channel are surrounded by a gate electrode, which allows for more adequate depletion in the channel and produces less short channel effects and better gate control. As transistor dimensions continue to shrink, further improvements in nanoflake FETs are needed.

Disclosure of Invention

Some embodiments of the application provide a semiconductor device structure comprising: one or more semiconductor layers; an interfacial layer surrounding at least one of the one or more semiconductor layers; work function metal arranged above the interface layer; and a high-K (HK) dielectric layer disposed between the interfacial layer and the work function metal, comprising; a first dopant region adjacent to a first interface of the high-K dielectric layer and the interface layer, wherein the first dopant region comprises a first dopant having a first polarity; and a second dopant region adjacent to a second interface of the high-K dielectric layer and the work function metal, wherein the second dopant region comprises a second dopant having a second polarity opposite the first polarity.

Other embodiments of the present application provide a semiconductor device structure comprising: a dielectric member; one or more first semiconductor layers disposed adjacent to the first side of the dielectric member, wherein each of the one or more first semiconductor layers has a first width; one or more second semiconductor layers disposed adjacent to the second side of the dielectric member, wherein each of the one or more second semiconductor layers has a second width greater than the first width; an interface layer surrounding each of the one or more first semiconductor layers and the one or more second semiconductor layers, wherein the interface layer comprises a first dopant region adjacent to a first interface of the interface layer and the first semiconductor layer and a second interface of the interface layer and the second semiconductor layer, respectively, and wherein the first dopant region comprises a first dopant having a first polarity; a first work function metal disposed over the interfacial layer surrounding at least one first semiconductor layer and one second semiconductor layer, wherein the first work function metal has a first conductivity type; a second work function metal disposed over the interfacial layer surrounding at least one second semiconductor layer, wherein the second work function metal has a second conductivity type opposite the first conductivity type; and a High K (HK) dielectric stack comprising: a first high-K dielectric layer comprising a second dopant region in contact with the first work function metal, wherein the second dopant region comprises a second dopant having a second polarity opposite the first polarity; and a second high-K dielectric layer disposed between and in contact with the first high-K dielectric layer and the interface layer.

Still further embodiments of the present application provide a method for forming a semiconductor device structure, comprising: forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; forming a sacrificial gate structure over the fin structure; forming source/drain features on opposite sides of the sacrificial gate structure, the source/drain features in contact with the plurality of first semiconductor layers of the fin structure; removing portions of the plurality of second semiconductor layers to expose portions of each of the plurality of first semiconductor layers; surrounding the interfacial layer around the exposed portion of each of the plurality of first semiconductor layers; depositing a first high-K (HK) dielectric layer on the interfacial layer; depositing a first additive layer on the first high-K dielectric layer, wherein the first additive layer comprises a first dopant having a first polarity; subjecting the fin structure to a first heat treatment; removing the first additive layer to expose the first high-K dielectric layer; depositing a second high-K dielectric layer over the first high-K dielectric layer; depositing a second additive layer on the second high-K dielectric layer, wherein the second additive layer comprises a second dopant having a second polarity opposite the first polarity; subjecting the fin structure to a second heat treatment; and removing the second additive layer.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1-8 are perspective views of various stages in the manufacture of a semiconductor device structure in accordance with some embodiments.

Fig. 9A-15A are perspective views of various stages of fabricating a semiconductor device structure, taken along section A-A of fig. 8, in accordance with some embodiments.

Fig. 9B-15B are cross-sectional side views of various stages of fabricating a semiconductor device structure, taken along section B-B of fig. 8, in accordance with some embodiments.

Fig. 9C-15C are cross-sectional side views of various stages of fabricating a semiconductor device structure, taken along section C-C of fig. 8, in accordance with some embodiments.

Fig. 15B-1 and 15B-3 illustrate enlarged views of portions of dielectric material showing curved surface contours, according to some embodiments.

Fig. 15B-2 illustrates an enlarged view of a portion of an insulating material showing a curved surface profile, according to some embodiments.

Fig. 16-28 are enlarged views of the area of fig. 15B showing various stages of fabricating a semiconductor device structure, in accordance with some embodiments.

Fig. 19-1 and 19-2 illustrate enlarged views of portions of a semiconductor device structure showing a layer having dopant profiles after heat treatment, in accordance with one embodiment.

Fig. 19-3 and 19-4 illustrate enlarged views of portions of a semiconductor device structure showing a layer having dopant profile after heat treatment, in accordance with another embodiment.

Fig. 23-1 through 23-8 illustrate enlarged views of portions of a semiconductor device structure showing a layer having dopant profiles after heat treatment, in accordance with some embodiments.

Fig. 29A-29D are cross-sectional side views of one of the stages of fabrication of a semiconductor device structure taken along the cross-sections A-A, B-B, C-C and D-D of fig. 8, in accordance with some embodiments.

Fig. 30A-30D are cross-sectional side views of one of the stages of fabrication of a semiconductor device structure taken along the cross-sections A-A, B-B, C-C, and D-D of fig. 8, in accordance with some embodiments.

Fig. 29A-1 and 29D-1 are enlarged views of portions of the semiconductor device structure in fig. 29A and 29D, respectively, showing the arrangement of layers between adjacent first semiconductor layers according to the embodiment of fig. 28.

Fig. 29A-2 and 29D-2 are enlarged views of portions of the semiconductor device structure in fig. 29A and 29D, respectively, showing the arrangement of layers between adjacent first semiconductor layers according to the embodiment of fig. 23-1.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms such as "under …," "under …," "lower," "above …," "above …," "over …," "top," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

While embodiments of the present invention are discussed with respect to a nanoflake channel FET, implementations of some aspects of the present invention may be used in other processes and/or other devices, such as planar FETs, fin-FETs, horizontal full-gate (HGAA) FETs, vertical full-gate (VGAA) FETs, and other suitable devices. Those of ordinary skill in the art will readily appreciate other modifications that may be made while remaining within the scope of the present invention. Where a full gate-all-around (GAA) transistor structure is employed, the GAA transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing creation of patterns with, for example, smaller pitches than are obtainable using single, direct photolithography processes. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the GAA structure.

Fig. 1-30D illustrate an exemplary process for fabricating a semiconductor device structure 100 in accordance with an embodiment of the present invention. It should be appreciated that additional operations may be provided before, during, and after the processes shown in fig. 1-30D, and that some of the operations described below may be replaced or eliminated for additional embodiments of the methods. The order of operations/processes is not limiting and may be interchangeable.

Fig. 1-8 are perspective views of various stages in the manufacture of a semiconductor device structure 100 in accordance with some embodiments. As shown in fig. 1, semiconductor device structure 100 includes a semiconductor layer stack 104 formed over a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include single crystal semiconductor materials such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (inaias), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), and indium phosphide (InP). In one embodiment, the substrate 101 is made of silicon. In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having P-type or N-type conductivity). The dopant may be, for example, boron for a P-type field effect transistor (P-type FET) and phosphorus for an N-type field effect transistor (N-type FET). For example, the substrate 101 may have a region 153 and a region 155 adjacent to the region 153. Region 153 may be designated as a P-type region or an N-type region, and region 155 may be designated as an N-type region or a P-type region. Alternatively, both regions 153, 155 may be designated as P-type regions or N-type regions. In one embodiment, region 153 is an N-type region and region 155 is a P-type region. Although not shown to scale in some figures, regions 153 and 155 belong to the continuous substrate 101. In some embodiments of the present invention, the P-type region is used to form PMOS structures thereon, and the N-type region is used to form NMOS structures thereon. Depending on the circuit design, the regions 153, 155 may be used to form different types of circuits. For example, region 153 may be used to form, for example, peripheral circuitry, input/output (I/O) circuitry, electrostatic discharge (ESD) circuitry, and/or analog circuitry, and region 155 may be used to form logic circuitry. Other regions for forming other types of circuits are contemplated and intended to be included within the scope of the present invention.

The semiconductor layer stack 104 includes semiconductor layers made of different materials to facilitate formation of a nanoplate channel, such as a nanoplate channel FET, in a multi-gate device. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivity and/or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe and the second semiconductor layer 108 may be made of Si. Optionally, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials, such as Ge, siC, geAs, gaP, inP, inAs, inSb, gaAsP, alInAs, alGaAs, inGaAs, gaInP, gaInAsP or any combination thereof.

The thickness of the first semiconductor layer 106 and the second semiconductor layer 108 may vary depending on application and/or device performance considerations. In some embodiments, each of the first semiconductor layer 106 and the second semiconductor layer 108 has a thickness in a range between about 3nm and about 30nm, for example, about 5nm and about 10nm. Each of the second semiconductor layers 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. The second semiconductor layer 108 may eventually be removed and used to define the vertical distance between adjacent channels of the semiconductor device structure 100.

The first semiconductor layer 106 or portions thereof may form the nanoplatelet channel of the semiconductor device structure 100 at a later stage of fabrication. The term nanoplatelet is used herein to denote any portion of material having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions of circular and substantially circular cross-section, as well as including beam-shaped or strip-shaped material portions of, for example, cylindrical or substantially rectangular cross-section. The nanoplatelet channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nano-sheet transistor. The nanoplate transistor may be referred to as a nanowire transistor, a full-gate-all-around-Gate (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is discussed further below.

The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, epitaxial growth of the layers of the semiconductor layer stack 104 may be performed by a Molecular Beam Epitaxy (MBE) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, and/or other suitable epitaxial growth processes. Although three first semiconductor layers 106 and three second semiconductor layers 108 are alternately arranged as shown in fig. 1, it is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, depending on the predetermined number of nanoflake channels required for each FET of the semiconductor device structure 100. For example, the number of first semiconductor layers 106 (which is the number of channels) may be between 2 and 8.

In fig. 2, fin structure 112 is formed from semiconductor layer stack 104. Each fin structure 112 has a portion that includes an upper portion of the semiconductor layers 106, 108, a well portion 116 formed by the substrate 101, and a mask structure 110. Prior to forming fin structure 112, mask structure 110 is formed over semiconductor layer stack 104. The mask structure 110 may include a pad layer 110a and a hard mask 110b. The underlayer 110a may be an oxygen-containing layer (such as SiO ₂ Layer) or a nitrogen-containing layer (such as Si ₃ N ₄ ). Mask structure 110 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD) process.

Fin structure 112 may be fabricated using suitable processes including photolithography and etching processes. In some embodiments, the photolithographic process may include forming a photoresist layer (not shown) over the mask structure 110, exposing the resist to a pattern, performing a post-exposure bake process, and developing the resist to form a patterned resist. The patterned resist may then be used to protect regions of the substrate 101 and layers formed thereon, while an etching process forms trenches 114 through the mask structure 110, the semiconductor layer stack 104, and into the substrate 101 in the unprotected regions, leaving behind extended fin structures 112. The trenches 114 may be etched using a dry etch (e.g., RIE), a wet etch, and/or a combination thereof. Although two fin structures 112 are shown, the number of fin structures is not limited to two.

In some embodiments, fin structure 112 may be fabricated such that fin structure 112 at region 155 (e.g., P-type region) has a width W1 and fin structure 112 at region 153 (e.g., N-type region) has a width W2 that is greater than width W1. Because holes are subjected to atomic forces that are stronger in the pulling of the core than electrons located in a higher shell or more distant shell, the mobility of electrons in the semiconductor is greater than the mobility of holes. Forming fin structure 112 at the P-type region to have a smaller width W1 (i.e., a shorter channel length) than the width W2 of fin structure 112 at the N-type region may increase the mobility of holes or compensate for the lower mobility of holes in fin structure 112 at the P-type region. In various embodiments, the ratio of W1 to W2 may be about 1:1.5 to 1:3, such as about 1:2 to about 1:2.5.

In fig. 3, after forming fin structures 112, an insulating material 118 is formed in trenches 114 between fin structures 112. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. A planarization operation, such as a Chemical Mechanical Polishing (CMP) process and/or an etchback process, is then performed to expose the top of fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), siOCN, siCN, fluorine doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as Low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced CVD (PECVD), or Flowable CVD (FCVD).

Next, insulating material 118 is recessed to form isolation regions 120. The recess of insulating material 118 exposes a portion of fin structure 112. Isolation regions 120 may be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 may be flush with the surface of the second semiconductor layer 108 in contact with the well portion 116 or below the surface of the second semiconductor layer 108 in contact with the well portion 116.

In fig. 4, a cladding layer 117 is formed over the exposed portions of fin structure 112 by an epitaxial process. In some embodiments, a semiconductor liner (not shown) may first be formed over fin structure 112, and then cladding layer 117 may be formed over the semiconductor liner. The semiconductor liner may diffuse into the cladding layer 117 during formation of the cladding layer 117. In either case, the cladding layer 117 is in contact with the semiconductor layer stack 104. In some embodiments, the cladding layer 117 and the second semiconductor layer 108 comprise the same material having the same etch selectivity. For example, the cladding layer 117 and the second semiconductor layer 108 may be or include SiGe. The cladding layer 117 and the second semiconductor layer 108 may then be removed to create space for the gate electrode layer.

In fig. 5, a pad 119 is formed on top of the cladding layer 117 and the insulating material 118. Liner 119 may include a low-k dielectric material (e.g., a material having a k value below 7), such as SiO ₂ SiN, siCN, siOC or SiOCN. Liner 119 may be formed by a conformal process, such as an ALD process. A dielectric material 121 is then formed in trench 114 (fig. 4) and over pad 119. The dielectric material 121 may be an oxygen-containing material, such as an oxide, formed by FCVD. The oxygen-containing material may have a K value of less than about 7, for example less than about 3. A planarization process, such as a CMP process, may be performed to remove the liner 119 and portions of the dielectric material 121 formed over the fin structure 112. The portion of the cladding layer 117 disposed on the hard mask 110b is exposed after the planarization process.

Next, liner 119 and dielectric material 121 are recessed to the level of the topmost first semiconductor layer 106 using any suitable process. For example, in some embodiments, after the recessing process, the top surfaces of liner 119 and dielectric material 121 may be recessed to be flush with the top surface of topmost first semiconductor layer 106. The etching process may be a selective etching process that does not remove the semiconductor material of the cladding layer 117. Due to the recess process, trenches 123 are formed between fin structures 112. The trenches 123 provide space for the subsequent dielectric material 125 (fig. 6). Alternatively, the dielectric material 125 may be optional and no dielectric material 125 is used. In this case, the liner 119 and the dielectric material 121 are formed between the fin structures 112 without a recess process.

In fig. 6, a dielectric material 125 is formed in trench 123 (fig. 5) and over dielectric material 121 and liner 119. The dielectric material 125 may include SiN, siC, siCN, siON, siCON, alO, alN, alON, zrO, zrN, zrAlO, hfO or other suitable dielectric material. In some embodiments, dielectric material 125 comprises a high-K dielectric material (e.g., a material having a K value greater than 7). The dielectric material 125 may be formed by any suitable process, such as CVD, PECVD, FCVD or ALD processes. A planarization process, such as a CMP process, is performed until the hard mask 110b of the mask structure 110 is exposed. The planarization process removes portions of the dielectric material 125 and the cladding layer 117 disposed over the mask structure 110. Together, liner 119, dielectric material 121, and dielectric material 125 may be referred to as dielectric element 127 or hybrid fin. Dielectric feature 127 serves as a dielectric fin separating subsequent source/drain (S/D) epitaxial features from adjacent gate electrode layers. In some embodiments, dielectric material 125 is omitted. In this case, the hybrid fin includes only liner 119 and dielectric material 121, which may be advantageous in some applications because the defect issues that may occur if a high-K dielectric material is used for dielectric material 125 are reduced.

In fig. 7, the cladding layer 117 is recessed and the mask structure 110 is removed. Portions of dielectric material 125 may also be removed due to the removal of cladding layer 117. Recessing of cladding layer 117 may be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. The recessing process may be controlled such that the remaining cladding layer 117 is located substantially at the same level as the top surface of the topmost first semiconductor layer 106 in the semiconductor layer stack 104. The removal of the mask structure 110 may be performed by any suitable process, such as dry etching, wet etching, or a combination thereof.

In fig. 8, one or more sacrificial gate structures 130 (only one shown) are formed over semiconductor device structure 100. Sacrificial gate structure 130 is formed over a portion of fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. Sacrificial gate dielectric layer 132, sacrificial gate electrode layer 134, and mask layer 136 may be formed by sequentially depositing blanket layers of sacrificial gate dielectric layer 132, sacrificial gate electrode layer 134, and mask layer 136, and subsequent patterning and etching processes. For example, the patterning process includes a photolithography process (e.g., photolithography or e-beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and/or hard baking), other suitable photolithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and/or combinations thereof.

By patterning the sacrificial gate structure 130, the semiconductor layer stack 104 of the fin structure 112 is partially exposed on opposite sides of the sacrificial gate structure 130. The portion of fin structure 112 covered by sacrificial gate electrode layer 134 of sacrificial gate structure 130 serves as a channel region for semiconductor device structure 100. The partially exposed fin structure 112 on opposite sides of the sacrificial gate structure 130 defines source/drain (S/D) regions for the semiconductor device structure 100. Although one sacrificial gate structure 130 is shown, two or more sacrificial gate structures 130 may be arranged in the X-direction in some embodiments.

Next, gate spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. The gate spacers 138 may be formed by first depositing a conformal layer that is then etched back to form sidewall gate spacers 138. For example, a layer of spacer material may be conformally disposed on the exposed surfaces of the semiconductor device structure 100. The conformal spacer material layer may be formed by an ALD process. Subsequently, anisotropic etching is performed on the spacer material layer using, for example, RIE. During the anisotropic etching process, most of the spacer material layer is removed from horizontal surfaces (such as the top of fin structure 112, cladding layer 117, dielectric material 125), leaving gate spacers 138 on vertical surfaces (such as the sidewalls of sacrificial gate structure 130). The gate spacers 138 may be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, siCN, silicon oxycarbide, siOCN, and/or combinations thereof.

Fig. 9A-15A are cross-sectional side views of various stages of fabricating a semiconductor device structure 100, taken along section A-A of fig. 8, in accordance with some embodiments. Fig. 9B-15B are cross-sectional side views of various stages of fabricating the semiconductor device structure 100, taken along section B-B of fig. 8, in accordance with some embodiments. Fig. 9C-15C are cross-sectional side views of various stages of fabricating semiconductor device structure 100, taken along section C-C of fig. 8, in accordance with some embodiments. The cross-section A-A lies in the plane of the fin structure 112 along the X-direction. Section B-B lies in a plane perpendicular to section A-A and lies in sacrificial gate structure 130. Section C-C lies in a plane perpendicular to section A-A and in the source/drain regions in the Y direction (e.g., epitaxial S/D feature 146 shown in FIG. 11C).

In fig. 9A-9C, the exposed portions of fin structure 112, the exposed portions of cladding layer 117, and the exposed portions of dielectric material 125 that are not covered by sacrificial gate structure 130 and gate spacer 138 are selectively recessed using one or more suitable etching processes, such as dry etching, wet etching, or a combination thereof. In some embodiments, the exposed portion of the semiconductor layer stack 104 of the fin structure 112 is removed, thereby exposing a portion of the well portion 116. As shown in fig. 9A, the exposed portion of fin structure 112 is recessed to a level at or slightly below the bottom surface of second semiconductor layer 108 that is in contact with well portion 116 of substrate 101. The recessing process may include an etching process that recessing the exposed portions of fin structure 112 and the exposed portions of cladding layer 117.

In the drawingsIn fig. 10A to 10C, an edge portion of each second semiconductor layer 108 of the semiconductor layer stack 104 is horizontally removed in the X direction. The removal of the edge portion of the second semiconductor layer 108 forms a cavity. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etch process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 may be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH) ₄ OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 may be made of a low K dielectric material, such as SiON, siCN, siOC, siOCN or SiN. The dielectric spacers 144 may be formed by first forming a conformal dielectric layer using a conformal deposition process (such as ALD), and then anisotropically etching to remove portions of the conformal dielectric layer other than the dielectric spacers 144. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is covered between the dielectric spacers 144 in the X-direction.

In fig. 11A-11C, epitaxial S/D feature 146 is formed on well portion 116 of fin structure 112. The epitaxial S/D feature 146 may include one or more layers of Si, siP, siC and SiCP for an N-type FET or Si, siGe, ge for a P-type FET. The epitaxial S/D features 146 may be grown vertically and horizontally to form facets, which may correspond to crystal planes of the material used for the substrate 101. The epitaxial S/D features 146 are formed by an epitaxial growth method using CVD, ALD, or MBE. The epitaxial S/D feature 146 is in contact with the first semiconductor layer 106 and the dielectric spacer 144. The epitaxial S/D feature 146 may be an S/D region. For example, one of the epitaxial S/D feature 146 pairs on one side of the sacrificial gate structure 130 may be a source region and the other of the epitaxial S/D feature 146 pairs on the other side of the sacrificial gate structure 130 may be a drain region. The epitaxial S/D feature 146 pair includes a source epitaxial feature 146 and a drain epitaxial feature 146 connected by a channel (i.e., the first semiconductor layer 106). The source epi feature 146 and the drain epi feature 146 may be referred to individually or collectively as a source region and a drain region, depending on the context. In the present invention, the source and the drain are used interchangeably and their structures are substantially the same.

In fig. 12A-12C, after forming the epitaxial S/D features 146, a Contact Etch Stop Layer (CESL) 162 is conformally formed on the exposed surfaces of the semiconductor device structure 100. CESL 162 covers the exposed surfaces of epitaxial S/D feature 146, gate spacer 138, dielectric material 125, and semiconductor layer stack 104. CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, and the like, or combinations thereof, and may be formed by CVD, PECVD, ALD or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed over the CESL 162 over the semiconductor device structure 100. Materials for ILD layer 164 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), and/or other suitable dielectric materials including Si, O, C, and/or H. ILD layer 164 may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after forming ILD layer 164, semiconductor device structure 100 may be subjected to a thermal treatment to anneal ILD layer 164.

In fig. 13A-13C, after formation of ILD layer 164, a planarization operation, such as CMP, is performed on semiconductor device structure 100 to remove portions of ILD layer 164, CESL 162, and mask layer 136 until sacrificial gate electrode layer 134 is exposed.

In fig. 14A-14C, the sacrificial gate structure 130 is removed. The removal of the sacrificial gate structure 130 forms a trench 166 in the region where the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 are removed. Trench 166 exposes a portion of cladding layer 117 and the top of first semiconductor layer 106. ILD layer 164 protects epitaxial S/D feature 146 during removal of sacrificial gate structure 130. The sacrificial gate structure 130 may be removed using a plasma dry etch and/or a wet etch. Sacrificial gate electrode layer 134 may be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by removal of sacrificial gate dielectric layer 132, which may also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer 134, but not the gate spacers 138, the dielectric material 125, and the CESL 162. In some embodiments, gate spacers 138 may be recessed by an etchant used to remove sacrificial gate electrode layer 134 and/or sacrificial gate dielectric layer 132.

In fig. 15A to 15C, the clad layer 117 and the second semiconductor layer 108 are removed. Removal of the cladding layer 117 and the second semiconductor layer 108 exposes the dielectric spacers 144 and the first semiconductor layer 106. The removal process may be any suitable etching process, such as dry etching, wet etching, or a combination thereof. The etching process may be a selective etching process that removes the capping layer 117 (fig. 14B) and the second semiconductor layer 108, but does not remove the gate spacers 138, the CESL 162, the dielectric material 125, and the first semiconductor layer 106. Accordingly, an opening 151 is formed around the first semiconductor layer 106, and a portion of the first semiconductor layer 106 not covered by the dielectric spacer 144 is exposed to the opening 151.

In some embodiments, which may be combined with any of the other embodiments of the present invention, an optional plasma treatment is performed to remove etching residues or mixed materials left by the removal of cladding layer 117 and second semiconductor layer 108. The plasma treatment may be an argon-based plasma, an oxygen-based plasma, or a combination thereof. In these embodiments, the top surface 125a of the dielectric material 125 and the top surface 118a of the insulating material 118 may be etched to have a curved profile. In some embodiments, the exposed top surface 125a of the dielectric material 125 and the exposed top surface 118a of the insulating material 118 are etched to have a concave surface profile, as shown in fig. 15B-1 and 15B-2, respectively. Without the use of dielectric material 125, the exposed portions of dielectric material 121 are etched to have a concave surface profile, such as top surface 121a shown in fig. 15B-3. While the top surfaces of dielectric material 125 and insulating material 118 are shown as planar surfaces in the present invention, it is contemplated that curved surface profiles as discussed herein may be applied.

Fig. 16-28 are enlarged views of region 147 of fig. 15B showing various stages of fabricating semiconductor device structure 100, in accordance with some embodiments. In fig. 16, an Interface Layer (IL) 150 is formed to surround the exposed surface of the first semiconductor layer 106. In some embodiments, the IL 150 may also be formed on the well portion 116 of the substrate 101. The IL 150 may include or be made of an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, nitrogen oxides, and the like. In one embodiment, the IL 150 is silicon oxide. The IL 150 may be formed by oxidizing an outer portion of the first semiconductor layer 106 and an outer portion of the exposed well portion 116 of the substrate 101. That is, the first semiconductor layer 106 and the outer portion of the substrate 101 that exposes the well portion 116 are the IL 150 or a portion of the IL 150. After the oxidation is completed, the outer portion surrounds the first semiconductor layer 106 and the well portion 116 of the substrate 101 and is in contact with the first semiconductor layer 106 and the well portion 116 of the substrate 101. In some embodiments, the IL 150 may be formed using an oxidation process, such as a thermal oxidation process, a Rapid Thermal Oxidation (RTO) process, an In Situ Stream Generation (ISSG) process, or an enhanced raw bit stream generation (EISSG) process. In one example, the IL 150 is formed by subjecting the first semiconductor layer 106 and the well portion 116 of the substrate 101 to a Rapid Thermal Anneal (RTA) in an oxygen-containing environment. Thermal oxidation may be performed at a temperature of about 600 degrees celsius to about 1100 degrees celsius for a time span of about 10 seconds to about 30 seconds. The temperature and time span of oxidation may affect the thickness of the IL 150. For example, higher temperatures and longer oxidation time spans may result in thicker IL 150. Additionally or alternatively, the IL 150 may also be an oxide formed by CVD, ALD, or any suitable conformal deposition technique. In either case, the IL 150 may have a thickness in the range from about 0.3nm to about 1.5 nm.

Alternatively, the IL 150 may be formed by first subjecting the first semiconductor layer 106 and the exposed well portion 116 of the substrate 101 to a pre-cleaning process. The pre-cleaning process may be any suitable wet cleaning process, such as an APM process (which includes at least water (H) ₂ O), ammonium hydroxide(NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ) HPM process (which includes at least H) ₂ O、H ₂ O ₂ And hydrogen chloride (HCl)), SPM processes (also known as piranha cleaning), which include at least H ₂ O ₂ And sulfuric acid (H) ₂ SO ₄ ) Or any combination thereof. After the preclean process is completed, the preclean first semiconductor layer 106 and the exposed well section 116 of the substrate 101 may be further oxidized using the oxidation process described above to form the IL 150.

In fig. 17, a first High K (HK) dielectric layer 152 is formed on the exposed surfaces of the semiconductor device structure 100. In some embodiments, the first HK dielectric layer 152 is formed to encapsulate the IL 150 over the first semiconductor layer 106 and to contact the IL 150 over the first semiconductor layer 106. A first HK dielectric layer 152 is also formed on and in contact with the exposed surface of insulating material 118. The first HK dielectric layer 152 may include or be composed of hafnium oxide (HfO ₂ ) Hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta) ₂ O ₅ ) Yttria (Y) ₂ O ₃ ) Silicon oxynitride (SiON) or other suitable high-K material. In one embodiment, the first HK dielectric layer 152 is HfO ₂ . The first HK dielectric layer 152 may be a conformal layer formed by a conformal process, such as an ALD process or a CVD process. The first HK dielectric layer 152 may have a thickness in a range from about 1.5nm to about 6 nm.

In fig. 18, a first additive layer 154 is formed on the first HK dielectric layer 152. The first additive layer 154 surrounds the first semiconductor layer 106 and is located over the well portion 116 of the substrate 101. The first additive layer 154 may include a dopant having a positive polarity or a negative polarity depending on the conductivity type of the nano-sheet transistor. In the embodiment shown in fig. 18, the nanoplatelet transistor at region 153 is designated an N-type FET and the nanoplatelet transistor at region 155 is designated a P-type FET. In this case, the first additive layer 154 may be wrappedIncluding materials having dopants of positive polarity. The first additive layer 154 serves as a source of dopants for introduction into the first HK dielectric layer 152 and IL 150. As will be discussed in more detail below, dopants (e.g., metal ions) from the first additive layer 154 may be controlled to accumulate at and/or near the IL 150/first semiconductor layer 106 interface or the IL 150/first HK dielectric layer 152 interface to help adjust the threshold voltage of the subsequent N-type or P-type work function layer. Thus, the flatband voltage (V) of the nanoplate transistor at regions 153, 155 _FB ) May be tailored to meet different threshold voltage requirements. In various embodiments, the concentration of the dopant in the first additive layer 154 may range from about 10ppm to about 400 ppm. In other words, the concentration of the dopant in the first additive layer 154 may be at about 1E10 ¹⁷ Atoms/cm ^-3 To about 5E10 ²¹ Atoms/cm ^-3 Within a range of (2).

In some embodiments, the first additive layer 154 may include a material that inherently has a positive polarity. Exemplary materials may include, but are not limited to, zinc-containing materials, aluminum-containing materials, titanium-containing materials, germanium-containing materials, gallium-containing materials, and the like. In some embodiments, the first additive layer 154 may also include oxygen. In this case, the first additive layer 154 may include, but is not limited to, zinc oxide (ZnO), aluminum oxide (Al ₂ O ₃ ) Titanium dioxide (TiO) ₂ ) Germanium oxide (GeO) ₂ ) Gallium oxide (GaO), or the like, or combinations of the above. In one exemplary embodiment, the first additive layer 154 is ZnO. The first additive layer 154 may be formed by ALD, atomic Layer Epitaxy (ALE), CVD, or any suitable conformal deposition technique. In some embodiments, the first additive layer 154 may have a thickness of about 0.1nm to about 1.5 nm. Greater or lesser thicknesses are contemplated, depending on the threshold voltage requirements of the device.

In fig. 19, a capping layer 156a is formed to cover the nanoplatelets transistors at the regions 153, 155. The capping layer 156a surrounds the first semiconductor layer 106 and is located over the well portion 116 of the substrate 101. The cap layer 156a fills the opening 151 (fig. 18) to a level such that the nano-sheet transistor at least at the regions 153, 155 is immersed in the cap layer 156 a. In some embodiments of the present invention, in some embodiments,the capping layer 156a is formed to a level at or slightly below the interface defined by the dielectric material 121 and the dielectric material 125. First additive layer 154 may act as a barrier to prevent first HK dielectric layer 152 from contacting the ambient atmosphere when transferred between different process chambers (e.g., from a deposition chamber to a thermal process chamber). The capping layer 156a enhances the barrier and prevents dopant atoms from penetrating during subsequent processes, such as heat treatment. The cover layer 156a may include or be comprised of TiN, taN, alO _x Etc., and may be formed by any suitable deposition technique, such as PVD, CVD, etc. In one embodiment, the cap layer 156a is TiN.

Next, a hard mask layer 157a is formed on the capping layer 156 a. In some embodiments, the hard mask layer 157a is deposited to a height above the top surface of the first additive layer 154 on the dielectric member 127. The hard mask layer 157a is in contact with the cap layer 156a and the exposed first additive layer 154 over the dielectric member 127. The hard mask layer 157a and the capping layer 156a prevent the first additive layer 154 from being oxidized when transferring between different process chambers. The hard mask layer 157a may include or be formed of a silicon-containing material or an oxygen-containing material, such as Si, siN, siO ₂ SiCN, siCON, etc., or combinations thereof, and may be formed by any suitable deposition technique, such as CVD, PVD, ALD, etc. In one embodiment, the hard mask layer 157a is a silicon layer, such as amorphous silicon.

Thereafter, the semiconductor device structure 100 is subjected to a heat treatment 158a (e.g., a rapid thermal anneal or a laser anneal process). The heat treatment 158a causes dopants (e.g., metal ions) in the first additive layer 154 to diffuse into the first HK dielectric layer 152 and the IL 150. Typically, the dopants are distributed over the first HK dielectric layer 152 and IL 150 in both the lateral and vertical directions. In some embodiments, the heat treatment 158a is performed such that dopants in the first additive layer 154 diffuse through the first HK dielectric layer 152 and into portions of the IL 150. The heat treatment 158a provides a thermal driving force to pull the dopants from the first additive layer 154. By adjusting the elevated temperature and residence time of the heat treatment, the target dopant may be positioned at a desired diffusion depth in the first HK dielectric layer 152 and IL 150, thereby utilizing N-type or P-type crystals at regions 153, 155Shift of threshold voltage of tube to control flatband voltage (V _FB )。

The first HK dielectric layer 152 after the heat treatment may have a concentration gradient profile having a first dopant concentration at and/or near the interface 159-1 (fig. 19-1) of the first additive layer 154 and the first HK dielectric layer 152 and a second dopant concentration at and/or near the interface 159-2 of the IL 150 and the first HK dielectric layer 152. In some embodiments, the second dopant concentration is greater than the first dopant concentration. In some embodiments, the second dopant concentration is less than the first dopant concentration. The region between interface 159-1 and interface 159-2 has a dopant concentration that varies gradually from a first dopant concentration to a second dopant concentration along the thickness of the region. Likewise, the IL 150 after heat treatment may have a concentration gradient profile with a third dopant concentration at and/or near the interface 159-2 of the IL 150 and the first HK dielectric layer 152 and a fourth dopant concentration at and/or near the interface 159-3 of the IL 150 and the first semiconductor layer 106. In some embodiments, the third dopant concentration is greater than the fourth dopant concentration. In some embodiments, the third dopant concentration is less than the fourth dopant concentration. The region between interface 159-2 and interface 159-3 has a dopant concentration that varies gradually along the thickness of the region from a third dopant concentration to a fourth dopant concentration. Although not discussed, the dopant profiles mentioned herein may be equally applicable to the first HK dielectric layer 152 and IL 150 disposed over the dielectric member 127 and the well portion 116 of the substrate 101. By controlling the degree of penetration of dopants in the first HK dielectric layer 152 and IL 150, the threshold voltages of the N-type or P-type transistors in the regions 153, 155 are adjustable.

In one exemplary embodiment, the heat treatment 158a is performed such that a majority of the dopants (e.g., metal ions) accumulate at and/or near the interface 159-3 of the IL 150 and the first semiconductor layer 106. Fig. 19-1 and 19-2 illustrate enlarged views of portions of semiconductor device structure 100 showing layers having dopant profiles after thermal treatment 158a, according to an example embodiment. As shown in fig. 19-1 and 19-2, dopant atoms (e.g., zn ions) diffuse to due to the heat treatment 158aIn the IL 150 and reacts with the IL 150 to form a modified region 150a of the IL 150. The modified region 150a of the IL 150 can extend from the interface 159-3 to a thickness T1 in the IL 150. In one embodiment, the thickness T1 is about 10% to about 60% of the thickness of the IL 150. The remainder of the IL 150, other than the modified region 150a of the IL 150, has a smaller dopant concentration and is indicated as region 150b when compared to the modified region 150a of the IL 150. In the present invention, the modified region 150a of the IL 150 may be referred to as a threshold voltage (V _th ) Adjusting layer 160-1a. After heat treatment 158a, first additive layer 154 has a reduced dopant atomic concentration and becomes modified first additive layer 154a.

In another exemplary embodiment, the heat treatment 158a is performed such that a majority of the dopants (e.g., metal ions) accumulate at and/or near the second interface 159-2 of the IL 150 and the first HK dielectric layer 152. Fig. 19-3 and 19-4 illustrate enlarged views of portions of the semiconductor device structure 100 showing a layer having dopant profile after a thermal treatment 158a, according to another example embodiment. As shown in fig. 19-3 and 19-4, due to the heat treatment 158a, dopant atoms (e.g., zinc ions) diffuse into the IL 150 and the first HK dielectric layer 152 and react with the IL 150 and the first HK dielectric layer 152 to form a modified region 150c of the IL 150 and a modified region 152a of the first HK dielectric layer 152. The modified region 150c of the IL 150 may extend from the interface 159-2 to a thickness T2 in the IL 150. In one embodiment, the thickness T2 is about 10% to about 55% of the thickness of the IL 150. The remainder of the IL 150, except for the modified region 150c of the IL 150, has a smaller dopant concentration and is indicated as region 150d.

Likewise, modified region 152a of first HK dielectric layer 152 may extend from interface 159-2 to a thickness T3 in first HK dielectric layer 152. In one embodiment, thickness T3 is about 5% to about 35% of the thickness of first HK dielectric layer 152. The remaining portion of the first HK dielectric layer 152, except for the modified region 152a of the first HK dielectric layer 152, has a smaller dopant concentration and is indicated as region 152b. Modified region 150c of IL 150 and modified region 152a of first HK dielectric layer 152 may be referred to as V in the present invention _th Adjusting layer 160-1b. Although the following FIGS. 20 to30D shows the use of V _th The semiconductor device structure 100 is illustrated with the adjustment layer 160-1b as an example, but V illustrated in fig. 19-1 and 19-2 is contemplated _th The adjustment layer 160-1a is equally applicable to various embodiments of the present invention.

In some embodiments, modified region 150c of IL150 and modified region 152a of first HK dielectric layer 152 may be IL150 and first HK dielectric layer 152 doped with metal ions from first additive layer 154. In some embodiments, modified region 150c of IL150 and modified region 152a of first HK dielectric layer 152 may be the reaction product of first additive layer 154 with IL150 and first HK dielectric layer 152, which may be a compound, composition, or mixture, depending on the thermal treatment used. In either case, modified region 150c of IL150 and modified region 152a of first HK dielectric layer 152 are formed to have a dopant concentration that is significantly higher than the dopant concentrations of IL150 and first HK dielectric layer 152. For example, the dopant concentration in modified region 150c of IL150 and modified region 152a of first HK dielectric layer 152 may be about 70% higher, such as about 85% -95% higher, than the dopant concentration in IL150 and first HK dielectric layer 152, respectively. After heat treatment 158a, first additive layer 154 has a reduced concentration of dopant atoms and becomes modified first additive layer 154a.

The heat treatment 158a may be performed in situ or ex situ and may be any type of anneal, such as a rapid thermal anneal, spike anneal, soak anneal, laser anneal, furnace anneal, or the like. The residence time of the heat treatment 158a may be about 1 microsecond to about 20 microseconds and at a temperature in the range of about 450 ℃ to about 1800 ℃, for example about 900 ℃ to about 1500 ℃. The heat treatment may be performed in a gaseous atmosphere, such as an oxygen-containing gas, a hydrogen-containing gas, an argon-containing gas, a helium-containing gas, or any combination thereof. Exemplary gases may include, but are not limited to, N ₂ 、NH ₃ 、O ₂ 、N ₂ O, ar, he, H, etc.

In fig. 20, the hard mask layer 157a, the capping layer 156a, and the modified first additive layer 154a are removed. The hard mask layer 157a, capping layer 156a, and modified first additive layer 154a may be removed using one or more etching processes, such asSuch as dry etching, wet etching, or a combination thereof. In some embodiments, the hard mask layer 157a, the capping layer 156a, and the modified first additive layer 154a are removed by one or more wet etching processes. The wet etch process may be an APM process (which includes at least water (H) ₂ O), ammonium hydroxide (NH) ₄ OH) and hydrogen peroxide (H ₂ O ₂ ) HPM process (which includes at least H) ₂ O、H ₂ O ₂ And hydrogen chloride (HCl)), SPM processes (also known as piranha cleaning), which include at least H ₂ O ₂ And sulfuric acid (H) ₂ SO ₄ ) Or any combination thereof. The semiconductor device structure 100 may be further cleaned with hot deionized water to remove any residues of the modified first additive layer 154a. One or more etching processes and wet cleaning processes may be performed under real-time monitoring to avoid unnecessary damage to the first HK dielectric layer 152. After removing the hard mask layer 157a and the cap layer 156a, the openings 151 (fig. 15A, 15B) over the regions 153, 155 are exposed, thereby exposing the modified first additive layer 154a.

In fig. 21, a second HK dielectric layer 161 is formed on the first HK dielectric layer 152. The second HK dielectric layer 161 may be deposited using the same materials as the first HK dielectric layer 152 and in the same manner as discussed above with respect to fig. 17. In one embodiment, the first HK dielectric layer 152 and the second HK dielectric layer 161 comprise or consist of hafnium oxide (HfO ₂ ) Is prepared. The second HK dielectric layer 161 may have the same thickness as the first HK dielectric layer 152. However, a greater or lesser thickness of the second HK dielectric layer 161 is also contemplated. In the present invention, the first HK dielectric layer 152 and the second HK dielectric layer 161 may be referred to as an HK dielectric stack 163. The second HK dielectric layer 161 confines the inserted additive (i.e., dopant atoms from the first additive layer 154) near the interface of the IL 150 and the first HK dielectric layer 152. In addition to the thickness of the first HK dielectric layer 152, the additional thickness provided by the second HK dielectric layer 161 ensures that dopants from the subsequent second additive layer 147 have sufficient space to be thermally driven and distributed at the desired regions of the HK dielectric stack 163.

In some embodiments, the second HK dielectric layer 161 comprises a layer that is the same as the first HK dielectric layer152 of a different material. For example, in one embodiment, the first HK dielectric material layer 152 includes HfO _x And the second HK dielectric layer 161 comprises LaO _x The method comprises the steps of carrying out a first treatment on the surface of the In one embodiment, the first HK dielectric material layer 152 includes HfO _x And the second HK dielectric layer 161 comprises AlO _x The method comprises the steps of carrying out a first treatment on the surface of the In one embodiment, the first HK dielectric material layer 152 comprises LaO _x And the second HK dielectric material layer 161 comprises AlO _x The method comprises the steps of carrying out a first treatment on the surface of the In one embodiment, the first HK dielectric material layer 152 includes HfO _x And the second HK dielectric material layer 161 comprises LaO _x And AlO _x The method comprises the steps of carrying out a first treatment on the surface of the In one embodiment, the first HK dielectric material layer 152 comprises LaO _x And the second HK dielectric material layer 161 includes HfO _x And AlO _x The method comprises the steps of carrying out a first treatment on the surface of the In one embodiment, the first HK dielectric material layer 152 comprises AlO _x And the second HK dielectric material layer 161 includes HfO _x And LaO _x . These embodiments may be used for P-type or N-type nanoflake transistors at regions 153, 155 and may be used in conjunction with the embodiments shown in fig. 23-1 through 23-8, as will be discussed in more detail below.

In fig. 22, a second additive layer 147 is formed on the second HK dielectric layer 161. The second additive layer 147 surrounds the first semiconductor layer 106 and is located over the well portion 116 of the substrate 101. The second additive layer 147 may include a dopant having a positive polarity or a negative polarity depending on the conductivity type of the nano-sheet transistor. In the embodiment shown in fig. 22, the nanoplatelet transistor at region 153 is designated an N-type FET and the nanoplatelet transistor at region 155 is designated a P-type FET. In this case, the second additive layer 147 may include a material having a dopant of negative polarity. The second additive layer 147 serves as a source for dopants introduced into the first HK dielectric layer 152 and the second HK dielectric layer 161. As with the first additive layer 154, dopants (e.g., metal ions) from the second additive layer 147 may be controlled to be distributed in the first HK dielectric layer 152 and the second HK dielectric layer 161 to adjust the threshold voltages of the N-type or P-type transistors in the regions 153, 155. V (V) _th Adjustment layer 160-1b (or, in some embodiments, V _th Adjusting the concentration and concentration of dopant atoms in layer 160-1 a)The concentration of dopant atoms to be distributed in the first HK dielectric layer 152 and the second HK dielectric layer 161, and the respective V _th The thickness of the adjustment layer may be configured such that V of the nano-sheet transistor in the N-type region _FB And V of the nanoflake transistor in the P-type region _FB At a ratio of about 1 to about 1.2. In various embodiments, the concentration of the dopant in the second additive layer 147 may be in the range from about 10ppm to about 400 ppm. In other words, the concentration of the dopant in the second additive layer 147 may be at about 1E10 ¹⁷ Atoms/cm ^-3 To about 5E10 ²¹ Atoms/cm ^-3 Within a range of (2).

In some embodiments, the second additive layer 147 may comprise a material that inherently has a negative polarity. Exemplary materials may include, but are not limited to, lanthanum-containing materials, magnesium-containing materials, yttrium-containing materials, gadolinium-containing materials, and the like. In some embodiments, the second additive layer 147 may also include oxygen. In this case, the second additive layer 147 may include, but is not limited to, lanthanum oxide (La ₂ O ₃ ) Magnesium oxide (MgO), yttrium oxide (Y) ₂ O ₃ ) Gadolinium oxide (Gd) ₂ O ₃ ) Etc. In one exemplary embodiment, the second additive layer 147 is La ₂ O ₃ . The second additive layer 147 may be formed by ALD, ALE, CVD or any suitable conformal deposition technique. In some embodiments, the second additive layer 147 may have a thickness of about 0.1nm to about 1 nm. Greater or lesser thicknesses are contemplated, depending on the threshold voltage requirements of the device.

In fig. 23, a capping layer 156b is formed to cover the nanoplatelets transistors at the regions 153, 155. A hard mask layer 157b is then formed on the cap layer 156 b. The cap layer 156b and the hard mask layer 157b may comprise the same materials as the cap layer 156a and the hard mask layer 157a, respectively, and may be deposited in a similar manner to those discussed above with respect to fig. 19. Thereafter, a heat treatment 158b is performed such that dopants (e.g., metal ions) in the second additive layer 147 diffuse into the HK dielectric stack 163. The heat treatment 158b may be the same or similar to the heat treatment 158a and may be configured to achieve a desired distribution profile of dopants in the first HK dielectric layer 152 and the second HK dielectric layer 161. For example, in some embodiments, the heat treatment 158b may be performed such that dopants (e.g., la ions) diffuse into the second HK dielectric layer 161. In some embodiments, the dopant diffuses through the second HK dielectric layer 161 and into portions of the first HK dielectric layer 152. In some embodiments, dopants diffuse through second HK dielectric layer 161 and first HK dielectric layer 152 and accumulate at and/or near interface 159-2. The threshold voltage of the N-type or P-type transistors in regions 153, 155 can be further adjusted by controlling the degree of penetration of dopants in HK dielectric stack 163.

The second HK dielectric layer 161 after the heat treatment 158b may have a concentration gradient profile with a first dopant concentration at and/or near the interface 159-4 of the second additive layer 147 and the second HK dielectric layer 161 and a second dopant concentration at the interface 159-2 of the first HK dielectric layer 161 and the IL 150. In some embodiments, the first dopant concentration is greater than the second dopant concentration. In some embodiments, the second dopant concentration is greater than the first dopant concentration. The region between interface 159-5 and interface 159-2 has a dopant concentration that varies gradually from a first dopant concentration to a second dopant concentration along the thickness of the region. Fig. 23-1 and 23-2 illustrate enlarged views of portions of the semiconductor device structure 100 showing a layer having dopant profile after a heat treatment 158b, according to one example embodiment. Due to the heat treatment 158b, dopant atoms (e.g., la ions) diffuse into the second HK dielectric layer 161 and react with the second HK dielectric layer 161 to form modified regions 161a of the second HK dielectric layer 161. The remaining portion of the second HK dielectric layer 161, except for the modified region 161a of the second HK dielectric layer 161, has a smaller dopant concentration and is indicated as region 161b. Modified region 161a of second HK dielectric layer 161 serves as V _th Adjust the layers and may be in combination with other V discussed in this invention _th Adjusting layer (e.g. V _th The tuning layers 160-1a, 160-1b, and 160-1 c) work together to effectively tune the flatband voltage (V) of the N-type or P-type FET at the regions 153, 155 _FB )。

HK dielectric stack 163 may have a thickness T4 measured from interface 159-5 to interface 159-2, and modified region 161a of second HK dielectric layer 161 may have a thickness T5. In some embodiments, thickness T5 is about 10% to about 60% of thickness T4, e.g., about 25% to about 45% of thickness T4. The modified region 161a of the second HK dielectric layer 161 may be the second HK dielectric layer 161 doped with metal ions (e.g., la ions) from the second additive layer 147. In some embodiments, modified region 161a of second HK dielectric layer 161 may be a reaction product of second additive layer 147, which may be a compound, composition, or mixture, depending on the heat treatment used. In either case, the modified region 161a of the second HK dielectric layer 161 has a dopant concentration that is significantly higher than the dopant concentration of the second HK dielectric layer 147. For example, the dopant concentration in modified region 161a of second HK dielectric layer 161 may be about 70% higher than the dopant concentration in second HK dielectric layer 147, such as about 85% -95% higher. After heat treatment 158b, second additive layer 147 has a reduced concentration of dopant atoms and becomes modified second additive layer 147a.

Fig. 23-3 and 23-4 illustrate enlarged views of portions of the semiconductor device structure 100 showing a layer having dopant profile after a heat treatment 158b, according to another example embodiment. The embodiment of fig. 23-3 and 23-4 is similar to the embodiment of fig. 23-1 and 23-2, except that a majority of the dopant (e.g., metal ions) accumulates at and/or near interface 159-5. Dopants (e.g., la ions) from the second additive layer 147 react with the upper portion of the first HK dielectric layer 152 and the lower portion of the second HK dielectric layer 161 to form a modified region 152c of the first HK dielectric layer 152 and a modified region 161c of the second HK dielectric layer 161, respectively. The remaining portion of the first HK dielectric layer 152, except for the modified region 152c of the first HK dielectric layer 152, has a smaller dopant concentration and is indicated as 152d. The remaining portion of the second HK dielectric layer 161, except for the modified region 161c of the second HK dielectric layer 161, has a smaller dopant concentration and is indicated as 161d. For example, the dopant concentration in modified region 152c of first HK dielectric layer 152 and modified region 161c of second HK dielectric layer 161 may be about 70%, such as high, higher than the dopant concentration in first HK dielectric layer 152 and second HK dielectric layer 161, respectively About 85% -95%. In the present invention, the modified region 152c of the first HK dielectric layer 152 and the modified region 161c of the second HK dielectric layer 161 may be referred to as a threshold voltage (V _th ) Adjusting layer 160-1c. In some embodiments, V _th Adjustment layer 160-1c may have a thickness T6, with thickness T6 being about 10% to about 60% of thickness T4, such as about 25% to about 45% of thickness T4.

Fig. 23-5 and 23-6 illustrate enlarged views of portions of the semiconductor device structure 100 showing a layer having dopant profile after a heat treatment 158b, according to another example embodiment. The embodiment of FIGS. 23-5 and 23-6 is substantially identical to the embodiment of FIGS. 23-3 and 23-4, except that no V is formed _th The adjustment layer 160-1a is instead formed by V _th The adjustment layer 160-1b is replaced as discussed above with respect to fig. 19-3 and 19-4. In this embodiment, the second HK dielectric layer 152 has an upper portion (e.g., modified region 152c with dopants from the second additive layer 147), a lower region (e.g., modified region 152a with dopants from the first additive layer 154), and an intermediate region (e.g., region 152 b) with dopants from the first and second additive layers 154 and 147.

Fig. 23-7 and 23-8 illustrate enlarged views of portions of the semiconductor device structure 100 showing a layer having dopant profile after a heat treatment 158b, in accordance with yet another exemplary embodiment. The embodiments of FIGS. 23-7 and 23-8 are substantially identical to the embodiments of FIGS. 23-5 and 23-6, except that no V is formed _th The tuning layer 160-1c is replaced with a modified region 161a of the second HK dielectric layer 161, as discussed above with respect to fig. 23-1 and 23-2. In this embodiment, HK dielectric stack 163 has an upper region adjacent interface 159-4 of second additive layer 147 and second HK dielectric layer 161 (i.e., modified region 161a of second HK dielectric layer 161) and a lower region adjacent interface 159-2 of first HK dielectric layer 161 and IL 150 (i.e., modified region 152a of first HK dielectric layer 152). The upper region includes a majority of the dopant (e.g., la ions) from the second additive layer 147, and the lower region includes a majority of the dopant from the first additive layer 154 (e.g.,zn ion). The intermediate region 163m between the interface 159-4 and the interface 159-2 may include a small amount of dopant from the first additive layer 154 and the second additive layer 147, and the concentration of dopant in the intermediate region 163m (dopant from the first additive layer 154 or the second additive layer 147) is less than the concentration of dopant in the upper and lower regions. While the dopants are distributed over HK dielectric stack 163 in both the lateral and vertical directions, the concentration of dopants from second additive layer 147 in intermediate region 163m gradually decreases in a direction away from interface 159-4, and the concentration of dopants from first additive layer 154 in intermediate region 163m gradually decreases in a direction away from interface 159-2. In most cases, the upper and lower regions of HK dielectric stack 163 have a dopant concentration that is significantly greater (e.g., about 80-95% higher) than the dopant concentration in middle region 163 m.

In fig. 24, the hard mask layer 157b, the capping layer 156b, and the modified second additive layer 147a are removed. The hard mask layer 157b, capping layer 156b, and modified second additive layer 147a may be removed in a similar manner to those discussed above with respect to fig. 20. Although the semiconductor device structure 100 in fig. 24-30D is based on the embodiments of fig. 23-7 and 23-8, it is contemplated that the layer arrangements of fig. 23-1 through 23-6 are equally applicable to the various embodiments of the present invention. 23-7 and 23-8, after removal of hard mask layer 157b, capping layer 156b, and modified second additive layer 147a, modified region 161a of second HK dielectric layer 161 is exposed, thereby producing at least two V embedded therein _th Adjustment layers (e.g., modified regions 161a and V of second HK dielectric layer 161) _th The HK dielectric stack 163 and IL 150 of layer 160-1 b) are tuned. This is advantageous for miniaturization of metal gate structures because typical metal gate structures may require multiple metal layers between the HK dielectric layer and the work function metal layer (or gate electrode layer) to adjust the threshold voltage for N-type/P-type FETs. Using the inventive methods discussed herein, dopant atoms having positive or negative polarity diffuse into certain regions (rather than the entire thickness) of IL 150 and/or HK dielectric stack 163 and are positioned at IL 150 and +. Or HK dielectric stack 163 to meet different threshold voltage requirements. Thus, there is no need to use multiple metal layers between the HK dielectric layer and the work function metal layer, which saves additional space for post work function metal filling. In addition, since dopant atoms are diffused into the HK dielectric layer by a thermal drive-in process rather than a multi-layer stack process, the formation of the HK dielectric layer (e.g., la doped HfO ₂ ) Surface defects generated during the process due to metal segregation. Thus, threshold voltage drop is avoided.

In fig. 25, a P-type work function metal (or P-metal) 165 is formed over the modified region 161a of the second HK dielectric layer 161. The P-type work function metal 165 may be deposited such that the nanoplatelet transistors at least at regions 153, 155 are immersed in the P-type work function metal 165. In some embodiments, the P-type work function metal 165 is deposited to a height above the top surface of the modified region 161a of the second HK dielectric layer 161 above the dielectric member 127. The P-type work function metal 165 may be formed by ALD, PVD, CVD, electroplating, or other suitable methods. Exemplary P-type work function metals may include, but are not limited to TiN, taN, ru, mo, al, WN, tiSiN, tiTaN, tiAlN, WCN, zrSi ₂ 、MoSi ₂ 、TaSi ₂ 、NiSi ₂ Or other suitable P-type work function material or any combination thereof. The P-type work function metal 165 may include multiple layers (e.g., composite layers). In one embodiment, the P-type work function metal is TiN.

In some embodiments, the P-type work function metal 165 may completely fill the openings 151 (fig. 24) between adjacent first semiconductor layers 106 of the nano-sheet transistor at the region 155, while the openings 151 between adjacent first semiconductor layers 106 of the nano-sheet transistor at the region 153 may not be completely filled due to loading effects. In this case, a void 177 may be formed in the P-type work function metal 165 at the region 153.

In fig. 26, a patterned resist layer 167 is formed to cover the P-type FET, such as the nano-sheet transistor at region 155, and not the dielectric member 127 and the N-type FET, such as the nano-sheet transistor at region 153. The patterned resist layer 167 protects the P-type work function metal 165 and the nano-sheet transistors at region 155, thereby removing the P-type work function metal 165 and the nano-sheet transistors at region 153 over the dielectric member 127. The patterned resist layer 167 may be formed by first forming a blanket layer over the semiconductor device structure 100, followed by patterning and etching processes to remove portions of the blanket layer at selected regions to form the patterned resist layer 167. The patterned resist layer 167 may be any suitable masking material, such as a photoresist layer, a BARC (bottom anti-reflective coating) layer, a SOG (spin on glass) layer, or a SOC (spin on carbon) layer, and may be deposited by spin coating or any suitable deposition technique. Once patterned resist layer 167 is formed, P-type work function metal 165 over dielectric feature 127 and the nano-sheet transistor at region 153 are removed. The P-type work function metal 165 may be removed using any suitable process, such as dry etching, wet etching, or a combination thereof. The removal process may be a selective etching process that removes the P-type work function metal 165 but does not remove the modified region 161a of the second HK dielectric layer 161. In some embodiments, due to the narrower spacing, portions of the P-type work function metal 165 may remain between adjacent first semiconductor layers 106 of the nanoplate transistor at region 153.

In fig. 27, an N-type work function metal 166 is formed over modified region 161a of second HK dielectric layer 161 not covered by patterned resist layer 167. The N-type work function metal 166 may be deposited such that the nanoplatelet transistor at least at region 153 is immersed in the N-type work function metal 166. In some embodiments, the N-type work function metal 166 is deposited to a height above the top surface of the modified region 161a of the second HK dielectric layer 161 above the dielectric member 127. The N-type work function metal 166 may be formed by ALD, PVD, CVD, electroplating, or other suitable methods. The N-type work function metal 166 may include or be formed of Ti, ag, taAl, taAlC, tiAlN, taC, taCN, taSiN, tiAl, tiTaN, mn, zr, other suitable N-type work function materials, or any combination thereof. The N-type work function metal 166 may include multiple layers (e.g., composite layers). In one embodiment, the N-type work function metal 166 is TiAl. In some embodiments, both the P-type work function metal 165 and the N-type work function metal 166 are disposed between adjacent first semiconductor layers 106 of the nanoplate transistor at region 153, as shown in fig. 27.

In fig. 28, portions of the P-type work function metal 165 and the N-type work function metal 166 are recessed, and a metal layer 169 is formed on the recessed P-type work function metal 165 and N-type work function metal 166. A first etch back process may be performed on the N-type work function metal 166 to recess the N-type work function metal 166, while the P-type work function metal 165 is covered by a patterned resist layer 167. The first etch back process uses an etchant that selectively removes the N-type work function metal 166 but does not remove the P-type work function metal 165 and the modified region 161a of the second HK dielectric layer 161. Portions of the patterned resist layer 167 may be removed during the first etch-back process. The N-type work function metal 166 may be recessed such that the top surface 166t of the N-type work function metal 166 is located at a level near or slightly below the top surface 121t of the dielectric material 121. Next, the patterned resist layer 167 is removed using, for example, an ashing process or other suitable removal process. A patterned resist layer (not shown) may be formed over the N-type work function metal 166 to protect the N-type work function metal 166 during subsequent processing. Then, a second etch back process may be performed on the exposed P-type work function metal 165 to recess the P-type work function metal 165. The second etch back process uses an etchant that selectively removes the P-type work function metal 165 but does not remove the N-type work function metal 166 and the modified region 161a of the second HK dielectric layer 161. The P-type work function metal 165 may be recessed such that the top surface 165t of the P-type work function metal 165 is located at a level near or slightly below the top surface 121t of the dielectric material 121. The top surface 166t of the N-type work function metal 166 at the region 153 and the top surface of the modified region 161a of the second HK dielectric layer 161 are at similar heights due to the first and second etch-back processes, and the top surface 165t of the P-type work function metal 165 at the region 155 and the top surface of the modified region 161a of the second HK dielectric layer 161 are at similar heights. The patterned resist layer over the N-type work function metal 166 is then removed.

Thereafter, a metal layer 169 is formed on the dielectric member 127, the recessed P-type work function metal 165 and the N-type work function metal 166. A metal layer 169 is deposited to a height above the top surface of ILD layer 164. The metal layer 169 may be a conductive material, such as a metal. Suitable materials may include, but are not limited to W, ru, mo, co, ni, ti, ta, cu, al and the like. In one embodiment, metal layer 169 comprises fluorine-free tungsten (FFW). The metal layer 169 may be formed by CVD, PVD, ALD, electroplating, or other suitable deposition method. In some embodiments, the metal layer 169 is a continuous layer that contacts the P-type work function metal 165, the N-type work function metal 166, and the modified region 161a of the second HK dielectric layer 161 at the regions 153, 155 and over the dielectric member 127. In some embodiments, the metal layer 169 may have a thickness of about 5nm to about 45 nm. If the thickness of the metal layer 169 is less than 5nm, the work function of the metal layer 169 may be lost. On the other hand, if the thickness of the metal layer 169 is greater than 45nm, there may be a loss of growth selectivity when filling metal (e.g., tungsten) in the gate contact opening at a later stage.

Fig. 29A-29D are perspective views of one of the stages of fabricating the semiconductor device structure 100, taken along the cross-sections A-A, B-B, C-C, and D-D of fig. 8, in accordance with some embodiments. Fig. 30A-30D are perspective views of one of the stages of fabricating the semiconductor device structure 100, taken along the cross-sections A-A, B-B, C-C, and D-D of fig. 8, in accordance with some embodiments. In fig. 29A-29D, after forming the metal layer 169, a planarization process, such as a CMP process, is performed on the semiconductor device structure 100. The planarization process removes the excess portion of metal layer 169 until the top surface of ILD layer 164 is exposed. After the planarization process, the top surfaces of metal layer 169, modified regions 161a of second HK dielectric layer 161, HK dielectric stack 163, gate spacers 138, CESL 162, and ILD layer 164 are substantially coplanar.

Fig. 29A-1 and 29D-1 are enlarged views of portions of the semiconductor device structure 100 in fig. 29A and 29D, respectively, showing the arrangement of layers between adjacent first semiconductor layers 106 according to the embodiment of fig. 28. Fig. 29A-2 and 29D-2 are enlarged views of portions of the semiconductor device structure 100 in fig. 29A and 29D, respectively, showing the arrangement of layers between adjacent first semiconductor layers 106 according to the embodiment of fig. 23-1. Fig. 29A-1, 29A-2 and 29D-1, 29D-2 show that portions of the first semiconductor layer 106 at regions 153, 155, respectively, are surrounded by layers as shown in the embodiments of fig. 28 and 23-1. It is contemplated that the various embodiments of fig. 23-3 and 23-4 through 23-5 and 23-6, and in particular the layers between interfaces 159-4 and 159-3, may be used alone or in combination to adjust the threshold voltages of the N-type and/or P-type FETs at regions 153, 155.

In fig. 30A-30D, one or more Metal Gate Etch Back (MGEB) processes are performed on the N-type and P-type FETs at regions 153, 155. The MGEB process is performed such that the metal layer 169, the modified region 161a of the second HK dielectric layer 161, and the top surface of the HK dielectric stack 163 are recessed to a level below the top surface of the gate spacer 138. In some embodiments, the gate spacers 138 are also recessed to a level below the top surface of the CESL 162, as shown in fig. 30A, 30D. A self-aligned contact layer 173 is formed over the metal layer 169, the modified region 161a of the second HK dielectric layer 161, and the HK dielectric stack 163 between the gate spacers 138. The self-aligned contact layer 173 may be a dielectric material having etch selectivity with respect to the gate spacer 138. In some embodiments, the self-aligned contact layer 173 comprises silicon nitride. The self-aligned contact layer 173 may be used to define a self-aligned contact region for the semiconductor device structure 100.

After forming the self-aligned contact layer 173, a contact opening is formed through ILD layer 164 and CESL 162 (fig. 29A and 29D) to expose epitaxial S/D feature 146. A silicide layer 178 is then formed on the epitaxial S/D features 146 to conductively couple the epitaxial S/D features 146 to subsequently formed S/D contacts 176. Silicide layer 178 may be formed by depositing a metal source layer over epitaxial S/D features 146 and performing a rapid thermal annealing process. The metal source layer includes a conductive layer selected from W, co, ni, ti, mo and Ta or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride, and tantalum nitride. During the rapid annealing process, the portion of the metal source layer that is located over the epitaxial S/D features 146 reacts with the silicon in the epitaxial S/D features 146 to form the silicide layer 178. The unreacted portion of the metal source layer is then removed.

After the silicide layer 178 is formed, a conductive material is formed in the contact openings and the S/D contacts 176 are formed. The conductive material may be made of a material including one or more of Ru, mo, co, ni, W, ti, ta, cu, al, tiN and TaN. Although not shown, a barrier layer (e.g., tiN, taN, etc.) may be formed on the sidewalls of the contact openings prior to forming the S/D contacts 176. A planarization process, such as CMP, is then performed to remove the excess deposition of contact material until the top surface of the self-aligned contact layer 173 is exposed.

It should be appreciated that the semiconductor device structure 100 may undergo further Complementary Metal Oxide Semiconductor (CMOS) and/or back-end-of-line (BEOL) processes to form various features such as transistors, contacts/vias, interconnect metal layers, dielectric layers, passivation layers, and the like. The semiconductor device structure 100 may also include backside contacts (not shown) on the backside of the substrate 101 by flipping the semiconductor device structure 100, removing the substrate 101, and selectively connecting the source or drain components/terminals of the epitaxial S/D components 146 to the backside power rails (e.g., positive voltage VDD or negative voltage VSS) through the backside contacts. Depending on the application, the source or drain features/terminals of the epitaxial S/D features 146 and the metal layer 169 may be connected to a front side power supply.

The various embodiments or examples described herein provide a number of advantages over the prior art. According to embodiments of the present invention, during a replacement gate process, one or more additive layers of dopants having positive or negative polarity are deposited over an Interfacial Layer (IL)/HK dielectric layer, and dopant atoms diffuse into and are positioned at certain regions of the IL and/or HK dielectric layer (not the entire thickness) to adjust the threshold voltage for the P-type and/or N-type work function layers. With this approach, multiple metal layers are not required between the HK dielectric layer and the subsequent work function metal layer, which saves additional space for the post work function metal fill. In addition, since dopant atoms are diffused into the HK dielectric layer by a thermal drive-in process rather than a multi-layer stack process, the formation of the HK dielectric layer (e.g., la doped HfO ₂ ) Surface defects generated during the process due to metal segregation. Thus, threshold voltage drop is avoided.

An embodiment is a semiconductor device structure. The structure comprises: one or more semiconductor layers; an interfacial layer surrounding at least one of the one or more semiconductor layers; work function metal arranged above the interface layer; and a high-K (HK) dielectric layer disposed between the interfacial layer and the work function metal. The HK dielectric layer includes a first dopant region adjacent to a first interface of the HK dielectric layer and the interface layer, wherein the first dopant region includes a first dopant having a first polarity. The HK dielectric layer also includes a second dopant region adjacent to the second interface of the HK dielectric layer and the work function metal, wherein the second dopant region includes a second dopant having a second polarity opposite the first polarity.

Another embodiment is a semiconductor device structure. The structure comprises: a dielectric member; one or more first semiconductor layers disposed adjacent to the first side of the dielectric member, wherein each of the one or more first semiconductor layers has a first width. The structure comprises: one or more second semiconductor layers disposed adjacent to the second side of the dielectric member, wherein each of the one or more second semiconductor layers has a second width that is greater than the first width. The structure also comprises: an interface layer surrounding each of the one or more first semiconductor layers and the one or more second semiconductor layers, wherein the interface layer comprises a first dopant region adjacent to a first interface of the interface layer and the first semiconductor layer and a second interface of the interface layer and the second semiconductor layer, respectively, and wherein the first dopant region comprises a first dopant having a first polarity. The structure further comprises: and a first work function metal disposed over the interfacial layer surrounding the at least one first semiconductor layer and the one second semiconductor layer, wherein the first work function metal has a first conductivity type. The structure further comprises: and a second work function metal disposed over the interfacial layer surrounding the at least one second semiconductor layer, wherein the second work function metal has a second conductivity type opposite to the first conductivity type. The structure also includes a high-K (HK) dielectric stack including a first HK dielectric layer including a second dopant region in contact with the first work function metal, wherein the second dopant region includes a second dopant having a second polarity opposite the first polarity. The HK dielectric stack also includes a second HK dielectric layer disposed between and in contact with the first HK dielectric layer and the interfacial layer.

Further embodiments are methods for forming semiconductor device structures. The method comprises the following steps: forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; forming a sacrificial gate structure over the fin structure; forming source/drain features on opposite sides of the sacrificial gate structure, the source/drain features in contact with the first plurality of semiconductor layers of the fin structure; removing portions of the plurality of second semiconductor layers to expose portions of each of the plurality of first semiconductor layers; surrounding the interfacial layer around the exposed portion of each of the plurality of first semiconductor layers; depositing a first high-K (HK) dielectric layer on the interfacial layer; depositing a first additive layer on the first HK dielectric layer, wherein the first additive layer comprises a first dopant having a first polarity; subjecting the fin structure to a first heat treatment; removing the first additive layer to expose the first HK dielectric layer; depositing a second HK dielectric layer over the first HK dielectric layer; depositing a second additive layer on the second HK dielectric layer, wherein the second additive layer includes a second dopant having a second polarity opposite the first polarity; subjecting the fin structure to a second heat treatment; and removing the second additive layer.

Some embodiments of the application provide a semiconductor device structure comprising: one or more semiconductor layers; an interfacial layer surrounding at least one of the one or more semiconductor layers; work function metal arranged above the interface layer; and a high-K (HK) dielectric layer disposed between the interfacial layer and the work function metal, comprising; a first dopant region adjacent to a first interface of the high-K dielectric layer and the interface layer, wherein the first dopant region comprises a first dopant having a first polarity; and a second dopant region adjacent to a second interface of the high-K dielectric layer and the work function metal, wherein the second dopant region comprises a second dopant having a second polarity opposite the first polarity. In some embodiments, the high-K dielectric layer further comprises: and a third dopant region located between the first and second dopant regions, wherein the third dopant region includes first and second dopants, and a concentration of the first and second dopants in the third dopant region is less than a concentration of the first or second dopants in the first and second dopant regions. In some embodiments, the concentration of the first dopant in the third dopant region decreases gradually in a direction away from the first interface, and the concentration of the second dopant in the third dopant region decreases gradually in a direction away from the second interface. In some embodiments, the interface layer includes a fourth dopant region adjacent to the first interface, wherein the fourth dopant region includes the first dopant. In some embodiments, the first dopant in the fourth dopant region has a concentration that gradually decreases in a direction away from the first interface. In some embodiments, the first dopant comprises zinc and the second dopant comprises lanthanum. In some embodiments, the semiconductor device structure further comprises: a metal layer in contact with the work function metal and the first dopant region. In some embodiments, the metal layer comprises fluorine-free tungsten.

Other embodiments of the present application provide a semiconductor device structure comprising: a dielectric member; one or more first semiconductor layers disposed adjacent to the first side of the dielectric member, wherein each of the one or more first semiconductor layers has a first width; one or more second semiconductor layers disposed adjacent to the second side of the dielectric member, wherein each of the one or more second semiconductor layers has a second width greater than the first width; an interface layer surrounding each of the one or more first semiconductor layers and the one or more second semiconductor layers, wherein the interface layer comprises a first dopant region adjacent to a first interface of the interface layer and the first semiconductor layer and a second interface of the interface layer and the second semiconductor layer, respectively, and wherein the first dopant region comprises a first dopant having a first polarity; a first work function metal disposed over the interfacial layer surrounding at least one first semiconductor layer and one second semiconductor layer, wherein the first work function metal has a first conductivity type; a second work function metal disposed over the interfacial layer surrounding at least one second semiconductor layer, wherein the second work function metal has a second conductivity type opposite the first conductivity type; and a High K (HK) dielectric stack comprising: a first high-K dielectric layer comprising a second dopant region in contact with the first work function metal, wherein the second dopant region comprises a second dopant having a second polarity opposite the first polarity; and a second high-K dielectric layer disposed between and in contact with the first high-K dielectric layer and the interface layer. In some embodiments, the first high-K dielectric layer and the second high-K dielectric layer comprise the same material. In some embodiments, the first dopant is zinc, the second dopant is lanthanum, and the first high-K dielectric layer and the second high-K dielectric layer comprise hafnium oxide. In some embodiments, the first high-K dielectric layer and the second high-K dielectric layer comprise materials that are chemically different from each other. In some embodiments, the second dopant in the second dopant region has a concentration that gradually decreases in a direction away from the first work function metal. In some embodiments, the first dopant in the first dopant region has a concentration that gradually decreases in a direction away from the first interface and the second interface. In some embodiments, the semiconductor device structure further comprises: and a metal layer in contact with the first work function metal and the second work function metal. In some embodiments, the metal layer is also in contact with the second dopant region.

Still further embodiments of the present application provide a method for forming a semiconductor device structure, comprising: forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; forming a sacrificial gate structure over the fin structure; forming source/drain features on opposite sides of the sacrificial gate structure, the source/drain features in contact with the plurality of first semiconductor layers of the fin structure; removing portions of the plurality of second semiconductor layers to expose portions of each of the plurality of first semiconductor layers; surrounding the interfacial layer around the exposed portion of each of the plurality of first semiconductor layers; depositing a first high-K (HK) dielectric layer on the interfacial layer; depositing a first additive layer on the first high-K dielectric layer, wherein the first additive layer comprises a first dopant having a first polarity; subjecting the fin structure to a first heat treatment; removing the first additive layer to expose the first high-K dielectric layer; depositing a second high-K dielectric layer over the first high-K dielectric layer; depositing a second additive layer on the second high-K dielectric layer, wherein the second additive layer comprises a second dopant having a second polarity opposite the first polarity; subjecting the fin structure to a second heat treatment; and removing the second additive layer. In some embodiments, the method further comprises: after depositing a first additive layer on the first high-K dielectric layer, surrounding a capping layer around the first additive layer; and forming a hard mask layer on the cover layer. In some embodiments, the first additive layer comprises zinc oxide and the second additive layer comprises lanthanum oxide. In some embodiments, the first high-K dielectric layer and the second high-K dielectric layer are formed of different materials.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device structure, comprising:

one or more semiconductor layers;

an interfacial layer surrounding at least one of the one or more semiconductor layers;

work function metal arranged above the interface layer; and

a High K (HK) dielectric layer disposed between the interfacial layer and the work function metal, comprising;

a first dopant region adjacent to a first interface of the high-K dielectric layer and the interface layer, wherein the first dopant region comprises a first dopant having a first polarity; and

a second dopant region adjacent to a second interface of the high-K dielectric layer and the work function metal, wherein the second dopant region comprises a second dopant having a second polarity opposite the first polarity.

2. The semiconductor device structure of claim 1, wherein the high-K dielectric layer further comprises:

and a third dopant region located between the first and second dopant regions, wherein the third dopant region includes first and second dopants, and a concentration of the first and second dopants in the third dopant region is less than a concentration of the first or second dopants in the first and second dopant regions.

3. The semiconductor device structure of claim 2, wherein the concentration of the first dopant in the third dopant region decreases progressively in a direction away from the first interface and the concentration of the second dopant in the third dopant region decreases progressively in a direction away from the second interface.

4. The semiconductor device structure of claim 1, wherein the interface layer comprises a fourth dopant region adjacent to the first interface, wherein the fourth dopant region comprises the first dopant.

5. The semiconductor device structure of claim 4, wherein the first dopant in the fourth dopant region has a concentration that gradually decreases in a direction away from the first interface.

6. The semiconductor device structure of claim 1, wherein the first dopant comprises zinc and the second dopant comprises lanthanum.

7. The semiconductor device structure of claim 1, further comprising:

a metal layer in contact with the work function metal and the first dopant region.

8. The semiconductor device structure of claim 7, wherein the metal layer comprises fluorine-free tungsten.

9. A semiconductor device structure, comprising:

a dielectric member;

one or more first semiconductor layers disposed adjacent to the first side of the dielectric member, wherein each of the one or more first semiconductor layers has a first width;

one or more second semiconductor layers disposed adjacent to the second side of the dielectric member, wherein each of the one or more second semiconductor layers has a second width greater than the first width;

an interface layer surrounding each of the one or more first semiconductor layers and the one or more second semiconductor layers, wherein the interface layer comprises a first dopant region adjacent to a first interface of the interface layer and the first semiconductor layer and a second interface of the interface layer and the second semiconductor layer, respectively, and wherein the first dopant region comprises a first dopant having a first polarity;

A first work function metal disposed over the interfacial layer surrounding at least one first semiconductor layer and one second semiconductor layer, wherein the first work function metal has a first conductivity type;

a second work function metal disposed over the interfacial layer surrounding at least one second semiconductor layer, wherein the second work function metal has a second conductivity type opposite the first conductivity type; and

a High K (HK) dielectric stack comprising:

a first high-K dielectric layer comprising a second dopant region in contact with the first work function metal, wherein the second dopant region comprises a second dopant having a second polarity opposite the first polarity; and

and a second high-K dielectric layer disposed between and in contact with the first high-K dielectric layer and the interface layer.

10. A method for forming a semiconductor device structure, comprising:

forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked;

forming a sacrificial gate structure over the fin structure;

forming source/drain features on opposite sides of the sacrificial gate structure, the source/drain features in contact with the plurality of first semiconductor layers of the fin structure;

Removing portions of the plurality of second semiconductor layers to expose portions of each of the plurality of first semiconductor layers;

surrounding the interfacial layer around the exposed portion of each of the plurality of first semiconductor layers;

depositing a first high-K (HK) dielectric layer on the interfacial layer;

depositing a first additive layer on the first high-K dielectric layer, wherein the first additive layer comprises a first dopant having a first polarity;

subjecting the fin structure to a first heat treatment;

removing the first additive layer to expose the first high-K dielectric layer;

depositing a second high-K dielectric layer over the first high-K dielectric layer;

depositing a second additive layer on the second high-K dielectric layer, wherein the second additive layer comprises a second dopant having a second polarity opposite the first polarity;

subjecting the fin structure to a second heat treatment; and

and removing the second additive layer.