CN116631474A - Integrated circuit and method of forming the same - Google Patents

Abstract

An integrated circuit includes a plurality of SRAM cells. Each SRAM cell includes a first inverter having a first N-type transistor and a first P-type transistor vertically stacked in a first active region. The SRAM cell includes a second inverter cross-coupled with the first inverter, and the second inverter includes a second N-type transistor and a second P-type transistor vertically stacked in the second active region. The SRAM cell includes a mating contact that electrically connects the output of the first inverter to the input of the second inverter. The mating contact is at least partially located within the first active region. Embodiments of the application also disclose a method of forming an integrated circuit.

Description

Integrated circuit and method of forming the same

Technical Field

Embodiments of the present application relate to an integrated circuit and a method of forming the same.

Background

There is a continuing need to increase computing power in electronic devices, including smart phones, tablet computers, desktop computers, notebook computers, and many other types of electronic devices. Integrated circuits provide computing power for these electronic devices. One way to increase the computational power of an integrated circuit is to increase the number of transistors and other integrated circuit components that can be included in a given area of a semiconductor substrate.

Complementary Field Effect Transistors (CFETs) may be used to increase the density of transistors in integrated circuits. The CFET may include vertically stacked N-type transistors and P-type transistors. The gate electrodes of the N-type transistor and the P-type transistor may be electrically shorted together.

CFET may be utilized to form a Static Random Access Memory (SRAM) cell. While this may reduce the layout area of the cells relative to non-CFET layouts, each SRAM cell may still occupy a relatively large amount of area.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided an integrated circuit including: a first inverter including a first N-type transistor and a first P-type transistor vertically stacked; a second inverter including a second N-type transistor and a second P-type transistor vertically stacked; and a first docking contact electrically connecting the output of the first inverter to the input of the second inverter, wherein the first contact is at least partially located within a first active region associated with the first inverter.

According to another aspect of an embodiment of the present application, there is provided an integrated circuit including: a first N-type transistor including a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the first N-type transistor; a first P-type transistor vertically stacked with the first N-type transistor and including a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the first P-type transistor; a first pass gate transistor including a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the first pass gate transistor, wherein source/drain regions of the first pass gate transistor, source/drain regions of the first N-type transistor, and source/drain regions of the first P-type transistor are all electrically connected; a dummy transistor vertically stacked with the first transfer gate transistor and including a gate electrode; and a docking contact electrically connected to the source/drain region of the first N-type transistor and the gate electrode of the pseudo transistor and at least partially under or over the semiconductor nanostructure of the first pass gate transistor and at least partially under or over the source/drain region of the first N-type transistor.

According to yet another aspect of an embodiment of the present application, there is provided a method of forming an integrated circuit, comprising: forming a first inverter in a first active region of the integrated circuit, the first inverter including a first N-type transistor vertically stacked with a first P-type transistor; forming a second inverter in a second active region of the integrated circuit, the second inverter being cross-coupled with the first inverter and including a second N-type transistor vertically stacked with a second P-type transistor; forming a first transfer gate transistor vertically stacked with the first dummy transistor in the first active region; and forming a first butting contact in contact with the gate metal of the pseudo transistor at the first active region and electrically connecting the output terminal of the first inverter to the input terminal of the second inverter, wherein the gate metal of the first pseudo transistor extends from the first active region to the second N-type transistor or the second P-type transistor.

Drawings

The various aspects of the application are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A is a schematic diagram of an SRAM cell in accordance with some embodiments.

FIG. 1B is a layout of an SRAM cell in accordance with some embodiments.

FIGS. 1C and 1D are half cross-sectional views of SRAM bitcells formed in accordance with the layout of FIG. 1B, in accordance with some embodiments.

FIGS. 2A-5B are half cross-sectional views of SRAM bitcells in accordance with some embodiments.

FIG. 6A is a layout of an SRAM cell in accordance with some embodiments.

FIG. 6B is a half cross-sectional view of an SRAM bitcell formed in accordance with the layout of FIG. 6A, in accordance with some embodiments.

Fig. 7-9 are half cross-sectional views of SRAM bit cells according to some embodiments.

FIG. 10 is a perspective view of an SRAM bitcell in accordance with some embodiments.

FIG. 11 is a schematic diagram of an SRAM array in accordance with some embodiments.

Fig. 12 is a flow chart of a method of forming an integrated circuit, according to some embodiments.

Detailed Description

In the following description, numerous thicknesses and materials are described for various layers and structures within an integrated circuit die. Specific dimensions and materials are given by way of example of various embodiments. Those of skill in the art will recognize that other dimensions and materials may be used in many cases in accordance with the present disclosure without departing from the scope of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, it will be understood by those skilled in the art that the present disclosure may be practiced without these specific details. In other instances, common structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring descriptions of the embodiments of the disclosure.

The term "comprising" and its variants (e.g., "including" and "comprising") throughout the specification and the disclosure should be interpreted in an open-ended sense as "including but not limited to," unless the context requires otherwise.

The use of ordinal numbers such as first, second and third does not necessarily imply a sequential order, but may merely distinguish between multiple instances of a single action or structure.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least some embodiments. Thus, appearances of the phrases "in one embodiment," "in an embodiment," or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this specification and this disclosure, the singular forms "a," "an," and "the" include plural references unless the content clearly dictates otherwise. It should also be noted that the term "or" generally includes "and/or" unless the context clearly dictates otherwise.

Embodiments of the present disclosure provide an integrated circuit having a CFET-based SRAM cell with reduced area consumption. Each SRAM cell includes a first inverter formed from a first CFET and a second inverter formed from a second CFET. The interface contact connecting the input of the first inverter to the output of the second inverter and the input of the second inverter to the output of the first inverter is formed to at least partially overlap the active region associated with the CFET. The butt contact may be formed by a back-end-of-line process or a front-end-of-line process. Because the mating contacts are positioned at least partially within the active region, the layout of the SRAM cell can be compressed relative to conventional SRAM layouts. The result is an integrated circuit with a denser SRAM cell array. This may result in an increased number of SRAM cells in the array or the inclusion of additional integrated circuit components in the integrated circuit.

FIG. 1A is a schematic diagram of an SRAM cell 101, in accordance with some embodiments. SRAM cell 101 is a six transistor SRAM cell. As will be explained in more detail below, the layout of the SRAM cell 101 provides a reduced area consumption for the SRAM cell. Further details regarding the layout and cross-sectional structure of SRAM cell 101 are shown in fig. 1B-1D.

The SRAM cell 101 includes a first inverter 103 and a second inverter 105. The first inverter 103 includes a first P-type transistor P1 and a first N-type transistor N1. The gate terminals of transistors P1 and N1 are coupled together. The drain terminals of transistors P1 and N1 are coupled together. The source terminal of the transistor P1 is coupled to the power supply voltage VDD. The source terminal of the transistor N1 is connected to ground. Transistors P1 and N1 collectively correspond to CFET transistor C1.

The second inverter 105 includes a P-type transistor P2 and an N-type transistor N2. The gate terminals of transistors P2 and N2 are coupled together. The drain terminals of transistors P2 and N2 are coupled together. The source terminal of the transistor P2 is coupled to the power supply voltage VDD. The source terminal of transistor N2 is coupled to ground (VSS). Transistors P2 and N2 collectively correspond to CFET transistor C2.

The SRAM cell 101 includes a first pass gate transistor PG1 and a second pass gate transistor PG2. The gate terminals of transistors P1 and P2 are coupled to word line WL. The drain terminal of transistor PG1 is coupled to the drain terminals of transistors P1 and N1, which collectively correspond to the output of inverter 103. The source terminal of transistor PG1 is coupled to bit line BL. The drain terminal of transistor PG2 is coupled to the drain terminals of transistors P2 and N2, which collectively correspond to the output of inverter 105. The source terminal of transistor PG2 is coupled to bit line BL. In the example of fig. 1A, the transistors PG1 and PG2 are N-type transistors, but in other examples the transistors PG1 or PG2 may be P-type transistors. The transistors P1 and P2 may be referred to as pull-up transistors. Transistors N1 and N2 may be referred to as pull-down transistors.

As described above, the output of inverter 103 is coupled to the input of inverter 105. The output of inverter 105 is coupled to the input of inverter 103. The connector coupling the output of inverter 105 to the input of inverter 103 is the first mating contact BCT1. The connector coupling the output of inverter 103 to the input of inverter 105 is the second docking contact BCT2.

The formation of the mating contacts of the SRAM cell may result in a relatively large layout area of the SRAM cell. This is because the mating contacts are typically offset from the active area of the transistors of the SRAM cell. However, the abutting contacts BCT1 and BCT2 of the SRAM cell 101 avoid the drawbacks of the conventional solutions. Specifically, the butting contacts BCT1 and BCT2 are formed to overlap or entirely within the active region of the SRAM cell. As a result, the area consumed by the SRAM cell 101 is significantly reduced relative to other SRAM cells. This will be more clearly seen in fig. 1B-1D.

FIG. 1B is a layout 102 of the SRAM cell 101 of FIG. 1A, according to some embodiments. The layout corresponds to a top view showing the relative positions of various regions and materials of SRAM cell 101 according to the X-axis and the Y-axis. The X-axis and the Y-axis are mutually orthogonal horizontal axes. Layout 102 does not show all of the materials and structures used to form the integrated circuit that includes SRAM cell 101. Instead, layout 102 shows the locations of active region 107, gate metal 109/111, source/drain metal 113, and the butting contacts BCT1 and BCT2.

The active region 107 corresponds to the location of the semiconductor material that forms the channel region and source/drain regions of the transistors of the SRAM cell 101. In some embodiments, the portion of the active region extending between adjacent source/drain metals 113 includes a plurality of semiconductor nanostructures that make up the channel region of the transistors of SRAM cell 101. The active regions 107 may correspond to regions of semiconductor material separated from one another by shallow trench isolation structures or other structures.

As used herein, the term "active region" refers to a set of X-Y coordinates associated with an active semiconductor material layout. If at least part of the docking contact BCT shares the X-Y coordinates of the active region, the docking contact BCT is considered to overlap with the active region even though the docking contact is above or below the actual semiconductor material of the active region. If the X-Y coordinates of the docking contact are entirely within the X-Y coordinates of the active area, then the docking contact BCT is considered to be entirely within the active area.

Each active region 107 may correspond to the location of a semiconductor fin that forms the source, drain, and channel regions of a plurality of transistors. Each active region 107 may include a number of source/drain and channel regions for transistors. In some embodiments, active regions 107 are separated from each other by inactive regions. A large number of first inverters 103, first pass gate transistors PG1, and first dummy transistors D1 of the SRAM cell 101 may be formed in the first active region 107. The second inverter 105, the second pass gate transistor PG2, and the second dummy transistor D2 of the SRAM cell 101 may be formed in the adjacent second active region 107, the second active region 107 being spaced apart from the first active region 107. Forming the mating contacts BCT as described herein enables adjacent active regions 107 to be placed closer together, thereby reducing the overall area of the SRAM cell 101 and enabling more SRAM cells to be formed in an integrated circuit.

The label MDS refers to the source/drain metal 113. In particular, MDS represents a line that extends through the source/drain metal 113 of the transistor of SRAM cell 101. The label G indicates a line extending through the gate metal 109/111 of the transistors of the SRAM cell 101. As will be described in more detail below, because SRAM cell 101 includes CFETs, each corresponding to a P-type transistor and an N-type transistor stacked in a vertical direction, gate metal 109 of the P-type transistor and gate metal 111 of the N-type transistor overlap each other in the X-Y plane. Specifically, the gate metal 109 of the P-type transistor is located directly below the gate metal 111 of the N-type transistor except at specific locations where the gate metal 111 is broken or cut.

The positions corresponding to the transistors P1 and N1 (C1) are at the upper left of the layout 102. The positions corresponding to the transistors P2 and N2 (C2) are at the lower right of the layout 102. Pass gate transistor PG1 and dummy transistor D1 are located at the upper right of layout 102. Pass gate transistor PG2 and dummy transistor D2 are located at the bottom left of layout 102. Transistors P1, N1, and PG1 share a common drain region. Transistors P2, N2, and PG2 share a common drain region.

The location corresponding to block VSS is the location where the ground contact is connected to the portion of source/drain metal 113 corresponding to the source regions of N-type transistors N1 and N2. The location corresponding to the block VDD is the location where the high power supply voltage contact is connected to the portion of the source/drain metal 113 corresponding to the source regions of the P-type transistors P1 and P2. The block WL corresponds to the location where the word line contact is connected to the gate metal 109/111. The location corresponding to the block BL is the location where the bit line contact is connected to the portion of the source/drain metal 113 corresponding to the source regions of the pass gate transistors PG1 and PG 2.

Layout 102 indicates the positions of the mating contacts BCT1 and BCT 2. The butting contacts BCT1 and BCT2 cover the active region 107. In the example of fig. 1B, BCT1 and BCT2 do not extend laterally beyond active region 107. Portions of BCT1 and BCT2 may be within active region 107, while other portions of BCT1 and BCT2 are outside active region 107.

BCT2 connects source/drain metal 113 associated with the drain terminal of transistor P1/N1/PG1 (the output of inverter 103) to the portion of gate metal 109 that is electrically connected to the gate terminals of transistors P2 and N2 (the input of inverter 105). Such an electrical connection is more apparent with respect to the cross-sectional views of fig. 1C and 1D.

BCT1 connects source/drain metal 113 associated with the drain terminal of transistor P2/N2/PG2 (the output of inverter 105) to the portion of gate metal 109 that is electrically connected to the gate terminals of transistors P1 and N1 (the input of inverter 103).

The location of the mating contacts BCT1 and BCT2 within the layout 102 provides a number of benefits. Since the mating contact only covers the active region 107, the area of the layout 102 is significantly reduced relative to a conventional SRAM layout in which the mating contact is completely outside the active region, but the SRAM cell layout is significantly enlarged in the Y-direction. The result is that the integrated circuit may include an array of denser SRAM cells, or the integrated circuit area may be used for other purposes.

FIG. 1C is a cross-sectional view of an integrated circuit 100 formed according to a layout 102 of the SRAM cell 101 of FIG. 1B, in accordance with some embodiments. The view of fig. 1C corresponds to cut line C in layout 102 of fig. 1B. The view of fig. 1C shows CFET C1 including transistors N1 and P1. The view of fig. 1C also shows transistor PG1 and dummy transistor D1. The transistor N1 is stacked over the transistor P1. The transistor PG1 is stacked on top of the dummy transistor D1.

The transistors of SRAM cell 101 (including N1, P1, and PG1 shown in fig. 1C) may correspond to full-gate-around transistors. The full-gate-all-around transistor structure may be patterned by any suitable method. For example, structures may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Typically, a double patterning or multiple patterning process combines lithography and a self-aligned process, allowing creation of patterns with, for example, a smaller pitch than is obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the full-ring gate structure. Further, the full-gate-all-around transistors may each include a plurality of semiconductor nanostructures corresponding to channel regions of the transistors. The semiconductor nanostructures may include nanoplatelets, nanowires, or other types of nanostructures. Full-gate-all-around transistors may also be referred to as nanostructure transistors.

Transistor N1 includes a plurality of semiconductor nanostructures 106. The semiconductor nanostructures 106 are stacked in the vertical direction or the Z-direction. In the example of fig. 1C, there are two stacked semiconductor nanostructures 106. In practice, however, there may be more than two stacked nanostructures 106 without departing from the scope of the disclosure. Furthermore, in some embodiments, only a single semiconductor nanostructure 106 may be present. Semiconductor nanostructure 106 corresponds to the channel region of transistor N1. The semiconductor nanostructures 106 may be nanoplatelets, nanowires, or other types of nanostructures.

The transistor P1 includes a plurality of semiconductor nanostructures 108. The semiconductor nanostructures 108 are stacked in the vertical direction or the Z-direction. In the example of fig. 1C, there are two stacked semiconductor nanostructures 108. In practice, however, more than two stacked nanostructures 108 or only a single nanostructure 108 may be present without departing from the scope of the present disclosure. The semiconductor nanostructure 108 corresponds to a channel region of the transistor P1. The semiconductor nanostructures 108 may be nanoplatelets, nanowires, or other types of nanostructures. In fig. 1C, the number of semiconductor nanostructures 106 is the same as the number of semiconductor nanostructures 108. However, in some embodiments, the number of nanostructures 106 may be different than the number of semiconductor nanostructures 108.

Semiconductor nanostructures 106 and 108 may comprise Si, siGe, or other semiconductor materials. In the non-limiting example described herein, the semiconductor nanostructure 106 is silicon. The vertical thickness of the semiconductor nanostructures 106 may be between 2nm and 5 nm. The semiconductor nanostructures 106 may be separated from each other by 4nm to 10nm in a vertical direction. Other thicknesses and materials may be used for the semiconductor nanostructures 106 without departing from the scope of the disclosure. The semiconductor nanostructures 108 may be of the same material and size as the semiconductor nanostructures 106 or of a different semiconductor material than the semiconductor nanostructures 106.

Transistors N1 and P1 include a gate dielectric. The gate dielectric includes an interfacial gate dielectric layer 120 and a high-K gate dielectric layer 122. Interfacial gate dielectric 120 is a low dielectric constant gate dielectric. An interfacial gate dielectric layer is in contact with semiconductor nanostructures 106 and 108. The high-K gate dielectric 122 is in contact with the low-K gate dielectric. An interfacial gate dielectric layer 120 is located between semiconductor nanostructure 106 and high-K gate dielectric layer 122 and between semiconductor nanostructure 108 and high-K gate dielectric layer 122.

Interfacial gate dielectric 120 may comprise a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric material. Interfacial dielectric layer 120 can comprise a relatively low K dielectric relative to a high K dielectric (such as hafnium oxide) or other high K dielectric material used in the gate dielectric of the transistor. Interfacial dielectric layer 120 can include a native oxide layer grown on the surface of semiconductor nanostructures 106 and 108. The interfacial dielectric layer 120 has a thickness between 0.4nm and 2 nm. Other materials, configurations, and thicknesses may be used for interfacial dielectric layer 120 without departing from the scope of this disclosure.

The high-K gate dielectric layer includes one or more layers of dielectric material, such as HfO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zirconia, alumina, titania, hafnia-alumina (HfO ₂ -Al ₂ O ₃ ) Alloys, other suitable high-K dielectric materials, and/or combinations thereof. The thickness of the high-K dielectric is in the range from about 1nm to about 3 nm. Other thicknesses, deposition processes, and materials may be used for the high-K gate dielectric layer without departing from the scope of the present disclosure. The high-K gate dielectric layer may include a first layer including dipole doped HfO including La and Mg, and a second layer ₂ And the second layer includes a high-K ZrO layer having crystals.

The transistor N1 includes a gate metal 111. Gate metal 111 surrounds semiconductor nanostructure 106. The gate metal 111 is in contact with the high-K gate dielectric layer 122. The gate metal 111 corresponds to the gate electrode of the transistor N1. In examples where transistor N1 is an N-type transistor, gate metal 111 may include a material that produces a desired work function with semiconductor nanostructure 106. In one example, the gate metal 111 comprises titanium aluminum, titanium, aluminum, tungsten, copper, gold, or other conductive material.

Fig. 1C shows a single gate metal 111. In practice, however, the gate electrode of transistor N1 may comprise multiple metal layers. For example, the gate metal 111 may include one or more liner layers or adhesion layers, such as tantalum, tantalum nitride, titanium nitride, or other materials. The gate metal 111 may include a gate fill material that fills the remaining volume between the semiconductor nanostructures 106 after the deposition of the one or more liner layers. Various materials, combinations of materials, and configurations may be used for the gate metal 111 without departing from the scope of the present disclosure.

The transistor P1 includes a gate metal 109. Gate metal 109 surrounds semiconductor nanostructure 108. The gate metal 109 is in contact with the high-K gate dielectric layer 122. The gate metal 109 corresponds to the gate electrode of the transistor P1. In examples where transistor P1 is a P-type transistor, the material comprising gate metal 109 may create a desired work function with semiconductor nanostructure 108. In one example, the gate metal 109 comprises titanium nitride, titanium, aluminum, tungsten, copper, gold, or other conductive material.

Fig. 1C shows a single gate metal 109. In practice, however, the gate electrode from transistor P1 may include multiple metal layers surrounding semiconductor nanostructure 108. For example, the gate metal 111 may include one or more liner layers or adhesion layers, such as tantalum, tantalum nitride, titanium nitride, or other materials. The gate metal 109 may include a gate fill material that fills the remaining volume between the semiconductor nanostructures 108 after deposition of the one or more liner layers. Various materials, combinations of materials, and configurations may be used for the gate metal 109 without departing from the scope of the present disclosure.

Transistor N1 includes source/drain regions 114. Source/drain regions 114 are in contact with each of the semiconductor nanostructures 106. Each semiconductor nanostructure 106 extends between source/drain regions 114 in the X-direction. Source/drain regions 114 comprise semiconductor material.

Transistor P1 includes source/drain regions 116. Source/drain regions 116 are in contact with each of the semiconductor nanostructures 108. Each semiconductor nanostructure 107 extends between source/drain regions 116 in the X-direction. Source/drain regions 116 comprise semiconductor material.

The source/drain regions 114 may be doped with N-type dopant species. The N-type dopant species may include P, as or other N-type dopant species. The source/drain regions 116 may be doped with P-type dopant species. The P-type dopant species may include B or other P-type dopant species. Doping may be performed in situ during the epitaxial growth process of the source/drain regions 116. Source/drain regions 114 and 116 may comprise other materials and structures without departing from the scope of the present disclosure.

As used herein, the term "source/drain region" may refer to either a source region or a drain region, depending on the context. Thus, one of the source/drain regions 114 may be a source region while the other of the source/drain regions 114 is a drain region, or vice versa. In one embodiment, the left source/drain region 114 is the source region of transistor N1 and the right source/drain region 114 is the drain region of transistor N1. The left source/drain region 116 is the source region of transistor P1 and the right source/drain region is the drain region of transistor P1.

Each of the transistors N1 and P1 includes an internal spacer 126. The inner spacer 126 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials without departing from the scope of the present disclosure. In one example, the inner spacer 126 comprises silicon oxynitride.

The internal spacers 126 of transistor N1 physically separate the gate metal 111 from the source/drain regions 114. This prevents shorting between the gate metal 111 and the source/drain regions 114. The internal spacers 126 of transistor P1 physically separate the gate metal 109 from the source/drain regions 116. This prevents shorting between the gate metal 109 and the source/drain regions 116.

The transistor PG1 may be substantially the same as the transistor N1. The transistor PG1 includes a semiconductor nanostructure 110 and source/drain regions 118. Semiconductor nanostructure 110 extends between source/drain regions 118 in the X-direction. Gate dielectric layers 120 and 122 surround semiconductor nanostructure 110. Gate metal 111 surrounds semiconductor nanostructure 110, and gate dielectric layers 120 and 122 are located between semiconductor nanostructure 110 and gate metal 111. In some embodiments, the right source/drain region 118 is the source region of transistor PG 1. The left source/drain region 118 is the drain region of transistor PG 1. In practice, the right source/drain region 114 and the left source/drain region 118 are integral with each other. In embodiments where transistors PG1 and N1 are both N-type transistors, the structure and materials of PG1 may be the same as those described with respect to transistor N1.

The dummy transistor D1 is located below the pass gate transistor PG 1. The dummy transistor D1 has a semiconductor nanostructure 112 surrounded by gate dielectric layers 120 and 122 and gate metal 109. In many respects, dummy transistor D1 is substantially identical to transistor P1. However, the dummy transistor D1 does not have a function of a transistor because the semiconductor nanostructure 112 is not connected to the source/drain region on the right side. Conversely, if dummy transistor D1 is active, dielectric layers 140 and 142 occupy the entire location where the source/drain regions are to be formed.

Nonetheless, the dummy transistor D1 plays a useful role in the SRAM cell 101. Specifically, although not shown in fig. 1C, the gate metal 109 extends uninterrupted in the Y direction to surround the semiconductor nanostructure of the transistor P2. Thus, the gate electrode of dummy transistor D1 is electrically shorted to the gate electrode of transistor P2, as shown in fig. 1D.

The left source/drain metal 113 is electrically connected to the left source/drain region 114 (source region in some embodiments) of the transistor N1. Although not shown in fig. 1C, contact VSS is connected to left source/drain metal 113. The center source/drain metal 113 is electrically connected to the right source/drain region 114 of transistor N1, the left source/drain region 118 of transistor PG1, and the right source region 116 of transistor P1. In the example of fig. 1C. The central source/drain region 113 is connected to the drain region of each of the transistors N1, P1, and PG 1. The right source/drain region 113 is electrically connected to a right source/drain region 118 (source terminal in some embodiments) of the transistor PG 1. The source/drain metal 113 may include titanium, aluminum, nickel, tungsten, tantalum, or other suitable conductive material.

In some embodiments, silicide may be located between the various source/drain regions and the source/drain metal 113. Conductive layers 132 and 134 may be positioned in contact with source/drain metal 113. Conductive layers 132 and 134 may include titanium nitride, tantalum nitride, titanium, tantalum, or other suitable conductive materials.

Fig. 1C shows a mating contact BCT2. The butt contact BCT2 electrically connects the gate metal 109 of the dummy transistor D1 to the right source/drain region 116 of the transistor P1. Since the gate metal 109 of the dummy transistor D1 is electrically shorted to the gate metal 109 of the transistor P2 and the gate metal 111 of the transistor N2, and since the drain terminals of the transistors N1, P1 and PG1 are shorted together, the butt contact BCT2 electrically connects the input terminal of the inverter 105 with the output terminal of the inverter 103. Thus, gate metal 109 of dummy transistor D1 acts as a bridge between the drain regions of N1, P1, and PG1 and the gate electrodes of N2 and P2.

As shown in fig. 1C, the butt contact BCT2 is formed under the semiconductor drain regions of the transistors N1, P1, and PG1, and under the semiconductor nanostructures 110 and 112 of the transistors PG1 and D1. Accordingly, the docking contact is formed under the active region 107 associated with transistors N1, P1, PG1, and D1. As previously described, this greatly reduces the layout of SRAM cell 101 relative to conventional SRAM cells.

The mating contact BCT2 may be formed as part of a back-end-of-line process of the integrated circuit 100. Specifically, after the front-end-of-line process for the transistors of the SRAM cell 101 has been performed, the integrated circuit 100 may be flipped for the back-end-of-line process. The back-end-of-line process may include replacing the semiconductor substrate material with a dielectric material such as dielectric material 144. The dielectric material may be patterned to expose the source/drain regions and the gate metal 109 at different locations. The mating contacts BCT1 and BCT2 may then be formed at the exposed locations. Although fig. 1C shows a backside mating contact, in practice, the mating contact may be formed on the front side above transistors N1, P1, PG1, and D1.

Fig. 1C shows transistors N1, PG1, P1, D1 and a docking contact BCT2. However, the butt contact BCT1 and the transistors N2, P2, PG2, and D2 are substantially the same as the transistors N1, PG1, P1, D1 and the butt contact BCT2, except for some differences in orientation. Accordingly, the principles, structures and materials shown in fig. 1C may be applied to the butt contact BCT1 and the transistors N2, P2, PG2 and D2.

The mating contact BCT2 may comprise one or more of aluminum, titanium, tantalum, titanium nitride, tantalum nitride, copper, gold, or other suitable conductive materials. The mating contact BCT2 may include a conductive layer 134 lining the mating contact BCT 1.

The integrated circuit 100 includes sidewall spacers 128. Sidewall spacers 128 are positioned adjacent the uppermost portion of gate metal 111 and electrically isolate gate metal 111 from source/drain metal 113. Sidewall spacers 128 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials. Other thicknesses and materials may be used for sidewall spacer 128 without departing from the scope of this disclosure.

Integrated circuit 100 may include a dielectric layer 144. The dielectric layer 144 may be positioned in contact with the bottom and sidewalls of the source/drain regions 116. Dielectric layer 144 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials.

The integrated circuit 100 includes hybrid nanostructures between semiconductor nanostructures 106 and semiconductor nanostructures 108. More specifically, the hybrid nanostructures are located directly between the lowest semiconductor nanostructure 106 and the highest semiconductor nanostructure 108 and between the lowest nanostructure 110 and the highest nanostructure 112. The hybrid nanostructure may be a hybrid nanoplatelet, a hybrid nanowire, or other type of nanostructure. The hybrid nanostructure may include an upper semiconductor layer 124 and a lower semiconductor layer 124, and a dielectric layer 129 between the upper semiconductor layer and the lower semiconductor layer 124. The hybrid nanostructures may take on a variety of structures and compositions without departing from the scope of the disclosure. Dielectric layer 129 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials.

The integrated circuit 100 may include a dielectric layer 130 between the gate spacer structure 128 and the source/drain metal 113. Dielectric layer 130 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials.

Integrated circuit 100 may include a dielectric layer 138 on top of the highest portion of gate metal 111. Dielectric layer 138 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials.

The integrated circuit 100 may include a dielectric layer 136 on top of the source/drain metal 113. Dielectric layer 136 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials.

Integrated circuit 100 may include a dielectric layer 140 and a dielectric liner 142 between left source/drain regions 114 and 116. Dielectric layer 140 and dielectric liner 142 may comprise different compositions of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride oxide, fluorine doped silicate glass (FSG), low K dielectric materials, or other dielectric materials.

Fig. 1D is a cross-sectional view of the integrated circuit 100 of fig. 1C taken at a location corresponding to cut line D in layout 102 of fig. 1B, in accordance with some embodiments. Fig. 1D shows portions of transistors PG1 and D1. Specifically, fig. 1D shows a gate metal 111 surrounding the semiconductor nanostructure 110 of the transistor PG 1. Fig. 1D also shows a gate metal 109 surrounding the semiconductor nanostructure 112 of the dummy transistor D1. The gate metal 109 and gate metal 111 at transistors PG1 and D1 are isolated from each other by the hybrid nanostructure and dielectric layer 142.

Fig. 1D also shows the height H of the top side of the cut-in gate metal 111. Specifically, the height H corresponds substantially to the height of the gate metal 111 of the transistor N2 above the gate metal 109 of the transistor P2. The height H may be between 20nm and 40nm, but other dimensions may be used without departing from the scope of the present disclosure. Fig. 1D also shows the width W of the top side of the cut-in gate metal 111. The width W may substantially correspond to the distance between the gate metal 111 of the transistor N2 and the gate metal 111 of the transistor PG 1. The width W may be between 40nm and 60nm, but other dimensions may be used without departing from the scope of the present disclosure. Fig. 1D also shows how the combination of gate metal 111 of transistor N2 and gate metals 109 of transistors P2 and D1 form an L-shape due to the isolation between gate metal 111 of transistor PG1 and gate metal 109 of transistor D1.

Fig. 1D shows that the top of gate metal 111 of transistor PG1 extends to the same vertical level as the top of gate metal 11 of transistor N2. However, the bottom of the gate metal 111 of the transistor PG1 does not extend as low as the bottom of the gate metal 111 of the transistor N2. This is because the gate metals 111 and 109 of transistors N2 and P2 are intended to be shorted together as the output of inverter 105, while the gate metal 111 of PG1 and the gate metal 109 of transistor D1 are not intended to be shorted together. Accordingly, the dielectric layer 142 is formed between the gate metals 109 and 111 of the transistors PG1 and D1, thereby ensuring that the bottom of the gate metal 111 of the transistor PG1 does not extend to contact the top of the gate metal 109 of the transistor D1.

Fig. 1D shows transistors N2 and P2, corresponding to CFET C2. Transistor N2 includes semiconductor nanostructure 150 and is substantially the same as transistor N1. Gate metal 111 surrounds semiconductor nanostructure 150 and gate dielectric layers 120 and 122 are located between gate metal 111 and semiconductor nanostructure 150. Transistor P2 includes semiconductor nanostructure 152 and is substantially the same as transistor P1. Gate metal 109 surrounds semiconductor nanostructure 152 and gate dielectric layers 120 and 122 are located between gate metal 109 and semiconductor nanostructure 152.

The gate metals 109 and 111 at transistors P2 and N2 are in direct contact with each other. Thus, the gate electrode of transistor N2 is shorted to the gate electrode of transistor P2, corresponding to the input terminal of inverter 105.

The above-mentioned butt contact BCT2 is electrically connected to the gate metal 109. The gate metal 109 extends as a bridge between the dummy transistor D1 and the transistor P2. Thus, the input of inverter 105 is coupled to the drain terminals of transistors N1, P1, and PG 1. The gate metal 111 of transistor PG1 is not shorted to the gate metal 111 of transistor N2 because the gate metal 111 between transistors N2 and PG1 is removed. A dielectric layer 136 extends over and between the gate metals 111 of transistors N2 and PG 1.

Fig. 2A and 2B are cross-sectional views of an integrated circuit 100 according to some embodiments. Fig. 2A corresponds to the view of fig. 1D. Fig. 2B corresponds to the view of fig. 1C. Referring to fig. 2A and 2B, the integrated circuit 100 is substantially similar to the integrated circuit 100 of fig. 1C and 1D, except that a P-type transistor is formed over an N-type transistor. Specifically, P1 is formed over N1, P2 is formed over N2, and D1 is formed over PG 1. Further, the butting contact BCT2 is a top side contact located on top of the center source/drain metal 113 and the gate metal 109 of the dummy transistor D1. Dielectric layer 136 has been patterned to expose the center source/drain metal 113 and gate metal 109 of transistor D1. The butting contacts BCT2 have been formed on the top surfaces of the gate metal 109 and the center source/drain metal 113 of the transistor D1. Gate metal 109 acts as a bridge extending between transistors D1 and P2. The gate metal 111 is coupled from the backside such that the gate metal 111 of N2 is not shorted to the gate metal 111 of PG 1. The backside dielectric layer 144 extends in the gap between the gate metal 111 of N2 and PG 1.

Fig. 3A and 3B are cross-sectional views of an integrated circuit 100 according to some embodiments. Fig. 3A corresponds to the view of fig. 1D. Fig. 3B corresponds to the view of fig. 1C. Referring to fig. 3A and 3B, the integrated circuit 100 is substantially similar to the integrated circuit 100 of fig. 1C and 1D, except that the pass gate transistor PG1 is a P-type transistor. Thus, D1 is an N-type transistor, and is formed over PG 1. The gate metal 111 acts as a bridge between D1 and N2 shorting the gate of D1 to the gates of N2 and P2. The butting contact BCT2 is a topside contact located on top of the center source/drain metal 113 and gate metal 111 of the dummy transistor D1. Dielectric layer 136 has been patterned to expose the center source/drain metal 113 and gate metal 109 of transistor D1. The butting contact BCT2 has been formed on the top surfaces of the gate metal 111 and the central source/drain metal 113 of the transistor D1. The gate metal 111 acts as a bridge extending between the transistors D1 and N2. The gate metal 109 is cut from the backside so that the gate metal 109 of P2 is not shorted to the gate metal 109 of PG 1. A backside dielectric layer 144 extends in the gap between the gate metal 109 of P2 and PG 1.

Fig. 4A and 4B are cross-sectional views of an integrated circuit 100 according to some embodiments. Fig. 4A corresponds to the view of fig. 1D. Fig. 4B corresponds to the view of fig. 1C. Referring to fig. 4A and 4B, the integrated circuit 100 is substantially similar to the integrated circuit 100 of fig. 1C and 1D, except that the pass gate transistor PG1 is a P-type transistor and is formed over an N-type transistor. Thus, D1 is an N-type transistor and is formed under PG 1. The gate metal 111 acts as a bridge between D1 and N2, shorting the gate of D1 to the gates of N2 and P2. The mating contact BCT2 is a backside contact.

Fig. 5A and 5B are cross-sectional views of an integrated circuit 100 according to some embodiments. Fig. 5A corresponds to the view of fig. 1D. Fig. 5B corresponds to the view of fig. 1C. Referring to fig. 5A and 5B, the integrated circuit 100 is substantially similar to the integrated circuit 100 of fig. 1C and 1D, except that the semiconductor nanostructures 112 of the dummy transistor D1 have been substantially removed prior to depositing the gate metal 109. In the view of fig. 5B, the gate metal 109 is located in the gaps or trenches between the cut portions of the semiconductor nanostructures 112. In fig. 5A, the remaining semiconductor nanostructures 112 are not shown. Removing portions of semiconductor nanostructure 112 and subsequently filling the gap with gate metal 109 results in a stronger electrical connection of the docking contact BCT2 with the gate metals 109 and 111 of transistors P2 and N2.

Fig. 6A is a layout 102 of an SRAM cell 101 according to some embodiments. Layout 102 of fig. 6A is substantially similar to layout 102 of fig. 1B, except that the docking contact BCT2 overlaps the edges of the active regions 107 of transistors P1, N1, PG1, and D1. This does not increase the overall area of the layout of SRAM cell 101 because BCT2 does not extend past source/drain metal 113 corresponding to the combined drains of P1, N1, and PG1 in the Y-direction. In fig. 6A, BCT1 is substantially in the same position as in fig. 1B. However, in some embodiments, BCT1 may also cover the edges of the active region 107 of transistors P2, N2, PG2, and D2. In some embodiments, BCT1 may cover the edges of active region 107, while BCT2 does not cover the edges of active region 108.

Fig. 6B is a cross-sectional view of an integrated circuit 100 formed in accordance with the layout 102 of fig. 6A, in accordance with some embodiments. The integrated circuit 100 of fig. 6B is substantially similar to the integrated circuit 100 of fig. 1D, except that the mating contact BCT2 overlaps the edge of the active region 107 in the Y-direction. Specifically, a first portion of the butting contact BCT2 is formed directly under the semiconductor nano-structures 112 and 110, and a second portion of the butting contact BCT1 is not formed directly under the semiconductor nano-particles 110 and 112. In some embodiments, it may be beneficial to position the mating contact BCT2 to overlap with the edge of the active region, as a narrower opening may be formed in the dielectric layer 144 than if BCT2 were entirely within the active region.

Fig. 7 is a cross-sectional view of an integrated circuit 100 according to some embodiments. The integrated circuit 100 of fig. 7 is substantially similar to the integrated circuit 100 of fig. 2A, except that the mating contact BCT2 overlaps the edge of the active region 107.

Fig. 8 is a cross-sectional view of an integrated circuit 100 according to some embodiments. The integrated circuit 100 of fig. 8 is substantially similar to the integrated circuit 100 of fig. 3A, except that the mating contact BCT2 overlaps the edge of the active region 107.

Fig. 9 is a cross-sectional view of an integrated circuit 100 according to some embodiments. The integrated circuit 100 of fig. 9 is substantially similar to the integrated circuit 100 of fig. 4A, except that the mating contact BCT2 overlaps the edge of the active region 107.

Fig. 10 is a perspective view of an integrated circuit 100 formed in accordance with the layout 102 of fig. 1B, in accordance with some embodiments. The view in fig. 10 does not show some of the dielectric layers. The view of fig. 10 shows the positions of transistors N1, P1, N2, P2, PG1, D1, PG2, and D2. The view of fig. 10 also shows source/drain region 168 of transistor P2, source/drain region 166 of transistor N2, and source/drain region 170 of transistor PG 2. Fig. 10 also shows semiconductor nanostructure 160 of transistor PG2 and semiconductor nanostructure 162 of pseudo-transistor D2. Fig. 10 shows some contacts such as WL, BL, VDD, VSS and BCT2. Other components of integrated circuit 100 block one of the contacts of BCT1 and backside VDD. Fig. 10 shows a dielectric layer 180 under dielectric layer 144. Various other configurations of integrated circuit 100 may be used without departing from the scope of this disclosure.

FIG. 11 is a schematic diagram of an SRAM array 180 in accordance with some embodiments. The SRAM array 180 includes a plurality of SRAM cells 101 arranged in rows and columns. Each SRAM cell 101 corresponds to an SRAM cell and may include the layout, configuration, and structure shown and described with respect to fig. 1A-10. SRAM array 180 may include a row decoder 182 and a column decoder 184. Addressing information may be provided to the row decoder 182 and the column decoder 184 to read data from or write data to the SRAM cell 101. In particular, data may be written and read via column decoder 184. The SRAM array 180 may be formed in the integrated circuit 100 as described with respect to fig. 1A-10.

Fig. 12 is a flow chart of a method 1200 for forming an integrated circuit, according to some embodiments. The method 1200 may utilize the components, structures, and processes described with respect to fig. 1A-11. At 1202, method 1200 includes forming a first inverter in a first active region of an integrated circuit, the first inverter including a vertically stacked first P-type transistor and a first N-type transistor. One example of an active region is active region 107 in fig. 1B. One example of an integrated circuit is integrated circuit 100 in fig. 1C. One example of a first inverter is the first inverter 103 in fig. 1A. One example of a first N-type transistor is N1 in fig. 1C. One example of a first P-type transistor is P-type transistor P1 in fig. 1C.

At 1204, method 1200 includes forming a second inverter in a second active region of the integrated circuit, the second inverter cross-coupled with the first inverter and including a vertically stacked second P-type transistor and second N-type transistor. One example of a second active region is the lower active region 107 of fig. 1B. One example of a second inverter is the second inverter 105 in fig. 1A. One example of a second N-type transistor is N2 in fig. 1D. One example of a second P-type transistor is P-type transistor P2 in fig. 1D.

At 1206, the method 1200 includes forming a vertical stack of a first dummy transistor and a first pass gate transistor in the first active region. One example of a first pass gate transistor is pass gate transistor PG1 in FIG. 1C. One example of a first dummy transistor is dummy transistor D1 in fig. 1C.

At 1208, the method 1200 includes forming a first mating contact at the first active region, the first mating contact in contact with a gate metal of the dummy transistor and electrically connecting an output of the first inverter to an input of the second inverter. The gate metal of the first dummy transistor extends from the first active region to the second N-type transistor or the second P-type transistor. One example of a first mating contact is mating contact BCT2 in fig. 1B.

Embodiments of the present disclosure provide an integrated circuit having CFET-based SRAM cells with reduced area consumption. Each SRAM cell includes a first inverter formed from a first CFET and a second inverter formed from a second CFET. A docking contact formed at least partially overlapping the active region associated with the CFET connects the input of the first inverter to the output of the second inverter and connects the input of the second inverter to the output of the first inverter. The butt contact may be formed by a back-end-of-line process or a front-end-of-line process. Because the mating contacts are positioned at least partially within the active region, the SRAM cell layout can be compressed relative to conventional SRAM layouts. The result is an integrated circuit with a denser SRAM cell array. This may result in an increased number of SRAM cells in the array or the inclusion of additional integrated circuit components in the integrated circuit.

In some embodiments, an integrated circuit includes: a first inverter including a first N-type transistor and a first P-type transistor vertically stacked; a second inverter including a second N-type transistor and a second P-type transistor vertically stacked; and a first docking contact electrically connecting the output of the first inverter to the input of the second inverter, wherein the first contact is at least partially located within a first active region associated with the first inverter.

In some embodiments, the integrated circuit further includes a first transfer gate transistor and a first dummy transistor vertically stacked in the first active region.

In some embodiments, the integrated circuit further comprises: a first gate metal extending uninterrupted between the first dummy transistor and the second N-type transistor or the second P-type transistor, wherein the first docking contact contacts the first gate metal at least partially within the first active region, wherein the first docking contact and the first gate metal electrically connect the output of the first inverter to the input of the second inverter.

In some embodiments, the first N-type transistor, the first P-type transistor, the first transfer gate transistor, and the first dummy transistor each comprise a respective set of stacked semiconductor nanostructures corresponding to channel regions of the first N-type transistor, the first P-type transistor, the first transfer gate transistor, and the first dummy transistor.

In some embodiments, the stacked semiconductor nanostructures of the first dummy transistor are cut in a central region, wherein the first gate metal fills the central region.

In some embodiments, the first pair of contact members is located under the first gate metal and the second gate metal.

In some embodiments, the first mating contact is located over both the first gate metal and the second gate metal.

In some embodiments, the integrated circuit further comprises: and a second docking contact electrically connecting the input of the first inverter to the output of the second inverter, wherein the second docking contact is located at least partially within a second active area associated with the second inverter.

In some embodiments, the integrated circuit further comprises: a second transfer gate transistor and a second dummy transistor vertically stacked in the second active region; and a second gate metal extending uninterrupted between the second dummy transistor and the first N-type transistor or the first P-type transistor, wherein the second docking contact contacts the second gate metal at least partially within the second active region, wherein the second docking contact and the second gate metal electrically connect the output of the first inverter to the input of the second inverter, wherein the first inverter and the second inverter and the first transfer gate transistor and the second transfer gate transistor are SRAM cells.

In some embodiments, the first mating contact is located entirely within the first active region.

In some embodiments, the first mating contact overlaps an edge of the first active region.

In some embodiments, an integrated circuit includes a first N-type transistor including a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the first N-type transistor. The integrated circuit includes a first P-type transistor vertically stacked with the first N-type transistor, and the first P-type transistor includes a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the first P-type transistor. The integrated circuit includes a first pass gate transistor including a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the first pass gate transistor, wherein source/drain regions of the first pass gate transistor, source/drain regions of the first N-type transistor, and source/drain regions of the first P-type transistor are all electrically connected. The integrated circuit includes a dummy transistor vertically stacked with the first pass gate transistor and including a gate electrode. The integrated circuit includes a docking contact electrically connected to the source/drain region of the first N-type transistor and the gate electrode of the pseudo transistor and at least partially under or over the semiconductor nanostructure of the first pass gate transistor and at least partially over or under the drain/source region of the first N-type transistor.

In some embodiments, the integrated circuit further comprises: a second N-type transistor including a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the second N-type transistor; and a second P-type transistor vertically stacked with the second N-type transistor and including a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the second P-type transistor, wherein the gate electrode of the pseudo transistor is integral with the gate electrode of the second P-type transistor.

In some embodiments, the integrated circuit further comprises: a first inverter including a first N-type transistor and a first P-type transistor; and a second inverter cross-coupled with the first inverter and including a second N-type transistor and a second P-type transistor.

In some embodiments, the first N-type transistor is located above the first P-type transistor and the first pass gate transistor is located above the first dummy transistor.

In some embodiments, the first P-type transistor is located above the first N-type transistor and the first dummy transistor is located above the first pass gate transistor.

In some embodiments, the gate electrode of the second N-type transistor, the gate electrode of the second P-type transistor, and the gate electrode of the dummy transistor collectively form an L-shape.

In some embodiments, a method of forming an integrated circuit includes: forming a first inverter in a first active region of the integrated circuit, the first inverter including a first N-type transistor vertically stacked with a first P-type transistor; forming a second inverter in a second active region of the integrated circuit, the second inverter being cross-coupled with the first inverter and including a second N-type transistor vertically stacked with a second P-type transistor; forming a first transfer gate transistor vertically stacked with the first dummy transistor in the first active region; and forming a first butting contact in contact with the gate metal of the pseudo transistor at the first active region and electrically connecting the output terminal of the first inverter to the input terminal of the second inverter, wherein the gate metal of the first pseudo transistor extends from the first active region to the second N-type transistor or the second P-type transistor.

In some embodiments, the method further comprises: the gate metal of the first pass gate transistor is vertically isolated from the gate metal of the first dummy transistor by a dielectric layer to electrically isolate the gate metal of the first pass gate transistor from the gate metal of the first dummy transistor.

In some embodiments, the method further comprises: forming a first N-type transistor, a second N-type transistor, a first P-type transistor and a second P-type transistor during a front end of line process of the integrated circuit; after forming a first N-type transistor, a second N-type transistor, a first P-type transistor and a second P-type transistor, turning over the integrated circuit; and forming a first mating contact during a back-end-of-line process after flipping the integrated circuit.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. An integrated circuit, comprising:

a first inverter including a first N-type transistor and a first P-type transistor vertically stacked;

a second inverter including a second N-type transistor and a second P-type transistor vertically stacked; and

a first pair of contact members electrically connecting the output of the first inverter to the input of the second inverter, wherein the first contact members are at least partially located within a first active region associated with the first inverter.

2. The integrated circuit of claim 1, comprising a first pass gate transistor and a first dummy transistor vertically stacked in the first active region.

3. The integrated circuit of claim 2, further comprising a first gate metal extending uninterrupted between the first dummy transistor and the second N-type transistor or between the first dummy transistor and the second P-type transistor, wherein the first docking contact contacts the first gate metal at least partially within the first active region, wherein the first docking contact and the first gate metal electrically connect an output of the first inverter to an input of the second inverter.

4. The integrated circuit of claim 3, wherein the first N-type transistor, the first P-type transistor, the first transfer gate transistor, and the first dummy transistor each comprise a respective set of stacked semiconductor nanostructures corresponding to channel regions of the first N-type transistor, the first P-type transistor, the first transfer gate transistor, and the first dummy transistor.

5. The integrated circuit of claim 4, wherein the stacked semiconductor nanostructures of the first dummy transistor are cut in a central region, wherein the first gate metal fills the central region.

6. The integrated circuit of claim 3, wherein the first pair of contacts is located under the first and second gate metals.

7. The integrated circuit of claim 3, wherein the first pair of contact members are located over both the first gate metal and the second gate metal.

8. The integrated circuit of claim 3, further comprising a second docking contact electrically connecting an input of the first inverter to an output of the second inverter, wherein the second docking contact is located at least partially within a second active region associated with the second inverter.

9. An integrated circuit, comprising:

a first N-type transistor including a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the first N-type transistor;

a first P-type transistor vertically stacked with the first N-type transistor and including a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the first P-type transistor;

a first pass gate transistor comprising a gate electrode and a plurality of semiconductor nanostructures corresponding to channel regions of the first pass gate transistor, wherein source/drain regions of the first pass gate transistor, source/drain regions of the first N-type transistor, and source/drain regions of the first P-type transistor are all electrically connected;

A dummy transistor vertically stacked with the first transfer gate transistor and including a gate electrode; and

a butting contact electrically connected to the source/drain region of the first N-type transistor and the gate electrode of the pseudo transistor and at least partially located under or over the semiconductor nanostructure of the first pass gate transistor and at least partially located under or over the source/drain region of the first N-type transistor.

10. A method of forming an integrated circuit, comprising:

forming a first inverter in a first active region of an integrated circuit, the first inverter comprising a first N-type transistor vertically stacked with a first P-type transistor;

forming a second inverter in a second active region of the integrated circuit, the second inverter being cross-coupled with the first inverter and comprising a second N-type transistor vertically stacked with a second P-type transistor;

forming a first transfer gate transistor vertically stacked with the first dummy transistor in the first active region; and

a first docking contact is formed that contacts the gate metal of the dummy transistor at the first active region and electrically connects the output of the first inverter to the input of the second inverter, wherein the gate metal of the first dummy transistor extends from the first active region to the second N-type transistor or the second P-type transistor.