CN116631468A - Dynamic random access memory array circuit - Google Patents

Dynamic random access memory array circuit Download PDF

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Publication number
CN116631468A
CN116631468A CN202310485805.9A CN202310485805A CN116631468A CN 116631468 A CN116631468 A CN 116631468A CN 202310485805 A CN202310485805 A CN 202310485805A CN 116631468 A CN116631468 A CN 116631468A
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voltage
write
transistor
word line
present disclosure
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潘立阳
谢翔
黄焘
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Tsinghua University
Beijing Superstring Academy of Memory Technology
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Tsinghua University
Beijing Superstring Academy of Memory Technology
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

The present disclosure provides a Dynamic Random Access Memory (DRAM) array circuit. A DRAM array circuit according to the present disclosure includes N rows and M columns of dynamic random access memory cell circuits, M and N being natural numbers greater than zero, wherein each of the dynamic random access memory cell circuits includes: a write transistor having a gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to the storage node; and a storage transistor having a gate connected to the storage node, a first source/drain connected to the read word line, and a second source/drain connected to the read bit line, wherein in a write operation, the write word line operates at a first voltage lower than a ground voltage and a second voltage higher than or equal to a power supply voltage. According to the DRAM array circuit disclosed by the invention, the data storage time can be prolonged, so that the frequency of interruption caused by refresh operation is reduced, and the power consumption of the whole circuit is reduced.

Description

Dynamic random access memory array circuit
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to a dynamic random access memory array circuit.
Background
Since the invention of dynamic random access memory (Dynamic Random Access Memory, DRAM) by intel corporation of seventies in the twentieth century (Intel Corporation), DRAM has been widely used in various computing or control electronic circuitry. With the development of semiconductor manufacturing processes, the manufacture of DRAM has evolved from using logic processes to using dedicated DRAM manufacturing processes, which has led to the DRAM becoming off-chip from logic chips to off-chip memories.
DRAM cell circuits are generally composed of one transistor and one capacitor (1T 1C structure), and have an advantage of high memory density. However, like other off-chip memories, the DRAM cell circuit has the disadvantages of limited bandwidth and high power consumption. Therefore, the current on-chip memory mainly adopts static random access memory (Static Random Access Memory, SRAM). The single-port SRAM cell circuit is composed of six transistors, has the advantages of high speed and stability, and has the defects of larger area and larger power consumption.
For the shortcomings of off-chip DRAM and on-chip SRAM, embedded dynamic random access memories (embedded Dynamic Random Access Memory, eDRAM) are proposed in the prior art. Compared with an off-chip DRAM, the eDRAM can be realized on-chip and has the advantage of high bandwidth, and compared with an on-chip SRAM, the eDRAM has the advantages of small area and low power consumption. eDRAM has been used in decoders, digital neural network accelerators, analog neural network accelerators, and the like.
DRAM, which is a dynamic random access memory, relies on a capacitor to store data, and the data stored in the capacitor gradually disappears with time due to leakage of a transistor, so that a refresh operation must be performed on the data before the data cannot be correctly read by a read circuit. However, the refresh operation causes additional power consumption and problems such as interruption of system operation. Particularly, as the scale of semiconductor process is reduced, the storage node of DRAM for storing data, i.e., the gate capacitance of the transistor is reduced, and the charge that can be stored is reduced accordingly. In addition, the process scaling down also causes the power supply voltage VDD to decrease, and the voltage difference between the voltages representing data 0 and data 1 (hereinafter referred to as 0/1 data voltage difference) to decrease accordingly. In addition, the shrinking process scale also increases the leakage of transistors. In summary, as the process scale is reduced, the voltage difference of 0/1 data stored in the DRAM storage node is reduced, the leakage speed is fast, the data retention time is shortened, and the problems of high power consumption, frequent interruption to system operation and the like caused by refresh operation are also gradually highlighted.
The above information disclosed in this background section is only for the understanding of the background of the inventive concept and therefore it may contain information that does not form the prior art.
Disclosure of Invention
In order to solve the above problems in the prior art, the present disclosure proposes a novel dynamic random access memory array circuit.
According to one aspect of the present disclosure, there is provided a dynamic random access memory array circuit comprising N rows and M columns of dynamic random access memory cell circuits, wherein M and N are natural numbers greater than zero, wherein each of the dynamic random access memory cell circuits comprises: a write transistor having a gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to the storage node; and a storage transistor having a gate connected to the storage node, a first source/drain connected to the read word line, and a second source/drain connected to the read bit line, wherein in a write operation, the write word line operates at a first voltage lower than a ground voltage and a second voltage higher than or equal to a power supply voltage.
According to another aspect of the present disclosure, there is provided a row driving method for use in a write operation of a dynamic random access memory array circuit according to the above aspect of the present disclosure, comprising: each of the dynamic random access memory cell circuits included in the dynamic random access memory array circuit is driven row by row according to a row address.
The dynamic random access memory array circuit according to the present disclosure solves the problem of incomplete data writing of the storage node due to the threshold voltage existing in the writing transistor and the gate-source coupling capacitance of the writing transistor, and a small 0/1 data voltage difference by using multiple levels of voltages on the writing word line for operation. Thus, the dynamic random access memory array circuit according to the present disclosure prolongs the data storage time, reduces the frequency of interruption due to the refresh operation, and thus reduces power consumption.
However, the effects of the present disclosure are not limited to the above-described effects, and various extensions are to be understood without departing from the spirit and scope of the present disclosure, both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the present disclosure as claimed.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the invention.
Fig. 1 is a circuit diagram showing a configuration of a Dynamic Random Access Memory (DRAM) cell circuit according to the related art.
Fig. 2 is a signal timing diagram illustrating a writing method of the DRAM cell circuit shown in fig. 1.
Fig. 3 is a circuit diagram showing a configuration of a DRAM cell circuit according to one embodiment of the present disclosure.
Fig. 4 is a signal timing diagram illustrating an exemplary write method of the DRAM cell circuit shown in fig. 3.
FIG. 5 is a signal timing diagram illustrating another exemplary write method of the DRAM cell circuit shown in FIG. 3.
Fig. 6 is a circuit diagram showing a configuration of an exemplary DRAM array circuit including the DRAM cell circuit shown in fig. 3.
Fig. 7 is a schematic diagram illustrating an exemplary row driving method in a write operation of the DRAM array circuit shown in fig. 6.
Fig. 8 is a circuit diagram showing a configuration of a DRAM cell circuit according to another embodiment of the present disclosure.
Fig. 9 is a signal timing diagram illustrating an exemplary write method of the DRAM cell circuit shown in fig. 8.
Fig. 10 is a signal timing diagram illustrating another exemplary write method of the DRAM cell circuit shown in fig. 8.
Fig. 11 is a circuit diagram showing a configuration of an exemplary DRAM array circuit including the DRAM cell circuit shown in fig. 8.
Fig. 12 is a schematic diagram showing an exemplary row driving method in a write operation of the DRAM array circuit shown in fig. 11.
Detailed Description
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments or implementations of the present disclosure. As used herein, "embodiments" and "implementations" are used interchangeably and are non-limiting examples of apparatus or methods employing one or more of the inventive concepts disclosed herein. It may be evident, however, that the exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, certain features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.
Unless otherwise indicated, the described exemplary embodiments should be understood to provide exemplary features of varying detail in some ways that the inventive concept may be practiced. Thus, unless otherwise indicated, features, components, modules, regions, and/or aspects of the embodiments (hereinafter referred to individually or collectively as "elements") may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.
For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as any combination of two or more of X only, Y only, Z only, or X, Y and Z, such as XYZ, XYY, YZ and ZZ, for example. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising," when used in this specification, mean that there are stated features, steps, operations, elements, components, and/or groups thereof, but that the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof is not precluded. It should also be noted that as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not degree terms and, therefore, are used to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 shows a circuit diagram of a configuration of a DRAM cell circuit 10 according to the prior art.
As shown in fig. 1, the DRAM cell circuit 10 may include a P-type write transistor PW 11 and an N-type memory transistor NS 12. As shown in fig. 1, the gate 111 of the write transistor PW 11 is connected to a write word line WWL, the first source/drain 112 thereof is connected to a write bit line WBL, and the second source/drain 113 thereof is connected to a storage node SN. Further, as shown in fig. 1, the gate 121 of the storage transistor NS 12 is connected to the storage node SN, the first source/drain 122 thereof is connected to the read word line RWL, and the second source/drain 123 thereof is connected to the read bit line RBL.
FIG. 2 illustrates a signal timing diagram of a write method 200 of the DRAM cell circuit 10 shown in FIG. 1.
As shown in fig. 2, the writing method 200 of the DRAM cell circuit 10 includes two steps, namely a first step (also referred to herein as a "writing step") S210 and a second step (also referred to herein as a "storing step") S220, which are sequentially performed.
As shown in fig. 2, in the first step S210, the write word line WWL is pulled down from the power supply voltage VDD to the ground voltage VSS so that the write transistor PW 11 is turned on, while the write bit line WBL is pulled up or pulled down from the equalizing voltage VBLQ to the power supply voltage VDD or the ground voltage VSS according to the write data being 1 or 0 for writing the power supply voltage VDD or the ground voltage VSS representing the data 1 or 0 into the storage node SN.
Specifically, as shown in fig. 2, when writing data 1, the voltage representing data 1, i.e., the power supply voltage VDD, can be completely written to the storage node SN. That is, at the time of writing data 1, in the first step S210, the voltage representing data 1 at the storage node SN is the power supply voltage VDD.
However, as shown in FIG. 2, when writing data 0, the threshold voltage Vth of the P-type write transistor PW 11 is due to PW Is indicative of the voltage of data 0I.e. the ground voltage VSS cannot be fully written to the storage node SN. Due to the threshold voltage Vth of the P-type write transistor PW 11 PW Is a negative voltage, so when writing data 0, the voltage at the storage node SN representing data 0 is-Vth in the first step S210 PW 。
Therefore, as shown in FIG. 2, in the first step S210, the 0/1 data voltage difference written into the storage node SN is VDD+Vth PW I.e. lower than the supply voltage VDD.
As shown in fig. 2, in the second step S220, the write word line WWL is pulled up from the ground voltage VSS to the power supply voltage VDD, so that the write transistor PW 11 is turned off, while the write bit line WBL is restored from the power supply voltage VDD or the ground voltage VSS to the equalizing voltage VBLQ. At this time, since there is a coupling effect between the gate 111 and the second source/drain 113 of the write transistor PW 11, the voltage at the storage node SN is pulled up. At this time, if the storage node SN stores data 1, the write transistor PW 11 is not completely turned off, resulting in leakage of charge of the storage node SN to the write bit line WBL. Further, if the storage node SN stores data 0, the write transistor PW 11 is almost completely turned off, the charge of the storage node SN is not changed, and only the voltage rises. That is, in the second step S220, the pull-up of the write word line WWL causes the storage node SN to further lose charge due to the coupling effect, so that the 0/1 data voltage difference is further reduced to VDD+Vth PW Vcou, where Vcou represents the loss of 0/1 data voltage difference due to the coupling effect described above.
As the semiconductor process scale shrinks, the storage node SN for storing data in the DRAM cell circuit 10 according to the prior art, i.e., the gate capacitance of the storage transistor NS 12, also shrinks, and the charge that can be stored also correspondingly decreases. In addition, the reduction of the process scale also reduces the power supply voltage VDD, and the 0/1 data voltage difference is correspondingly reduced. In addition, the shrinking process scale also increases the leakage of transistors. In summary, as the process scale is reduced, the voltage difference of 0/1 data stored by the storage node SN of the DRAM cell circuit 10 is reduced, the leakage speed is fast, the data retention time is shortened, and the problems of high power consumption, frequent interruption to the system operation and the like caused by the refresh operation become more obvious.
Although fig. 1 is described by taking a write transistor as a P-type transistor and a memory transistor as an N-type transistor as an example, it should be appreciated by those skilled in the art that the above-described technical problems remain when implementing DRAM cell circuits using other types of transistors in the prior art, such as when implementing a write transistor using an N-type transistor.
In response to the problems in the prior art, the present disclosure proposes a novel Dynamic Random Access Memory (DRAM) cell circuit and a writing method thereof. A dynamic random access memory cell circuit suitable for on-chip embedded applications and a writing method thereof according to the present disclosure are described in detail below with reference to fig. 3 to 8.
Fig. 3 shows a circuit diagram of a configuration of a DRAM cell circuit 30 according to one embodiment of the present disclosure.
As shown in fig. 3, a DRAM cell circuit 30 according to an embodiment of the present disclosure may include a P-type write transistor PW 31 and an N-type memory transistor NS 32. As shown in fig. 3, the gate 311 of the write transistor PW 31 may be connected to a write word line WWL, a first source/drain 312 thereof may be connected to a write bit line WBL, and a second source/drain 313 thereof may be connected to a storage node SN. Further, as shown in fig. 3, according to an embodiment of the present disclosure, a gate 321 of the storage transistor NS 32 may be connected to the storage node SN, a first source/drain 322 thereof may be connected to the read word line RWL, and a second source/drain 323 thereof may be connected to the read bit line RBL.
In addition, as further described below in connection with fig. 4, in a write operation of the DRAM cell circuit 30, the write word line WWL operates at a first voltage VBB lower than the ground voltage VSS and a second voltage VPP higher than or equal to the power supply voltage VDD, according to an embodiment of the present disclosure.
Fig. 4 illustrates a signal timing diagram of an exemplary write method 400 of the DRAM cell circuit 30 shown in fig. 3.
As shown in fig. 4, a writing method 400 of a DRAM cell circuit 30 according to an embodiment of the present disclosure may include two steps, a first step (also referred to herein as a "writing step") S410 and a second step (also referred to herein as a "storing step") S420, which are sequentially performed.
As shown in fig. 4, in a first step S410, the write word line WWL is pulled down from the second voltage VPP to the first voltage VBB, causing the write transistor PW 31 to turn on, according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the first voltage VBB may be lower than the ground voltage VSS. Preferably, the first voltage VBB can be lower than the threshold voltage of the write transistor PW 31, i.e., VBB<Vth PW . Note that the threshold voltage Vth of the P-type write transistor PW 31 PW Is a negative voltage. Further, according to an embodiment of the present disclosure, the first voltage VBB may be higher than the threshold voltage Vth in consideration of the withstand voltage capability of the P-type write transistor PW 31 PW Twice as many as (x). That is, according to an embodiment of the present disclosure, the first voltage VBB may satisfy 2Vth PW <VBB<Vth PW <VSS. According to embodiments of the present disclosure, the first voltage VBB may be in the range of-1.2V to-0.4V.
Further, as shown in fig. 4, according to an embodiment of the present disclosure, in the first step S410, the write bit line WBL may be pulled up or pulled down from the equalizing voltage VBLQ to the power supply voltage VDD or the ground voltage VSS according to the write data being 1 or 0. According to the embodiment of the present disclosure, since the first voltage VBB at the gate electrode 311 of the write transistor PW 31 is lower than the threshold voltage Vth of the write transistor PW 31 PW Thus, the power supply voltage VDD or the ground voltage VSS representing data 1 or 0 can be entirely written to the storage node SN.
According to an embodiment of the present disclosure, the equalizing voltage VBLQ may be a voltage at an intersection point between a time-degraded voltage curve when the storage node SN stores data 0 and a time-degraded voltage curve when the storage node SN stores data 1. Setting the normal state of the write bit line WBL to the equalizing voltage VBLQ facilitates the memory degradation rate uniformity of the data 0 and 1, thereby extending the data memory time and facilitating the sense amplifier to set the reference voltage.
As shown in fig. 4, in a second step S420, the write word line WWL may be pulled up from the first voltage VBB to the second voltage VPP, such that the write transistor PW 31 is turned off, according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the second voltage VPP may be higher than or equal to the power supply voltage VDD. Further, according to an embodiment of the present disclosure, the second voltage VPP may be less than or equal to twice the power supply voltage VDD in consideration of the withstand voltage capability of the P-type write transistor PW 31. That is, according to embodiments of the present disclosure, the second voltage VPP may satisfy vdd+.vpp+.2vdd. According to an embodiment of the present disclosure, the second voltage VPP may be in a range of 0.8V to 3.6V. According to the embodiment of the present disclosure, the adoption of the second voltage VPP as the off-state voltage is advantageous in reducing the leakage current of the write transistor PW 31, thereby extending the data storage time, thereby reducing the frequency of interruption due to the refresh operation of the DRAM cell circuit 30, thereby reducing the power consumption of the DRAM cell circuit 30.
Further, according to an embodiment of the present disclosure, in the second step S420, the write bit line WBL may return the equalizing voltage VBLQ from the power supply voltage VDD or the ground voltage VSS representing data 1 or 0.
Accordingly, the writing method 400 of the DRAM cell circuit 30 according to the embodiment of the present disclosure may increase the 0/1 data voltage difference of the storage node SN to VDD-Vcou, where Vcou represents a voltage loss of the 0/1 data voltage difference due to the coupling effect existing between the gate 311 of the writing transistor PW 31 and the second source/drain 313, as compared to the related art.
Further, according to an embodiment of the present disclosure, during a write operation of the DRAM cell circuit 30, although not shown, the read word line RWL may be connected to the power supply voltage VDD, and the read bit line RBL may be connected to the power supply voltage VDD.
It should be noted that the method 400 of writing to the DRAM cell circuit 30 according to the embodiments of the present disclosure can be used for both a simple write operation of the DRAM cell circuit 30 and a write back operation in a refresh operation of the DRAM cell circuit 30.
FIG. 5 illustrates a signal timing diagram of another exemplary write method 500 of the DRAM cell circuit 30 shown in FIG. 3.
As shown in fig. 5, a writing method 500 of a DRAM cell circuit 30 according to an embodiment of the present disclosure may include three steps, namely a first step (also referred to herein as a "writing step") S510, a second step (also referred to herein as an "boosting step") S515, and a third step (also referred to herein as a "storing step") S520, which are sequentially performed.
As shown in fig. 5, according to an embodiment of the present disclosure, the first step S510 of the writing method 500 is substantially the same as the first step S410 of the writing method 400 described above, i.e., the writing word line WWL is pulled down from the second voltage VPP to the first voltage VBB such that the writing transistor PW 31 is turned on, and the writing bit line WBL may be pulled up or down from the equalizing voltage VBLQ to the power voltage VDD or the ground voltage VSS according to the writing data of 1 or 0 such that the power voltage VDD or the ground voltage VSS representing the data of 1 or 0 may be entirely written to the storage node SN. According to an embodiment of the present disclosure, the first voltage VBB may be lower than the ground voltage VSS. Preferably, the first voltage VBB can be lower than the threshold voltage of the write transistor PW 31, i.e., VBB<Vth PW . More preferably, the first voltage VBB may satisfy 2Vth PW <VBB<Vth PW <VSS。
Subsequently, as shown in fig. 5, in the second step S515, the write word line WWL is pulled up from the first voltage VBB to the third voltage VQQ according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the third voltage VQQ may be a certain voltage value between the first voltage VBB and the second voltage VPP. In order to make the write enhancement effect as described further below more efficient, according to embodiments of the present disclosure, the third voltage VQQ should place the write transistor PW 31 in a semi-conductive state, so the third voltage VQQ can be lower than the power supply voltage VDD and the (negative) threshold voltage Vth of the write transistor PW 31 PW And is higher than the threshold voltage Vth of the write transistor PW 31 PW Third voltage VQQ satisfies Vth PW <VQQ<VDD+Vth PW . Preferably, the third voltage VQQ can be equal to the ground voltage VSS, i.e., VQQ =vss=0v.
Further, as shown in fig. 5, according to an embodiment of the present disclosure, in the second step S515, the read word line RWL is pulled down from the power supply voltage VDD to the ground voltage VSS, while the write bit line WBL still holds the power supply voltage VDD or the ground voltage VSS according to the write data 1 or 0. At this time, as described above, since the write transistor PW 31 is in a semi-conductive stateIn a state, and the read word line RWL is pulled down to the ground voltage VSS, the voltage of the storage node SN is also pulled down accordingly. Since the write transistor PW 31 is capable of transmitting the high voltage representing the data 1, i.e., the power supply voltage VDD, to the storage node SN entirely, the voltage representing the data 1 may be gradually restored to the power supply voltage VDD after being pulled down. Further, since the write transistor PW 31 transfers the low voltage representing data 0, i.e., the ground voltage VSS, to the storage node SN due to the threshold voltage Vth PW While there is a voltage loss such that the voltage representing data 0 still maintains the voltage Vcs1 after pull-down. Here, vcs1 represents a potential drop of the storage node SN storing data 0 due to the read word line RWL being pulled down to the ground voltage VSS. Thus, according to an embodiment of the present disclosure, in the second step S515, a write enhancing effect of the storage node SN, that is, increasing the 0/1 data voltage difference of the storage node SN, may be achieved.
Subsequently, as shown in fig. 5, in a third step S520, the write word line WWL may be pulled up from the third voltage VQQ to the second voltage VPP such that the write transistor PW 31 is completely turned off, according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the second voltage VPP may be higher than or equal to the power supply voltage VDD. Preferably, the second voltage VPP may satisfy vdd.ltoreq.vpp.ltoreq.2vdd. Further, as shown in fig. 5, according to an embodiment of the present disclosure, in the third step S520, the read word line RWL may be pulled up from the ground voltage VSS to the power supply voltage VDD, and the write bit line WBL may return to the equalizing voltage VBLQ from the power supply voltage VDD or the ground voltage VSS representing data 1 or 0.
Accordingly, the writing method 500 of the DRAM cell circuit 30 according to the embodiment of the present disclosure may further increase the 0/1 data voltage difference of the storage node SN to vdd+vcs1-Vcou, as compared to the writing method 400 described above, wherein Vcs1 represents a potential drop of the storage node SN storing the data 0 caused by the read word line RWL being pulled down to the ground voltage VSS in the boosting step S515, and Vcou represents a voltage loss of the 0/1 data voltage difference caused by the coupling effect existing between the gate 311 and the second source/drain 313 of the writing transistor PW 31.
It should be noted that the method 500 of writing to the DRAM cell circuit 30 according to the embodiment of the present disclosure may be used for both a simple write operation of the DRAM cell circuit 30 and a write back operation in a refresh operation of the DRAM cell circuit 30.
Fig. 6 shows a circuit diagram of a configuration of an exemplary DRAM array circuit 60 including the DRAM cell circuit 30 shown in fig. 3.
As shown in fig. 6, a DRAM array circuit 60 according to an embodiment of the present disclosure may include a plurality of DRAM cell circuits. Specifically, as shown in FIG. 6, DRAM array circuit 60 may include N rows and M columns of identical DRAM cell circuits 30 as shown in FIG. 3, where M and N are natural numbers. For ease of description, some reference numerals in each DRAM cell circuit 30 are omitted from fig. 6. In addition, peripheral circuits of the DRAM array circuit 60, such as reference cells, sense amplifiers, and the like, are omitted from fig. 6 for convenience of description.
As shown in FIG. 6, DRAM array circuit 60 has N write word lines WWL [0] to WWL [ N-1] and N read word lines RWL [0] to RWL [ N-1] corresponding to N rows of DRAM cell circuits, according to an embodiment of the present disclosure. Further, as shown in FIG. 6, according to an embodiment of the present disclosure, DRAM array circuit 60 has M write bit lines WBL [0] through WBL [ M-1] and M read bit lines RBL [0] through RBL [ M-1] corresponding to M columns of DRAM cell circuits, respectively.
Fig. 7 shows a schematic diagram of an exemplary row driving method in a write operation of the DRAM array circuit 60 shown in fig. 6.
As shown in fig. 7, in the DRAM array circuit 60, enable signals wwl_en0 to wwl_en [ N-1] for driving N write word lines WWL [0] to WWL [ N-1] are obtained by decoding row address signals, thereby driving the respective write word lines WWL [0] to WWL [ N-1] by the respective N write word line drivers WWL DRV [0] to WWL DRV [ N-1], according to an embodiment of the present disclosure.
Further, as shown in fig. 7, in the DRAM array circuit 60, the enable signals rwl_en0 to rwl_en [ N-1] for driving the N read word lines RWL [0] to RWL [ N-1] are obtained by decoding the row address signals, so that the respective read word lines RWL [0] to RWL [ N-1] are driven by the respective N read word line drivers RWL [0] to RWL DRV [ N-1].
According to an embodiment of the present disclosure, when a write operation is performed on the DRAM array circuit 60 using the write method 400 described with reference to fig. 4, each of the N write word lines WWL [0] to WWL [ N-1] of the DRAM array circuit 60 may operate at the first voltage VBB and the second voltage VPP as described above.
Alternatively, according to an embodiment of the present disclosure, when a write operation is performed on the DRAM array circuit 60 using the write method 500 described with reference to fig. 5, as described above, each of the N write word lines WWL [0] to WWL [ N-1] of the DRAM array circuit 60 may operate at the first voltage VBB, the second voltage VPP, and the third voltage VQQ.
According to embodiments of the present disclosure, row driving operations in the write operation of the DRAM array circuit 60 may be implemented by a row-by-row driving manner.
In the row-by-row driving method according to the embodiment of the present disclosure, driving operations may be performed on N rows of DRAM cell circuits row by row according to row addresses as shown in table 1 below.
TABLE 1
Row address Corresponding WWL/RWL number
0 0
1 1
… …
N-2 N-2
N-1 N-1
Specifically, assume that the K-bit row address of DRAM array circuit 60 is A [ K-1:0]N rows of DRAM cell circuits corresponding to DRAM array circuit 60, i.e. 2 K-1 <N≤2 K Preferably, n=2 K . As described above, by counting row addresses a [ K-1:0 ]]Decoding can obtain WWL [0] for driving N write word lines]To WWL [ N-1]]Enable signal WWL_EN [0]]To WWL_EN [ N-1]]For driving N read word lines RWL [0]]To RWL [ N-1]]Enable signal RWL_EN [0]]To RWL_EN [ N-1]]。
Although embodiments of the present disclosure are described above in connection with fig. 3-7 taking the write transistor as a P-type transistor and the memory transistor as an N-type transistor as examples, it will be appreciated in the art that similar technical effects may still be achieved when implementing DRAM cell circuits according to the present disclosure with other types of transistors. An embodiment in which the write transistor is an N-type transistor will be described in detail below with reference to fig. 8 to 12.
Fig. 8 is a circuit diagram showing a configuration of a DRAM cell circuit 80 according to another embodiment of the present disclosure.
Unlike the DRAM cell circuit 30 according to the embodiment of the present disclosure shown in fig. 3, the DRAM cell circuit 80 according to the embodiment of the present disclosure shown in fig. 8 may include a write transistor NW 81 and a memory transistor NS 82, both of which are N-type. As shown in fig. 8, the gate 811 of the write transistor NW 81 may be connected to the write word line WWL, the first source/drain 812 thereof may be connected to the write bit line WBL, and the second source/drain 813 thereof may be connected to the storage node SN. Further, as shown in fig. 8, according to an embodiment of the present disclosure, a gate 821 of a storage transistor NS 82 may be connected to a storage node SN, a first source/drain 822 thereof may be connected to a read word line RWL, and a second source/drain 823 thereof may be connected to a read bit line RBL.
In addition, as further described below in connection with fig. 9, in a write operation of the DRAM cell circuit 80, the write word line WWL operates at a first voltage VBB lower than the ground voltage VSS and a second voltage VPP higher than or equal to the power supply voltage VDD, according to an embodiment of the present disclosure.
FIG. 9 illustrates a signal timing diagram of an exemplary write method 900 of the DRAM cell circuit 80 shown in FIG. 8.
As shown in fig. 9, a writing method 900 of a DRAM cell circuit 80 according to an embodiment of the present disclosure may include two steps, namely a first step (also referred to herein as a "writing step") S910 and a second step (also referred to herein as a "storing step") S920, which are sequentially performed.
As shown in fig. 9, in a first step S910, the write word line WWL is pulled up from the first voltage VBB to the second voltage VPP, so that the write transistor NW 81 is turned on. According to an embodiment of the present disclosure, the second voltage VPP may be higher than or equal to the power supply voltage VDD. Further, according to an embodiment of the present disclosure, the second voltage VPP may be less than or equal to twice the power supply voltage VDD in consideration of the withstand voltage capability of the N-type write transistor NW 81. That is, according to embodiments of the present disclosure, the second voltage VPP may satisfy vdd+.vpp+.2vdd. According to an embodiment of the present disclosure, the second voltage VPP may be in a range of 0.8V to 3.6V.
Further, as shown in fig. 9, according to an embodiment of the present disclosure, in the first step S910, the write bit line WBL may be pulled up or pulled down to the power supply voltage VDD or the ground voltage VSS by the equalizing voltage VBLQ according to the write data being 1 or 0. According to an embodiment of the present disclosure, the equalizing voltage VBLQ may be a voltage at an intersection point between a time-degraded voltage curve when the storage node SN stores data 0 and a time-degraded voltage curve when the storage node SN stores data 1. Setting the normal state of the write bit line WBL to the equalizing voltage VBLQ facilitates the memory degradation rate uniformity of the data 0 and 1, thereby extending the data memory time and facilitating the sense amplifier to set the reference voltage.
According to an embodiment of the present disclosure, in the first step S910, since the second voltage VPP is much higher than the threshold voltage Vth of the writing transistor NW 81 NW Thus representing data 0 orThe voltage of 1, i.e., the ground voltage VSS or the power supply voltage VDD, can be completely written to the storage node SN.
As shown in fig. 9, in a second step S920, the write word line WWL may be pulled down from the second voltage VPP to the first voltage VBB such that the write transistor NW 81 is turned off, according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the first voltage VBB may be lower than the ground voltage VSS. Further, according to the embodiment of the present disclosure, the first voltage VBB may be determined according to a voltage difference between the first voltage VPP and the second voltage VPP in consideration of the withstand voltage capability of the N-type writing transistor NW 81 to avoid breakdown of the gate 611 of the N-type writing transistor NW 61. Preferably, the first voltage VBB may be in the range of-1V to 0V. According to the embodiment of the present disclosure, the adoption of the first voltage VBB as the off-state voltage is advantageous in reducing the leakage current of the write transistor NW 81, thereby extending the data storage time, thereby reducing the frequency of interruption due to the refresh operation of the DRAM cell circuit 80, and thus reducing the power consumption of the DRAM cell circuit 80.
Further, according to an embodiment of the present disclosure, in the second step S920, the write bit line WBL may return the equalizing voltage VBLQ from the power supply voltage VDD or the ground voltage VSS representing data 1 or 0.
Accordingly, the writing method 900 of the DRAM cell circuit 80 according to the embodiment of the present disclosure may increase the 0/1 data voltage difference of the storage node SN to VDD-Vcou, where Vcou represents a voltage loss of the 0/1 data voltage difference due to the coupling effect existing between the gate 811 of the writing transistor NW 81 and the second source/drain 813, as compared to the related art.
Further, according to an embodiment of the present disclosure, during a write operation of the DRAM cell circuit 80, although not shown, the read word line RWL may be connected to the power supply voltage VDD, and the read bit line RBL may be connected to the power supply voltage VDD.
It should be noted that the method 900 of writing to the DRAM cell circuit 80 according to the embodiments of the present disclosure can be used for both a simple write operation of the DRAM cell circuit 80 and a write back operation in a refresh operation of the DRAM cell circuit 80.
FIG. 10 illustrates a signal timing diagram of another exemplary write method 1000 of the DRAM cell circuit 80 shown in FIG. 8.
As shown in fig. 10, a writing method 1000 of a DRAM cell circuit 80 according to an embodiment of the present disclosure may include three steps, namely a first step (also referred to herein as a "writing step") S1010, a second step (also referred to herein as an "boosting step") S1015, and a third step (also referred to herein as a "storing step") S1020, which are sequentially performed.
As shown in fig. 10, according to an embodiment of the present disclosure, a first step S1010 of the writing method 1000 is substantially the same as the first step S910 of the writing method 900 described above, i.e., the writing word line WWL is pulled up from the first voltage VBB to the second voltage VPP so that the writing transistor NW 81 is turned on, and the writing bit line WBL may be pulled up or down from the equalizing voltage VBLQ to the power supply voltage VDD or the ground voltage VSS according to the writing data of 1 or 0 so that the power supply voltage VDD or the ground voltage VSS representing the data of 1 or 0 may be entirely written to the storage node SN. According to an embodiment of the present disclosure, the first voltage VBB may be lower than the ground voltage VSS. Preferably, the first voltage VBB may be determined according to a voltage difference between it and the second voltage VPP to avoid breakdown of the gate 611 of the N-type write transistor NW 61. Preferably, the first voltage VBB may be in the range of-1V to 0V. According to an embodiment of the present disclosure, the second voltage VPP may be higher than or equal to the power supply voltage VDD. Preferably, the second voltage VPP satisfies VDD.ltoreq.VPP.ltoreq.2VDD.
The following is a more detailed description of the differences between the first step S1010 of the writing method 1000 and the first step S910 of the writing method 900 described above. As shown in fig. 10, according to an embodiment of the present disclosure, in a first step S1010, the read word line RWL may be pulled down from the power supply voltage VDD to the ground voltage VSS.
Subsequently, as shown in fig. 10, in a second step S1015, the write word line WWL is pulled down from the second voltage VPP to the third voltage VQQ according to an embodiment of the present disclosure. In order to make the write enhancement effect as described further below more efficient, according to embodiments of the present disclosure, the third voltage VQQ should place the write transistor NW 81 in a semi-conductive state, so the third voltage VQQ may be a writeInto the (positive) threshold voltage Vth of transistor NW 81 NW A certain voltage value between the second voltage VPP, i.e. the third voltage VQQ can satisfy Vth NW VQQ is less than or equal to VPP. Preferably, the third voltage VQQ can be equal to half the supply voltage VDD, i.e., VQQ =1/2 VDD.
Further, as shown in fig. 10, according to the embodiment of the present disclosure, in the second step S1015, the read word line RWL is pulled up from the ground voltage VSS to the power voltage VDD, while the write bit line WBL still maintains the power voltage VDD or the ground voltage VSS according to the write data 1 or 0. At this time, as described above, since the write transistor NW 81 is in a semi-conductive state and the read word line RWL is pulled up to the power supply voltage VDD, the voltage of the storage node SN is also pulled up. Since the write transistor NW 81 can transfer the low voltage representing the data 0, i.e., the ground voltage VSS, to the storage node SN entirely, the voltage representing the data 0 may be gradually restored to the ground voltage VSS after the pull-up. Further, since the write transistor NW 81 is due to the threshold voltage Vth when transmitting the high voltage representing the data 1, i.e., the power supply voltage VDD, to the storage node SN NW While there is a voltage loss such that the voltage representing data 1 still maintains the pulled-up voltage vdd+vcs2. Here, vcs2 represents a potential rise of the storage node SN storing the data 1 due to the read word line RWL being pulled up to the power supply voltage VDD. Thus, according to an embodiment of the present disclosure, in the second step S1015, a write enhancing effect of the storage node SN, that is, increasing the 0/1 data voltage difference of the storage node SN, may be achieved.
Subsequently, as shown in fig. 10, in a third step S1020, the write word line WWL may be pulled down from the third voltage VQQ to the first voltage VBB such that the write transistor NW 81 is completely turned off, according to an embodiment of the present disclosure. Further, as shown in fig. 10, according to an embodiment of the present disclosure, in the third step S1020, the read word line RWL may hold the power supply voltage VDD, and the write bit line WBL may return the equalizing voltage VBLQ from the power supply voltage VDD or the ground voltage VSS representing data 1 or 0.
Accordingly, the writing method 1000 of the DRAM cell circuit 80 according to the embodiment of the present disclosure may further increase the 0/1 data voltage difference of the storage node SN to vdd+vcs2-Vcou, where Vcs2 represents a potential rise of the storage node SN of the storage data 1 due to the read word line RWL being pulled up to the power supply voltage VDD in the boosting step S1015, and Vcou represents a voltage loss of the 0/1 data voltage difference due to the coupling effect existing between the gate 811 of the writing transistor NW 81 and the second source/drain 813, as compared to the writing method 900 described above.
It should be noted that the method 1000 of writing to the DRAM cell circuit 80 according to the embodiments of the present disclosure can be used for both a simple write operation of the DRAM cell circuit 80 and a write back operation in a refresh operation of the DRAM cell circuit 80.
Fig. 11 shows a circuit diagram of a configuration of an exemplary DRAM array circuit 110 including the DRAM cell circuit 80 shown in fig. 8.
As shown in fig. 11, a DRAM array circuit 110 according to an embodiment of the present disclosure may include a plurality of DRAM cell circuits. Specifically, as shown in FIG. 11, DRAM array circuit 110 may include N rows and M columns of identical DRAM cell circuits 80 as shown in FIG. 8, where M and N are natural numbers. For ease of description, some reference numerals in each DRAM cell circuit 80 are omitted from fig. 11. In addition, peripheral circuits of the DRAM array circuit 110, such as reference cells, sense amplifiers, and the like, are omitted in fig. 11 for convenience of description.
As shown in FIG. 11, DRAM array circuit 110 has N write word lines WWL [0] to WWL [ N-1] and N read word lines RWL [0] to RWL [ N-1] corresponding to N rows of DRAM cell circuits, according to an embodiment of the present disclosure. Further, as shown in FIG. 11, according to an embodiment of the present disclosure, DRAM array circuit 110 has M write bit lines WBL [0] through WBL [ M-1] and M read bit lines RBL [0] through RBL [ M-1] corresponding to M columns of DRAM cell circuits, respectively.
Fig. 12 shows a schematic diagram of an exemplary row driving method in a write operation of the DRAM array circuit 110 shown in fig. 11.
As shown in fig. 12, in the DRAM array circuit 110, enable signals wwl_en0 to wwl_en [ N-1] for driving N write word lines WWL [0] to WWL [ N-1] are obtained by decoding row address signals, thereby driving the respective write word lines WWL [0] to WWL [ N-1] by the respective N write word line drivers WWL DRV [0] to WWL DRV [ N-1], according to an embodiment of the present disclosure.
Further, as shown in fig. 12, in the DRAM array circuit 110, the enable signals rwl_en0 to rwl_en [ N-1] for driving the N read word lines RWL [0] to RWL [ N-1] are obtained by decoding the row address signals, so that the respective read word lines RWL [0] to RWL [ N-1] are driven by the respective N read word line drivers RWL [0] to RWL DRV [ N-1].
According to an embodiment of the present disclosure, when a write operation is performed on the DRAM array circuit 110 using the write method 900 described with reference to fig. 9, each of the N write word lines WWL [0] to WWL [ N-1] of the DRAM array circuit 110 may operate at the first voltage VBB and the second voltage VPP as described above.
Alternatively, according to an embodiment of the present disclosure, when a write operation is performed on the DRAM array circuit 110 using the write method 1000 described with reference to fig. 10, as described above, each of the N write word lines WWL [0] to WWL [ N-1] of the DRAM array circuit 110 may operate at the first voltage VBB, the second voltage VPP, and the third voltage VQQ.
The row driving method in the write operation of the DRAM array circuit 110 shown in fig. 12 may employ the same driving method as the row-by-row driving method in the write operation of the DRAM array circuit 60 described above with reference to fig. 7, and thus will not be described in detail herein.
According to the DRAM array circuit disclosed by the invention, the multi-stage voltage (VPP, VBB and VQQ) operation of the write word line WWL is performed, and the signal control of the write word line RWL is introduced to fully enhance the 0/1 data voltage difference in the DRAM unit circuit by utilizing the gate-source coupling capacitance and the gate-drain coupling capacitance of the storage transistor, so that the problems that the data writing of the storage node is incomplete and the 0/1 data voltage difference is smaller due to the threshold voltage existing in the write specific tube and the gate-source coupling capacitance of the write specific tube are solved, the data storage time is prolonged, the frequency of interruption due to the refresh operation is further reduced, and the power consumption of the whole circuit is reduced. In particular, DRAM array circuits according to the present disclosure are particularly suitable for on-chip embedded applications.
The foregoing has been presented for purposes of illustration a limited number of possible embodiments of the present disclosure. Although the present disclosure has been described with reference to the embodiments thereof, those skilled in the art will understand that various modifications and changes may be made thereto without departing from the spirit and scope of the disclosure as disclosed in the appended claims.
Although numerous details are contained herein, these details should not be construed as limitations on the scope of the disclosure or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Claims (10)

1. A dynamic random access memory array circuit comprises N rows and M columns of dynamic random access memory cell circuits, wherein M and N are natural numbers greater than zero,
wherein each of the dynamic random access memory cell circuits includes: a write transistor having a gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to the storage node; and a memory transistor having a gate connected to the memory node, a first source/drain connected to a read word line, and a second source/drain connected to a read bit line,
wherein, in the write operation, the write word line operates at a first voltage lower than a ground voltage and a second voltage higher than or equal to a power supply voltage.
2. The DRAM array circuit according to claim 1,
wherein, in a write operation, the write word line operates at the first voltage, the second voltage, and a third voltage between the first voltage and the second voltage.
3. The dynamic random access memory array circuit according to claim 1 or 2,
wherein in each of the dynamic random access memory cell circuits, the write transistor is a P-type transistor and the storage transistor is an N-type transistor.
4. The DRAM array circuit according to claim 3,
wherein the first voltage is lower than the threshold voltage of the write transistor and higher than twice the threshold voltage of the write transistor, and
wherein the second voltage is less than or equal to twice the supply voltage.
5. The DRAM array circuit according to claim 3,
wherein the third voltage is lower than a sum of a power supply voltage and a threshold voltage of the write transistor and is higher than the threshold voltage of the write transistor.
6. The DRAM array circuit according to claim 3,
wherein, in a write operation, the read word line is operated at a ground voltage when the write word line is operated at the third voltage, and the read word line is operated at a power supply voltage when the write word line is not operated at the third voltage.
7. The dynamic random access memory array circuit according to claim 1 or 2,
wherein, in each of the dynamic random access memory cell circuits, the write transistor and the memory transistor are both N-type transistors.
8. The DRAM array circuit according to claim 7,
Wherein the first voltage is determined according to a voltage difference between the first voltage and the second voltage to avoid breakdown of the gate of the write transistor, and
wherein the second voltage is less than or equal to twice the supply voltage.
9. The DRAM array circuit according to claim 7,
wherein the third voltage is lower than or equal to the second voltage and higher than or equal to a threshold voltage of the write transistor.
10. The DRAM array circuit according to claim 7,
wherein, in a write operation, the read word line is operated at a ground voltage when the write word line is operated at the second voltage, and the read word line is operated at a power supply voltage when the write word line is not operated at the second voltage.
CN202310485805.9A 2023-04-28 2023-04-28 Dynamic random access memory array circuit Pending CN116631468A (en)

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