CN116629713A - Performance evaluation method of wafer-level chip system - Google Patents
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Abstract
The disclosure relates to a performance evaluation method, a device, an electronic device and a storage medium of a wafer level chip system. Wherein the method comprises the following steps: analyzing the wafer-level chip system to construct a wafer-level chip system evaluation index set, wherein the wafer-level chip system evaluation index set comprises wafer-level chip system evaluation indexes; constructing a wafer-level chip system weight system, and establishing a performance evaluation model of the wafer-level chip system based on the wafer-level chip system weight system; and taking parameter index values corresponding to the wafer-level chip system evaluation index set as input, and completing performance evaluation of the wafer-level chip system based on the performance evaluation model of the wafer-level chip system. The method and the device establish the performance evaluation model of the wafer-level chip system by constructing the evaluation index set and the weight system, and the performance evaluation model evaluates the wafer-level chip system architecture, so that support can be provided for heuristic optimization of the system architecture.
Description
Technical Field
The present disclosure relates to the field of performance evaluation of wafer-level chip systems, and more particularly, to a method, an apparatus, an electronic device, and a computer-readable storage medium for performance evaluation of a wafer-level chip system.
Background
The software-defined wafer-level chip takes structure adaptation application as a guiding idea, integrates software and hardware collaborative architecture innovation on the basis of wafer integration process innovation, and realizes the unification of high flexibility and high efficiency of application in the field. The wafer-level chip integrates heterogeneous resources with different functions and mixed granularity, and has the characteristics of large resource scale, high integration density, high dynamic matching of tasks and resources and the like. Because the system on chip architecture can be reconstructed and iteratively optimized according to heterogeneous resources and application requirements, an efficient and accurate architecture design evaluation method is required for supporting.
The existing system performance evaluation methods are all special index sets designed for specific information systems, and the index sets cannot cover all the characteristics of the wafer-level chip system and cannot accurately evaluate the wafer-level chip system. In order to promote the efficient development of integrated software and hardware architecture design, a wafer-level chip system performance evaluation framework is needed to be designed, the system-on-chip architecture design scheme is comprehensively and objectively evaluated, and scientific data reference is provided for further optimization of the wafer-level chip software and hardware collaborative design.
Accordingly, there is a need for one or more approaches to address the above-described problems.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The disclosure provides a performance evaluation method, a device, an electronic device and a computer readable storage medium for a wafer level chip system, which can be used for quantitatively evaluating design schemes in the process of designing the wafer level chip system, so as to guide iterative optimization of the wafer level chip system architecture design.
According to one aspect of the present disclosure, there is provided a performance evaluation method of a wafer level chip system, including:
analyzing the wafer-level chip system to construct a wafer-level chip system evaluation index set, wherein the wafer-level chip system evaluation index set comprises wafer-level chip system evaluation indexes;
constructing a wafer-level chip system weight system, and establishing a performance evaluation model of the wafer-level chip system based on the wafer-level chip system weight system;
and taking parameter index values corresponding to the wafer-level chip system evaluation index set as input, and completing performance evaluation of the wafer-level chip system based on the performance evaluation model of the wafer-level chip system.
In an exemplary embodiment of the present disclosure, the method further comprises:
analyzing the wafer-level chip system to construct an initial evaluation index set of the wafer-level chip system;
performing grading treatment on the wafer-level chip system initial evaluation index set based on a special method;
carrying out structured quantitative treatment on unstructured indexes in the initial evaluation index set of the wafer-level chip system;
and performing redundancy elimination processing on the initial evaluation index set of the wafer-level chip system to generate the evaluation index set of the wafer-level chip system.
In an exemplary embodiment of the present disclosure, the method further comprises:
and analyzing the wafer-level chip system, and constructing an initial evaluation index set of the wafer-level chip system based on the system performance, the system architecture and the wafer-level chip physical limit parameters.
In an exemplary embodiment of the present disclosure, the method further comprises:
and carrying out grading treatment on the wafer-level chip system initial evaluation index set based on a special method to finish the expansion of the hierarchical structure of the wafer-level chip system initial evaluation index set.
In an exemplary embodiment of the present disclosure, the method further comprises:
carrying out structured quantitative treatment on unstructured indexes in the initial evaluation index set of the wafer-level chip system based on a quantization method or a preset index substitution method;
and comprehensively analyzing the multi-standard prefabricated members in the initial evaluation index set of the wafer-level chip system, and confirming the appointed standard of the initial evaluation index set of the wafer-level chip system.
In an exemplary embodiment of the present disclosure, the method further comprises:
and performing redundancy elimination processing on the initial evaluation index set of the wafer-level chip system based on a conditional attribute reduction algorithm to generate the evaluation index set of the wafer-level chip system.
In an exemplary embodiment of the present disclosure, the method further comprises:
generating a first set of weights based on performance test data of a wafer level chip system of a preset heterogeneous platform;
weighting an index system of the wafer-level chip system evaluation index set based on an analytic hierarchy process in the subjective weighting method to generate a second group of weights;
and fusing the first group of weights and the second group of weights based on the subjective and objective weight fusion method of the Euclidean distance, and establishing a performance evaluation model of the wafer-level chip system.
In one aspect of the present disclosure, there is provided a performance evaluation apparatus of a wafer level chip system, comprising:
the index set construction module is used for analyzing the wafer-level chip system and constructing a wafer-level chip system evaluation index set, wherein the wafer-level chip system evaluation index set comprises wafer-level chip system evaluation indexes;
the performance evaluation modeling module is used for constructing a wafer-level chip system weight system and establishing a performance evaluation model of the wafer-level chip system based on the wafer-level chip system weight system;
and the performance evaluation module is used for taking the parameter index value corresponding to the wafer-level chip system evaluation index set as input and completing the performance evaluation of the wafer-level chip system based on the performance evaluation model of the wafer-level chip system.
In one aspect of the present disclosure, there is provided an electronic device comprising:
a processor; and
a memory having stored thereon computer readable instructions which, when executed by the processor, implement a method according to any of the above.
In one aspect of the present disclosure, a computer readable storage medium is provided, on which a computer program is stored, which when executed by a processor, implements a method according to any of the above.
A method for evaluating performance of a wafer level chip system in an exemplary embodiment of the present disclosure, wherein the method comprises: analyzing the wafer-level chip system to construct a wafer-level chip system evaluation index set, wherein the wafer-level chip system evaluation index set comprises wafer-level chip system evaluation indexes; constructing a wafer-level chip system weight system, and establishing a performance evaluation model of the wafer-level chip system based on the wafer-level chip system weight system; and taking parameter index values corresponding to the wafer-level chip system evaluation index set as input, and completing performance evaluation of the wafer-level chip system based on the performance evaluation model of the wafer-level chip system. The method and the device establish the performance evaluation model of the wafer-level chip system by constructing the evaluation index set and the weight system, and the performance evaluation model evaluates the wafer-level chip system architecture, so that support can be provided for heuristic optimization of the system architecture.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
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The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
FIG. 1 illustrates a flowchart of a method of performance evaluation of a wafer level chip system according to an exemplary embodiment of the present disclosure;
FIG. 2 illustrates a block diagram of a device for performance evaluation of a wafer level chip system according to an exemplary embodiment of the present disclosure;
FIG. 3 schematically illustrates a block diagram of an electronic device according to an exemplary embodiment of the present disclosure; and
fig. 4 schematically illustrates a schematic diagram of a computer-readable storage medium according to an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, components, materials, devices, steps, etc. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.
In the present exemplary embodiment, a method for evaluating performance of a wafer level chip system is provided first; referring to fig. 1, the method for evaluating the performance of the wafer level chip system may include the following steps:
step S110, analyzing a wafer-level chip system to construct a wafer-level chip system evaluation index set, wherein the wafer-level chip system evaluation index set comprises wafer-level chip system evaluation indexes;
step S120, a wafer-level chip system weight system is built, and a performance evaluation model of the wafer-level chip system is built based on the wafer-level chip system weight system;
step S130, taking the parameter index value corresponding to the wafer level chip system evaluation index set as input, and completing the performance evaluation of the wafer level chip system based on the performance evaluation model of the wafer level chip system.
A method for evaluating performance of a wafer level chip system in an exemplary embodiment of the present disclosure, wherein the method comprises: analyzing the wafer-level chip system to construct a wafer-level chip system evaluation index set, wherein the wafer-level chip system evaluation index set comprises wafer-level chip system evaluation indexes; constructing a wafer-level chip system weight system, and establishing a performance evaluation model of the wafer-level chip system based on the wafer-level chip system weight system; and taking parameter index values corresponding to the wafer-level chip system evaluation index set as input, and completing performance evaluation of the wafer-level chip system based on the performance evaluation model of the wafer-level chip system. The method and the device establish the performance evaluation model of the wafer-level chip system by constructing the evaluation index set and the weight system, and the performance evaluation model evaluates the wafer-level chip system architecture, so that support can be provided for heuristic optimization of the system architecture.
Next, a method for evaluating the performance of a wafer level chip system in this exemplary embodiment will be further described.
Embodiment one:
in step S110, the wafer level chip system may be analyzed to construct a wafer level chip system evaluation index set, which includes wafer level chip system evaluation indexes.
In an embodiment of the present example, the method further comprises:
analyzing the wafer-level chip system to construct an initial evaluation index set of the wafer-level chip system;
performing grading treatment on the wafer-level chip system initial evaluation index set based on a special method;
carrying out structured quantitative treatment on unstructured indexes in the initial evaluation index set of the wafer-level chip system;
and performing redundancy elimination processing on the initial evaluation index set of the wafer-level chip system to generate the evaluation index set of the wafer-level chip system.
In an embodiment of the present example, the method further comprises:
and analyzing the wafer-level chip system, and constructing an initial evaluation index set of the wafer-level chip system based on the system performance, the system architecture and the wafer-level chip physical limit parameters.
In an embodiment of the present example, the method further comprises:
and carrying out grading treatment on the wafer-level chip system initial evaluation index set based on a special method to finish the expansion of the hierarchical structure of the wafer-level chip system initial evaluation index set.
In an embodiment of the present example, the method further comprises:
carrying out structured quantitative treatment on unstructured indexes in the initial evaluation index set of the wafer-level chip system based on a quantization method or a preset index substitution method;
and comprehensively analyzing the multi-standard prefabricated members in the initial evaluation index set of the wafer-level chip system, and confirming the appointed standard of the initial evaluation index set of the wafer-level chip system.
In an embodiment of the present example, the method further comprises:
and performing redundancy elimination processing on the initial evaluation index set of the wafer-level chip system based on a conditional attribute reduction algorithm to generate the evaluation index set of the wafer-level chip system.
In step S120, a wafer level chip system weight system may be constructed, and a performance evaluation model of the wafer level chip system may be established based on the wafer level chip system weight system.
In an embodiment of the present example, a first set of weights is generated based on performance test data of a wafer level chip system of a preset heterogeneous platform;
weighting an index system of the wafer-level chip system evaluation index set based on an analytic hierarchy process in the subjective weighting method to generate a second group of weights;
and fusing the first group of weights and the second group of weights based on the subjective and objective weight fusion method of the Euclidean distance, and establishing a performance evaluation model of the wafer-level chip system.
In step S130, the performance evaluation of the wafer level chip system may be completed based on the performance evaluation model of the wafer level chip system by using the parameter index value corresponding to the evaluation index set of the wafer level chip system as an input.
In the embodiment of the present example, the parameter index values corresponding to the wafer level chip system evaluation index set include, but are not limited to, a system architecture, a running time, a running power consumption, a preform area, a number, and the like of the wafer level chip system.
In the embodiment of the present example, the conventional performance evaluation manner is mostly aimed at a specific system, and cannot fully reflect the performance index and the reference performance index of the on-chip reconfigurable system, so as to solve the above problem, to implement accurate, comprehensive and convenient evaluation on the comprehensive performance of the software and hardware of the ultra-high density mixed granularity reconfigurable wafer level chip, and to study the performance evaluation framework of the grain reconfigurable system, specifically including the multi-dimensional special evaluation index system construction technology, the measurement method of unstructured data in index set, and scientific and reasonable comprehensive performance evaluation model construction aiming at the characteristics of the reconfigurable, high performance and flexible architecture of the wafer level chip system. The evaluation results can provide support for subsequent optimization of the wafer-level chip system architecture.
Embodiment two:
in the exemplary embodiment, the performance evaluation framework of the present disclosure is composed of two parts, namely a wafer-level system-on-chip index set and weights corresponding to the indices.
In an embodiment of the present example, constructing the evaluation index set includes:
firstly, the characteristics of a wafer-level chip system are required to be analyzed and further described, index mining is carried out from different layers of an evaluation target, and an initial index set is obtained according to the logic relationship among elements in an index system. Compared with other heterogeneous systems, the wafer-level chip system is structurally adaptive, the network structure is more flexible and changeable, the system architecture is more complex, the physical form is greatly different from that of the existing heterogeneous system, the interconnection mode and time delay of heterogeneous units are greatly different, and the power consumption, heat dissipation and area caused by stacking of core particles are greatly different, so that an index set needs to be constructed from three aspects of system performance, system architecture and wafer-level chip physical limitation during evaluation. That is, in addition to evaluating some performance indexes of heterogeneous systems, such as floating point computing capability, multithreading capability, memory access speed, etc., factors such as applicability of the current wafer-level chip system architecture to applications, utilization of various resources, and actual power consumption, heat dissipation, die stacking mode, wafer area, and time delay of interconnection communication of the wafer-level chips need to be considered.
And secondly, after the index set of the initial version is determined, further perfecting the index by using an expert method, expanding the index, determining the upper and lower relationship of the index, and determining the interrelationship among the indexes of each level to form an index system level structure. The importance of the evaluation indexes of the same level is basically consistent, and the evaluation content and the efficiency are not overlapped in a crossing way and are in contradiction; the evaluation index of the next level should be a component of the evaluation index of the previous level, and the evaluation content and the performance should not exceed the range corresponding to the index of the previous level.
Thirdly, researching an unstructured data quantification method or an index alternative scheme for indexes of some unstructured data formats, and converting the unstructured data quantification method or the index alternative scheme into quantitative indexes; if the prefabricated members with different indexes have different standards, comprehensive analysis is performed, and the unique standard of the index is selected. Finally, the quantitative and rationing of the evaluation contents of each evaluation index are realized, and visual presentation and comparison can be realized.
Finally, the existing index sets are optimized, one index set is comprehensive and has no redundancy, but the more comprehensive the indexes are, the greater the number of indexes is, the greater the overlapping degree of the indexes is possible, and some unimportant indexes are also possibly included, so that the evaluation accuracy is affected. Therefore, the comprehensiveness and the evaluation precision of the index are required to be balanced, redundant indexes are removed, and the index optimization is completed. And the attribute reduction theory in the rough set is adopted as a support, and the attribute reduction algorithm based on the condition is used to ensure the rationality of the reduction result.
In an embodiment of the present example, constructing the weighting system includes:
firstly, more than one heterogeneous platform needs to be constructed, and whether a constructed index system can cover the evaluation index of the heterogeneous platform is checked; and weighting the index system by using a weight calculation method based on the rough set according to the test data of the platforms, thereby obtaining a first group of weights.
And secondly, weighting the index system by using an Analytic Hierarchy Process (AHP) in a subjective weighting method to obtain a second group of weights.
According to the obtained two groups of weights, the difference between the two groups of weights is reduced as much as possible based on the subjective and objective weight fusion method of Euclidean distance, and the fused weights are obtained. And according to the constructed index system and the weights, completing the mathematical model of the evaluation model. And tests are carried out on different heterogeneous platforms for multiple times, so that the validity of the evaluation result is ensured.
In the embodiment of the present example, the evaluation method evaluates the wafer-level chip system architecture, and may provide support for heuristic optimization of the system architecture; the evaluation method can evaluate various heterogeneous resources, and under the conditions of determining the system architecture and the test application, the power consumption, the computing performance, the resource utilization rate, the computing precision and the like of the system are tested; the evaluation method is used for evaluating physical factors of the wafer-level chip and can be used for verifying the authenticity of the simulation result.
It should be noted that although the steps of the methods of the present disclosure are illustrated in the accompanying drawings in a particular order, this does not require or imply that the steps must be performed in that particular order or that all of the illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.
In addition, in the present exemplary embodiment, a performance evaluation apparatus of a wafer level chip system is also provided. Referring to fig. 2, the performance evaluation apparatus 200 of the wafer level chip system may include: the index set construction module 210, the performance evaluation modeling module 220, and the performance evaluation module 230. Wherein:
the index set construction module 210 is configured to analyze the wafer level chip system and construct a wafer level chip system evaluation index set, where the wafer level chip system evaluation index set includes wafer level chip system evaluation indexes;
the performance evaluation modeling module 220 is configured to construct a wafer level chip system weight system, and based on the wafer level chip system weight system, establish a performance evaluation model of the wafer level chip system;
the performance evaluation module 230 is configured to complete performance evaluation of the wafer level chip system based on the performance evaluation model of the wafer level chip system by taking the parameter index value corresponding to the evaluation index set of the wafer level chip system as an input.
The details of the performance evaluation device module of a wafer level chip system are described in detail in the corresponding performance evaluation method of a wafer level chip system, and thus are not repeated here.
It should be noted that although several modules or units of the performance evaluation apparatus 200 of a wafer level chip system are mentioned in the above detailed description, this division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
In addition, in an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.
Those skilled in the art will appreciate that the various aspects of the application may be implemented as a system, method, or program product. Accordingly, aspects of the application may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.
An electronic device 300 according to such an embodiment of the application is described below with reference to fig. 3. The electronic device 300 shown in fig. 3 is merely an example and should not be construed as limiting the functionality and scope of use of embodiments of the present application.
As shown in fig. 3, the electronic device 300 is embodied in the form of a general purpose computing device. Components of electronic device 300 may include, but are not limited to: at least one processing unit 310, at least one memory unit 320, a bus 330 connecting the different system components, including the memory unit 320 and the processing unit 310, a display unit 340.
Wherein the storage unit 320 stores program code executable by the processing unit 310 such that the processing unit 310 performs the steps according to various exemplary embodiments of the present application described in the above methods of the present specification. For example, the processing unit 310 may perform steps S110 to S130 as shown in fig. 1.
Storage unit 320 may include readable media in the form of volatile storage units, such as Random Access Memory (RAM) 3201 and/or cache memory 3202, and may further include Read Only Memory (ROM) 3203.
The storage unit 320 may also include a program/utility 3204 having a set (at least one) of program modules 3205, such program modules 3205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.
Bus 330 may be one or more of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.
The electronic device 300 may also communicate with one or more external devices 370 (e.g., keyboard, pointing device, bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 300, and/or any device (e.g., router, modem, etc.) that enables the electronic device 300 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 350. Also, electronic device 300 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet, through network adapter 360. As shown, the network adapter 360 communicates with other modules of the electronic device 300 over the bus 330. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 300, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, and includes several instructions to cause a computing device (may be a personal computer, a server, a terminal device, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.
In an exemplary embodiment of the present disclosure, a computer-readable storage medium having stored thereon a program product capable of implementing the method described above in the present specification is also provided. In some possible embodiments, the various aspects of the application may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps according to the various exemplary embodiments of the application as described in the "exemplary methods" section of this specification, when said program product is run on the terminal device.
Referring to fig. 4, a program product 400 for implementing the above-described method according to an embodiment of the present application is described, which may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable signal medium may include a data signal propagated in baseband or as part of a carrier wave with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).
Furthermore, the above-described drawings are only schematic illustrations of processes included in the method according to the exemplary embodiment of the present application, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A method for evaluating performance of a wafer level chip system, the method comprising:
analyzing the wafer-level chip system to construct a wafer-level chip system evaluation index set, wherein the wafer-level chip system evaluation index set comprises wafer-level chip system evaluation indexes;
constructing a wafer-level chip system weight system, and establishing a performance evaluation model of the wafer-level chip system based on the wafer-level chip system weight system;
and taking parameter index values corresponding to the wafer-level chip system evaluation index set as input, and completing performance evaluation of the wafer-level chip system based on the performance evaluation model of the wafer-level chip system.
2. The method of claim 1, wherein the method further comprises:
analyzing the wafer-level chip system to construct an initial evaluation index set of the wafer-level chip system;
performing grading treatment on the wafer-level chip system initial evaluation index set based on a special method;
carrying out structured quantitative treatment on unstructured indexes in the initial evaluation index set of the wafer-level chip system;
and performing redundancy elimination processing on the initial evaluation index set of the wafer-level chip system to generate the evaluation index set of the wafer-level chip system.
3. The method of claim 2, wherein the method further comprises:
and analyzing the wafer-level chip system, and constructing an initial evaluation index set of the wafer-level chip system based on the system performance, the system architecture and the wafer-level chip physical limit parameters.
4. The method of claim 2, wherein the method further comprises:
and carrying out grading treatment on the wafer-level chip system initial evaluation index set based on a special method to finish the expansion of the hierarchical structure of the wafer-level chip system initial evaluation index set.
5. The method of claim 2, wherein the method further comprises:
carrying out structured quantitative treatment on unstructured indexes in the initial evaluation index set of the wafer-level chip system based on a quantization method or a preset index substitution method;
and comprehensively analyzing the multi-standard prefabricated members in the initial evaluation index set of the wafer-level chip system, and confirming the appointed standard of the initial evaluation index set of the wafer-level chip system.
6. The method of claim 2, wherein the method further comprises:
and performing redundancy elimination processing on the initial evaluation index set of the wafer-level chip system based on a conditional attribute reduction algorithm to generate the evaluation index set of the wafer-level chip system.
7. The method of claim 1, wherein the method further comprises:
generating a first set of weights based on performance test data of a wafer level chip system of a preset heterogeneous platform;
weighting an index system of the wafer-level chip system evaluation index set based on an analytic hierarchy process in the subjective weighting method to generate a second group of weights;
and fusing the first group of weights and the second group of weights based on the subjective and objective weight fusion method of the Euclidean distance, and establishing a performance evaluation model of the wafer-level chip system.
8. A performance evaluation apparatus for a wafer level chip system, the apparatus comprising:
the index set construction module is used for analyzing the wafer-level chip system and constructing a wafer-level chip system evaluation index set, wherein the wafer-level chip system evaluation index set comprises wafer-level chip system evaluation indexes;
the performance evaluation modeling module is used for constructing a wafer-level chip system weight system and establishing a performance evaluation model of the wafer-level chip system based on the wafer-level chip system weight system;
and the performance evaluation module is used for taking the parameter index value corresponding to the wafer-level chip system evaluation index set as input and completing the performance evaluation of the wafer-level chip system based on the performance evaluation model of the wafer-level chip system.
9. An electronic device, comprising
A processor; and
a memory having stored thereon computer readable instructions which, when executed by the processor, implement the method according to any of claims 1 to 7.
10. A computer-readable storage medium, characterized in that a computer program is stored thereon, which computer program, when being executed by a processor, implements the method according to any of claims 1 to 7.
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