CN116627894A - Medium access control layer, communication method and system - Google Patents
Medium access control layer, communication method and system Download PDFInfo
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Abstract
The application relates to a medium access control layer, a communication method and a system, wherein the medium access control layer comprises the following components: a data link protocol bridge module for establishing a logical data link between the on-chip communication interface and the inter-chip communication interface; the medium access controller module is used for encoding the on-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface and transmitting the frame data to the inter-chip communication interface; and the configuration module is used for receiving and analyzing the configuration packet transmitted by the data link protocol bridge module so as to configure the inter-chip communication interface. The application solves the problem that the medium access control layer cannot be compatible with various chip communication interfaces with different specifications on the market, and cannot be reused.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a medium access control layer, a communication method, and a system.
Background
To address the large chip manufacturing problem, chiplet technology has grown, which is also known as "Chiplet" or "die," which is a functional circuit block. The chip technology is used for respectively manufacturing the small functional blocks by splitting the chip, and then realizing interconnection among the functional blocks through a chip interface protocol and an advanced packaging technology, so that the manufacturability problem of a large chip is avoided, and the problems of high cost and long construction period of an application specific integrated circuit (Application Specific Integrated Circuit, ASIC) design are reduced. Chiplet technology has become a popular technology.
In addition, in recent years, many-core architecture is increasingly widely applied, and the core of many-core design is to fully develop high-performance computing power on chip, which is also a necessary development trend of high-performance computing. Many-core processors in possession today contain a large number of separate cores and tightly coupled memory interconnected by a high-speed Network on Chip (NoC) infrastructure. From the point of view of the open system interconnection model (Open System Interconnect, OSI), the inter-chip-to-chip protocol belongs to the physical layer protocol, while the communication network inside the chip belongs to the network layer component, both layers requiring the data link layer as an intermediary on the model, such component requiring the provision of the medium access control layer (MediaAccess Control, MAC).
The MAC belongs to a sub-layer in the data link layer in OSI, but it has the feature of coupling with the physical layer, and different physical media correspond to completely different MAC protocols and circuit module designs. Existing MAC modules for other scenarios (e.g., ethernet MAC as defined by IEEE-802.3) are almost impossible to use directly for inter-chip communication scenarios. Meanwhile, the chip communication interfaces with different specifications are available in the market, the bit width, the communication rate and the clock frequency of the interfaces are very different, the communication interfaces around the core particle are generally located in different clock domains with circuits inside the core particle, the currently provided medium access control layer cannot be compatible with the chip communication interfaces with different specifications in the market, and the medium access control layer cannot be reused.
Aiming at the problem that the medium access control layer cannot be compatible with various inter-chip communication interfaces with different specifications on the market and cannot be reused in the related art, no effective solution is proposed at present.
Disclosure of Invention
Based on this, it is necessary to provide a medium access control layer, a communication method and a system for solving the above technical problems.
In a first aspect, an embodiment of the present application provides a medium access control layer, where the medium access control layer is connected between an intra-chip communication interface and an inter-chip communication interface of a core, where the medium access control layer includes:
a data link protocol bridge module for establishing a logical data link between the on-chip communication interface and the inter-chip communication interface;
the medium access controller module is connected with the data link protocol bridge module and is used for receiving the on-chip communication interface data transmitted by the data link protocol bridge module, encoding the on-chip communication interface data into frame data corresponding to the specification of the on-chip communication interface and transmitting the frame data to the on-chip communication interface;
and the configuration module is connected with the data link protocol bridge module and is used for receiving and analyzing the configuration packet transmitted by the data link protocol bridge module so as to configure the inter-chip communication interface.
In one embodiment, the medium access controller module includes a first frame encoder, configured to encode the intra-chip communication interface data into frame data corresponding to a specification of the inter-chip communication interface according to a bit width and a clock frequency corresponding to the inter-chip communication interface.
In one embodiment, the medium access controller module further includes a first arbiter, configured to arbitrate the on-chip communication interface data according to a subnet priority corresponding to the on-chip communication interface data and a data link protocol bridge module priority corresponding to the on-chip communication interface data.
In one embodiment, the data link protocol bridge module comprises:
the first data processing module is used for receiving and processing the on-chip communication interface data and transmitting the processed on-chip communication interface data to the medium access controller module;
and the second arbiter is used for arbitrating the on-chip communication interface data according to whether the subnet corresponding to the on-chip communication interface data holds downstream messages and the subnet priority corresponding to the on-chip communication interface data.
In one embodiment, the data processing module includes:
the first memory is used for storing the on-chip communication interface data;
the multiplexer is used for outputting corresponding on-chip communication interface data according to the arbitration result obtained by the second arbiter;
and the second frame encoder is used for encoding the intra-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface.
In one embodiment, the data link protocol bridge module further includes a second data processing module, configured to receive and process the inter-chip communication interface data transmitted by the medium access controller module, and transmit the processed inter-chip communication interface data to the intra-chip communication interface.
In one embodiment, the second data processing module includes: the device comprises a frame decoder, a demultiplexer and a second memory, wherein the frame decoder is used for decoding inter-chip communication interface data transmitted by the medium access controller module; the demultiplexer is configured to input the inter-chip communication interface data to the second memory for storage according to the source of the inter-chip communication interface data.
In a second aspect, an embodiment of the present application further provides a communication method based on a medium access control layer, where the method includes:
receiving the on-chip communication interface data transmitted by the data link protocol bridge module;
encoding the intra-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface;
the frame data is transmitted to the inter-chip communication interface.
In one embodiment, the method further comprises:
receiving inter-chip communication interface data transmitted by the medium access control module;
and decoding the inter-chip communication interface data and transmitting the inter-chip communication interface data to the inter-chip communication interface according to a source corresponding to the inter-chip communication interface data.
In a third aspect, an embodiment of the present application further provides an inter-chip communication system, including a first medium access control layer and a second medium access control layer, where the first medium access control layer is communicatively connected to the second medium access control layer; the first medium access control layer and/or the second medium access control layer implement the method as described in the second aspect above.
The medium access control layer, the communication method and the system are used for establishing a logic data link between the on-chip communication interface and the inter-chip communication interface through a data link protocol bridge module; the medium access controller module is connected with the data link protocol bridge module and is used for receiving the on-chip communication interface data transmitted by the data link protocol bridge module, encoding the on-chip communication interface data into frame data corresponding to the specification of the on-chip communication interface and transmitting the frame data to the on-chip communication interface; and the configuration module is connected with the data link protocol bridge module and is used for receiving and analyzing the configuration packet transmitted by the data link protocol bridge module so as to configure the inter-chip communication interface. The method solves the problem that the medium access control layer cannot be compatible with various inter-chip communication interfaces with different specifications on the market, and the medium access control layer cannot be reused.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a diagram of a medium access control layer structure according to an embodiment of the present application;
FIG. 2 is a diagram of a medium access control layer structure according to another embodiment of the present application;
FIG. 3 is a block diagram of a media access controller module according to an embodiment of the application;
fig. 4 is a schematic diagram of a frame format corresponding to an inter-chip access interface according to an embodiment of the present application;
FIG. 5 is a block diagram of a media access controller module according to another embodiment of the application;
fig. 6 is a block diagram of a data link protocol bridge module according to an embodiment of the present application;
FIG. 7 is a block diagram of a first data processing module according to an embodiment of the present application;
fig. 8 is a schematic diagram of a frame format corresponding to an on-chip access interface according to an embodiment of the present application;
fig. 9 is a data link protocol bridge structure diagram according to an embodiment of the present application;
FIG. 10 is a flow chart of a communication method based on a medium access control layer according to an embodiment of the present application;
fig. 11 is a structural diagram of an inter-chip communication system according to an embodiment of the present application.
11, a data link protocol bridge module; 12. a media access controller module; 13. a configuration module; 1110. a data link protocol bridge; 1210. a first frame encoder; 1220. a first arbiter; 21. a first data processing module; 22. a second arbiter; 31. a first memory; 32. a multiplexer; 33. a second frame encoder; 23. a second data processing module; 34. a frame decoder; 35. a demultiplexer; 36. a second memory; 51. a first medium access control layer; 52. a second medium access control layer.
Detailed Description
The present application will be described and illustrated with reference to the accompanying drawings and examples in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. All other embodiments, which can be made by a person of ordinary skill in the art based on the embodiments provided by the present application without making any inventive effort, are intended to fall within the scope of the present application.
It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is possible for those of ordinary skill in the art to apply the present application to other similar situations according to these drawings without inventive effort. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the described embodiments of the application can be combined with other embodiments without conflict.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," and similar referents in the context of the application are not to be construed as limiting the quantity, but rather as singular or plural. The terms "comprising," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in connection with the present application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The terms "first," "second," "third," and the like, as used herein, are merely distinguishing between similar objects and not representing a particular ordering of objects.
The present embodiment provides a medium access control layer, as shown in fig. 1, where the medium access control layer is connected between an intra-chip communication interface and an inter-chip communication interface of a core particle, and the medium access control layer includes:
a data link protocol bridge module 11, configured to establish a logical data link between the on-chip communication interface and the inter-chip communication interface;
a medium access controller module 12 connected to the data link protocol bridge module 11, configured to receive the intra-chip communication interface data transmitted by the data link protocol bridge module 11, encode the intra-chip communication interface data into frame data corresponding to a specification of the inter-chip communication interface, and transmit the frame data to the inter-chip communication interface;
and the configuration module 13 is connected with the data link protocol bridge module 11 and is used for receiving and analyzing the configuration packet transmitted by the data link protocol bridge module 11 so as to configure the inter-chip communication interface.
The data link protocol bridge module 11, as shown in fig. 2, bridges two data link protocols, one being an on-chip link protocol for interconnection with on-chip components and the other being a side MAC to side MAC data link protocol. In the OSI model, the chip-to-chip communication interface belongs to the physical layer, while the medium access controller module 12 belongs to the medium access control sub-layer of the data link protocol bridge module 11, and the logical link control sub-layer of the data link protocol bridge module 11 is implemented by the data link protocol bridge 1110 to establish a logical link from one side MAC to the other side MAC.
The intra-chip link protocol uses a credit-based flow control method commonly used in the NoC field, and credit-based flow control is an effective way to realize flow control of each virtual loop in a link-by-link, before data is transmitted through a connection, a transmitting end needs to receive a credit value transmitted by a receiving end through a virtual loop, and in different periods, the receiving end transmits the credit to the transmitting end, which indicates the available buffer area size of the receiving end. When the credit is received, the transmitting end transmits data to the receiving end according to the credit, and after each time the transmitting end transmits the data, the corresponding credit is reduced, so that network blocking caused by failed retransmission can be effectively reduced. As shown in table 1, a set of on-chip communication interfaces has the following signals:
wherein the data_in, valid_in, credit_in signals are used for data and related flow control received by the MAC from the on-chip communication interface; data_out, valid_out, credit_out these signals are used for data and related flow control sent by the MAC to the on-chip communication interface. For each on-chip link protocol noted in fig. 2, there may be more than one set of interfaces as described above, where each set of interfaces is used to serve one physical subnet or one abstract priority. In this embodiment, the bit width N of each group of data lines (in a single direction) on the on-chip link protocol side is set to 128.
In order to enable the inter-chip communication interface to be applied to various occasions, the flexibility of interface design is improved, configurable options are added into the interface, and the interface is configured according to design requirements before normal operation. The whole configuration process is divided into two steps, wherein the first step is to analyze the configuration package transmitted from the chip, and the second step is to perform register configuration according to the analyzed configuration address and configuration data.
The configuration package in this embodiment has a proprietary format as shown in table 2. The configuration packet has a number of consecutive flits, each flit having a bit width of 128 bits. The first flit is the header of the packet, and the value of msgtype can be used to confirm that the packet is a configuration packet.
When the configuration module 13 determines that the data of the data link protocol bridge module 11 is the configuration packet currently, the whole MAC circuit is switched to the configuration state, and the current data of the data link protocol bridge module 11 and a plurality of pieces of data (the number identified by the value of the packetSize in the first flit) flow into the configuration module instead of flowing through the media access controller module 12 as in the normal mode.
For the first two flits of the configuration packet, the configuration module fetches the haddr, adX and dataX signals (X is 0,1,2,3, times identified by size) therein. The complete address is derived by concatenating haddr with adX to derive the required information for write-once: (register address_x, register data_x). Such data may be written via any commonly used configuration interface, depending on which configuration interface is provided by the Chiplet inter-chip communication interface. For each subsequent flit, a maximum of 3 pieces of configuration information can be loaded, and the processing method is the same as the above method. After the configuration process is completed, the MAC returns to the normal state for data transmission, and the configuration module in this embodiment is a state machine circuit.
The data link protocol bridge module is used for establishing a logic data link between the on-chip communication interface and the inter-chip communication interface; the medium access controller module is connected with the data link protocol bridge module and is used for receiving the on-chip communication interface data transmitted by the data link protocol bridge module, encoding the on-chip communication interface data into frame data corresponding to the specification of the on-chip communication interface and transmitting the frame data to the on-chip communication interface; and the configuration module is connected with the data link protocol bridge module and is used for receiving and analyzing the configuration packet transmitted by the data link protocol bridge module so as to configure the inter-chip communication interface. The method solves the problem that the medium access control layer cannot be compatible with various inter-chip communication interfaces with different specifications on the market, and the medium access control layer cannot be reused.
In one embodiment, as shown in fig. 3, the medium access controller module 12 includes a first frame encoder 1210, configured to encode the intra-chip communication interface data into frame data corresponding to a specification of the inter-chip communication interface according to a bit width and a clock frequency corresponding to the inter-chip communication interface.
The inter-chip transmission bandwidth provided by the inter-chip communication interfaces under different specifications is always the same, but due to various reasons such as process limitations, the interfaces provided to the chip have different clock frequencies and bit widths, and in this embodiment, the bit width of each group of data lines (in a single direction) on the intra-chip link protocol side is 128. The number of the subnets supported by the MAC is 2, and the inter-chip communication interfaces correspond to the following three specifications:
(1) 4X specification
The medium access controller module 12 under this specification is designed for large bit widths and low clock frequencies. The inter-chip access provides a bit width of 640 bits, which the MAC sees as four sets of 160 bits of data bit width, each set 160 bits can accommodate 128 bits of data from the intra-chip access and some additional data.
(2) 2X specification
The inter-chip access interface provides a bit width of 320 bits, which the MAC sees as two sets of 160 bits of data bit width, each set 160 bits can accommodate 128 bits of data from the intra-chip interface and some additional data. The clock frequency is twice that of the 4X specification.
(3) 1X specification
The media access controller under this specification is designed for small bit widths and high clock frequencies. The inter-chip access is provided as a bit width of 160 bits, which the MAC sees as a set of 160 bits of data bit width that accommodates only one 128 bits of data and a few bits of additional information. The clock frequency is four times that of the 4X specification.
The data bit widths provided under different specifications are different, the 1X specification lower bit width is 160 bits, the frame format is shown in fig. 4, the sel bit indicates which subnet route the data originates from, the val bit indicates whether the data segment data is valid, the dat bit indicates the transmission data segment, the QID indicates which data link protocol bridge 1110 the arbitrated data originates from, and the yms identifies the flow control information. For the frames obtained by encoding the 2X specification and the 4X specification, the frame has 320 bits and 640 bits respectively, wherein the bit segment definitions of 319-160 bits, 639-480 bits and 479-320 bits are consistent with the lower 160 bits, but no flow control information (the position of the offset 23-16 in the segment is 0) is required to be filled.
In one embodiment, as shown in fig. 5, the medium access controller module 12 further includes a first arbiter 1220 for arbitrating the on-chip communication interface data according to the subnet priority corresponding to the on-chip communication interface data and the data link protocol bridge module priority corresponding to the on-chip communication interface data. The first arbiter 1220 is responsible for arbitrating the data to be arbitrated from the data link protocol bridge 1110. For each group of data interfaces to be arbitrated, as shown in Table 3, there are the following signals:
the first arbiter 1220 in the media access controller module 12 has the following arbitration rules: for the data to be arbitrated from the data link protocol bridge module 11, the priority arbitrates according to the subnet priority corresponding to the on-chip communication interface data, the arbitration rule is that the total priority of the response subnet is higher than the request subnet, and for the data to be arbitrated with the same priority, the priority of the data link protocol bridge module 11 corresponding to the on-chip communication interface data is adopted, and particularly the priority of the data link protocol bridge 1110 is arbitrated. For example, in this embodiment, the data link protocol bridge module 11 has four data link protocol bridges 1110, where the IDs are 0,1,2, and 3, and the fixed priorities may be 0,1,2, and 3 in order from high to low.
In the embodiment, taking four data link protocol bridges 1110 as examples, the first arbiter 1220 performs the following arbitration according to the specification corresponding to the inter-chip communication interface: for the 4X specification, no arbitration is required, and the data of the four data link protocol bridges 1110 are all output data; for the 2X specification, the first arbiter 1220 arbitrates two out of the data of the four data link protocol bridges 1110 as output data; for the 1X specification, the first arbiter 1220 arbitrates one out of the data of the four data link protocol bridges 1110 as output data.
For chips with many-core architecture, nocs are often employed as an on-chip interconnect system. In some cases, to avoid deadlock at the protocol level, different NoC physical subnets are often equipped according to different phases of transactions of upper layer protocols carried on the NoC. These physical NoC subnetworks are generally identical in topology and routing aspects, but carry different packets. For example, into request and response subnets, which transmit only request and response packets, respectively, in such a way that the different priorities are physically separated, deadlock is avoided.
The medium access control layer in the embodiment supports the physical subnets with different priorities inside the chip to communicate by using the inter-chip communication interfaces, and ensures that the priority relation among the physical subnets is still maintained on the premise that the plurality of physical subnets share the same inter-chip interface at the same time, thereby prolonging the property of deadlock avoidance to the whole core particle interconnection system through the medium access control layer.
In one embodiment, as shown in fig. 6, the data link protocol bridge module 11 includes:
a first data processing module 21, configured to receive and process the on-chip communication interface data, and transmit the processed on-chip communication interface data to the media access controller module 12;
and the second arbiter 22 is configured to arbitrate the on-chip communication interface data according to whether the subnet corresponding to the on-chip communication interface data has a downstream message and a subnet priority corresponding to the on-chip communication interface data.
After the first data processing module 21 receives data from the chip, the data makes a request to the second arbiter 22, the arbiter decides whether the data has transmission qualification according to whether the subnet corresponding to the data holds the downstream credit, the downstream credit is sent from the MAC on the other side, the credit received by the MAC on the own side obtains an arbitration result according to the subnet priority from all the data having the transmission request and the transmission qualification, and the first data processing module 21 processes the data according to the arbitration result and transmits the data to the media access controller module 12.
In one embodiment, as shown in fig. 7, the first data processing module 21 includes:
a first memory 31 for storing the on-chip communication interface data;
a multiplexer 32, configured to output corresponding on-chip communication interface data according to the arbitration result obtained by the second arbiter 22;
and a second frame encoder 33, configured to encode the intra-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface.
The first memory 31 in this embodiment is FIFO (First In First Out), the FIFO is a first-in first-out data buffer, and the FIFO is used to temporarily store interface data adjacent to the on-chip interface for flow control, and divide the on-chip clock domain and the MAC clock domain. The data received from the chip is stored in the memory, and then arbitrated by the second arbiter 22 to determine which FIFO the data stored in can pass. Each non-empty FIFO may make a request to the arbiter and the second arbiter 22 decides whether the FIFO is eligible for transmission based on whether the FIFO's corresponding subnet holds downstream credits. The multiplexer 32 is configured to output corresponding data according to the arbitration result obtained by the second arbiter 22.
The second frame encoder 33 encodes the output data into a data link frame corresponding to the specification of the inter-chip communication interface, for carrying 128 bits of data and additional information from the chip, and the frame format is shown in fig. 8.
The subnet bit identifies which physical NoC subnet the data comes from, the valid bit indicates whether the data segment is valid, the dat bit is the transmission data segment, and ym1 and ym0 are the flow control credit (referred to as credit_in or credit_out signal lines) signals that need to be transmitted to the peer MAC, respectively. This is true in the transmission of the data link protocol bridge 1110 and the media access controller module 12, regardless of the input and output.
The data link protocol bridge module 11 further includes a second data processing module 23, configured to receive and process the inter-chip communication interface data transmitted by the medium access controller module, and transmit the processed inter-chip communication interface data to the intra-chip communication interface. Fig. 9 is a structure of a data link protocol bridge 1110 in the case of two physical NoC subnets within a chip. The solid lines represent the data flow direction and the dashed lines represent the control flow direction. The second data processing module 23 includes a frame decoder 34, a demultiplexer 35, and a second memory 36, where the frame decoder 34 is used to decode the inter-chip communication interface data transmitted from the medium access controller module 12, and the demultiplexer 35 is used to store the data into the second memory 36 according to the source of the data, and the second memory in this embodiment is also a FIFO.
The embodiment of the application also provides a communication method based on the medium access control layer, as shown in fig. 10, comprising the following steps:
step S401, receiving the on-chip communication interface data transmitted by the data link protocol bridge module;
step S402, encoding the on-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface;
step S403, transmitting the frame data to the inter-chip communication interface.
In this embodiment, the on-chip communication interface data transmitted by the data link protocol bridge module is received; encoding the intra-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface; the frame data is transmitted to the inter-chip communication interface. The method solves the problem that the medium access control layer cannot be compatible with various inter-chip communication interfaces with different specifications on the market, and the medium access control layer cannot be reused.
In one embodiment, the method further comprises the steps of:
step 1, receiving inter-chip communication interface data transmitted by the medium access control module;
and 2, decoding the inter-chip communication interface data and transmitting the inter-chip communication interface data to the inter-chip communication interface according to a source corresponding to the inter-chip communication interface data.
The embodiment of the application also provides a communication system between the chip chips, as shown in fig. 11, the system comprises a first medium access control layer 51 and a second medium access control layer 52, and the first medium access control layer 51 is in communication connection with the second medium access control layer 52; the first medium access control layer 51 and/or the second medium access control layer 52 implement a communication method based on a medium access control layer as described above.
When the whole system is powered on and reset, the first medium access control layer 51 and the second medium access control layer 52 need to receive configuration data packets from the on-chip, configure the inter-chip communication interface accordingly, and wait for the inter-chip communication interface to establish connection with the inter-chip communication interface, and then can enter normal use. When the configuration phase is completed, the common phase is entered, and communication can be performed across the core particles. The following describes the transmission of data over the entire data path in a specific example.
First, data from within the chip is transferred to the first medium access control layer 51 at the intra-chip interface protocol, and the data is received and written into the subnet corresponding FIFO of the data link bridge through the inter-chip communication interface. Once the data is stored in the FIFO, a request may be made to the second arbiter 22, and the second arbiter 22 derives the arbitration result from all FIFOs having the transmission request and the transmission qualification according to the subnet priority. A data link frame is then constructed from the data of the winning requester in this step of arbitration and an arbitration request is made to the medium access controller module 12 to compete with requests from other data link bridges. The medium access controller module 12 selects different data according to different specifications, constructs a new data frame and sends the new data frame to the inter-chip communication interface. The inter-chip communication interface transfers data to the corresponding inter-chip communication interface of the opposite second medium access control layer 52 and delivers the data to the second medium access control layer 52 for processing.
The second medium access control layer 52 treats each 160 bits of received data bit width as a portion, and processes it separately. And takes out all flow control signals in the lowest 160 bits of data. The second medium access control layer 52 assigns data to the corresponding data link bridge based on the QID number in the data bit segment. The flow control signal is also assigned to the data link bridge.
After each data link bridge receives the data frame, it assigns to the corresponding subnet FIFO according to the subnet number (subnet number or sel number) in the data frame. The data is then submitted to the on-chip component via the on-chip interface protocol. The above is the process of completing one end-to-end transmission.
The inter-chip communication system of the embodiment can be specially used for an inter-chip communication scene inter-chip communication system through the first medium access control layer 51 and the second medium access control layer 52, and solves the problem that the medium access control layer cannot be compatible with various inter-chip communication interfaces with different specifications on the market, and therefore cannot be reused.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. A medium access control layer connected between an intra-chip communication interface and an inter-chip communication interface of a core, the medium access control layer comprising:
a data link protocol bridge module for establishing a logical data link between the on-chip communication interface and the inter-chip communication interface;
the medium access controller module is connected with the data link protocol bridge module and is used for receiving the on-chip communication interface data transmitted by the data link protocol bridge module, encoding the on-chip communication interface data into frame data corresponding to the specification of the on-chip communication interface and transmitting the frame data to the on-chip communication interface;
and the configuration module is connected with the data link protocol bridge module and is used for receiving and analyzing the configuration packet transmitted by the data link protocol bridge module so as to configure the inter-chip communication interface.
2. The medium access control layer of claim 1, wherein the medium access controller module comprises a first frame encoder configured to encode the intra-chip communication interface data into frame data corresponding to a specification of the inter-chip communication interface according to a bit width and a clock frequency corresponding to the inter-chip communication interface.
3. The medium access control layer of claim 1, wherein the medium access controller module further comprises a first arbiter for arbitrating the on-chip communication interface data according to a subnet priority corresponding to the on-chip communication interface data and a data link protocol bridge module priority corresponding to the on-chip communication interface data.
4. The medium access control layer of claim 2, wherein the data link protocol bridge module comprises:
the first data processing module is used for receiving and processing the on-chip communication interface data and transmitting the processed on-chip communication interface data to the medium access controller module;
and the second arbiter is used for arbitrating the on-chip communication interface data according to whether the subnet corresponding to the on-chip communication interface data holds downstream messages and the subnet priority corresponding to the on-chip communication interface data.
5. The medium access control layer of claim 4, wherein the first data processing module comprises:
the first memory is used for storing the on-chip communication interface data;
the multiplexer is used for outputting corresponding on-chip communication interface data according to the arbitration result obtained by the second arbiter;
and the second frame encoder is used for encoding the intra-chip communication interface data into frame data corresponding to the specification of the inter-chip communication interface.
6. The medium access control layer of claim 4, wherein the data link protocol bridge module further comprises a second data processing module for receiving and processing inter-chip communication interface data transmitted by the medium access controller module and transmitting the processed inter-chip communication interface data to the intra-chip communication interface.
7. The medium access control layer of claim 6, wherein the second data processing module comprises: a frame decoder, a demultiplexer, and a second memory,
the frame decoder is used for decoding the inter-chip communication interface data transmitted by the medium access controller module;
the demultiplexer is configured to input the inter-chip communication interface data to the second memory for storage according to a source of the inter-chip communication interface data.
8. A method of communication based on a medium access control layer, the method comprising:
receiving on-chip communication interface data transmitted by a data link protocol bridge module;
encoding the intra-chip communication interface data into frame data corresponding to the specification of an inter-chip communication interface;
the frame data is transmitted to the inter-chip communication interface.
9. The medium access control layer-based communication method of claim 8, further comprising:
receiving inter-chip communication interface data transmitted by a medium access controller module;
and decoding the inter-chip communication interface data and transmitting the inter-chip communication interface data to the inter-chip communication interface according to a source corresponding to the inter-chip communication interface data.
10. The inter-chip communication system is characterized by comprising a first medium access control layer and a second medium access control layer, wherein the first medium access control layer is in communication connection with the second medium access control layer; the first medium access control layer and/or the second medium access control layer implement the method of claim 8.
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