CN116627739A - I2C controller detection method and device, switch and storage medium - Google Patents
I2C controller detection method and device, switch and storage medium Download PDFInfo
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The application provides an I2C controller detection method, a device, a switch and a storage medium, wherein the method comprises the following steps: monitoring the operation index of the I2C controller based on the accompany equipment to obtain an operation index monitoring result of the I2C controller; in the process of state transition of the accompanying equipment, determining a signal quality detection result of the I2C controller according to the read-write state change condition between the I2C controller and the accompanying equipment; determining an abnormal handling measure detection result of the I2C controller according to the abnormal handling measure adopted by the I2C controller when the accompanying equipment is in a functional abnormal state; and determining the performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormality treatment measure detection result of the I2C controller. By utilizing the accompanying and testing equipment, the automatic test of all performances of the I2C controller is realized, and the detection efficiency of the I2C controller is improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to an I2C controller detection method, an apparatus, a switch, and a storage medium.
Background
At present, a large number of I2C controllers are used in a management plane of a switch product, and the number of I2C controllers carried by a general CPU is insufficient, so that the self-grinding of the I2C controllers is required, and the testing of the self-grinding of the I2C controllers naturally becomes a problem to be solved.
In the prior art, performance tests are typically performed on I2C controllers by a tester with the aid of an oscilloscope. However, the manual testing process is complicated, and the detection efficiency of the I2C controller is reduced.
Disclosure of Invention
The application provides an I2C controller detection method, an I2C controller detection device, an exchanger and a storage medium, which are used for solving the defects that the detection efficiency of an I2C controller is reduced in the prior art.
The first aspect of the present application provides an I2C controller detection method, applied to an exchange, where the exchange includes an I2C controller and a partner device, and the partner device is used as an I2C receiving end, and the method includes:
in the running process of the I2C controller, the running index of the I2C controller is monitored based on the accompanying equipment to obtain a running index monitoring result of the I2C controller;
configuring the accompanying and testing equipment to convert an I2C signal abnormal state into an I2C signal normal state, and determining a signal quality detection result of the I2C controller according to the read-write state change condition between the I2C controller and the accompanying and testing equipment in the state conversion process of the accompanying and testing equipment;
Configuring the accompanying and testing equipment into a functional abnormality state, and determining an abnormality treatment measure detection result of the I2C controller according to an abnormality treatment measure adopted by the I2C controller when the accompanying and testing equipment is in the functional abnormality state;
and determining the performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormality treatment measure detection result of the I2C controller.
Optionally, the configuring the accompanying device to perform conversion from an I2C signal abnormal state to an I2C signal normal state, and determining, in a process of performing state conversion by the accompanying device, a signal quality detection result of the I2C controller according to a change condition of a read-write state between the I2C controller and the accompanying device, where the determining includes:
configuring the accompany device into an I2C signal abnormal state;
controlling the I2C controller to send a read-write command to the accompanying and testing equipment in the abnormal state of the I2C signal;
if the I2C controller and the accompanying equipment do not enter a read-write state, the accompanying equipment is restored to an I2C signal normal state, and the I2C controller is controlled to send a read-write command to the accompanying equipment;
and judging whether the I2C controller and the accompanying equipment normally enter a read-write state or not, and obtaining a signal quality detection result of the I2C controller.
Optionally, the abnormal function state includes a busy state, and the determining, according to an abnormal handling measure taken by the I2C controller when the accompanying device is in the abnormal function state, an abnormal handling measure detection result of the I2C controller includes:
configuring the co-device to a busy state;
controlling the I2C controller to send a read-write command to the accompanying device in a busy state; after receiving a read-write command, the accompanying measurement equipment in a busy state sends a waiting request to the I2C controller;
if the I2C controller receives a waiting request, the I2C controller enters a waiting state, and the detection result of the abnormal processing measure of the I2C controller is determined to be normal;
and if the I2C controller does not enter a waiting state after receiving the waiting request, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
Optionally, the abnormal function state includes an I2C SDA signal valley state, and the determining, according to an abnormal handling measure taken by the I2C controller when the accompanying device is in the abnormal function state, an abnormal handling measure detection result of the I2C controller includes:
Configuring the co-testing device to be in an I2C SDA signal off-valley state;
controlling the I2C controller to send a read-write command to the accompanying and testing equipment in the low valley state of the I2C SDA signal; the I2C controller determines whether the accompanying and testing equipment is in an I2C SDA signal valley state according to the response condition of the accompanying and testing equipment to a read-write command;
if the I2C controller determines that the accompanying and testing equipment is in the I2C SDA signal valley state, sending a target repair command to the accompanying and testing equipment, and determining that the detection result of the abnormal processing measure of the I2C controller is normal;
if the I2C controller determines that the accompanying and testing equipment is in the I2C SDA signal valley state and does not send a target repair command to the accompanying and testing equipment, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
Optionally, the abnormal function state includes a single command response abnormal state, and the determining, according to an abnormal handling measure adopted by the I2C controller when the accompanying device is in the abnormal function state, an abnormal handling measure detection result of the I2C controller includes:
configuring the accompanying and testing equipment into a single command response abnormal state;
Controlling the I2C controller to send a read-write command to the accompanying device under the abnormal state of single command response;
if the I2C controller sends the read-write command to the accompanying and testing equipment again under the condition that the accompanying and testing equipment does not respond to the read-write command, determining that the detection result of the abnormal processing measure of the I2C controller is normal;
and if the I2C controller does not send the read-write command to the accompanying device again, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
Optionally, the determining the performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result, and the abnormality processing measure detection result of the I2C controller includes:
generating a performance detection report of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormal processing measure detection result of the I2C controller; the performance detection report includes performance detection results of the I2C controller.
Optionally, the operation index at least includes CLK frequency, communication throughput, tbuf time and communication data accuracy.
A second aspect of the present application provides an I2C controller detection apparatus applied to a switch, where the switch includes an I2C controller and a partner device, and the partner device is used as an I2C receiving end, and the apparatus includes:
The monitoring module is used for monitoring the operation index of the I2C controller based on the accompany device in the operation process of the I2C controller to obtain an operation index monitoring result of the I2C controller;
the first determining module is used for configuring the accompanying and testing equipment to convert the abnormal state of the I2C signal into the normal state of the I2C signal, and determining a signal quality detection result of the I2C controller according to the change condition of the read-write state between the I2C controller and the accompanying and testing equipment in the process of converting the state of the accompanying and testing equipment;
the second determining module is used for configuring the accompanying and testing equipment into a functional abnormal state, and determining an abnormal processing measure detection result of the I2C controller according to abnormal processing measures adopted by the I2C controller when the accompanying and testing equipment is in the functional abnormal state;
and the detection module is used for determining the performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormality treatment measure detection result of the I2C controller.
Optionally, the first determining module is specifically configured to:
configuring the accompany device into an I2C signal abnormal state;
controlling the I2C controller to send a read-write command to the accompanying and testing equipment in the abnormal state of the I2C signal;
If the I2C controller and the accompanying equipment do not enter a read-write state, the accompanying equipment is restored to an I2C signal normal state, and the I2C controller is controlled to send a read-write command to the accompanying equipment;
and judging whether the I2C controller and the accompanying equipment normally enter a read-write state or not, and obtaining a signal quality detection result of the I2C controller.
Optionally, the abnormal function state includes a busy state, and the second determining module is specifically configured to:
configuring the co-device to a busy state;
controlling the I2C controller to send a read-write command to the accompanying device in a busy state; after receiving a read-write command, the accompanying measurement equipment in a busy state sends a waiting request to the I2C controller;
if the I2C controller receives a waiting request, the I2C controller enters a waiting state, and the detection result of the abnormal processing measure of the I2C controller is determined to be normal;
and if the I2C controller does not enter a waiting state after receiving the waiting request, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
Optionally, the abnormal function state includes an I2C SDA signal low-valley state, and the second determining module is specifically configured to:
Configuring the co-testing device to be in an I2C SDA signal off-valley state;
controlling the I2C controller to send a read-write command to the accompanying and testing equipment in the low valley state of the I2C SDA signal; the I2C controller determines whether the accompanying and testing equipment is in an I2C SDA signal valley state according to the response condition of the accompanying and testing equipment to a read-write command;
if the I2C controller determines that the accompanying and testing equipment is in the I2C SDA signal valley state, sending a target repair command to the accompanying and testing equipment, and determining that the detection result of the abnormal processing measure of the I2C controller is normal;
if the I2C controller determines that the accompanying and testing equipment is in the I2C SDA signal valley state and does not send a target repair command to the accompanying and testing equipment, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
Optionally, the abnormal function state includes a single command response abnormal state, and the second determining module is specifically configured to:
configuring the accompanying and testing equipment into a single command response abnormal state;
controlling the I2C controller to send a read-write command to the accompanying device under the abnormal state of single command response;
if the I2C controller sends the read-write command to the accompanying and testing equipment again under the condition that the accompanying and testing equipment does not respond to the read-write command, determining that the detection result of the abnormal processing measure of the I2C controller is normal;
And if the I2C controller does not send the read-write command to the accompanying device again, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
Optionally, the detection module is specifically configured to:
generating a performance detection report of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormal processing measure detection result of the I2C controller; the performance detection report includes performance detection results of the I2C controller.
Optionally, the operation index at least includes CLK frequency, communication throughput, tbuf time and communication data accuracy.
A third aspect of the present application provides a switch, comprising: the system comprises an I2C controller, a companion test device, at least one processor and a memory;
the accompanying equipment is used as an I2C receiving end;
the memory stores computer-executable instructions;
the at least one processor executes the computer-executable instructions stored by the memory such that the at least one processor performs the method as described above in the first aspect and the various possible designs of the first aspect.
A fourth aspect of the application provides a computer readable storage medium having stored therein computer executable instructions which when executed by a processor implement the method as described above for the first aspect and the various possible designs of the first aspect.
The technical scheme of the application has the following advantages:
the application provides an I2C controller detection method, a device, a switch and a storage medium, wherein the method comprises the following steps: in the running process of the I2C controller, monitoring the running index of the I2C controller based on the accompany equipment to obtain the running index monitoring result of the I2C controller; configuring a partner device to convert an I2C signal abnormal state into an I2C signal normal state, and determining a signal quality detection result of the I2C controller according to the read-write state change condition between the I2C controller and the partner device in the state conversion process of the partner device; configuring the accompanying and testing equipment into a functional abnormal state, and determining an abnormal processing measure detection result of the I2C controller according to an abnormal processing measure adopted by the I2C controller when the accompanying and testing equipment is in the functional abnormal state; and determining the performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormality treatment measure detection result of the I2C controller. According to the method provided by the scheme, the automatic test of all performances of the I2C controller is realized by using the accompanying equipment, and the detection efficiency of the I2C controller is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the prior art descriptions, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.
FIG. 1 is a schematic diagram of a detection system of an I2C controller according to an embodiment of the present application;
fig. 2 is a flow chart of a method for detecting an I2C controller according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an exemplary I2C controller detection system according to an embodiment of the present application;
FIG. 4 is a flowchart illustrating an exemplary I2C controller detection method according to an embodiment of the present application;
FIG. 5 is a flowchart illustrating another exemplary I2C controller detection method according to an embodiment of the present application;
FIG. 6 is a flowchart illustrating a method for detecting an I2C controller according to another embodiment of the present application;
fig. 7 is a schematic structural diagram of an I2C controller detection device according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a switch according to an embodiment of the present application;
Fig. 9 is a schematic structural diagram of an exemplary switch according to an embodiment of the present application.
Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. These drawings and the written description are not intended to limit the scope of the disclosed concept in any way, but to illustrate the inventive concept to those skilled in the art by reference to specific embodiments.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. In the following description of the embodiments, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the prior art, performance tests are typically performed on I2C controllers by a tester with the aid of an oscilloscope. However, the manual testing process is complicated, and the detection efficiency of the I2C controller is reduced.
In order to solve the above problems, the method, device, switch and storage medium for detecting an I2C controller provided by the embodiments of the present application include: in the running process of the I2C controller, monitoring the running index of the I2C controller based on the accompany equipment to obtain the running index monitoring result of the I2C controller; configuring a partner device to convert an I2C signal abnormal state into an I2C signal normal state, and determining a signal quality detection result of the I2C controller according to the read-write state change condition between the I2C controller and the partner device in the state conversion process of the partner device; configuring the accompanying and testing equipment into a functional abnormal state, and determining an abnormal processing measure detection result of the I2C controller according to an abnormal processing measure adopted by the I2C controller when the accompanying and testing equipment is in the functional abnormal state; and determining the performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormality treatment measure detection result of the I2C controller. According to the method provided by the scheme, the automatic test of all performances of the I2C controller is realized by using the accompanying equipment, and the detection efficiency of the I2C controller is improved.
The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
First, a configuration of an I2C controller detection system according to the present application will be described:
the I2C controller detection method, the I2C controller detection device, the switch and the storage medium provided by the embodiment of the application are suitable for automatically detecting the self-grinding I2C controller in the switch. Fig. 1 is a schematic structural diagram of an I2C controller detection system according to an embodiment of the present application, which mainly includes an I2C controller, an accompanying device, and an I2C controller detection apparatus, and specifically, the I2C controller and the accompanying device may be controlled based on the I2C controller detection apparatus, so as to utilize the accompanying device to automatically detect the I2C controller.
The embodiment of the application provides an I2C controller detection method which is applied to a switch, wherein the switch comprises an I2C controller and accompanying equipment, the accompanying equipment is used as an I2C receiving end, and the method is used for automatically detecting a self-grinding I2C controller in the switch. The execution subject of the embodiment of the application is electronic equipment such as switches, servers, desktop computers, notebook computers, tablet computers and other electronic equipment which can be used for detecting the I2C controller.
As shown in fig. 2, a flow chart of an I2C controller detection method according to an embodiment of the present application is shown, where the method includes:
step 201, in the running process of the I2C controller, monitoring the running index of the I2C controller based on the accompanying device to obtain the running index monitoring result of the I2C controller.
The operation index at least comprises CLK frequency, communication throughput, tbuf time and communication data accuracy.
As shown in fig. 3, a schematic structural diagram of an exemplary I2C controller detection system provided by an embodiment of the present application is shown, where an I2C controller is connected to a partner device through an I2C bus, and the I2C bus includes an SCL and an SDA, where the SCL is used to transmit a clock, and the SDA is used to transmit data. The I2C controller comprises a plurality of I2C initiating terminals (such as I2C Master1 and I2C Master 2), the accompanying and testing equipment comprises a plurality of I2C receiving terminals (such as I2C Slave1 and I2C Slave 2), and a command channel is further arranged between the I2C controller and the accompanying and testing equipment.
Specifically, as shown in fig. 4, a flow chart of an exemplary I2C controller detection method provided by the embodiment of the present application mainly represents a determining process of an operation index monitoring result, and is used for counting and testing normal function and performance data of an I2C controller. Firstly, a CLK frequency monitoring function, a communication throughput statistics function, a Tbuf time monitoring function and a data correctness checking function of a partner test device are sequentially started, the Tbuf time is the interval time from the end of the communication to the beginning of the next communication, the minimum interval requirement of the time under the 100K communication frequency is 4.7us, and the correctness of the communication data is determined by carrying out correctness calibration on the data sent by an I2C controller. And secondly, controlling the I2C controller to send a read-write command to the accompanying and testing equipment, detecting whether the I2C controller and the accompanying and testing equipment normally enter a read-write state, after stopping testing, controlling the I2C controller to acquire all monitoring data (operation indexes of the I2C controller) in the accompanying and testing equipment through a command channel, further determining an operation index monitoring result of the I2C controller according to the size relation between each operation index and a preset threshold value, and generating a corresponding test report.
Step 202, configuring a partner device to perform conversion from an I2C signal abnormal state to an I2C signal normal state, and determining a signal quality detection result of the I2C controller according to a read-write state change condition between the I2C controller and the partner device in a state conversion process of the partner device.
Specifically, through configuration of the accompanying and testing equipment to perform conversion from an I2C signal abnormal state to an I2C signal normal state, simulation of communication abnormality of the I2C controller is realized, and the testing mode is mainly used for testing the robustness of the I2C controller.
And 203, configuring the accompanying and testing equipment into a functional abnormality state, and determining an abnormality treatment measure detection result of the I2C controller according to an abnormality treatment measure adopted by the I2C controller when the accompanying and testing equipment is in the functional abnormality state.
Specifically, in order to perform additional function test on the I2C controller, the accompanying and testing device may be configured to be in a plurality of abnormal function states, and the detection result of the abnormal processing measure of the I2C controller is determined by judging whether the abnormal processing measure taken by the I2C controller when the accompanying and testing device is in the abnormal function state is reasonable. The exception handling measures include retry and bus clear transmission, etc., and when a specified failure occurs, the I2C controller should execute corresponding rescue measures (exception handling measures) that are implemented without error, and can be checked by the accompanying device. Therefore, whether the function abnormality is recovered or not can be judged according to the final communication result, and further detailed verification can be obtained according to the I2C bus monitoring function of the accompanying and testing equipment.
Step 204, determining a performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormality processing measure detection result of the I2C controller.
Specifically, the performance detection result of the I2C controller may be obtained by summarizing the operation index monitoring result, the signal quality detection result, and the abnormality processing measure detection result of the I2C controller.
Specifically, in an embodiment, a performance detection report of the I2C controller may be generated according to an operation index monitoring result, a signal quality detection result, and an exception handling measure detection result of the I2C controller; the performance test report includes the performance test results of the I2C controller.
Specifically, according to a preset performance detection report template, a performance detection report of the I2C controller can be generated according to an operation index monitoring result, a signal quality detection result and an abnormal processing measure detection result of the I2C controller; the performance detection report includes information such as a performance detection result and detection time of the I2C controller.
On the basis of the foregoing embodiment, as an implementation manner, in an embodiment, the configuration of the accompanying device to perform a transition from an abnormal state of an I2C signal to a normal state of the I2C signal, and in a process of performing a state transition by the accompanying device, determining a signal quality detection result of the I2C controller according to a change condition of a read-write state between the I2C controller and the accompanying device, includes:
Step 2021, configuring the accompanying device to be in an I2C signal abnormal state;
step 2022, controlling the I2C controller to send a read-write command to the accompanying device in the abnormal state of the I2C signal;
step 2023, if the I2C controller and the accompanying device do not enter a read-write state, restoring the accompanying device to the I2C signal normal state, and controlling the I2C controller to send a read-write command to the accompanying device;
and step 2024, judging whether the I2C controller and the accompanying equipment normally enter a read-write state, and obtaining a signal quality detection result of the I2C controller.
Specifically, the accompanying and testing device simulates various I2C signal anomalies according to configuration, firstly controls the I2C controller to send a read-write command in the I2C signal anomaly state of the accompanying and testing device, and when fault simulation is canceled, controls the I2C controller to send the read-write command again for checking whether the functions of the I2C controller are recovered to be normal. The I2C controller should be able to communicate normally after the abnormality of the accompanying device is recovered, and if the I2C controller is continuously abnormal, it is indicated that the robustness of the I2C controller design is problematic, that is, the signal quality detection result of the I2C controller is abnormal.
As shown in fig. 5, a flow chart of another exemplary I2C controller detection method provided by the embodiment of the present application is that first, a test accompanying device is configured as an I2C signal abnormal state (SCL/SDA signal abnormal state) through a command channel, so as to simulate the SCL/SDA signal abnormal state by using the test accompanying device, and control the I2C controller to send a read-write command to the test accompanying device in the I2C signal abnormal state, and determine whether the I2C controller and the test accompanying device enter the read-write state, if the read-write state is entered, i.e., the read-write is successful, then determine that the signal quality detection result of the I2C controller is abnormal, if the read-write state is not entered, i.e., the read-write is failed, then further recover the test accompanying device to be the I2C signal normal state, i.e., the SCL/SDA signal abnormal state simulation function of the test accompanying device is canceled, then control the I2C controller to send the read-write command to the test accompanying device, and further determine that the read-write state is normal at this moment, if the I2C controller and the test accompanying device enter the read-write state, I2C controller is the read-write signal normal, I2C controller is determined to be able to be the normal, and if the read-write signal quality is detected after the read-write controller is normal, and the test signal quality is normal, and if the test signal quality is normal, and the test signal quality is normal is detected.
On the basis of the foregoing embodiment, as an implementation manner, in an embodiment, the abnormal function state includes a busy state, and determining, according to an abnormal processing measure taken by the I2C controller when the accompanying device is in the abnormal function state, a detection result of the abnormal processing measure of the I2C controller includes:
step 2031, configuring a co-testing device as a busy state;
step 2032, controlling the I2C controller to send a read/write command to the accompanying device in the busy state; after receiving the read-write command, the accompanying measurement equipment in the busy state sends a waiting request to the I2C controller;
step 2033, if the I2C controller enters a waiting state after receiving the waiting request, determining that the detection result of the exception handling measure of the I2C controller is normal;
step 2034, if the I2C controller does not enter the waiting state after receiving the waiting request, determining that the detection result of the exception handling measure of the I2C controller is abnormal.
Specifically, as shown in fig. 6, a flowchart of another exemplary I2C controller detection method provided by an embodiment of the present application is that a configuration command is issued to a partner device to configure the partner device to a busy state, i.e., to simulate I2C clock, at which time the partner device suspends a transmission by pulling the SCL line low until the SCL line is released to be high, and the transmission is not continued. And then controlling the I2C controller to send a read-write command to the accompanying device in the busy state, and after the accompanying device receives the read-write command, sending a waiting request to the I2C controller to prompt the I2C controller to wait for a preset time and then start the read-write command. Therefore, if the I2C controller receives the waiting request and the I2C controller enters the waiting state, the I2C controller is characterized by taking correct exception handling measures, so as to determine that the detection result of the exception handling measures of the I2C controller is normal, otherwise, the detection result is abnormal.
Specifically, in an embodiment, the abnormal function state includes an I2C SDA signal off-valley state, and the test accompanying device may be configured to be an I2C SDA signal off-valley state; controlling the I2C controller to send a read-write command to the accompanying and testing equipment in the low valley state of the I2C SDA signal; the I2C controller determines whether the accompanying and tested equipment is in an I2C SDA signal valley state according to the response condition of the accompanying and tested equipment to the read-write command; if the I2C controller determines that the accompanying and testing equipment is in the I2C SDA signal valley state, sending a target repair command to the accompanying and testing equipment, and determining that the detection result of the abnormal processing measure of the I2C controller is normal; if the I2C controller determines that the accompanying and testing equipment is in the low-valley state of the I2C SDA signal, a target repair command is not sent to the accompanying and testing equipment, and the detection result of the abnormality processing measure of the I2C controller is determined to be abnormal.
Specifically, as shown in fig. 6, a configuration command is first issued to the co-device to configure the co-device to be in the I2C SDA signal off-state, i.e., to simulate the I2C SDA signal off-state, with SDA continuously pulled low. Then controlling the I2C controller to send a read-write command to the accompanying device in the I2C SDA signal valley state, wherein the I2C controller can determine that the accompanying device is currently in the I2C SDA signal valley state according to the response condition of the accompanying device to the read-write command, at the moment, if the I2C controller sends a target repair command (I2C bus clear) to the accompanying device first, then sends the read-write command to the accompanying device again, the abnormal handling measure detection result of the I2C controller is determined to be normal, and if the I2C controller does not send the target repair command to the accompanying device, the abnormal handling measure detection result of the I2C controller is determined to be abnormal. Wherein I2Cbus clear is to send 9 consecutive CLK clock attempts to resume the I2C bus.
Specifically, in an embodiment, the abnormal function state includes a single command response abnormal state, and the test accompanying device may be configured to be a single command response abnormal state; the I2C controller is controlled to send a read-write command to the accompanying device under the abnormal state of single command response; under the condition that the accompanying and testing equipment does not respond to the read-write command, if the I2C controller sends the read-write command to the accompanying and testing equipment again, determining that the detection result of the abnormal processing measure of the I2C controller is normal; if the I2C controller does not send the read-write command to the accompanying device again, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
Specifically, as shown in fig. 6, a configuration command is first issued to the partner device to configure the partner device to a single command response abnormal state, that is, to simulate a single communication ACK signal response abnormality. Then controlling the I2C controller to send a read-write command to the accompanying device in the single command response abnormal state, wherein the accompanying device does not respond to the read-write command at the moment, and determining that the detection result of the abnormal processing measure of the I2C controller is normal if the I2C controller sends the read-write command to the accompanying device again at the moment; if the I2C controller does not send the read-write command to the accompanying device again, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
According to the I2C controller detection method provided by the embodiment of the application, the operation index of the I2C controller is monitored based on the accompany device in the operation process of the I2C controller, so that the operation index monitoring result of the I2C controller is obtained; configuring a partner device to convert an I2C signal abnormal state into an I2C signal normal state, and determining a signal quality detection result of the I2C controller according to the read-write state change condition between the I2C controller and the partner device in the state conversion process of the partner device; configuring the accompanying and testing equipment into a functional abnormal state, and determining an abnormal processing measure detection result of the I2C controller according to an abnormal processing measure adopted by the I2C controller when the accompanying and testing equipment is in the functional abnormal state; and determining the performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormality treatment measure detection result of the I2C controller. According to the method provided by the scheme, the automatic test of all performances of the I2C controller is realized by using the accompanying and testing equipment, the detection efficiency of the I2C controller is improved, and a foundation is laid for improving the research and development quality and efficiency of the switch.
The embodiment of the application provides an I2C controller detection device which is used for executing the I2C controller detection method provided by the embodiment.
Fig. 7 is a schematic structural diagram of an I2C controller detection device according to an embodiment of the present application. The I2C controller detecting device 70 includes: a monitoring module 701, a first determining module 702, a second determining module 703 and a detecting module 704.
The monitoring module is used for monitoring the operation index of the I2C controller based on the accompany equipment in the operation process of the I2C controller to obtain an operation index monitoring result of the I2C controller; the first determining module is used for configuring the accompanying and testing equipment to convert the abnormal state of the I2C signal into the normal state of the I2C signal, and determining the signal quality detection result of the I2C controller according to the change condition of the read-write state between the I2C controller and the accompanying and testing equipment in the process of converting the state of the accompanying and testing equipment; the second determining module is used for configuring the accompanying and testing equipment into a functional abnormal state, and determining an abnormal processing measure detection result of the I2C controller according to an abnormal processing measure adopted by the I2C controller when the accompanying and testing equipment is in the functional abnormal state; the detection module is used for determining the performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormality treatment measure detection result of the I2C controller.
Specifically, in an embodiment, the first determining module is specifically configured to:
configuring a partner device to be in an I2C signal abnormal state;
controlling an I2C controller to send a read-write command to the accompanying device under the abnormal state of the I2C signal;
if the I2C controller and the accompanying equipment do not enter a read-write state, the accompanying equipment is restored to an I2C signal normal state, and the I2C controller is controlled to send a read-write command to the accompanying equipment;
and judging whether the I2C controller and the accompanying equipment normally enter a read-write state or not, and obtaining a signal quality detection result of the I2C controller.
Specifically, in an embodiment, the abnormal functional state includes a busy state, and the second determining module is specifically configured to:
configuring the co-device to a busy state;
controlling the I2C controller to send a read-write command to the accompanying device under the busy state; after receiving the read-write command, the accompanying measurement equipment in the busy state sends a waiting request to the I2C controller;
if the I2C controller receives the waiting request, the I2C controller enters a waiting state, and the abnormal processing measure detection result of the I2C controller is determined to be normal;
if the I2C controller receives the waiting request and the I2C controller does not enter the waiting state, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
Specifically, in an embodiment, the abnormal function state includes an I2C SDA signal low state, and the second determining module is specifically configured to:
configuring a co-testing device to be in an I2C SDA signal low-valley state;
controlling the I2C controller to send a read-write command to the accompanying and testing equipment in the low valley state of the I2C SDA signal; the I2C controller determines whether the accompanying and tested equipment is in an I2C SDA signal valley state according to the response condition of the accompanying and tested equipment to the read-write command;
if the I2C controller determines that the accompanying and testing equipment is in the I2C SDA signal valley state, sending a target repair command to the accompanying and testing equipment, and determining that the detection result of the abnormal processing measure of the I2C controller is normal;
if the I2C controller determines that the accompanying and testing equipment is in the low-valley state of the I2C SDA signal, a target repair command is not sent to the accompanying and testing equipment, and the detection result of the abnormality processing measure of the I2C controller is determined to be abnormal.
Specifically, in an embodiment, the abnormal function state includes a single command response abnormal state, and the second determining module is specifically configured to:
configuring the companion device as a single command response exception state;
the I2C controller is controlled to send a read-write command to the accompanying device under the abnormal state of single command response;
Under the condition that the accompanying and testing equipment does not respond to the read-write command, if the I2C controller sends the read-write command to the accompanying and testing equipment again, determining that the detection result of the abnormal processing measure of the I2C controller is normal;
if the I2C controller does not send the read-write command to the accompanying device again, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
Specifically, in an embodiment, the detection module is specifically configured to:
generating a performance detection report of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormal processing measure detection result of the I2C controller; the performance test report includes the performance test results of the I2C controller.
Specifically, in one embodiment, the operation index includes at least CLK frequency, communication throughput, tbuf time, and communication data accuracy.
The specific manner in which the respective modules perform the operations of the I2C controller detection apparatus in this embodiment has been described in detail in the embodiments related to the method, and will not be described in detail here.
The detection device for the I2C controller provided by the embodiment of the present application is configured to execute the detection method for the I2C controller provided by the foregoing embodiment, and its implementation manner and principle are the same and will not be described again.
The embodiment of the application provides a switch for executing the I2C controller detection method provided by the embodiment.
Fig. 8 is a schematic structural diagram of a switch according to an embodiment of the present application. The switch 80 includes: an I2C controller 81, a companion device 82, at least one processor 83, and a memory 84.
The accompanying equipment is used as an I2C receiving end to realize the functions of all I2C Slave devices; the memory stores computer-executable instructions; at least one processor executes computer-executable instructions stored in a memory, causing the at least one processor to perform the I2C controller detection method as provided by the embodiments above.
As shown in fig. 9, in the schematic structural diagram of an exemplary switch provided in the embodiment of the present application, the FPGA implements the function of a PCIE to I2C controller. The CPLD module is used as a accompany device to realize the I2C Slave function and realize all monitoring and fault simulation functions required by automatic test. And using the CPLD to simulate a plurality of I2C Slave interfaces as accompanying test equipment of the I2C controller, wherein the accompanying test equipment simulates the plurality of I2C Slave interfaces for testing, and simultaneously provides one I2C Slave interface for receiving test configuration and obtaining test results.
The switch provided by the embodiment of the present application is used for executing the detection method of the I2C controller provided by the foregoing embodiment, and its implementation manner and principle are the same and will not be described again.
The embodiment of the application provides a computer readable storage medium, wherein computer executable instructions are stored in the computer readable storage medium, and when a processor executes the computer executable instructions, the I2C controller detection method provided by any embodiment is realized.
The storage medium including the computer executable instructions in the embodiments of the present application may be used to store the computer executable instructions of the I2C controller detection method provided in the foregoing embodiments, and the implementation manner and principle of the implementation are the same, and are not repeated.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform part of the steps of the methods according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the functions described above. The specific working process of the above-described device may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (10)
1. An I2C controller detection method applied to a switch, wherein the switch includes an I2C controller and a partner device, and the partner device is used as an I2C receiving end, the method includes:
In the running process of the I2C controller, the running index of the I2C controller is monitored based on the accompanying equipment to obtain a running index monitoring result of the I2C controller;
configuring the accompanying and testing equipment to convert an I2C signal abnormal state into an I2C signal normal state, and determining a signal quality detection result of the I2C controller according to the read-write state change condition between the I2C controller and the accompanying and testing equipment in the state conversion process of the accompanying and testing equipment;
configuring the accompanying and testing equipment into a functional abnormality state, and determining an abnormality treatment measure detection result of the I2C controller according to an abnormality treatment measure adopted by the I2C controller when the accompanying and testing equipment is in the functional abnormality state;
and determining the performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormality treatment measure detection result of the I2C controller.
2. The method according to claim 1, wherein the configuring the accompanying device to perform a transition from an I2C signal abnormal state to an I2C signal normal state, and determining a signal quality detection result of the I2C controller according to a change condition of a read-write state between the I2C controller and the accompanying device during the state transition of the accompanying device, includes:
Configuring the accompany device into an I2C signal abnormal state;
controlling the I2C controller to send a read-write command to the accompanying and testing equipment in the abnormal state of the I2C signal;
if the I2C controller and the accompanying equipment do not enter a read-write state, the accompanying equipment is restored to an I2C signal normal state, and the I2C controller is controlled to send a read-write command to the accompanying equipment;
and judging whether the I2C controller and the accompanying equipment normally enter a read-write state or not, and obtaining a signal quality detection result of the I2C controller.
3. The method of claim 1, wherein the abnormal function state comprises a busy state, and wherein determining an abnormal handling measure detection result of the I2C controller according to an abnormal handling measure taken by the I2C controller when the accompanying device is in the abnormal function state comprises:
configuring the co-device to a busy state;
controlling the I2C controller to send a read-write command to the accompanying device in a busy state; after receiving a read-write command, the accompanying measurement equipment in a busy state sends a waiting request to the I2C controller;
if the I2C controller receives a waiting request, the I2C controller enters a waiting state, and the detection result of the abnormal processing measure of the I2C controller is determined to be normal;
And if the I2C controller does not enter a waiting state after receiving the waiting request, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
4. The method of claim 1, wherein the abnormal function state comprises an I2CSDA signal valley state, and wherein determining an abnormal handling measure detection result of the I2C controller according to an abnormal handling measure taken by the I2C controller when the accompanying device is in the abnormal function state comprises:
configuring the co-testing device to be in an I2C SDA signal off-valley state;
controlling the I2C controller to send a read-write command to the accompanying and testing equipment in the low valley state of the I2C SDA signal; the I2C controller determines whether the accompanying and testing equipment is in an I2C SDA signal valley state according to the response condition of the accompanying and testing equipment to a read-write command;
if the I2C controller determines that the accompanying and testing equipment is in the I2C SDA signal valley state, sending a target repair command to the accompanying and testing equipment, and determining that the detection result of the abnormal processing measure of the I2C controller is normal;
if the I2C controller determines that the accompanying and testing equipment is in the I2C SDA signal valley state and does not send a target repair command to the accompanying and testing equipment, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
5. The method of claim 1, wherein the abnormal function state comprises a single command response abnormal state, and wherein determining an abnormal handling measure detection result of the I2C controller according to an abnormal handling measure taken by the I2C controller when the accompanying device is in the abnormal function state comprises:
configuring the accompanying and testing equipment into a single command response abnormal state;
controlling the I2C controller to send a read-write command to the accompanying device under the abnormal state of single command response;
if the I2C controller sends the read-write command to the accompanying and testing equipment again under the condition that the accompanying and testing equipment does not respond to the read-write command, determining that the detection result of the abnormal processing measure of the I2C controller is normal;
and if the I2C controller does not send the read-write command to the accompanying device again, determining that the detection result of the abnormality processing measure of the I2C controller is abnormal.
6. The method of claim 1, wherein determining the performance test result of the I2C controller according to the operation index monitoring result, the signal quality test result, and the exception handling measure test result of the I2C controller comprises:
Generating a performance detection report of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormal processing measure detection result of the I2C controller; the performance detection report includes performance detection results of the I2C controller.
7. The method of claim 1, wherein the operation index comprises at least CLK frequency, communication throughput, tbuf time, and communication data accuracy.
8. An I2C controller detection device, applied to a switch, wherein the switch includes an I2C controller and a partner device, and the partner device is used as an I2C receiving end, the device includes:
the monitoring module is used for monitoring the operation index of the I2C controller based on the accompany device in the operation process of the I2C controller to obtain an operation index monitoring result of the I2C controller;
the first determining module is used for configuring the accompanying and testing equipment to convert the abnormal state of the I2C signal into the normal state of the I2C signal, and determining a signal quality detection result of the I2C controller according to the change condition of the read-write state between the I2C controller and the accompanying and testing equipment in the process of converting the state of the accompanying and testing equipment;
The second determining module is used for configuring the accompanying and testing equipment into a functional abnormal state, and determining an abnormal processing measure detection result of the I2C controller according to abnormal processing measures adopted by the I2C controller when the accompanying and testing equipment is in the functional abnormal state;
and the detection module is used for determining the performance detection result of the I2C controller according to the operation index monitoring result, the signal quality detection result and the abnormality treatment measure detection result of the I2C controller.
9. A switch, comprising: the system comprises an I2C controller, a companion test device, at least one processor and a memory;
the accompanying equipment is used as an I2C receiving end;
the memory stores computer-executable instructions;
the at least one processor executing computer-executable instructions stored in the memory causes the at least one processor to perform the method of any one of claims 1 to 7.
10. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor implement the method of any of claims 1 to 7.
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| CN202310609206.3A CN116627739A (en) | 2023-05-26 | 2023-05-26 | I2C controller detection method and device, switch and storage medium |
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