CN116613113A - Semiconductor packaging structure - Google Patents

Abstract

The invention provides a semiconductor packaging structure, which comprises a packaging substrate, a semiconductor bare crystal, an intermediate layer, an adhesive layer and a molding material. The semiconductor die is disposed over the package substrate. An interposer is disposed over the semiconductor die. An adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer. The semiconductor packaging structure provided by the invention can improve the heat dissipation efficiency.

Description

Semiconductor packaging structure

Technical Field

The present disclosure relates to semiconductor packaging technology, and more particularly, to a semiconductor packaging structure.

Background

The semiconductor package structure can provide not only protection of the semiconductor die (die) from environmental contamination, but also electrical connection between the semiconductor die packaged in the semiconductor package structure and a substrate such as a printed circuit board (printed circuit board, PCB). As the demand for smaller devices capable of performing more functions increases, package-on-package (PoP) technology is becoming more popular. PoP technology stacks two or more packages vertically together, thereby reducing the area they occupy on a motherboard.

However, the existing semiconductor package structure is not satisfactory in all respects, although it generally satisfies the requirements. For example, if the heat generated during operation of the semiconductor die is not sufficiently removed, the elevated temperature may cause damage to the semiconductor component. Heat dissipation is a critical issue to be addressed because it affects the performance of semiconductor packages. Accordingly, further improvements in semiconductor package structures are needed.

Disclosure of Invention

The following summary is illustrative only and is not intended to be in any way limiting. That is, the following summary is provided to introduce a selection of concepts, emphasis, benefits, and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described in the detailed description below. Accordingly, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

In a first aspect, the present invention provides a semiconductor package structure, comprising: packaging a substrate; a semiconductor die disposed over the package substrate; an interposer disposed over the semiconductor die; an adhesive layer connecting (e.g., physically contacting) the semiconductor die and the interposer; and molding material surrounding the semiconductor die and the adhesive layer.

In some embodiments, the semiconductor package further includes a conductive structure disposed between the package substrate and the interposer and surrounded by the molding material.

In some embodiments, the semiconductor die is disposed over a recess of the package substrate, and the molding material extends into the recess of the package substrate.

In some embodiments, the semiconductor package structure further includes: a plurality of conductive structures disposed between the semiconductor die and the package substrate; and an underfill material surrounding the plurality of conductive structures;

wherein the plurality of conductive structures and the underfill material are disposed in the recess.

In some embodiments, the adhesive layer is disposed within a first recess of the interposer.

In some embodiments, the semiconductor die is disposed between the first recess of the interposer and the second recess of the package substrate, and the molding material extends into the first recess of the interposer and/or the second recess of the package substrate.

In some embodiments, the interposer includes a mesa structure.

In some embodiments, the mesa structure is in contact with the adhesion layer.

In some embodiments, the mesa structure is composed of metal.

In a second aspect, the present invention provides a semiconductor package structure, comprising: packaging a substrate; a semiconductor die disposed over the package substrate; an interposer disposed over the semiconductor die and having a first bottom surface, a second bottom surface, and sidewalls connecting the first bottom surface and the second bottom surface;

an adhesive layer connecting the semiconductor die and the first bottom surface of the interposer; and a conductive structure connecting the package substrate and the second bottom surface of the interposer.

In some embodiments, a distance between the first bottom surface and the package substrate is greater than a distance between the second bottom surface and the package substrate.

In some embodiments, the package substrate has a first top surface under the semiconductor die and a second top surface in contact with the conductive structure, wherein the first top surface and the second top surface form a step shape.

In some embodiments, a distance between the first bottom surface and the package substrate is less than a distance between the second bottom surface and the package substrate.

In some embodiments, the semiconductor package further includes a molding material surrounding the first bottom surface, the semiconductor die, and the adhesive layer.

In some embodiments, the first bottom surface has a larger projected area than the adhesive layer and/or the semiconductor die.

In a third aspect, the present invention provides a semiconductor package structure, comprising: packaging a substrate; an interposer disposed above the package substrate and having a cavity; a semiconductor bare die disposed above the package substrate and located in the cavity; and molding material surrounding the semiconductor die.

In some embodiments, the semiconductor package further includes a conductive structure adjacent to the cavity and connecting the package substrate and the interposer.

In some embodiments, the sidewalls of the interposer, the sidewalls of the molding material, and the sidewalls of the package substrate are substantially coplanar.

In some embodiments, a top surface of the interposer is substantially coplanar with a top surface of the molding material, and the molding material extends into the cavity.

In some embodiments, the top surface of the interposer is substantially coplanar with a top surface of the semiconductor die.

These and other objects of the present invention will be readily understood by those skilled in the art after reading the following detailed description of the preferred embodiments as illustrated in the accompanying drawings. The detailed description will be given in the following embodiments with reference to the accompanying drawings.

Drawings

The accompanying drawings, in which like numerals indicate like components, illustrate embodiments of the invention. The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this embodiment of the invention. The drawings illustrate the implementation of embodiments of the invention and together with the description serve to explain the principles of embodiments of the invention. It will be appreciated that the drawings are not necessarily to scale, since some components may be shown out of scale from actual implementation to clearly illustrate the concepts of the embodiments of the invention.

Fig. 1A, 1B, and 1C are cross-sectional views of a semiconductor package structure at various stages of fabrication, according to some embodiments of the invention.

Fig. 2, 3, 4, 5, 6, and 7 are cross-sectional views illustrating semiconductor package structures according to some embodiments of the invention.

In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention. It will be apparent, however, that one or more embodiments may be practiced without these specific details, and that different embodiments may be combined as desired and should not be limited to the embodiments set forth in the drawings.

Detailed Description

The following description is of preferred embodiments of the invention, which are intended to illustrate the technical features of the invention, but not to limit the scope of the invention. Certain terms are used throughout the description and claims to refer to particular elements, and it will be understood by those skilled in the art that manufacturers may refer to a like element by different names. Therefore, the present specification and claims do not take the difference in names as a way of distinguishing elements, but rather take the difference in functions of elements as a basis for distinction. The terms "element," "system," and "apparatus" as used in the present invention may be a computer-related entity, either hardware, software, or a combination of hardware and software. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …". Furthermore, the term "coupled" means an indirect or direct electrical connection. Thus, if one device is coupled to another device, that device can be directly electrically connected to the other device or indirectly electrically connected to the other device through other devices or connection means.

Wherein corresponding numerals and symbols in the various drawings generally refer to corresponding parts, unless otherwise indicated. The drawings are clearly illustrative of relevant portions of the embodiments and are not necessarily drawn to scale.

The term "substantially" or "approximately" as used herein means that within an acceptable range, a person skilled in the art can solve the technical problem to be solved, substantially to achieve the technical effect to be achieved. For example, "substantially equal" refers to a manner in which a technician can accept a certain error from "exactly equal" without affecting the accuracy of the result.

The invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on actual scale for illustrative purposes. In the practice of the present invention, the dimensions and relative dimensions do not correspond to actual dimensions.

Additional components may be added on the basis of the embodiments described below. For example, the description of "forming a first component on a second component" may include embodiments in which the first component is in direct contact with the second component, and may also include embodiments in which additional components are disposed between the first component and the second component such that the first component and the second component are not in direct contact.

The spatially related descriptors of the first component and the second component may vary as the apparatus is operated or used in different directions. Further, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments discussed.

Semiconductor package structures having enhanced heat dissipation efficiency (enhanced efficiency of thermal dissipation) are described according to some embodiments of the invention. The heat dissipation path (e.g., the path between the die and the interposer) can be shortened, thereby improving the performance of the semiconductor package. The invention can be used as a mobile phone heat dissipation scheme.

Fig. 1A-1C are cross-sectional views of a semiconductor package 100 at various stages of fabrication, according to some embodiments of the invention. Additional features may be added to the semiconductor package 100. Some features described below may be replaced or removed for different embodiments. For simplicity of the schematic, only a portion of the semiconductor package 100 is shown.

As shown in fig. 1A, a package substrate (package substrate) 102 is provided. The package substrate 102 has a wiring structure (wiring structure) therein. In some embodiments, the wiring structure of the package substrate 102 includes a conductive layer, a conductive via, a conductive post, etc., or a combination thereof, as the invention is not limited in this regard. The wiring structure of the package substrate 102 may be formed of a metal including, for example, copper, aluminum, tungsten, or the like, an alloy thereof, or a combination thereof.

The wiring structure of the package substrate 102 is disposed in (or may be described as "located" in) the passivation layer (passivation layer). The passivation layer may be formed of a polymer (also referred to as "made"), for example, including Polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy (epoxy), and the like, or a combination thereof. Alternatively, the passivation layer may be formed of a dielectric material (dielectric material), for example, including silicon oxide (silicon oxide), silicon carbide (silicon carbide), silicon nitride (silicon nitride), silicon oxynitride (silicon oxynitride), or the like, or a combination thereof.

It should be noted that the configuration of the package substrate 102 shown in the drawings is merely an example, and is not a limitation of the present invention. Any desired semiconductor components may be formed in the package substrate 102 and/or on the package substrate 102. However, for simplicity of the schematic diagram, only the planarization substrate (flat substrate) 102 is shown.

As shown in fig. 1A, according to some embodiments, the semiconductor package structure 100 includes a plurality of conductive terminals (conductive terminal) 104 disposed below (below) the package substrate 102 and electrically coupled to the wiring structure of the package substrate 102. The conductive terminals 104 may include micro bumps (microbump), controlled collapse chip connection (controlled collapse chip connection, C4) bumps, solder balls (ball balls), ball Grid Array (BGA) balls, or the like, or combinations thereof. In some embodiments, the conductive terminals 104 are formed from a conductive material, including, for example, copper, aluminum, tungsten, and the like, alloys thereof, or combinations thereof.

As further shown in fig. 1A, according to some embodiments, the semiconductor package structure 100 includes a semiconductor die (die) 112, the semiconductor die 112 being disposed above (over) the package substrate 102. In some embodiments, the semiconductor die 112 includes a system-on-chip (SoC) die, a logic device (logic device), a memory device (memory device), a Radio Frequency (RF) device, or the like, or any combination thereof. For example, the semiconductor die 112 may include a micro control unit (micro control unit, MCU) die, a microprocessor unit (microprocessor unit, MPU) die, a power management integrated circuit (power management integrated circuit, PMIC) die, a radio frequency front end (radio frequency front end, RFFE) die, an acceleration processing unit (accelerated processing unit, APU) die, a central processing unit (central processing unit, CPU) die, a graphics processing unit (graphics processing unit, GPU) die, an input-output (IO) die, a dynamic random access memory (dynamic random access memory, DRAM) controller, a Static Random Access Memory (SRAM), a high bandwidth memory (high bandwidth memory, HBM), an application processor (application processor, AP) die, and the like, or any combination thereof.

According to some embodiments, the semiconductor package 100 may include more than one semiconductor die, and the number of semiconductor dies is not limited in the embodiments of the present invention. In addition, the semiconductor package 100 may further include one or more passive components (not shown) that may be adjacent to the semiconductor die 112, such as resistors, capacitors, inductors, and the like, or combinations thereof.

The semiconductor die 112 may be electrically coupled to the wiring structure of the package substrate 102 through a plurality of conductive structures (conductive structure) 108 and a plurality of connectors (connectors) 106. As shown in fig. 1A, the conductive structure 108 is disposed under (below) the semiconductor die 112 and is bonded to the (bonded to) package substrate 102 by the connector 106.

In some embodiments, the conductive structures 108 include conductive pads (conductive pads), conductive posts (conductive pillar), or the like, or a combination thereof. The conductive structure 108 is formed of a conductive material including, for example, copper, aluminum, tungsten, titanium (titanium), tantalum (tantalum), and the like, alloys thereof, or combinations thereof. The conductive structure 108 may be formed by an electroplating process, an electroless plating process, or any suitable process.

In some embodiments, the connector 106 is formed of a solder material (solder material), including, for example, tin (tin), snAg, snPb, or the like, or a combination thereof. The connector 106 may be formed by an electroplating process, an electroless plating process, or any suitable process.

As shown in fig. 1A, according to some embodiments, the semiconductor package 100 includes an underfill material (underfill material) 110, the underfill material 110 being located between the package substrate 102 and the semiconductor die 112. The underfill material 110 fills the gap between the conductive structure 108 and the connector 106 and surrounds each of the conductive structure 108 and the connector 106 to provide structural support. In some embodiments, the underfill material 110 is formed from a polymer, such as an epoxy. The underfill material 110 may be capillary filled and then cured by any suitable curing process.

As shown in fig. 1A, according to some embodiments, the semiconductor package structure 100 includes an adhesive layer 114, the adhesive layer 114 being disposed over the semiconductor die 112. The adhesion layer 114 may cover the entire top surface (top surface) of the semiconductor die 112. In some embodiments, the adhesion layer 114 includes Conductive Paste (CP), non-conductive paste (NCP), high-k film (high-k film), epoxy, or any suitable material. It will be appreciated that the thickness of the adhesive layer 114 is a given default value, the particular value of which is determined by the particular process, and the invention is not limited in this regard. The sidewalls (sidewall) of the adhesion layer 114 may be substantially coplanar (coplaner) with the sidewalls of the semiconductor die 112. It is understood that substantially coplanar includes completely coplanar and/or substantially coplanar.

As shown in fig. 1B, an interposer 118 is bonded (bonded onto) to the semiconductor die 112 through an adhesive layer 114, according to some embodiments. It will be appreciated that semiconductor die are obtained by wafer dicing, and that wafer thickness is typically around 700um, as produced by foundry (fourdry) in order to maintain a certain handleability. Then, the packaging factory must grind the wafer to be thinner for dicing and assembling, and typically needs to grind to about a predetermined thickness, particularly, for the die used in the stack/lamination structure, it is typically required to grind to below the predetermined thickness (e.g., 100 um), that is, the thickness of the die in the stack/lamination structure/package is typically less than 100um, so as to reduce the size as much as possible under the conventional packaging process. In some embodiments of the present invention, the thickness of the semiconductor die 112 is increased to increase the heat dissipation efficiency and thus achieve power budget enhancement, that is, in embodiments of the present invention, it need not be thinned to a thickness required by conventional packaging processes, but may be thicker than required by conventional packaging processes, such that the die may be in direct contact with the interposer through the adhesive layer, e.g., without molding material disposed between the passive side of the die and the interposer. It is appreciated that in embodiments of the present invention, the thickness of the semiconductor die 112 may be greater than a predetermined thickness required by conventional packaging processes. For example, in the case of stacked/stacked packages, the die may be cut from the wafer without grinding the wafer to less than 100um, but with a thicker thickness (e.g., greater than 100 um) to provide a semiconductor package with better heat dissipation according to embodiments of the present invention. For example, semiconductor die 112 is thick enough to directly connect to interposer 118 through adhesive layer 114 such that heat from a heat source (e.g., semiconductor die 112) can be transferred to interposer 118 through adhesive layer 114. Therefore, the heat dissipation path can be shortened.

According to some embodiments, a ratio (ratio) of a thickness Tl of the semiconductor die 112 in a direction substantially perpendicular to the top surface of the package substrate 102 to a distance Dl between the interposer 118 and the package substrate 102 is in a range of about (about) 0.5 to about 0.95, for example, about 0.9.

As shown in fig. 1A and 1B, the adhesive layer 114 is disposed on the semiconductor die 112 prior to bonding the interposer 118 to the semiconductor die 112, but the invention is not limited thereto. As an example, the adhesive layer 114 is disposed on the interposer 118 prior to bonding the interposer 118 to the semiconductor die 112. As another example, the adhesive layer 114 is disposed on both the interposer 118 and the semiconductor die 112 prior to bonding the interposer 118 to the semiconductor die 112.

The interposer 118 may have a wiring structure therein. In some embodiments, the wiring structure of interposer 118 may include conductive layers, conductive vias, conductive pillars, etc., or a combination thereof. The wiring structure of the interposer 118 may be formed of a metal including, for example, copper, aluminum, tungsten, or the like, an alloy thereof, or a combination thereof.

The wiring structure of the interposer 118 may be disposed in the passivation layer (passivation layer). The passivation layer may be formed of a polymer, for example, the polymer includes Polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy, or the like, or a combination thereof. Alternatively, the passivation layer may be formed of a dielectric material, including, for example, silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, or the like, or a combination thereof.

As shown in fig. 1B, according to some embodiments, the semiconductor package 100 includes a plurality of conductive structures 116 disposed between the package substrate 102 and an interposer 118. The wiring structure of interposer 118 may be electrically coupled to the wiring structure of package substrate 102 through conductive structure 116. In some embodiments, the conductive structures 116 include conductive pillars, solder balls, copper core solder balls, and the like, or combinations thereof. The conductive structure 116 may be formed of a conductive material, including, for example, copper, aluminum, tungsten, and the like, alloys thereof, or combinations thereof.

As shown in fig. 1C, according to some embodiments, the semiconductor package structure 100 includes a molding material 120, the molding material 120 surrounding the semiconductor die 112, the adhesive layer 114, the underfill material 110, and the conductive structure 116. The molding material 120 includes a non-conductive material, such as a moldable polymer, epoxy, resin (resin), or the like, or a combination thereof.

The molding material 120 may protect the semiconductor die 112, the adhesive layer 114, and the conductive structure 116 from the environment, thereby protecting these components from damage due to, for example, stress, chemicals, and/or moisture. As shown in fig. 1C, the sidewalls of the molding material 120 may be substantially coplanar with the sidewalls of the package substrate 102 and the sidewalls of the interposer 118.

In conventional packages (e.g., package-on-package structures), the thickness of the semiconductor die is not thick enough to bond to the interposer (i.e., there is some gap between the semiconductor die and the interposer) such that a portion of the molding material is disposed between the semiconductor die and the interposer. In these embodiments, some voids (void) may be formed in the molding material due to the narrow gap (gap) between the semiconductor die and the interposer. In addition, the low thermal conductivity of the molding material makes heat dissipation difficult. However, in the solution provided by the present invention (as in the embodiment shown in fig. 1B), the semiconductor die 112 directly contacts the interposer 118 through the adhesive layer 114, so that no molding material 120 is formed between the semiconductor die 112 and the interposer 118. In particular, the thickness of the semiconductor die 112 is increased (e.g., greater than 100um, and possibly even greater than 150 um) as compared to the thickness required for conventional packages, such that, in some embodiments, the present invention includes a thicker (thicker) semiconductor die 112 and uses an adhesive layer 114 to connect the semiconductor die 112 and the interposer 118. Thus, voids (void) between the semiconductor die 112 and the interposer 118 can be reduced or avoided. In addition, since the adhesive layer 114 has a higher thermal conductivity than the molding material 120, the heat dissipation efficiency can be further improved. In addition, the thicker semiconductor bare die has higher heat dissipation efficiency due to the increased volume of heat dissipation per se. In summary, in embodiments of the present invention, the semiconductor die is in direct contact with the interposer through the adhesive layer 114, for example, when the conventional thickness of the die obtained by conventional processes is insufficient to connect the interposer through the adhesive layer, the thickness of the die is increased as needed (e.g., a greater thickness is left during wafer thinning to be desirable to obtain a die of increased thickness), thereby enabling the thickness of the die to directly contact the interposer through the adhesive layer.

In addition, the thicker semiconductor die 112 can provide greater support than the molding material 120, such that the thicker semiconductor die 112 enables the semiconductor package structure 100 to have a better warp morphology (warp beam).

As described above, the sidewalls of the adhesion layer 114 may be substantially coplanar with the sidewalls of the semiconductor die 112, as shown in fig. 1C, but the invention is not limited thereto. By way of example, the semiconductor package structure 200 includes an adhesive layer 114a that extends beyond the sidewalls of the semiconductor die 112, as shown in fig. 2. The sidewalls of the adhesive layer 114a may be tapered (tapered). In particular, the adhesive layer 114a may have a larger projected area (projection area) than the semiconductor die 112.

As another example, the semiconductor package structure 300 includes an adhesive layer 114b, with sidewalls of the adhesive layer 114b being located between sidewalls of the semiconductor die 112, as shown in fig. 3. The sidewalls of the adhesive layer 114b may be rounded. In particular, semiconductor die 112 has a larger projected area than adhesive layer 114 b.

Fig. 4 is a cross-sectional view of a semiconductor package 400 shown in accordance with some embodiments of the present invention. It should be noted that the semiconductor package structure 400 may include the same or similar components as those of the semiconductor package structure 100 shown in fig. 1C, and those components will not be discussed in detail for simplicity. In the following embodiments, the package substrate has a recess (also referred to as a "dimple") for accommodating the thicker semiconductor die.

As shown in fig. 4, according to some embodiments, the package substrate 102 has a recess 202, and the semiconductor die 112 is disposed directly above (above) the recess 202. In particular, the semiconductor die 112 is disposed in/over a thinner region (thin region) of the package substrate 102. Thus, a thicker semiconductor die 112 may be further accommodated, further enhancing heat dissipation.

As shown in fig. 4, the package substrate 102 has a first top surface (i.e., the bottom surface of the recess 202) located below the semiconductor die 112 and a second top surface in contact with the conductive structure 116. The first top surface and the second top surface of the package substrate 102 are formed in a stepped shape.

According to some embodiments, in the region without the recess 202, a ratio of a thickness T2 of the semiconductor die 112 in a direction substantially perpendicular to the top surface of the package substrate 102 to a distance Dl between the interposer 118 and the package substrate 102 is in a range of about 0.5 to about 0.98, such as about 0.9. According to some embodiments, the ratio of the thickness T2 of the semiconductor die 112 to the distance D2 between the interposer 118 and the package substrate 102 in the region with the recess 202 is in the range of about 0.5 to about 0.95, such as about 0.9. Distance D2 is greater than distance D1. According to some embodiments, the ratio of distance D2 to distance D1 is in the range of about 1.05 to about 1.5, for example about 1.07.

As shown in fig. 4, the sidewall of the recess 202 is substantially perpendicular to the second top surface of the package substrate 102, but the present invention is not limited thereto. For example, at least one sidewall of the recess 202 may be tapered or sloped.

As shown in fig. 4, the conductive structures 108, the connectors 106, and the underfill material 110 may be disposed in the recess 202, and a portion of the molding material 120 may extend into the recess 202. However, this will vary depending on the size or shape of the recess 202. For example, in some other embodiments, the underfill material 110 may completely fill the groove 202, and the molding material 120 does not extend into the groove 202.

Fig. 5 is a cross-sectional view of a semiconductor package 500 shown in accordance with some embodiments of the present invention. It should be noted that the semiconductor package 500 may include the same or similar components as the components of the semiconductor package 100 illustrated in fig. 1C. For simplicity, those components will not be discussed in detail. In the embodiment of fig. 5, both the package substrate and interposer have grooves for accommodating thicker semiconductor die.

As shown in fig. 5, according to some embodiments, the package substrate 102 has a recess 202 and the interposer 118 has a recess 302, e.g., the recess 302 is located above the recess 202. Semiconductor die 112 is disposed between recess 202 and recess 302. Specifically, the semiconductor die 112 is disposed between a thinner region of the package substrate 102 and a thinner region of the interposer 118. Thus, a thicker semiconductor die 112 may be accommodated to further improve heat dissipation.

As shown in fig. 5, interposer 118 has a first bottom surface in contact with adhesive layer 114 (i.e., the bottom surface of recess 302) and a second bottom surface in contact with conductive structure 116. The first bottom surface and the second bottom surface of the interposer 118 are formed in a stepped shape.

As shown in fig. 5, the package substrate 102 has a first top surface (i.e., the bottom surface of the recess 202) located below the semiconductor die 112 and a second top surface in contact with the conductive structure 116. The first top surface and the second top surface of the package substrate 102 are formed in a stepped shape.

As shown in fig. 5, the groove 302 has a larger projected area than the groove 202, but the present invention is not limited thereto. For example, groove 202 may have a larger projected area than groove 302. Alternatively, the size of groove 202 is substantially equal to the size of groove 302 (e.g., the same projected area).

According to some embodiments, the ratio of the thickness T3 of the semiconductor die 112 in a direction substantially perpendicular to the top surface of the package substrate 102 to the distance Dl between the interposer 118 and the package substrate 102 in the region without the grooves 202 and 302 is in the range of about 0.5 to about 1.5, e.g., about 1. According to some embodiments, the ratio of the thickness T3 of the semiconductor die 112 to the distance D3 between the interposer 118 and the package substrate 102 in the region with the grooves 202 and 302 is in the range of about 0.5 to about 0.95, such as about 0.85. Distance D3 is greater than distance D1. According to some embodiments, the ratio of distance D3 to distance D1 is in the range of about 1.05 to about 1.5, for example about 1.07.

As shown in fig. 5, the sidewalls of the recess 202 are substantially perpendicular to the second top surface of the package substrate 102 and the sidewalls of the recess 302 are substantially perpendicular to the second bottom surface of the interposer 118, although the invention is not limited in this respect. For example, at least one of the sidewalls of groove 202 and the sidewalls of groove 302 may be tapered or sloped.

As shown in fig. 5, the conductive structures 108, the connectors 106, and the underfill material 110 are disposed in the recess 202. A portion of the molding material 120 extends into the groove 202 and covers the sidewalls of the groove 202. However, this may vary depending on the size or shape of the recess 202. For example, in some other embodiments, the underfill material 110 completely fills the recess 202 and the molding material 120 does not extend into the recess 202.

As shown in fig. 5, the bottom surface of the groove 302 has a larger projected area than the adhesive layer 114. A portion of the molding material 120 extends into the recess 302 and covers the sidewalls of the recess 302. However, this varies depending on the size or shape of the groove 302. For example, in some other embodiments, the adhesive layer 114 may completely (full) fill the groove 302, and the molding material 120 does not extend into the groove 302.

Fig. 6 is a cross-sectional view of a semiconductor package structure 600 shown in accordance with some embodiments of the present invention. It should be noted that the semiconductor package structure 600 may include the same or similar components as the components of the semiconductor package structure 100 illustrated in fig. 1C. For simplicity, those components will not be discussed in detail. In the embodiment of fig. 6, the interposer has a mesa structure (mesa structure) to facilitate heat transfer from the semiconductor die.

As shown in fig. 6, the interposer 118 has a mesa structure 402, and the semiconductor die 112 is disposed under (e.g., directly under) the mesa structure 402, in accordance with some embodiments. In particular, the semiconductor die 112 is disposed in/under a thicker region of the interposer 118.

According to some embodiments, mesa structure 402 includes an embedded heat spreader (embedded heat sink). Mesa structure 402 may be formed from a metal, including, for example, copper, aluminum, tungsten, and the like, alloys thereof, or combinations thereof. In some embodiments, mesa structure 402 is part of the wiring structure of interposer 118 and is formed during formation of the wiring structure of interposer 118. In some other embodiments, mesa structure 402 is formed after forming the wiring structure of intermediate layer 118.

As shown in fig. 6, the interposer 118 has a first bottom surface (i.e., the bottom surface of the mesa structure 402) above the semiconductor die 112 and a second bottom surface in contact with the conductive structure 116. The first bottom surface and the second bottom surface of the interposer 118 are formed in a stepped shape.

According to some embodiments, the ratio of the thickness T4 of the semiconductor die 112 in a direction substantially perpendicular to the top surface of the package substrate 102 to the distance Dl between the interposer 118 and the package substrate 102 in the region without the mesa structure 402 is in the range of about 0.2 to about 0.95, for example about 0.8. According to some embodiments, the ratio of the thickness T4 of the semiconductor die 112 to the distance D4 between the interposer 118 and the package substrate 102 in the region with the mesa structure 402 is in the range of about 0.25 to about 0.95, for example, about 0.85. Distance D4 is less than distance D1. According to some embodiments, the ratio of distance D4 to distance D1 is in the range of about 0.65 to about 0.98, for example, about 0.95.

As shown in fig. 6, the sidewalls of mesa structure 402 are substantially perpendicular to the second bottom surface of interposer 118, although the invention is not limited in this regard. For example, at least one of the sidewalls of mesa structure 402 may be tapered or sloped.

Mesa structure 402 may be surrounded by molding material 120. As shown in fig. 6, mesa structure 402 may have a larger projected area than adhesion layer 114 and semiconductor die 112, but the invention is not limited thereto. As one example, the adhesion layer 114 and/or the semiconductor die 112 may have a larger projected area than the mesa structure 402. As another example, the sidewalls of mesa structure 402 may be aligned or coplanar with the sidewalls of adhesion layer 114 and/or the sidewalls of semiconductor die 112.

Fig. 7 is a cross-sectional view of a semiconductor package structure 700 shown in accordance with some embodiments of the present invention. It should be noted that the semiconductor package 700 may include the same or similar components as the components of the semiconductor package 100 illustrated in fig. 1C. For simplicity, those components will not be discussed in detail. In the embodiment of fig. 7, the interposer has cavities (also referred to as "holes" or "trenches") for accommodating thicker semiconductor dies.

As shown in fig. 7, the interposer 118 has a cavity 502, and the semiconductor die 112 is located in the cavity 502, according to some embodiments. Thus, a thicker semiconductor die 112 may be accommodated to further improve heat dissipation. In the embodiment shown in fig. 7, the thicker semiconductor die dissipates heat well through the thicker material of the die itself.

According to some embodiments, the ratio of the thickness T5 of the semiconductor die 112 in a direction substantially perpendicular to the top surface of the package substrate 102 to the distance Dl between the interposer 118 and the package substrate 102 in the region without the cavity 502 is in the range of about 0.85 to about 1.5, e.g., about 1.2. According to some embodiments, the ratio of the thickness T5 of the semiconductor die 112 to the distance D5 between the interposer 118 and the package substrate 102 in the region having the cavity 502 is in the range of about 0.75 to about 0.95, such as about 0.85. Distance D5 is greater than distance D1. According to some embodiments, the ratio of distance D5 to distance D1 is in the range of about 1.15 to about 1.5, for example about 1.45.

As shown in fig. 7, the cavity 502 may extend through the interposer 118. Specifically, cavity 502 may extend from a bottom surface of interposer 118 to a top surface of interposer 118. The sidewalls of cavity 502 may be substantially perpendicular to the bottom surface of interposer 118, although the invention is not limited in this regard. For example, at least one sidewall of cavity 502 may be tapered or sloped. In the example shown in fig. 7, the molding material 120 may extend into the cavity 502 and may cover the sidewalls of the cavity 502, but the invention is not limited thereto. For example, in another example, the sides of the die 112 are in physical contact with the sides of the interposer 118 without the molding material 120 extending into the cavity 502. The top surface of the interposer 118 and the top surface of the molding material 120 are substantially coplanar.

In some embodiments, the top surface of the semiconductor die 112 is exposed (exposed) to increase the heat dissipation efficiency, as shown in fig. 7. The top surface of the semiconductor die 112 is substantially coplanar with the top surface of the interposer 118, the top surface of the molding material 120. The cavity 502 may have a dimension (e.g., width) that is greater than a dimension (e.g., width) of the semiconductor die 112.

In summary, in some embodiments, semiconductor package structures according to the present invention are capable of increasing the thickness of a semiconductor die to achieve power budget enhancements. Therefore, the heat dissipation efficiency can be improved, and the efficiency of the semiconductor packaging structure is further improved.

According to some embodiments, the semiconductor die extends to a (reach) interposer to shorten the heat dissipation path. Better warp behavior and fewer (or no) voids can also be achieved. Further, according to some embodiments, the interposer has a mesa structure to facilitate heat transfer from the semiconductor die. According to some embodiments, the top surface of the semiconductor die is exposed for better heat dissipation.

In the claims, ordinal terms such as "first," "second," "third," etc., are used to modify a claim element, and do not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a same name from another element having a same name using the ordinal term.

While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art), e.g., combinations or alternatives of the different features in the different embodiments. The scope of the following claims is, therefore, to be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Claims (20)

1. A semiconductor package structure, comprising:

packaging a substrate;

a semiconductor die disposed over the package substrate;

an interposer disposed over the semiconductor die;

an adhesive layer connecting the semiconductor die and the interposer; the method comprises the steps of,

and molding material surrounding the semiconductor die and the adhesive layer.

2. The semiconductor package according to claim 1, further comprising a conductive structure disposed between the package substrate and the interposer and surrounded by the molding material.

3. The semiconductor package according to claim 1, wherein the semiconductor die is disposed over the recess of the package substrate and the molding material extends into the recess of the package substrate.

4. The semiconductor package according to claim 3, further comprising:

a plurality of conductive structures disposed between the semiconductor die and the package substrate; the method comprises the steps of,

an underfill material surrounding the plurality of conductive structures;

wherein the plurality of conductive structures and the underfill material are disposed in the recess.

5. The semiconductor package according to claim 1, wherein the adhesive layer is disposed in the first recess of the interposer.

6. The semiconductor package according to claim 5, wherein the semiconductor die is disposed between the first recess of the interposer and the second recess of the package substrate, and the molding material extends into the first recess of the interposer and/or the second recess of the package substrate.

7. The semiconductor package according to claim 1, wherein the interposer comprises a mesa structure.

8. The semiconductor package according to claim 7, wherein the mesa structure is in contact with the adhesion layer.

9. The semiconductor package according to claim 7, wherein the mesa structure is composed of metal.

10. A semiconductor package structure, comprising:

packaging a substrate;

a semiconductor die disposed over the package substrate;

an interposer disposed over the semiconductor die and having a first bottom surface, a second bottom surface, and sidewalls connecting the first bottom surface and the second bottom surface;

an adhesive layer connecting the semiconductor die and the first bottom surface of the interposer; the method comprises the steps of,

and a conductive structure connecting the package substrate and the second bottom surface of the interposer.

11. The semiconductor package according to claim 10, wherein a distance between the first bottom surface and the package substrate is greater than a distance between the second bottom surface and the package substrate.

12. The semiconductor package according to claim 10, wherein the package substrate has a first top surface under the semiconductor die and a second top surface in contact with the conductive structure, wherein the first top surface and the second top surface form a step shape.

13. The semiconductor package according to claim 10, wherein a distance between the first bottom surface and the package substrate is smaller than a distance between the second bottom surface and the package substrate.

14. The semiconductor package according to claim 13, further comprising a molding material surrounding the first bottom surface, the semiconductor die, and the adhesive layer.

15. The semiconductor package according to claim 10, wherein the first bottom surface has a larger projected area than the adhesive layer and/or the semiconductor die.

16. A semiconductor package structure, comprising:

packaging a substrate;

an interposer disposed above the package substrate and having a cavity;

a semiconductor bare die disposed above the package substrate and located in the cavity; the method comprises the steps of,

and molding material surrounding the semiconductor die.

17. The semiconductor package according to claim 16, further comprising a conductive structure adjacent to the cavity and connecting the package substrate and the interposer.

18. The semiconductor package according to claim 16, wherein the sidewalls of the interposer, the sidewalls of the molding material, and the sidewalls of the package substrate are substantially coplanar.

19. The semiconductor package according to claim 16, wherein a top surface of the interposer is substantially coplanar with a top surface of the molding material, and wherein the molding material extends into the cavity.

20. The semiconductor package according to claim 19, wherein the top surface of the interposer is substantially coplanar with the top surface of the semiconductor die.