CN116610370A - Starting method, starting device, starting equipment and storage medium - Google Patents

Starting method, starting device, starting equipment and storage medium Download PDF

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Publication number
CN116610370A
CN116610370A CN202310572074.1A CN202310572074A CN116610370A CN 116610370 A CN116610370 A CN 116610370A CN 202310572074 A CN202310572074 A CN 202310572074A CN 116610370 A CN116610370 A CN 116610370A
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Prior art keywords
processor core
core
starting
data
processor
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Chinese (zh)
Inventor
李楠
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Shenzhen Lichi Semiconductor Technology Co ltd
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Shenzhen Lichi Semiconductor Technology Co ltd
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Priority to CN202310572074.1A priority Critical patent/CN116610370A/en
Publication of CN116610370A publication Critical patent/CN116610370A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4406—Loading of operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/575—Secure boot
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present disclosure provides a startup method, apparatus, device, and storage medium, where the method includes: after a first processor core of the multi-core heterogeneous chip acquires first pre-loading starting data and first starting data from a target storage medium, starting a first software system according to the first starting data, sending the first pre-loading starting data to a second processor core of the multi-core heterogeneous chip, after the first processor core releases the control authority of a controller of the target storage medium to the second processor core, receiving the first pre-loading starting data by the second processor core, and starting the second software system according to the first pre-loading starting data.

Description

Starting method, starting device, starting equipment and storage medium
Technical Field
The disclosure relates to the technical field of information interaction, and in particular relates to a starting method, a starting device, starting equipment and a storage medium.
Background
SoC (System on Chip) chips typically use EMMC (Embedded Multi Media Card, embedded memory) as a storage medium for System start-up operations. For the starting problem of each software system deployed on the multi-core chip, since the EMMC controller on the multi-core chip is usually fixed on one processor core in the multi-core chip, when each software system deployed on a different processor core of the multi-core chip needs to be started, loading of all software systems in the multi-core chip needs to be completed simultaneously by using EMMC on the processor core subordinate to the EMMC controller, so as to realize starting of a plurality of software systems deployed on the multi-core chip. The multi-core chip refers to a chip having a plurality of processor cores.
However, some software systems deployed on the multi-core chip are complex and huge, and a software system starting method using the existing multi-core chip needs a large memory requirement for starting the software systems at the same time. The EMMC, however, is difficult to meet the memory requirement required for simultaneously starting the software systems, and thus, the starting efficiency of the software systems is low.
Therefore, how to improve the starting efficiency of the software system on the multi-core chip is a urgent problem to be solved.
Disclosure of Invention
The present disclosure provides a starting method, apparatus, device, and storage medium, so as to at least solve the above technical problems in the prior art.
According to a first aspect of the present disclosure, there is provided a startup method applied to a multi-core heterogeneous chip, where each processor core of the multi-core heterogeneous chip and a hardware resource connected to the processor core form a hardware domain, and physical isolation exists between each hardware domain in the multi-core heterogeneous chip, the method includes:
a first processor core of the multi-core heterogeneous chip acquires control authority of a corresponding controller of a target storage medium in the multi-core heterogeneous chip, controls the controller to read first preloading starting data and first starting data from the target storage medium based on the control authority, starts a first software system according to the first starting data, and sends the first preloading starting data to a second processor core of the multi-core heterogeneous chip, wherein the first software system is a software system configured to be deployed on the first processor core, the first processor core and the second processor core are processor cores with different architectures, and a hardware domain where the first processor core is located is a security domain in the multi-core heterogeneous chip;
After the first processor core releases the control authority to the second processor core, the second processor core receives the first preloading starting data and starts a second software system according to the first preloading starting data, wherein the second software system is configured to be deployed on the second processor core.
In an embodiment, the starting the second software system according to the first pre-load starting data includes:
pre-starting a second software system based on the first pre-loading starting data;
the second processor core obtains residual second starting data from the target storage medium based on the control authority;
and completing the starting of the second software system according to the second starting data.
In an embodiment, the target storage medium is a storage unit commonly corresponding to each processor core of the multi-core heterogeneous chip.
In an embodiment, the controlling the controller to read the first preloaded startup data and the first startup data from the target storage medium based on the control authority includes:
determining a target storage data partition from among the storage data partitions in the target storage medium;
And controlling the controller to read the first preloading starting data and the first starting data from the target storage data partition according to the control authority.
In an embodiment, the method further comprises:
the N-1 processor core of the multi-core heterogeneous chip acquires second preloading starting data from the target storage medium based on the control authority and sends the second preloading starting data to the N processor core, wherein N is an integer larger than 2;
after the N-1 processor core is monitored to release the control authority to the N processor core, the N processor core starts an N software system according to the second preloading starting data, wherein the N software system is configured to be deployed on the N processor core, and the N-1 processor core and the N processor core are processor cores with different architectures.
In an embodiment, before the first processor core releases the control authority to the second processor core, the method further comprises:
the first processor core obtains third preloading starting data from the target storage medium according to the control authority, and sends the third preloading starting data to an N-th processor core of the multi-core heterogeneous chip, wherein N is an integer greater than 2;
After the booting of the second software system according to the first preload boot data, the method further comprises:
the N-1 processor core releases the control authority to the N processor core;
and the N-1-th processor core and the N-th processor core are processor cores with different architectures.
In an embodiment, the sending the first preload boot data to the second processor core of the multi-core heterogeneous chip includes:
the first processor core stores the first preloading starting data to a designated memory, and sends a storage address of the designated memory to a second processor core of the multi-core heterogeneous chip;
the second processor core receiving the first preload initiation data, comprising:
the second processor core receives the memory address and retrieves the first preload initiation data based on the memory address.
In an embodiment, the method further comprises:
and initializing the target storage medium according to the control authority after the processor cores acquire the control authority aiming at each processor core of the multi-core heterogeneous chip.
According to a second aspect of the present disclosure, there is provided a starting device, which is applied to a multi-core heterogeneous chip, where each processor core of the multi-core heterogeneous chip and a hardware resource connected to the processor core form a hardware domain, and physical isolation exists between each hardware domain in the multi-core heterogeneous chip, and the device includes:
the first starting module is used for acquiring control authority of a controller corresponding to a target storage medium in the multi-core heterogeneous chip by a first processor core of the multi-core heterogeneous chip, controlling the controller to read first preloading starting data and first starting data from the target storage medium based on the control authority, starting a first software system according to the first starting data, and sending the first preloading starting data to a second processor core of the multi-core heterogeneous chip, wherein the first software system is a software system configured to be deployed on the first processor core, the first processor core and the second processor core are processor cores with different architectures, and a hardware domain where the first processor core is located is a security domain in the multi-core heterogeneous chip;
And the second starting module is used for receiving the first preloading starting data by the second processor core after the first processor core releases the control authority to the second processor core, and starting a second software system according to the first preloading starting data, wherein the second software system is configured to be deployed on the second processor core.
According to a third aspect of the present disclosure, there is provided an electronic device comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the present disclosure.
According to a fourth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of the present disclosure.
By adopting the starting method, the device, the equipment and the storage medium, the first processor core of the multi-core heterogeneous chip acquires the control authority of the corresponding controller of the target storage medium in the multi-core heterogeneous chip, the controller is controlled based on the control authority to read the first pre-loading starting data and the first starting data from the target storage medium, the first pre-loading starting data is sent to the second processor core of the multi-core heterogeneous chip according to the first starting data, after the first processor core releases the control authority of the controller of the target storage medium to the second processor core, the second processor core receives the first pre-loading starting data, and starts the second software system according to the first pre-loading starting data, wherein the first software system is a software system configured to be deployed on the first processor core, the second software system is a software system configured to be deployed on the second processor core, and the first processor core and the second processor core are different processor core architectures. In the method, for each software system configured to be deployed on each processor core of the multi-core heterogeneous chip, the control authority of the controller of the target storage medium can be checked by switching each processor in the multi-core heterogeneous chip, and starting data of different software systems are loaded from the target storage medium in batches to realize starting of the software system, so that operability of the storage device is improved, flexibility of a starting mode of the software system is improved, and the problem that the starting efficiency of the software system is low because the storage device is difficult to meet memory requirements required for simultaneously starting a plurality of complex software systems is solved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 is a schematic flow chart of an implementation of a startup method provided by an embodiment of the present disclosure;
FIG. 2 is a schematic flow chart of another implementation of the startup method provided by the embodiments of the present disclosure;
FIG. 3 is a schematic diagram of a structure of an actuating device according to an embodiment of the present disclosure;
fig. 4 shows a schematic diagram of a composition structure of an electronic device according to an embodiment of the disclosure.
Detailed Description
In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.
Since EMMC hardly satisfies the memory requirement required for simultaneously starting a plurality of software systems of a multi-core chip, the software system starting efficiency becomes low. Therefore, in order to improve the starting efficiency of the software system on the multi-core chip, the present disclosure provides a starting method, a device, equipment and a storage medium. The method provided by the disclosure is applied to a multi-core heterogeneous chip, wherein the multi-core heterogeneous chip comprises at least two processor cores with different architectures, and each processor core corresponds to a software system. Each processor core and the hardware resource connected with the processor core form a hardware domain, physical isolation exists among the hardware domains in the multi-core heterogeneous chip, a software system is deployed on each hardware domain of the multi-core heterogeneous chip, the processor core can be a CPU Cluster, and the hardware resource can comprise an interrupt controller, a clock controller, a memory space and the like.
The technical solutions of the embodiments of the present disclosure will be described below with reference to the drawings in the embodiments of the present disclosure.
Fig. 1 shows a schematic flow chart of an implementation of a startup method provided by an embodiment of the present disclosure, where, as shown in fig. 1, the method is applied to a multi-core heterogeneous chip, and the method includes:
S101, a first processor core of the multi-core heterogeneous chip acquires control authority of a controller corresponding to a target storage medium in the multi-core heterogeneous chip, controls the controller to read first preloading starting data and first starting data from the target storage medium based on the control authority, starts a first software system according to the first starting data, and sends the first preloading starting data to a second processor core of the multi-core heterogeneous chip.
The first software system is configured to be deployed on the first processor core, the first processor core and the second processor core are processor cores with different architectures, each processor core of the multi-core heterogeneous chip and a hardware resource connected with the processor core form a hardware domain, physical isolation exists among all the hardware domains in the multi-core heterogeneous chip, and the hardware domain where the first processor core is located is a security domain in the multi-core heterogeneous chip.
In this step, after the first preloaded start-up data and the first start-up data are read, the first processor core may start up the first software system by running the first start-up data. And releasing the control authority of the controller of the target storage medium to the second processor core during the process of starting the first software system.
In the present disclosure, data is transferred between different processor cores through a multi-core heterogeneous inter-core communication program.
In one possible implementation, the first processor core may send the first preload initiation data to the second processor core through an inter-core communication program of a multi-core heterogeneous chip.
In another possible implementation manner, the first processor core may store the first preloaded start data to a specified memory and send a storage address of the specified memory to a second processor core of the multi-core heterogeneous chip, and specifically, the first processor core may send the storage address of the specified memory to the second processor core of the multi-core heterogeneous chip through an inter-core communication program. The second processor core, upon receiving the memory address, may invoke the first preload initiation data based on the memory address. The appointed memory is a memory which is not easy to be destroyed in the multi-core heterogeneous chip.
S102, after the first processor core releases the control authority to the second processor core, the second processor core receives the first preloading starting data and starts a second software system according to the first preloading starting data.
Wherein the second software system is a software system configured to be deployed on the second processor core.
In the present disclosure, if the second processor core receives the first preload starting data sent by the first processor core through the inter-core communication program, the second software system may be started directly according to the first preload starting data; if the second processor core receives the memory address of the designated memory sent by the first processor core through the inter-core communication program, the first pre-loading starting data can be called from the designated memory according to the memory address, and then the second software system is started according to the first pre-loading starting data.
If the second processor core fails in the process of starting the second software system and needs to restart the second software system, the first pre-loading starting data can be called from the appointed memory again according to the storage address of the appointed memory, and then the second software system is restarted according to the first pre-loading starting data.
In this step, if the first preloaded start-up data includes all data for starting up the second software system, the second software system may be completely started up according to the first preloaded start-up data.
If the first pre-load start-up data does not comprise all data for starting up the second software system, said starting up the second software system according to said first pre-load start-up data may comprise the steps A1-A3:
and step A1, pre-starting the second software system based on the first pre-loading starting data.
Specifically, the second processor core may execute the first preloaded start data to implement a pre-start of the second software system.
And step A2, the second processor core acquires the remaining second starting data from the target storage medium based on the control authority.
During or after the pre-boot of the second software system, the second processor core may control the controller to read remaining second boot data from the target storage medium using the control authority.
And step A3, completing the starting of the second software system according to the second starting data.
After the remaining second start-up data is read, the second processor core may run the second start-up data to complete the start-up of the second software system.
In the disclosure, since the hardware domain where the processor core having the control authority of the controller is located in the multi-core heterogeneous chip is usually a security domain, when the processor core currently having the control authority releases the control authority to the next processor core in the multi-core heterogeneous chip, it needs to determine whether the hardware domain where the next processor core is located is a security domain, and if so, the control authority may be released to the next processor core. For example, the first processor core needs to determine whether the hardware domain where the second processor core is located is a secure domain, if the hardware domain where the second processor core is located is the secure domain, the first processor core may release the control authority of the controller to the second processor core, if the hardware domain where the second processor core is located is not the secure domain, the first processor core cannot release the control authority of the controller to the second processor core, and at this time, the first processor core may release the control authority of the controller to the processor cores where other hardware domains of the multi-core heterogeneous chip are secure domains.
By adopting the starting method, the device, the equipment and the storage medium, the first processor core of the multi-core heterogeneous chip acquires the control authority of the corresponding controller of the target storage medium in the multi-core heterogeneous chip, the controller is controlled based on the control authority to read the first pre-loading starting data and the first starting data from the target storage medium, the first pre-loading starting data is sent to the second processor core of the multi-core heterogeneous chip according to the first starting data, after the first processor core releases the control authority of the controller of the target storage medium to the second processor core, the second processor core receives the first pre-loading starting data, and starts the second software system according to the first pre-loading starting data, wherein the first software system is a software system configured to be deployed on the first processor core, the second software system is a software system configured to be deployed on the second processor core, and the first processor core and the second processor core are different processor core architectures. In the method, for each software system configured to be deployed on each processor core of the multi-core heterogeneous chip, the control authority of the controller of the target storage medium can be checked by switching each processor in the multi-core heterogeneous chip, and starting data of different software systems are loaded from the target storage medium in batches to realize starting of the software system, so that operability of the storage device is improved, flexibility of a starting mode of the software system is improved, and the problem that the starting efficiency of the software system is low because the storage device is difficult to meet memory requirements required for simultaneously starting a plurality of complex software systems is solved.
In the present disclosure, the target storage medium stores therein startup data for starting up the respective software systems. The target storage medium may in particular be an EMMC (Embedded Multi Media Card, embedded memory). The controller of the target storage medium is configured in the multi-core heterogeneous chip, and each processor core of the multi-core heterogeneous chip can control whether to read data from the target storage medium or not through the controller. The controller of the target storage medium is generally fixed on one processor core in the multi-core heterogeneous chip, and if each processor core needs to utilize the controller to control the data read from the target storage medium, the control authority of the controller needs to be acquired first. The target storage medium may be a storage unit commonly corresponding to each processor core of the multi-core heterogeneous chip.
The initial control authority of the controller may be configured to any one of the processor cores in the multi-core heterogeneous chip, and the processor core currently having the control authority may release the control authority to the other processor cores. For example, a multi-core heterogeneous chip includes three processor cores of different architecture: processor core a, processor core B, and processor core C, processor core a may release control authority to processor core B or processor core C after using the controller if the initial control authority of the controller may be configured to processor core a.
In the disclosure, for each processor core of the multi-core heterogeneous chip, after the processor core acquires the control authority, initializing the target storage medium according to the control authority. Specifically, after the control authority is acquired by each processor core, the startup data required by the processor core can be read again from the target storage medium by initializing the target storage medium.
In one embodiment, after the first processor core of the multi-core heterogeneous chip obtains the first preloaded startup data and the first startup data from the target storage medium, before starting the first software system according to the first startup data, the startup method further includes the following steps B1-B2 to obtain the startup data:
and B1, the first processor core acquires the control authority of a controller corresponding to the target storage medium in the multi-core heterogeneous chip.
Specifically, if the first processor core may be configured as a processor core having the initial authority of the controller, or if the first processor core is not a processor core having the initial authority of the controller, the first processor core may request that other processor cores having the control authority release the control authority to themselves.
And step B2, based on the control authority, controlling the controller to read the first preloading starting data and the first starting data from the target storage medium.
Specifically, based on the control authority, the controller is controlled to read the first preloaded startup data and the first startup data from the target storage medium, and the method includes steps of:
and C1, determining a target storage data partition from all storage data partitions in the target storage medium.
The target storage medium stores other starting data for starting each software in advance, and in this step, the target storage data partition can be determined from each storage data partition in the target storage medium according to the identifier of the software system to be started, where the target storage data partition stores the starting data of the software system to be started.
And step C2, controlling the controller to read the first preloading starting data and the first starting data from the target storage data partition according to the control authority.
In one embodiment, the method of starting further comprises steps D1-D2:
and D1, acquiring second preloading starting data from the target storage medium based on the control authority by the N-1 processor core of the multi-core heterogeneous chip, and sending the second preloading starting data to the N processor core.
Wherein N is an integer greater than 2.
And D2, after the N-1 processor core is monitored to release the control authority to the N processor core, the N processor core starts the N software system according to the second preloading start data.
The N-1-th processor core and the N-th processor core are processor cores with different architectures.
For example, if N is equal to 3, the multi-core heterogeneous chip includes a first processor core, a second processor core, and a third processor core. The second processor core may obtain second preload boot data from the target storage medium in accordance with the control authority and send the second preload boot data to the third processor core before releasing the control authority to the next processor core. After the second processor core obtains the second pre-loading start-up data, the second processor core can release the control authority to the third processor core, and the third processor core can start up the third piece of system according to the second pre-loading start-up data. If the second preloaded start-up data comprises all data to start up the third software system, a complete start-up of the third software system may be performed according to the second preloaded start-up data. If the second preloaded starting data does not include all data for starting the third software system, the third processor core can run the second preloaded starting data to realize the pre-starting of the third software system, then acquire the residual starting data from the target storage medium based on the control authority, and finish the starting of the third software system according to the residual starting data.
That is, in the present disclosure, when three or more processor cores exist in the multi-core heterogeneous chip, other processor cores except the processor core where the last started software system is located need to load the pre-loaded start-up data for starting the software system corresponding to the next processor core with the control authority. By the mode, the loading start data time is reasonably distributed, the operability of the storage device is improved, the flexibility of a software system start mode is improved, and the problem that the software system start efficiency is low due to the memory requirement for simultaneously starting a plurality of complex software systems is solved.
In an embodiment, before the first processor core releases the control authority to the second processor core, the startup method further includes step E1:
and E1, the first processor core acquires third preloading starting data from the target storage medium according to the control authority, and sends the third preloading starting data to an N-th processor core of the multi-core heterogeneous chip.
Wherein N is an integer greater than 2.
After said booting a second software system according to said first preloaded booting data, said booting method further comprises the steps F1-F2:
And F1, releasing the control authority to the N-1 processor core by the N-1 processor core.
And F2, starting a third software system by the Nth processor core according to the third preloading starting data, wherein the third software system is configured to be deployed on the Nth processor core, and the N-1 th processor core and the Nth processor core are processor cores with different architectures.
For example, if N is equal to 3, the multi-core heterogeneous chip includes a first processor core, a second processor core, and a third processor core. The first processor core may further continue to obtain third preload startup data from the target storage medium according to the control authority after obtaining the first preload startup data and the first startup data from the target storage medium, and send the third preload startup data to the third processor core. After the first processor core acquires the third pre-loading starting data, the control authority is released to the second processor core, so that the second processor core receives the first pre-loading starting data and starts the second software system according to the first pre-loading starting data. The second processor core releases the control authority to the third processor core after receiving the first preload startup data. The third processor core starts a third software system according to third pre-load start data sent by the first processor core. If the third preloaded start-up data comprises all data to start up the third software system, a complete start-up of the third software system may be performed according to the third preloaded start-up data. If the third preloaded starting data does not include all data for starting the third software system, the third processor core can run the third preloaded starting data to realize the pre-starting of the third software system, then acquire the residual starting data from the target storage medium based on the control authority, and finish the starting of the third software system according to the residual starting data.
That is, in the present disclosure, when three or more processor cores exist in the multi-core heterogeneous chip, the software system corresponding to the other processor cores may be pre-started by preloading part of the start data of the first processor core and the other processor cores, so as to increase the flexibility of the software system start mode, and solve the problem that the memory requirement required for simultaneously starting multiple complex software systems results in low software system start efficiency.
Fig. 2 shows another implementation flow diagram of a boot method provided by an embodiment of the present disclosure, where, as shown in fig. 2, the method is applied to a multi-core heterogeneous chip, as shown in fig. 2, a Cluster represents a processor core of the multi-core heterogeneous chip, a Cluster-1 represents a processor core 1 of the multi-core heterogeneous chip, a Cluster-2 represents a processor core 2 of the multi-core heterogeneous chip, a Cluster-3 represents a processor core 3 of the multi-core heterogeneous chip, an EMMC storage medium represents a target storage medium, a boot image represents boot data for booting a software system, a preloaded boot image represents preloaded boot data, and a partition table represents a list of respective storage data partitions of the EMMC.
As shown in FIG. 2, when the heterogeneous multi-core chip is started, cluster-1 has the control authority of the EMMC controller, after the Cluster-1 initializes the EMMC, a target storage data partition is determined from the EMMC partition table, then the startup image data of Cluster-1 and the preloaded image data of Cluster-2 are read from the target storage data partition of the EMMC according to the control authority into corresponding memory addresses, then the chip can jump to the system running address of the first software system deployed on Cluster-1, the first software system on Cluster-1 is started according to the startup image data of Cluster-1, and the resource (the resource, namely, the control authority of the EMMC controller) of the EMMC controller is released to Cluster-2 during or after the first software system is started, so as to start Cluster-2.rest Cluster-2 refers to start Cluster-2.
As shown in FIG. 2, after Cluster-1 releases the control authority of the EMMC controller to Cluster-2, cluster-2 can jump to the running address corresponding to the preloaded mirror data loaded by Cluster-1, pre-start the second software system deployed on Cluster-2, initialize EMMC by using the control authority, after initializing EMMC, determine the target storage data partition from the EMMC partition table by using the control authority, then read the start mirror data of Cluster-2 and Cluster-3 from the target storage data partition of EMMC to the corresponding memory address, then the chip can jump to the system running address of the second software system deployed on Cluster-2, finish the start of the second software system on Cluster-2 according to the start mirror data of Cluster-2, and pre-start the third software system deployed on Cluster-3. rest Cluster-3 refers to start Cluster-3. And, cluster-2 can also release the control authority of the EMMC controller to Cluster-3 during or after starting the second software system, so as to start Cluster-3.
As shown in FIG. 2, after Cluster-2 sends the boot image data of Cluster-3 to Cluster-3, cluster-3 may jump to the system running address boot system corresponding to the boot image data of Cluster-3, that is, boot the third software system deployed in Cluster-3, and after the third software system is started, it means that all software systems on the heterogeneous multi-core chip are started.
By adopting the method provided by the embodiment of the disclosure, the control authority of the controller of the target storage medium is released respectively, and the starting data of different software systems can be loaded from the target storage medium in batches in time division to realize the starting of the software systems, so that the operability of the storage device is improved, the flexibility of a starting mode of the software systems is improved, and the problem of low starting efficiency of the software systems caused by the fact that the storage device is difficult to meet the memory requirement required for simultaneously starting a plurality of complex software systems is solved.
In the disclosure, for each processor core, if the processor core obtains the pre-load startup data and/or startup data from the target storage medium by using the control authority, the pre-load startup data and/or startup data may be stored into the designated memory, and the storage address of the designated memory may be sent to other corresponding processor cores. If the processor core fails in the process of starting the software system, when restarting the software system, the corresponding starting data does not need to be acquired from the target storage medium any more, and the starting data stored before can be directly loaded from the appointed memory and used for restarting the software system.
Based on the same inventive concept, according to the starting method provided by the above embodiment of the present disclosure, correspondingly, another embodiment of the present disclosure further provides a starting device, a schematic structure diagram of which is shown in fig. 3, where the device is applied to a multi-core heterogeneous chip, each processor core of the multi-core heterogeneous chip and a hardware resource connected with the processor core form a hardware domain, and physical isolation exists between each hardware domain in the multi-core heterogeneous chip, and the device specifically includes:
the first starting module 301 is configured to obtain, by a first processor core of the heterogeneous multi-core chip, a control right of a controller corresponding to a target storage medium in the heterogeneous multi-core chip, control the controller to read first preloaded starting data and first starting data from the target storage medium based on the control right, and start a first software system according to the first starting data, and send the first preloaded starting data to a second processor core of the heterogeneous multi-core chip, where the first software system is a software system configured to be deployed on the first processor core, the first processor core and the second processor core are processor cores with different architectures, and a hardware domain where the first processor core is located is a security domain in the heterogeneous multi-core chip;
And a second starting module 302, configured to receive the first pre-load starting data by the second processor core after the first processor core releases the control authority to the second processor core, and start a second software system according to the first pre-load starting data, where the second software system is a software system configured to be deployed on the second processor core.
By adopting the device provided by the embodiment of the disclosure, the first processor core of the multi-core heterogeneous chip acquires the control authority of the corresponding controller of the target storage medium in the multi-core heterogeneous chip, the controller is controlled based on the control authority to read the first pre-load starting data and the first starting data from the target storage medium, the first software system is started according to the first starting data, the first pre-load starting data is sent to the second processor core of the multi-core heterogeneous chip, after the first processor core releases the control authority of the controller of the target storage medium to the second processor core, the second processor core receives the first pre-load starting data, and the second software system is started according to the first pre-load starting data, wherein the first software system is a software system configured to be deployed on the first processor core, the second software system is a software system configured to be deployed on the second processor core, and the first processor core and the second processor core are processor cores with different architectures. In the method, for each software system configured to be deployed on each processor core of the multi-core heterogeneous chip, the control authority of the controller of the target storage medium can be checked by switching each processor in the multi-core heterogeneous chip, and starting data of different software systems are loaded from the target storage medium in batches to realize starting of the software system, so that operability of the storage device is improved, flexibility of a starting mode of the software system is improved, and the problem that the starting efficiency of the software system is low because the storage device is difficult to meet memory requirements required for simultaneously starting a plurality of complex software systems is solved.
In an embodiment, the second starting module 302 is specifically configured to pre-start the second software system based on the first pre-load starting data; the second processor core obtains residual second starting data from the target storage medium based on the control authority; and completing the starting of the second software system according to the second starting data.
In an embodiment, the target storage medium is a storage unit commonly corresponding to each processor core of the multi-core heterogeneous chip.
In one implementation manner, the data loading module is specifically configured to determine a target storage data partition from each storage data partition in the target storage medium; and controlling the controller to read the first preloading starting data and the first starting data from the target storage data partition according to the control authority.
In an embodiment, the device further comprises:
the second starting module 302 is further configured to obtain second pre-load starting data from the target storage medium based on the control authority, where N is an integer greater than 2, and send the second pre-load starting data to the nth processor core;
And a third starting module (not shown in the figure) is used for starting an nth software system according to the second preloading starting data after the nth processor core is monitored to release the control authority to the nth processor core, wherein the nth software system is configured to be deployed on the nth processor core, and the nth processor core are processor cores with different architectures.
In an implementation manner, the first starting module 301 is further configured to obtain, by the first processor core, third preload starting data from the target storage medium according to the control authority, and send the third preload starting data to an nth processor core of the multi-core heterogeneous chip, where N is an integer greater than 2;
the apparatus further comprises:
a fourth boot module (not shown) for releasing the control authority to the nth processor core by the nth-1 processor core; and the N-1-th processor core and the N-th processor core are processor cores with different architectures.
In an embodiment, the first starting module 301 is specifically configured to store the first preloaded starting data to a specified memory by the first processor core, and send a storage address of the specified memory to a second processor core of the heterogeneous multi-core chip;
the second boot module 302 is specifically configured to receive the storage address by the second processor core, and invoke the first preloaded boot data based on the storage address.
In an embodiment, the device further comprises:
an initialization module (not shown in the figure) is configured to initialize, for each processor core of the multi-core heterogeneous chip, the target storage medium according to the control authority after the processor core acquires the control authority.
By adopting the device provided by the embodiment of the disclosure, the control authority of the controller of the target storage medium is released respectively, and the starting data of different software systems can be loaded from the target storage medium in batches in time division to realize the starting of the software systems, so that the operability of the storage device is improved, the flexibility of a starting mode of the software systems is improved, and the problem that the starting efficiency of the software systems is low due to the fact that the storage device is difficult to meet the memory requirement required for simultaneously starting a plurality of complex software systems is solved.
According to embodiments of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.
Fig. 4 illustrates a schematic block diagram of an example electronic device 400 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 4, the apparatus 400 includes a computing unit 401 that can perform various suitable actions and processes according to a computer program stored in a Read Only Memory (ROM) 402 or a computer program loaded from a storage unit 408 into a Random Access Memory (RAM) 403. In RAM 403, various programs and data required for the operation of device 400 may also be stored. The computing unit 401, ROM 402, and RAM 403 are connected to each other by a bus 404. An input/output (I/O) interface 405 is also connected to bus 404.
Various components in device 400 are connected to I/O interface 405, including: an input unit 406 such as a keyboard, a mouse, etc.; an output unit 407 such as various types of displays, speakers, and the like; a storage unit 408, such as a magnetic disk, optical disk, etc.; and a communication unit 409 such as a network card, modem, wireless communication transceiver, etc. The communication unit 409 allows the device 400 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The computing unit 401 may be a variety of general purpose and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 401 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 401 performs the respective methods and processes described above, such as a startup method. For example, in some embodiments, the initiation method may be implemented as a computer software program, which is tangibly embodied on a machine-readable medium, such as the storage unit 408. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 400 via the ROM 402 and/or the communication unit 409. When the computer program is loaded into RAM 403 and executed by computing unit 401, one or more steps of the start-up method described above may be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to perform the startup method by any other suitable means (e.g. by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems-on-a-chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (11)

1. The starting method is characterized by being applied to a multi-core heterogeneous chip, wherein each processor core of the multi-core heterogeneous chip and a hardware resource connected with the processor core form a hardware domain, and physical isolation exists among all hardware domains in the multi-core heterogeneous chip, and the method comprises the following steps:
a first processor core of the multi-core heterogeneous chip acquires control authority of a corresponding controller of a target storage medium in the multi-core heterogeneous chip, controls the controller to read first preloading starting data and first starting data from the target storage medium based on the control authority, starts a first software system according to the first starting data, and sends the first preloading starting data to a second processor core of the multi-core heterogeneous chip, wherein the first software system is a software system configured to be deployed on the first processor core, the first processor core and the second processor core are processor cores with different architectures, and a hardware domain where the first processor core is located is a security domain in the multi-core heterogeneous chip;
after the first processor core releases the control authority to the second processor core, the second processor core receives the first preloading starting data and starts a second software system according to the first preloading starting data, wherein the second software system is configured to be deployed on the second processor core.
2. The method of claim 1, wherein the launching the second software system in accordance with the first preload launch data comprises:
pre-starting a second software system based on the first pre-loading starting data;
the second processor core obtains residual second starting data from the target storage medium based on the control authority;
and completing the starting of the second software system according to the second starting data.
3. The method of claim 1, wherein the target storage medium is a storage unit that corresponds in common to each processor core of the multi-core heterogeneous chip.
4. The method of claim 1, wherein controlling the controller to read the first preloaded startup data and the first startup data from the target storage medium based on the control rights comprises:
determining a target storage data partition from among the storage data partitions in the target storage medium;
and controlling the controller to read the first preloading starting data and the first starting data from the target storage data partition according to the control authority.
5. The method according to claim 1, wherein the method further comprises:
the N-1 processor core of the multi-core heterogeneous chip acquires second preloading starting data from the target storage medium based on the control authority and sends the second preloading starting data to the N processor core, wherein N is an integer larger than 2;
after the N-1 processor core is monitored to release the control authority to the N processor core, the N processor core starts an N software system according to the second preloading starting data, wherein the N software system is configured to be deployed on the N processor core, and the N-1 processor core and the N processor core are processor cores with different architectures.
6. The method of claim 1, wherein prior to the first processor core releasing the control authority to the second processor core, the method further comprises:
the first processor core obtains third preloading starting data from the target storage medium according to the control authority, and sends the third preloading starting data to an N-th processor core of the multi-core heterogeneous chip, wherein N is an integer greater than 2;
After the booting of the second software system according to the first preload boot data, the method further comprises:
the N-1 processor core releases the control authority to the N processor core;
and the N-1-th processor core and the N-th processor core are processor cores with different architectures.
7. The method of claim 1, wherein the sending the first preload initiation data to the second processor core of the multi-core heterogeneous chip comprises:
the first processor core stores the first preloading starting data to a designated memory, and sends a storage address of the designated memory to a second processor core of the multi-core heterogeneous chip;
the second processor core receiving the first preload initiation data, comprising:
the second processor core receives the memory address and retrieves the first preload initiation data based on the memory address.
8. The method according to any one of claims 1-7, further comprising:
And initializing the target storage medium according to the control authority after the processor cores acquire the control authority aiming at each processor core of the multi-core heterogeneous chip.
9. A starting device, characterized in that it is applied to a multi-core heterogeneous chip, each processor core of the multi-core heterogeneous chip and a hardware resource connected to the processor core form a hardware domain, and physical isolation exists between each hardware domain in the multi-core heterogeneous chip, the device includes:
the first starting module is used for acquiring control authority of a controller corresponding to a target storage medium in the multi-core heterogeneous chip by a first processor core of the multi-core heterogeneous chip, controlling the controller to read first preloading starting data and first starting data from the target storage medium based on the control authority, starting a first software system according to the first starting data, and sending the first preloading starting data to a second processor core of the multi-core heterogeneous chip, wherein the first software system is a software system configured to be deployed on the first processor core, the first processor core and the second processor core are processor cores with different architectures, and a hardware domain where the first processor core is located is a security domain in the multi-core heterogeneous chip;
And the second starting module is used for receiving the first preloading starting data by the second processor core after the first processor core releases the control authority to the second processor core, and starting a second software system according to the first preloading starting data, wherein the second software system is configured to be deployed on the second processor core.
10. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein, the liquid crystal display device comprises a liquid crystal display device,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.
11. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1-8.
CN202310572074.1A 2023-05-19 2023-05-19 Starting method, starting device, starting equipment and storage medium Pending CN116610370A (en)

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