CN116610262A - Method, device, equipment and medium for reducing SSD sequential reading delay - Google Patents
Method, device, equipment and medium for reducing SSD sequential reading delay Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
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- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to a method, a device, equipment and a medium for reducing SSD sequential read delay, wherein the method comprises the following steps: judging whether the current read command issued by the host meets the triggering condition or not; initiating a pre-reading command and inquiring a mapping table to acquire a flash memory physical address; reading a data page corresponding to the pre-reading command to obtain pre-reading data, and carrying the pre-reading data into a flash memory buffer area; receiving a new read command issued by a host; acquiring a flash memory physical address of a new read command; judging whether the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command; sending a new read command to a flash memory buffer area to obtain pre-read data; and sending the acquired data to the host. According to the application, the logic judgment is added to identify the low command depth sequence read scene, the internal pre-read operation is initiated, the data is loaded into the cache in advance, the data is obtained from the cache and sent to the host, the flash memory page read time can be reduced, and the sequence read delay under the low command depth is reduced.
Description
Technical Field
The application relates to the technical field of SSD sequential reading delay, in particular to a method, a device, equipment and a medium for reducing SSD sequential reading delay.
Background
The sequential read-write performance is an important index parameter for evaluating the SSD, the performance bottleneck of data read-write with large command depth is limited by physical characteristics such as host interface speed, flash memory interface speed and the like, and the performance bottleneck of data read-write with low command depth is not in the physical interface speed, and the command processing flow of the SSD can have great influence on the read-write performance.
The minimum unit of the host computer and the solid state disk for communication is LBA (logical block address), the indicated data size is determined by the host computer, the data read-write amount of each time of the host computer is determined according to the maximum command transmission data amount supported by the SSD and the data amount that the host computer command wants to read, and the data transmission process of the whole command is illustrated by taking a typical 128KB read command as an illustration, as shown in fig. 1:
the host computer issues a read command; after receiving a read command issued by a host, the SSD analyzes the LBA address and the data volume read by the host; the SSD acquires a data physical address according to the logic address query mapping table; the SSD sends a flash memory read command to read data from the flash memory; the SSD waits for the data to be prepared after the flash memory is read; the SSD sends the data read in the flash memory to a host; the SSD returns a command complete state to the host.
The completion of a read command includes multiple steps, serial completion, and the delay time of each stage of the current main stream SSD of fig. 2 to complete the 128K read command is about 75us, which is a considerable delay time for sequential read commands and has a large optimization space.
Disclosure of Invention
The application aims to overcome the defects of the prior art and provides a method, a device, equipment and a medium for reducing SSD sequential reading delay.
In order to solve the technical problems, the application adopts the following technical scheme:
in a first aspect, the present embodiment provides a method for reducing SSD sequential read latency, including the steps of:
judging whether the current read command issued by the host meets the condition of triggering the pre-read command;
if the condition for triggering the pre-reading command is met, the pre-reading command is initiated, and a mapping table of a logical address and a physical address is queried to obtain a flash memory physical address of the pre-reading command;
sending a pre-reading command to the flash memory, reading a data page corresponding to a flash memory physical address of the pre-reading command to obtain pre-reading data, and carrying the pre-reading data into a flash memory buffer area;
receiving a new read command issued by a host;
inquiring a mapping table of a logical address and a physical address according to the new read command to acquire a flash memory physical address of the new read command;
judging whether the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command;
if the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command, the new read command hits the pre-read cache, the new read command is sent to the flash memory buffer area, and pre-read data is acquired from the flash memory buffer area to obtain acquired data;
and sending the acquired data to the host.
The further technical scheme is as follows: the condition for triggering the pre-read command comprises:
all the read command starting and ending addresses are continuous, namely the sequential read condition is satisfied;
the depth of the current read command is 1.
The further technical scheme is as follows: the sending the acquired data to the host includes:
sending the acquired data to a flash memory controller;
the flash memory controller transmits the acquired data to the NVME module;
the NVME module sends the acquired data to the host.
The further technical scheme is as follows: after the step of sending the acquired data to the host, the method further comprises: and replying command completion state information to the host, and sending the next read command after the host receives the command completion state information.
In a second aspect, the present embodiment provides an apparatus for reducing SSD sequential read latency, including: the device comprises a first judging unit, a query initiating and acquiring unit, a sending, reading and carrying-in unit, a receiving unit, a query acquiring unit, a second judging unit, a sending and acquiring unit and a sending unit;
the first judging unit is used for judging whether the current read command issued by the host meets the condition of triggering the pre-read command;
the inquiry initiating and acquiring unit is used for initiating the pre-reading command if the condition for triggering the pre-reading command is met, and inquiring a mapping table of a logical address and a physical address so as to acquire the flash memory physical address of the pre-reading command;
the read carrying-in unit is used for sending a pre-read command to the flash memory, reading a data page corresponding to a flash memory physical address of the pre-read command to obtain pre-read data, and carrying the pre-read data into a flash memory buffer area;
the receiving unit is used for receiving a new read command issued by the host;
the inquiry obtaining unit is used for inquiring the mapping table of the logical address and the physical address according to the new read command so as to obtain the flash memory physical address of the new read command;
the second judging unit is used for judging whether the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command;
the sending and acquiring unit is configured to, if the flash physical address of the new read command is consistent with the flash physical address of the pre-read command, hit the pre-read buffer with the new read command, send the new read command to the flash buffer, and acquire pre-read data from the flash buffer to obtain acquired data;
the sending unit is used for sending the acquired data to the host.
The further technical scheme is as follows: the condition for triggering the pre-read command comprises:
all the read command starting and ending addresses are continuous, namely the sequential read condition is satisfied;
the depth of the current read command is 1.
The further technical scheme is as follows: the transmitting unit includes: the device comprises a first sending module, a second sending module and a third sending module;
the first sending module is used for sending the acquired data to the flash memory controller;
the second sending module is used for transmitting the acquired data to the NVME module by the flash memory controller;
and the third sending module is used for sending the acquired data to the host by the NVME module.
The further technical scheme is as follows: the apparatus further comprises: and the reply transmitting unit is used for replying the command completion state information to the host, and transmitting the next read command after the host receives the command completion state information.
In a third aspect, the present embodiment provides a computer device, where the computer device includes a memory and a processor, where the memory stores a computer program, and the processor implements a method for reducing SSD sequential read latency as described above when executing the computer program.
In a fourth aspect, the present embodiment provides a storage medium storing a computer program comprising program instructions which, when executed by a processor, implement a method of reducing SSD sequential read latency as described above.
Compared with the prior art, the application has the beneficial effects that: the SSD is added with logic to judge and identify a low command depth sequence read scene, under the scene, the SSD actively initiates internal pre-read operation, mapping table inquiry and flash memory read are completed before a host computer sends the next read command, data are loaded into a cache in advance, and when the read command issued by the host computer arrives, the data can be directly obtained from the cache and sent to the host computer.
The application is further described below with reference to the drawings and specific embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of NVME read command processing in the prior art;
FIG. 2 is a diagram illustrating the processing time of 128K read commands according to the prior art;
FIG. 3 is a flowchart illustrating a method for reducing SSD sequential read latency according to an embodiment of the present application;
FIG. 4 is a schematic diagram of command depth determination according to an embodiment of the present application;
FIG. 5 is a schematic diagram of post-optimization delay analysis provided by an embodiment of the present application;
FIG. 6 is a schematic block diagram of an apparatus for reducing SSD sequential read latency provided by an embodiment of the present application;
fig. 7 is a schematic block diagram of a computer device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
Referring to the embodiment shown in fig. 3 to 5, the application discloses a method for reducing sequential read delay of SSD, comprising the following steps:
s1, judging whether a current read command issued by a host meets the condition of triggering a pre-read command; if the condition triggering the pre-read command is not satisfied, the host read command is normally executed, and the pre-read mechanism is not triggered.
In an embodiment, the condition for triggering the pre-read command includes:
all the read command starting and ending addresses are continuous, namely the sequential read condition is satisfied;
the current read command has a depth of 1, i.e., the command depth determination logic shown in FIG. 4 returns a result of 1.
Specifically, referring to fig. 4, taking 2 queues as an example, the difference between the tail pointers of all the completion queues and the tail pointer of the commit queue is calculated as the depth of the current read command.
Specifically, because the sequential read condition is satisfied, the logical address of the read-ahead command initiated by the SSD is the pre-calculated logical address of the next host to be read.
S2, if the condition for triggering the pre-reading command is met, initiating the pre-reading command, and inquiring a mapping table of a logical address and a physical address to acquire a flash memory physical address of the pre-reading command;
specifically, when the condition of triggering the pre-read command is satisfied, the pre-read command is initiated in the SSD, and the mapping table of the logical address and the physical address is queried through the FTL algorithm module, so as to obtain the flash memory physical address of the pre-read command.
S3, sending a pre-reading command to the flash memory, reading a data page corresponding to a flash memory physical address of the pre-reading command to obtain pre-reading data, and carrying the pre-reading data into a flash memory buffer area;
specifically, the SSD sends a pre-read command to the flash memory through the flash memory controller, the pre-read command does not require the flash memory to return data, at this time, the SSD records a physical data page address corresponding to the flash memory buffer, and the flash memory reads the physical address data page corresponding to the pre-read command to obtain pre-read data, and then carries the pre-read data into the flash memory buffer.
S4, receiving a new read command issued by the host;
s5, inquiring a mapping table of a logical address and a physical address according to the new read command to acquire a flash memory physical address of the new read command;
specifically, according to the new read command SSD, the FTL algorithm module inside the SSD queries a mapping table of logical addresses and physical addresses to obtain the flash memory physical addresses of the new read command.
S6, judging whether the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command; if the flash physical address of the new read command is inconsistent with the flash physical address of the pre-read command, the new read command does not hit the cache, and a flash data page read command needs to be sent to read data from the original data address.
S7, if the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command, the new read command hits the pre-read cache, the new read command is sent to the flash memory buffer area, and pre-read data is acquired from the flash memory buffer area to obtain acquired data;
s8, sending the acquired data to the host.
In one embodiment, the sending the acquired data to the host includes:
sending the acquired data to a flash memory controller;
the flash memory controller transmits the acquired data to the NVME module;
specifically, the application takes NVME SSD as an example, and the data interaction between the SSD and the host is realized through NVME protocol.
The NVME module sends the acquired data to the host.
In an embodiment, after the step of sending the acquired data to the host, the method further includes: and replying command completion state information to the host, and sending the next read command after the host receives the command completion state information.
Referring to fig. 5, in order to enable the SSD performance test data (the test tool is an IO meter, and the sequential reading is within 1G) before and after the pre-reading function, it can be seen from the figure that since the SSD sends the read command in advance to read the data to the flash memory buffer, the flash memory data page reading time can be saved, and the average delay time of the whole command is reduced from 75us to 45us, so that the corresponding performance is greatly improved.
According to the method, a logic judgment is added to the SSD to identify a low command depth sequence read scene, the SSD actively initiates internal pre-reading operation under the scene, mapping table inquiry and flash memory reading are completed before a host sends a next read command, data are loaded into a cache in advance, and when the read command sent by the host arrives, the data can be directly obtained from the cache and sent to the host.
Referring to fig. 6, the application also discloses a device for reducing SSD sequential read delay, including: a first judgment unit 10, an inquiry initiation acquisition unit 20, a transmission reading carry-in unit 30, a reception unit 40, an inquiry acquisition unit 50, a second judgment unit 60, a transmission acquisition unit 70, and a transmission unit 80;
the first judging unit 10 is configured to judge whether a current read command issued by the host meets a condition for triggering a pre-read command;
the query initiation acquiring unit 20 is configured to initiate a pre-read command if a condition for triggering the pre-read command is satisfied, and query a mapping table of a logical address and a physical address to acquire a flash physical address of the pre-read command;
the sending and reading carry-in unit 30 is configured to send a pre-reading command to the flash memory, and read a data page corresponding to a flash memory physical address of the pre-reading command, so as to obtain pre-reading data, and carry the pre-reading data into a flash memory buffer;
the receiving unit 40 is configured to receive a new read command issued by the host;
the query obtaining unit 50 is configured to query a mapping table of logical addresses and physical addresses according to a new read command to obtain a flash physical address of the new read command;
the second judging unit 60 is configured to judge whether the flash physical address of the new read command is consistent with the flash physical address of the pre-read command;
the sending and obtaining unit 70 is configured to, if the flash physical address of the new read command is consistent with the flash physical address of the pre-read command, hit the pre-read buffer with the new read command, send the new read command to the flash buffer, and obtain pre-read data from the flash buffer to obtain obtained data;
the sending unit 80 is configured to send the acquired data to a host.
In an embodiment, the condition for triggering the pre-read command includes:
all the read command starting and ending addresses are continuous, namely the sequential read condition is satisfied;
the depth of the current read command is 1.
In one embodiment, the transmitting unit 80 includes: the device comprises a first sending module, a second sending module and a third sending module;
the first sending module is used for sending the acquired data to the flash memory controller;
the second sending module is used for transmitting the acquired data to the NVME module by the flash memory controller;
and the third sending module is used for sending the acquired data to the host by the NVME module.
In an embodiment, the device further comprises: and the reply transmitting unit is used for replying the command completion state information to the host, and transmitting the next read command after the host receives the command completion state information.
It should be noted that, as those skilled in the art can clearly understand, the above-mentioned device for reducing the sequential read delay of the SSD and the specific implementation process of each unit may refer to the corresponding descriptions in the foregoing method embodiments, and for convenience and brevity of description, the description is omitted here.
The above-described means for reducing SSD sequential read latency may be implemented in the form of a computer program that is executable on a computer device as shown in fig. 7.
Referring to fig. 7, fig. 7 is a schematic block diagram of a computer device according to an embodiment of the present application; the computer device 500 may be a terminal or a server, where the terminal may be an electronic device with a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster formed by a plurality of servers.
With reference to FIG. 7, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.
The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform a method of reducing SSD sequential read latency.
The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.
The internal memory 504 provides an environment for the execution of a computer program 5032 in the non-volatile storage medium 503, which computer program 5032, when executed by the processor 502, causes the processor 502 to perform a method of reducing SSD sequential read latency.
The network interface 505 is used for network communication with other devices. It will be appreciated by those skilled in the art that the architecture shown in fig. 7 is merely a block diagram of some of the architecture relevant to the present inventive arrangements and is not limiting of the computer device 500 to which the present inventive arrangements may be implemented, as a particular computer device 500 may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
Wherein the processor 502 is configured to execute a computer program 5032 stored in a memory to implement the steps of:
judging whether the current read command issued by the host meets the condition of triggering the pre-read command; if the condition for triggering the pre-reading command is met, the pre-reading command is initiated, and a mapping table of a logical address and a physical address is queried to obtain a flash memory physical address of the pre-reading command; sending a pre-reading command to the flash memory, reading a data page corresponding to a flash memory physical address of the pre-reading command to obtain pre-reading data, and carrying the pre-reading data into a flash memory buffer area; receiving a new read command issued by a host; inquiring a mapping table of a logical address and a physical address according to the new read command to acquire a flash memory physical address of the new read command; judging whether the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command; if the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command, the new read command hits the pre-read cache, the new read command is sent to the flash memory buffer area, and pre-read data is acquired from the flash memory buffer area to obtain acquired data; and sending the acquired data to the host.
It should be appreciated that in an embodiment of the application, the processor 502 may be a central processing unit (Central Processing Unit, CPU), the processor 502 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Those skilled in the art will appreciate that all or part of the flow in a method embodying the above described embodiments may be accomplished by computer programs instructing the relevant hardware. The computer program comprises program instructions, and the computer program can be stored in a storage medium, which is a computer readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.
Accordingly, the present application also provides a storage medium. The storage medium may be a computer readable storage medium. The storage medium stores a computer program, wherein the computer program comprises program instructions which, when executed by a processor, implement the above-described method of reducing SSD sequential read latency. The storage medium stores a computer program comprising program instructions which, when executed by a processor, implement the method described above. The program instructions include the steps of:
judging whether the current read command issued by the host meets the condition of triggering the pre-read command; if the condition for triggering the pre-reading command is met, the pre-reading command is initiated, and a mapping table of a logical address and a physical address is queried to obtain a flash memory physical address of the pre-reading command; sending a pre-reading command to the flash memory, reading a data page corresponding to a flash memory physical address of the pre-reading command to obtain pre-reading data, and carrying the pre-reading data into a flash memory buffer area; receiving a new read command issued by a host; inquiring a mapping table of a logical address and a physical address according to the new read command to acquire a flash memory physical address of the new read command; judging whether the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command; if the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command, the new read command hits the pre-read cache, the new read command is sent to the flash memory buffer area, and pre-read data is acquired from the flash memory buffer area to obtain acquired data; and sending the acquired data to the host.
The storage medium may be a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, or other various computer-readable storage media that can store program codes.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed.
The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the application can be combined, divided and deleted according to actual needs. In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The integrated unit may be stored in a storage medium if implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a terminal, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application.
The foregoing embodiments are preferred embodiments of the present application, and in addition, the present application may be implemented in other ways, and any obvious substitution is within the scope of the present application without departing from the concept of the present application.
Claims (10)
1. The method for reducing the SSD sequential read delay is characterized by comprising the following steps:
judging whether the current read command issued by the host meets the condition of triggering the pre-read command;
if the condition for triggering the pre-reading command is met, the pre-reading command is initiated, and a mapping table of a logical address and a physical address is queried to obtain a flash memory physical address of the pre-reading command;
sending a pre-reading command to the flash memory, reading a data page corresponding to a flash memory physical address of the pre-reading command to obtain pre-reading data, and carrying the pre-reading data into a flash memory buffer area;
receiving a new read command issued by a host;
inquiring a mapping table of a logical address and a physical address according to the new read command to acquire a flash memory physical address of the new read command;
judging whether the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command;
if the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command, the new read command hits the pre-read cache, the new read command is sent to the flash memory buffer area, and pre-read data is acquired from the flash memory buffer area to obtain acquired data;
and sending the acquired data to the host.
2. The method of reducing SSD sequential read latency of claim 1, wherein the condition triggering a read-ahead command comprises:
all the read command starting and ending addresses are continuous, namely the sequential read condition is satisfied;
the depth of the current read command is 1.
3. The method of reducing SSD sequential read latency of claim 1, wherein the sending the fetch data to the host comprises:
sending the acquired data to a flash memory controller;
the flash memory controller transmits the acquired data to the NVME module;
the NVME module sends the acquired data to the host.
4. The method of reducing SSD sequential read latency of claim 1, further comprising, after the step of sending the fetch data to the host: and replying command completion state information to the host, and sending the next read command after the host receives the command completion state information.
5. An apparatus for reducing SSD sequential read latency, comprising: the device comprises a first judging unit, a query initiating and acquiring unit, a sending, reading and carrying-in unit, a receiving unit, a query acquiring unit, a second judging unit, a sending and acquiring unit and a sending unit;
the first judging unit is used for judging whether the current read command issued by the host meets the condition of triggering the pre-read command;
the inquiry initiating and acquiring unit is used for initiating the pre-reading command if the condition for triggering the pre-reading command is met, and inquiring a mapping table of a logical address and a physical address so as to acquire the flash memory physical address of the pre-reading command;
the read carrying-in unit is used for sending a pre-read command to the flash memory, reading a data page corresponding to a flash memory physical address of the pre-read command to obtain pre-read data, and carrying the pre-read data into a flash memory buffer area;
the receiving unit is used for receiving a new read command issued by the host;
the inquiry obtaining unit is used for inquiring the mapping table of the logical address and the physical address according to the new read command so as to obtain the flash memory physical address of the new read command;
the second judging unit is used for judging whether the flash memory physical address of the new read command is consistent with the flash memory physical address of the pre-read command;
the sending and acquiring unit is configured to, if the flash physical address of the new read command is consistent with the flash physical address of the pre-read command, hit the pre-read buffer with the new read command, send the new read command to the flash buffer, and acquire pre-read data from the flash buffer to obtain acquired data;
the sending unit is used for sending the acquired data to the host.
6. The apparatus for reducing SSD sequential read latency of claim 5, wherein the condition that triggers a read-ahead command comprises:
all the read command starting and ending addresses are continuous, namely the sequential read condition is satisfied;
the depth of the current read command is 1.
7. The apparatus for reducing SSD sequential read latency of claim 5, wherein the transmitting unit comprises: the device comprises a first sending module, a second sending module and a third sending module;
the first sending module is used for sending the acquired data to the flash memory controller;
the second sending module is used for transmitting the acquired data to the NVME module by the flash memory controller;
and the third sending module is used for sending the acquired data to the host by the NVME module.
8. The apparatus for reducing SSD sequential read latency of claim 5, further comprising: and the reply transmitting unit is used for replying the command completion state information to the host, and transmitting the next read command after the host receives the command completion state information.
9. A computer device comprising a memory and a processor, the memory having stored thereon a computer program, the processor implementing the method of reducing SSD sequential read latency as recited in any of claims 1-4 when the computer program is executed.
10. A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement the method of reducing SSD sequential read latency as recited in any of claims 1-4.
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| CN117032594A (en) * | 2023-10-09 | 2023-11-10 | 北京忆恒创源科技股份有限公司 | Read command scheduling method, processing method, device and storage equipment |
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| CN117032594A (en) * | 2023-10-09 | 2023-11-10 | 北京忆恒创源科技股份有限公司 | Read command scheduling method, processing method, device and storage equipment |
| CN117032594B (en) * | 2023-10-09 | 2024-01-23 | 北京忆恒创源科技股份有限公司 | Read command scheduling method, processing method, device and storage equipment |
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