CN116600597A

CN116600597A - Display panel and display device

Info

Publication number: CN116600597A
Application number: CN202211558803.XA
Authority: CN
Inventors: 刘畅畅; 方飞; 石领
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-12-06
Filing date: 2022-12-06
Publication date: 2023-08-15

Abstract

The present disclosure provides a display panel and a display device. The display panel comprises a substrate, at least one conducting layer and a first switching layer, wherein the conducting layer comprises a plurality of driving signal lines and a plurality of signal switching lines, the orthographic projection of the driving signal lines on the substrate extends along the direction of a pixel row, and the driving signal lines are used for providing GOA for at least part of transistors in the pixel driving circuit; the signal switching line is positioned in a transition area between the first display area and the second display area and is used for connecting driving signal lines for transmitting the same GOA in a first sub-pixel row and a second sub-pixel row in the same pixel row; the first switching layer comprises a plurality of bridging lines, orthographic projections of the bridging lines on the substrate extend along the pixel row direction and are positioned in the first display area, and the bridging lines are connected with gate signal lines which transmit the same GOA in two adjacent pixel driving circuits in the same sub-pixel row.

Description

Display panel and display device

Technical Field

The disclosure relates to the technical field of display, in particular to a display panel and a display device.

Background

With the development of the full-screen display technology in the forms of Liu Haibing, perforated screens, water drop screens, lifting screens and the like, the requirements of consumers on the full-screen display technology are higher.

The full screen generally places a sensor such as a camera on the side of the lower non-display surface of the display substrate, and the under-screen image pickup area has certain transmittance and a display function. In the related art, there is a display problem in an under-screen image pickup area.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to overcoming the drawbacks of the prior art and providing a display panel and a display device.

According to one aspect of the present disclosure, there is provided a display panel including a first display region for image display and transmitting light, and a second display region at least partially surrounding the first display region for image display; the first display area comprises a plurality of pixel rows, the pixel rows comprise a first sub-pixel row and a second sub-pixel row, the first sub-pixel row and the second sub-pixel row are not overlapped, and the first sub-pixel row and the second sub-pixel row comprise a plurality of pixel driving circuits; the display panel further includes: a substrate base; at least one conductive layer located on one side of the substrate base plate, the conductive layer comprising: a plurality of driving signal lines extending in a pixel row direction in orthographic projection on the substrate, the driving signal lines for supplying gate driving signals to at least part of the transistors in the pixel driving circuit; the signal switching lines are positioned in a transition region between the first display region and the second display region and are used for connecting driving signal lines for transmitting the same grid driving signals in a first sub-pixel row and a second sub-pixel row in the same pixel row; the first transfer layer is positioned on one side of the conducting layer, which is away from the substrate, and the first transfer layer comprises a plurality of bridging lines, the orthographic projections of the bridging lines on the substrate extend along the pixel row direction and are positioned in the first display area, and the bridging lines are connected with gate signal lines for transmitting the same gate driving signals in two adjacent pixel driving circuits in the same sub-pixel row.

In an exemplary embodiment of the present disclosure, in the same pixel row, the driving signal lines transmitting the same gate driving signal in any adjacent two pixel driving circuits located in the first display region are all connected by corresponding to the bridge lines.

In an exemplary embodiment of the present disclosure, in the same pixel row, in any two adjacent pixel driving circuits located in the first display area, driving signal lines partially transmitting the same gate driving signal are connected through corresponding bridge lines, and driving signal lines partially transmitting the same gate driving signal are connected through signal connection lines located in the conductive layer.

In an exemplary embodiment of the present disclosure, the plurality of bridge lines includes a first bridge line and a second bridge line, the first bridge line is connected to a driving signal line transmitting the same gate driving signal in two adjacent pixel driving circuits in the first subpixel row, and the second bridge line is connected to a driving signal line transmitting the same gate driving signal in two adjacent pixel driving circuits in the second subpixel row.

In an exemplary embodiment of the present disclosure, each pixel driving circuit includes a first transistor, a second transistor, and fourth to seventh transistors, where a gate of the first transistor is connected to a reset signal terminal, a gate of the second transistor is connected to a second gate signal terminal, gates of the fifth and sixth transistors are both connected to an enable signal terminal, and gates of the fourth and seventh transistors are both connected to a first gate signal terminal; the at least one conductive layer includes: a first conductive layer located at one side of the substrate base plate, the first conductive layer comprising: an enable signal line having a partial structure for forming a gate of the fifth transistor and a partial structure for forming a gate of the sixth transistor; a first gate signal line having a partial structure for forming a gate of the fourth transistor and a partial structure for forming a gate of the seventh transistor; a third conductive layer between the first conductive layer and the first transfer layer, the third conductive layer comprising: a fourth gate signal line having a partial structure for forming a top gate of the second transistor; a second reset signal line, part of which is used for forming a top gate of the first transistor; the orthographic projections of the enabling signal lines, the first grid signal lines, the fourth grid signal lines and the second reset signal lines on the substrate base plate are distributed at intervals along the pixel column direction.

In an exemplary embodiment of the present disclosure, the display panel further includes: a fourth conductive layer between the third conductive layer and the first transfer layer, the fourth conductive layer comprising: an eighth bridge portion connected to one end of the first gate signal line through a via hole; a ninth bridge portion connected to the other end of the first gate signal line through a via hole; the first bridge wire comprises a first sub-bridge wire and a second sub-bridge wire, and the first sub-bridge wire is connected with an eighth bridge part of one pixel driving circuit and a ninth bridge part of the adjacent other pixel driving circuit in a first sub-pixel row through a through hole respectively so as to be connected with the adjacent first grid signal wire; the second sub-bridge wire is connected with the enabling signal wires in the two adjacent pixel driving circuits in the first sub-pixel row through the through holes respectively; the second bridge wire comprises a tenth sub-bridge wire and a twentieth sub-bridge wire, and the tenth sub-bridge wire is connected with an eighth bridge part of a pixel driving circuit in a second sub-pixel row and a ninth bridge part of an adjacent other pixel driving circuit through a via hole respectively so as to be connected with the adjacent first grid signal wire; the twenty-second sub-bridge wire is connected with the enabling signal wires in the two adjacent pixel driving circuits in the second sub-pixel row through the through holes respectively.

In an exemplary embodiment of the present disclosure, the display panel further includes: a fourth conductive layer between the third conductive layer and the first transfer layer, the fourth conductive layer comprising: a first bridge portion connected to one end of the fourth gate signal line through a via hole; the second bridging part is connected with the second reset signal line through a via hole; a sixth bridge portion connected to the other end of the fourth gate signal line through a via hole; the first bridge wire further comprises a third sub-bridge wire and a fifth sub-bridge wire, and the third sub-bridge wire is connected with the sixth bridge part of one pixel driving circuit and the first bridge part of the other pixel driving circuit in the first sub-pixel row through a through hole respectively so as to be connected with the fourth grid electrode signal wire in the two pixel driving circuits; the fifth sub-bridge wire is connected with the second bridging part of one pixel driving circuit and the second bridging part of the adjacent other pixel driving circuit in the first sub-pixel row through a through hole respectively so as to be connected with the reset signal wire in the adjacent two pixel driving circuits; the second bridge line further comprises a thirty-first bridge line and a fifty-second bridge line, wherein the thirty-first bridge line is respectively connected with the sixth bridge part of one pixel driving circuit in a second sub-pixel row and the first bridge part of the other adjacent pixel driving circuit so as to be connected with the fourth grid electrode signal line of the two adjacent pixel driving circuits; the fifty-th sub-bridge line is connected to the second bridge portion of one pixel driving circuit and the second bridge portion of the adjacent other pixel driving circuit in the second sub-pixel row, respectively, so as to connect the reset signal lines in the adjacent two pixel driving circuits.

In an exemplary embodiment of the present disclosure, the first conductive layer further includes: a first gate signal patch cord connected to the first gate signal lines in two adjacent pixel driving circuits in a first subpixel row; and the second grid signal patch cord is connected with the first grid signal lines in two adjacent pixel driving circuits in the second sub-pixel row.

In an exemplary embodiment of the present disclosure, the third conductive layer further includes: a first reset signal patch cord connected to the second reset signal lines in two adjacent pixel driving circuits in the first subpixel row; and the second reset signal patch cord is connected with the reset signal lines in two adjacent pixel driving circuits in the second sub-pixel row.

In an exemplary embodiment of the present disclosure, in the same pixel row, a front projection of a first gate signal patch cord on the substrate overlaps a front projection portion of the second reset signal patch cord on the substrate; in any two adjacent pixel rows, the orthographic projection of the second reset signal switching wire of the previous pixel row on the substrate is overlapped with the orthographic projection part of the first grid signal switching wire of the next pixel row on the substrate.

In an exemplary embodiment of the present disclosure, in the same pixel row, a front projection of the second reset signal patch cord on the substrate is located on a front projection of the enable signal cord in the first subpixel row on the substrate; in any two adjacent pixel rows, the orthographic projection of the first reset signal patch cord of the next pixel row on the substrate is positioned on the orthographic projection of the enabling signal cord of the second sub-pixel row in the previous pixel row on the substrate.

In an exemplary embodiment of the present disclosure, the first conductive layer further includes: the first enabling signal switching line is positioned in a transition region between the first display region and the second display region, and orthographic projection of the first enabling signal switching line on the substrate extends along the direction of the pixel columns; in the same pixel row, the first enabling signal patch cord is respectively connected with the enabling signal line in the first sub-pixel row and the enabling signal line in the second sub-pixel row.

In an exemplary embodiment of the present disclosure, the fourth conductive layer further includes: the third reset signal switching line is positioned in a transition area between the first display area and the second display area; in the same pixel row, the third reset signal patch cord is respectively connected with the second bridging portion in the first sub-pixel row and the second bridging portion in the second sub-pixel row.

In an exemplary embodiment of the present disclosure, the fourth conductive layer further includes: the third grid signal switching line is positioned in a transition region between the first display region and the second display region, and orthographic projection of the third grid signal switching line on the substrate extends along the direction of the pixel columns; in the same pixel row, the third gate signal patch cord is connected to the eighth bridge portion in the first sub-pixel row and the ninth bridge portion in the second sub-pixel row respectively.

In an exemplary embodiment of the present disclosure, the third conductive layer further includes: a fourth gate signal patch cord located in a transition region between the first display region and the second display region, wherein a orthographic projection of the fourth gate signal patch cord on the substrate extends along a pixel column direction; in the same pixel row, the fourth gate signal patch cord is respectively connected with the fourth gate signal line in the first sub-pixel row and the fourth gate signal line in the second sub-pixel row; the fourth gate signal patch cord is located between two adjacent second reset signal lines in the second sub-pixel row.

In an exemplary embodiment of the present disclosure, an orthographic projection of the fourth gate signal patch cord on the substrate overlaps with an orthographic projection portion of the third gate signal patch cord on the substrate.

In an exemplary embodiment of the present disclosure, the first conductive layer further includes: a first gate signal bridge line located at a transition region between the first display region and the second display region; in the same pixel row, the first gate signal bridging line is connected to the first gate signal line in the first sub-pixel row and the first gate signal line in the second sub-pixel row respectively.

In an exemplary embodiment of the present disclosure, the third conductive layer further includes: a fourth reset signal patch cord located in a transition region between the first display region and the second display region, wherein a orthographic projection of the fourth reset signal patch cord on the substrate extends along a pixel column direction; in the same pixel row, the fourth reset signal patch cord is respectively connected with the first reset signal patch cord in the first sub-pixel row and the second reset signal patch cord in the second sub-pixel row, and the fourth reset signal patch cord is located between two adjacent fourth gate signal lines in the first sub-pixel row.

In an exemplary embodiment of the present disclosure, the third conductive layer further includes: a fifth gate signal patch cord located at a transition region between the first display region and the second display region; the fifth gate signal patch cord is respectively connected with the fourth gate signal line in the first sub-pixel row and the fourth gate signal line in the second sub-pixel row, and orthographic projection of the fifth gate signal patch cord on the substrate overlaps with orthographic projection of the first gate signal patch cord on the substrate.

In an exemplary embodiment of the present disclosure, the display panel further includes: a fourth conductive layer between the third conductive layer and the first transfer layer, the fourth conductive layer comprising: the second enabling signal switching line is positioned in a transition area between the first display area and the second display area; in the same pixel row, the second enabling signal patch cord is connected with the enabling signal line in the first sub-pixel row and the enabling signal line in the second sub-pixel row through a through hole respectively.

In an exemplary embodiment of the disclosure, the second enable signal patch cord includes a first component and a second component, the orthographic projection of the first component on the substrate is located on the orthographic projection of the first gate signal bridge cord on the substrate, and the orthographic projection of the second component on the substrate is located on the orthographic projection of the first reset signal patch cord in the next pixel row on the substrate.

In an exemplary embodiment of the present disclosure, each pixel driving circuit further includes a driving transistor, a first pole of the first transistor being connected to a gate of the driving transistor; the first pole of the second transistor is connected with the grid electrode of the driving transistor, and the second pole of the second transistor is connected with the first pole of the driving transistor; the first electrode of the fourth transistor and the first electrode of the fifth transistor are both connected with the second electrode of the driving transistor, the first electrode of the sixth transistor is connected with the first electrode of the driving transistor, and the first electrode of the seventh transistor is connected with the second electrode of the sixth transistor; the display panel further includes: a first active layer between the substrate base plate and the first conductive layer, the first active layer comprising: a third active portion for forming a channel region of the driving transistor; a fourth active portion for forming a channel region of the fourth transistor; a fifth active portion for forming a channel region of a fifth transistor; a sixth active portion for forming a channel region of the sixth transistor; a seventh active part for forming a channel region of the seventh transistor; a second conductive layer between the first conductive layer and the third conductive layer, the second conductive layer comprising: a second gate signal line, the orthographic projection on the substrate covering the orthographic projection of the second active portion on the substrate and being located on the orthographic projection of the fourth gate signal line on the substrate, a part of the second gate signal line being used for forming a bottom gate of the second transistor; a first reset signal line, wherein the orthographic projection of the first active part on the substrate is covered by the orthographic projection of the first active part on the substrate and overlapped with the orthographic projection part of the second reset signal line on the substrate, and a part of the first reset signal line is used for forming a bottom gate of the first transistor; a second active layer between the second conductive layer and the third conductive layer, the second active layer comprising: the first active part is used for forming a channel region of the first transistor; the second active part is used for forming a channel region of the second transistor; the enabling signal line, the first grid signal line, the fourth grid signal line and the first reset signal line are sequentially distributed in the direction of pixel columns in orthographic projection mode on the substrate; the fourth active portion and the fifth active portion are located at one side of the third active portion in the pixel row direction, and the sixth active portion and the seventh active portion are located at the other side of the third active portion in the pixel row direction.

In an exemplary embodiment of the present disclosure, the second pole of the first transistor and the second pole of the seventh transistor are both connected to an initialization signal line; the first active layer further includes: a seventh sub-active portion connected to one side of the seventh active portion for forming a second pole of the seventh transistor; the second active layer further includes: a ninth sub-active portion connected to one side of the first active portion for forming a second pole of the first transistor; the display panel further includes: a fourth conductive layer between the third conductive layer and the first transfer layer, the fourth conductive layer further comprising: initializing a signal line, wherein orthographic projection on the substrate extends along the pixel row direction, one end of the initial signal line is connected with the ninth sub-active part through a via hole, and the other end of the initial signal line is connected with the seventh sub-active part through a via hole; the first bridge wire further comprises a fourth sub-bridge wire, and the fourth sub-bridge wire is connected with the initialization signal wires in two adjacent pixel driving circuits in the first sub-pixel row through the through holes respectively; the second bridge line further includes a forty-second bridge line, one end of the forty-second bridge line being connected to the initialization signal line in two adjacent pixel driving circuits in the second sub-pixel row through a via hole.

According to a second aspect of the present disclosure, there is also provided a display device including the display panel according to any embodiment of the present disclosure.

In the display panel provided by the disclosure, in the first display area, because the same pixel row comprises the first sub-pixel row and the second sub-pixel row, driving signal lines for transmitting the same signal in the same pixel row are not on the same straight line, the bridge lines are arranged at the part of the first switching layer, which is positioned in the first display area, of the display panel, the driving signal lines for transmitting the same signal in each pixel driving circuit in the same sub-pixel row are connected by the bridge lines, and then the driving signal lines for transmitting the same signal in two sub-pixel rows in the same pixel row are connected by the conducting layer in the transition area of the first display area and the second display area, so that the driving signal lines which are arranged in a staggered manner in the same pixel row are not connected with each other, thereby the bridge lines of the first switching layer can be simplified, and because of space optimization, the line width of each bridge line of the first switching layer can be widened, thereby being beneficial to reducing the load of the line.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic circuit configuration diagram of a pixel driving circuit in a display panel according to an embodiment of the present disclosure;

FIG. 2 is a timing diagram of nodes in a driving method of the pixel driving circuit of FIG. 1;

fig. 3 is a schematic structural view of a display panel according to an embodiment of the present disclosure;

FIG. 4 is a partial enlarged view of the first display area of FIG. 3;

FIG. 5 is a structural layout of a display panel according to one embodiment of the present disclosure;

FIG. 6 is a structural layout of a display panel in a transition region of a first display region and a second display region according to one embodiment of the present disclosure;

FIG. 7 is a structural layout of a display panel according to another embodiment of the present disclosure;

FIG. 8 is a structural layout of a display panel in a transition region of a first display region and a second display region according to another embodiment of the present disclosure;

FIG. 9 is a structural layout of the first active layer of FIG. 5;

FIG. 10 is a layout of the first conductive layer of FIG. 5;

FIG. 11 is a layout of the first conductive layer of FIG. 6;

FIG. 12 is a layout of the first conductive layer of FIG. 7;

FIG. 13 is a layout of the first conductive layer of FIG. 8;

FIG. 14 is a layout of the second conductive layer of FIG. 5;

FIG. 15 is a layout of the second active layer of FIG. 5;

FIG. 16 is a layout of the third conductive layer of FIG. 5;

FIG. 17 is a layout of the third conductive layer of FIG. 6;

FIG. 18 is a layout of the third conductive layer of FIG. 7;

FIG. 19 is a layout of the third conductive layer of FIG. 8;

FIG. 20 is a layout of the fourth conductive layer of FIG. 5;

FIG. 21 is a layout of the fourth conductive layer of FIG. 6;

FIG. 22 is a layout of the fourth conductive layer of FIG. 8;

FIG. 23 is a layout of the first interposer of FIG. 5;

fig. 24 is a structural layout of the first switching layer in fig. 7.

FIG. 25 is a layout of the second interposer of FIG. 5;

FIG. 26 is a layout of the fifth conductive layer of FIG. 5;

FIG. 27 is a layout of the fourth conductive layer and the first switching layer of FIG. 5;

FIG. 28 is a layout of the first interposer and the second interposer of FIG. 5;

FIG. 29 is a layout structure of the first conductive layer and the third conductive layer of FIG. 8;

FIG. 30 is a layout structure of the first, third and fourth conductive layers of FIG. 8;

fig. 31 is a partial cross-sectional view taken along the broken line AA in fig. 5.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The matched reference numerals in the drawings denote matched or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Fig. 1 is a schematic circuit diagram of a pixel driving circuit in a display panel according to an embodiment of the present disclosure. The pixel driving circuit may include: the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the storage capacitor Cst. Wherein, the second pole of the first transistor T1 is connected with the initial signal terminal Vinit, the first pole is connected with the first node N1, and the grid is connected with the Reset signal terminal reset_N; the first pole of the second transistor T2 is connected with the grid electrode of the driving transistor T3, the second pole is connected with the second node N2, and the grid electrode is connected with the second grid electrode driving signal end gate_N; the gate of the driving transistor T3 is connected to the first node N1; the second pole of the fourth transistor T4 is connected with the Data signal end Data, the first pole is connected with the second pole of the driving transistor T3, and the grid is connected with the first grid driving signal end gate_P; the first pole of the fifth transistor T5 is connected with the second pole of the driving transistor T3, the second pole is connected with the first power supply end VDD, and the grid electrode is connected with the enabling signal end EM; the first pole of the sixth transistor T6 is connected with the first pole of the driving transistor T3, and the grid electrode is connected with the enabling signal end EM; the second pole of the seventh transistor T7 is connected to the initial signal terminal Vinit, the first pole is connected to the second pole of the sixth transistor T6, and the Gate is connected to the first Gate driving signal terminal gate_p. The storage capacitor Cst is connected between the gate of the driving transistor T3 and the first power supply terminal VDD. The pixel driving circuit may be connected to a light emitting unit OLED for driving the light emitting unit OLED to emit light, and the light emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power source terminal VSS. The first transistor T1 and the second transistor T2 may be N-type transistors, for example, the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors, and the N-type metal oxide transistors have smaller leakage current, so that the light emitting stage can be avoided, and the node N2 leaks electricity through the first transistor T1 and the second transistor T2. Meanwhile, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low temperature polysilicon transistors having higher carrier mobility, thereby being beneficial to realizing a display panel with high resolution, high reaction speed, high pixel density, and high aperture ratio.

It should be noted that, the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.

Fig. 2 is a timing diagram of each node in a driving method of the pixel driving circuit in fig. 1. Wherein G1 represents the timing of the first Gate driving signal terminal gate_p, G2 represents the timing of the second Gate driving signal terminal gate_n, re represents the timing of the Reset signal terminal reset_n, and EM represents the timing of the enable signal terminal EM. The driving method of the pixel driving circuit may include a reset phase t1, a compensation phase t2, and a light emitting phase t3. In the reset phase t1: the Reset signal terminal reset_n outputs a high level signal, the first transistor T1 is turned on, and the initial signal terminal Vinit inputs an initial signal to the first node N1. In the compensation phase t2: the second Gate driving signal terminal gate_n outputs a high level signal, the first Gate driving signal terminal gate_p outputs a low level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the Data signal terminal Data outputs a Data signal to write a voltage vdata+vth (i.e., a sum of the voltages Vdata and Vth) to the second node N2, wherein Vdata is a Data voltage of the Data signal terminal, and Vth is a threshold voltage of the driving transistor T3. Light emitting phase t3: the enable signal terminal EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage vdata+vth stored in the capacitor Cst.

According to the output current formula I= of the driving transistorμWCox/2L)(Vgs-Vth) ² Wherein μ is carrier mobility; cox is the gate storage capacitance per unit area, W is the width of the drive transistor channel, L is the length of the drive transistor channel, vgs is the drive transistor gate-source voltage difference, and Vth is the drive transistor threshold voltage. Output current i= (μwcox/2L) (vdata+vth-Vdd-Vth) of driving transistor in the pixel driving circuit of the present disclosure ² . The pixel driving circuit can avoid the influence of the threshold value of the driving transistor on the output current of the driving transistor.

The display panel provided by the present exemplary embodiment may include a plurality of pixel driving circuits distributed in an array along a pixel row direction and a pixel column direction, the pixel driving circuits for driving the light emitting devices to emit light, the pixel row direction and the pixel column direction being added.

Fig. 3 is a schematic structural view of a display panel according to an embodiment of the present disclosure, and fig. 4 is a partial enlarged view of a first display area in fig. 3, and as shown in fig. 3 and 4, the display panel of the present disclosure may include a first display area 101 and a second display area 102 at least partially surrounding the first display area 101, the first display area 101 being used for image display and transmitting light, the second display area 102 being used for image display; the first display area 101 may include a plurality of pixel rows X0, each pixel row X0 includes a first sub-pixel row X1 and a second sub-pixel row X2, the first sub-pixel row X1 and the second sub-pixel row X2 are not coincident, and each of the first sub-pixel row X1 and the second sub-pixel row X2 includes a plurality of pixel driving circuits; fig. 5 is a structural layout of a display panel according to an embodiment of the present disclosure, where the display panel may further include a substrate base, at least one conductive layer and a first switching layer ITO1, the conductive layer being located on one side of the substrate base, and the conductive layer may include a plurality of driving signal lines and a plurality of signal switching lines, a front projection of the driving signal lines on the substrate base extending along a pixel row direction X, the driving signal lines being operable to provide gate driving signals to at least some of the transistors in the pixel driving circuit; the signal patch cord is located in the transition region between the first display region 101 and the second display region 102, and the signal patch cord can be used for connecting the driving signal lines for transmitting the same gate driving signal in the first sub-pixel row X1 and the second sub-pixel row X2 in the same pixel row X0; the first transfer layer ITO1 is located one side of the conducting layer, which is away from the substrate, and the first transfer layer ITO1 comprises a plurality of bridging lines, the orthographic projections of the bridging lines on the substrate extend along the pixel row direction X and are located in the first display area 101, and the bridging lines are connected with gate signal lines for transmitting the same gate driving signals in two adjacent pixel driving circuits in the same sub-pixel row X0.

In the display panel provided by the present disclosure, in the first display area 101, because the same pixel row X0 includes the first sub-pixel row X1 and the second sub-pixel row X2, the driving signal lines transmitting the same gate driving signal in the same pixel row X0 are not on the same straight line, and by setting the bridge line at the portion of the first switching layer ITO1 located in the first display area 101, the bridge lines connect the driving signal lines transmitting the same gate driving signal in each pixel driving circuit in the same sub-pixel row X0, and then connect the driving signal lines transmitting the same gate driving signal in the two sub-pixel rows X0 in the same pixel row X0 through the conductive layer in the transition area of the first display area 101 and the second display area 102, so that the driving signal lines in the same pixel row X0 are not connected with each other any more, thereby simplifying the bridge line connection of the first switching layer ITO1, and because the space is optimized, the line width of each bridge line of the first switching layer ITO1 can be widened, thereby being beneficial to reducing the load.

The first display area 101 may be, for example, an FDC area (Full Display with camera, under-screen camera area), the second display area 102 may be a normal display area AA, and the position of the first display area 101 in the second display area 102 may be not limited, may be located at an upper portion or a lower portion of the second display area 102, or may be located at an edge position of the second display area 102. In the present exemplary embodiment, the shape of the first display area 101 may be any one or more of the following in a plane parallel to the display substrate: square, rectangular, polygonal, circular, oval, etc., and optical devices such as a fingerprint recognition device, an image pickup device, or an optical sensor for 3D imaging may be disposed in the first display area 101. The transition regions of the first display region 101 and the second display region 102 can be understood as the region where the sub-pixels adjacent to the second display region 102 in the first display region 10 are located, and obviously, the transmission direction of the gate driving signal is output along the GOA circuit, and the sub-pixels in the transition region are the sub-pixels in the last stage in the sub-pixel row.

The pixel row X0 can be understood as a display row defined by a row scan signal. Each pixel row X0 includes a first sub-pixel row X1 and a second sub-pixel row X2, and specifically, one pixel row X0 may include a plurality of pixel units arranged in the pixel row direction X, each pixel unit may include a plurality of sub-pixels, wherein a part of the sub-pixels of each pixel unit are located in the same row to form the first sub-pixel row X1, and another part of the sub-pixels are located in another row to form the second sub-pixel row X2. The first sub-pixel row X1 and the second sub-pixel row X2 do not coincide, which means that the first sub-pixel row X1 and the second sub-pixel row X2 are staggered in the pixel column direction Y. For example, as shown in fig. 4, one pixel unit includes a first sub-pixel R, a second sub-pixel G and a third sub-pixel B, the first sub-pixel R and the third sub-pixel B of each pixel unit are located in the same row, i.e. a first sub-pixel row X1, the second sub-pixel G of each pixel unit is located in the same row to form a second sub-pixel row X2, and the second sub-pixel G is staggered with the first sub-pixel R and the third sub-pixel B in the pixel column direction Y, so that the first display area 101 forms a pixel arrangement mode of RGBG.

It should be noted that, the pixel driving circuits of the present disclosure are disposed corresponding to the sub-pixels, that is, the arrangement manner of the pixel driving circuits of each pixel row X0 in the first display area 101 is the same as the arrangement manner of the sub-pixels, so that the driving signal lines for transmitting the same gate driving signal in the pixel driving circuits of different sub-pixel rows X0 in the same pixel row X0 are not on the same line, for example, the enabling signal line of the first sub-pixel row X1 and the enabling signal line of the second sub-pixel row X2 are not on the same line, and the reset signal line of the first sub-pixel row X1 and the reset signal line of the second sub-pixel row X2 are not on the same line. Further, the gate driving signal described in the present disclosure can be understood as a signal supplied to the gate of each transistor in the pixel driving circuit. For example, the Gate driving signal may include an enable signal EM supplied to the gates of the fifth and sixth transistors T5 and T6, a Reset signal reset_n supplied to the Gate of the first transistor T1, a second Gate signal gate_n supplied to the Gate of the second transistor T2, a first Gate signal gate_p supplied to the gates of the fourth and seventh transistors T4 and T7, and the like.

In the related art, the corresponding driving signal lines of the first sub-pixel row X1 and the second sub-pixel row X2 in the same pixel unit are connected, for example, in each pixel unit of the same pixel row X0, the enable signal line EM, the Reset signal line Reset, the gate signal line (gate ) in the R, B sub-pixel of the first sub-pixel row X1 and the enable signal line EM, the Reset signal line Reset, the gate signal line (gate ) of the G sub-pixel of the second sub-pixel row X2 are connected correspondingly through each bridge line of the first switching layer ITO1, so that the number of wirings of the first switching layer ITO1 in the first display area 101 is numerous, on one hand, the line width of each bridge line is narrow due to limited space, and the Loading of the bridge line is large. On the other hand, since the R, B subpixels of the first subpixel row X1 all need to be bridged with the G subpixels of the second subpixel row X2, numerous pixel column direction Y wirings are generated, resulting in numerous longitudinal slits, which may cause diffraction. Further, this wiring scheme is limited to a pixel space, and when the pixel size cannot be reduced to a small size, the drive signal lines in the pixel drive circuits of the respective sub-pixels cannot be connected.

In the present disclosure, in the first display area 101, the driving signal lines of two adjacent pixel driving circuits in the same sub-pixel row X0, which transmit the same gate driving signal, are connected through the bridge line, that is, the same driving signal line of two adjacent pixel driving circuits in the first sub-pixel row X1 is connected through the bridge line of the first switching layer ITO1, the same driving signal line of two adjacent pixel driving circuits in the second sub-pixel row X2 is connected through the corresponding bridge line of the first switching layer ITO1, and the pixel driving circuits in the first sub-pixel row X1 and the second sub-pixel row X2 are connected only in the transition area of the first display area 101 and the second display area 102 through the corresponding signal switching lines of the conductive layer, so that the same driving signal lines of two sub-pixel rows X0 in each pixel unit in the first display area 101 are no longer connected in sequence, thereby reducing the number of the first switching layer ITO1, which is equivalent to increasing the wiring space of each signal line in the first switching layer ITO1, and thus solving the problem of the related ITO technology.

The same kind of driving signal line described in the present disclosure is understood as a signal line transmitting the same kind of gate driving signal. For example, the signal line transmitting the enable signal in the first pixel driving circuit and the signal line transmitting the enable signal in the second pixel driving circuit are the same type of driving signal line.

In some embodiments of the present disclosure, in the same pixel row X0, the driving signal lines transmitting the same gate driving signal in any adjacent two pixel driving circuits located in the first display region 101 are all connected through corresponding bridge lines. That is, the same type of driving signal lines in the first pixel driving circuit and the third pixel driving circuit in the first sub-pixel row X1 are sequentially connected through the corresponding bridge lines of the first switching layer ITO1, while the same type of driving signal lines in the second pixel driving circuit in the second sub-pixel row X2 are sequentially connected through the bridge lines of the first switching layer ITO1, in other words, the driving signal lines in each pixel driving circuit have the corresponding bridge lines of the first switching layer ITO1 to connect with the same type of driving signal lines in the pixel driving circuits adjacent to the same sub-pixel row X0.

In other embodiments of the present disclosure, in the same pixel row X0, in any two adjacent pixel driving circuits located in the first display area 101, driving signal lines partially transmitting the same gate driving signal are connected through corresponding bridge lines, and driving signal lines partially transmitting the same gate driving signal are connected through signal connection lines located in the conductive layer. For example, the enable signal lines EM in the adjacent pixel driving circuits in the same sub-pixel row X0 may be connected through the bridge line of the first switching layer ITO1, and the gate signal lines (gate ) and the Reset signal lines Reset in the adjacent two pixel driving circuits in the same sub-pixel row X0 may be connected through the signal connection lines of the corresponding conductive layers, in other words, the gate signal lines (gate ) and the Reset signal lines Reset are no longer connected through the bridge line of the first switching layer ITO 1. In this way, compared to the scheme in which all the driving signal lines are connected using the bridge wires of the first switching layer ITO1, the number of wirings of the first switching layer ITO1 can be reduced, and thus the space required for the first switching layer ITO1 is correspondingly reduced, and therefore, the scheme of the present exemplary embodiment can be applied to the case where the available wiring space is small due to the large size of the sub-pixel, and the PPI of the display panel can be improved.

It should be understood that the terms "first," "second," and "third," etc. of the present disclosure are used merely as labels, and are used to distinguish between different structures, and are not intended to limit the number of objects or order of their relationship.

The structure of the display panel of the present disclosure is specifically described below in connection with a specific layout.

Fig. 9 is a structural layout of the first active layer in fig. 5, fig. 10 is a structural layout of the first conductive layer in fig. 5, fig. 14 is a structural layout of the second conductive layer in fig. 5, fig. 15 is a structural layout of the second active layer in fig. 5, fig. 16 is a structural layout of the third conductive layer in fig. 5, fig. 20 is a structural layout of the fourth conductive layer in fig. 5, fig. 23 is a structural layout of the first switching layer in fig. 5, fig. 25 is a structural layout of the second switching layer in fig. 5, fig. 26 is a structural layout of the fifth conductive layer in fig. 5, fig. 27 is a laminated layout of the fourth conductive layer and the first switching layer in fig. 5, and fig. 28 is a laminated layout of the first switching layer and the second switching layer in fig. 5.

Fig. 6 is a structural layout of a display panel in a transition region of a first display region and a second display region according to an embodiment of the present disclosure, fig. 11 is a structural layout of a first conductive layer in fig. 6, fig. 17 is a structural layout of a third conductive layer in fig. 6, and fig. 21 is a structural layout of a fourth conductive layer in fig. 6.

As shown in fig. 9, in an exemplary embodiment, the first active layer 10 may include third to seventh active portions AC3 to AC7, the third active portion AC3 is used to form a channel region of the driving transistor T3, the fourth to seventh active portions AC4 to AC7 are used to form a channel region of the fourth to seventh transistors T4 to AC7, respectively, wherein the fourth and fifth active portions AC4 and AC5 are located at the same side of the third active portion AC3 in the pixel column direction Y, the sixth and seventh active portions AC6 and AC7 are located at the other side of the third active portion AC3 in the pixel column direction Y, and the fifth and sixth active portions AC5 and AC6 are located at the same side of the third active portion AC3 in the pixel row direction X, that is, the fourth and seventh active portions AC4 and AC7 are located at the other side of the third active portion AC3 in the pixel row direction X, that is, the fourth and seventh active portions AC7 are distributed around the third active portion AC4 to AC 7.

The first active layer 10 may further include first to seventh sub-active portions AC11 to AC17, wherein the first sub-active portion AC11 is connected between the third, fourth and fifth active portions AC3, AC4 and AC5 to form a second pole of the driving transistor T3, a first pole of the fourth transistor T4 and a first pole of the fifth transistor T5.

The second sub-active portion AC12 is connected between the third active portion AC3 and the sixth active portion AC6, and the second sub-active portion AC12 is used to form the first pole of the driving transistor T3 and the first pole of the sixth transistor T6.

The third sub-active portion AC13 is connected to a side of the fourth active portion AC4 remote from the first sub-active portion AC11 for forming a second pole of the fourth transistor T4.

The fourth sub-active portion AC14 is connected to a side of the fifth active portion AC5 remote from the first sub-active portion AC11 for forming a second pole of the fifth transistor T5.

The fifth sub-active portion AC15 is connected to a side of the sixth active portion AC6 remote from the second sub-active portion AC12 for forming a second pole of the sixth transistor T6.

The sixth sub-active portion AC16 and the seventh sub-active portion AC17 are connected to both sides of the seventh active portion AC7, respectively, the sixth sub-active portion AC16 being for forming a first pole of the seventh transistor T7, and the seventh sub-active portion AC17 being for forming a second pole of the seventh transistor T7.

The first active layer 1011 of the present disclosure may be formed of a polysilicon semiconductor material, and accordingly, the transistor in the display panel of the present disclosure may be a P-type low temperature polysilicon thin film transistor.

As shown in fig. 10, in an exemplary embodiment, the first conductive layer 1 may include a first Gate signal line Gate for providing the first Gate signal terminal gate_p in fig. 1 and an enable signal line EM, the front projection of the first Gate signal line Gate on the substrate extending along the pixel row direction X and respectively covering the front projection of the fourth active portion AC4 on the substrate and the front projection of the seventh active portion AC7 on the substrate, a part of the first Gate signal line Gate being used to form the Gate of the fourth transistor T4 and a part of the first Gate signal line Gate being used to form the Gate of the seventh transistor T7.

It should be understood that a certain structure a according to the present disclosure extends in the direction B, and that a may include a main portion and a sub portion connected to the main portion, the main portion being a line, a line segment, or a bar-shaped body, the main portion extending in the direction B, and the length of the main portion extending in the direction B being greater than the length of the sub portion extending in other directions.

The enable signal line EM is used to provide the enable signal terminal EM in fig. 1, the orthographic projection of the enable signal line EM on the substrate extends along the pixel row direction X, the orthographic projection of the enable signal line EM on the substrate covers the orthographic projection of the fifth active portion AC5 on the substrate and the orthographic projection of the sixth active portion AC6 on the substrate, and a part of the structure of the enable signal line EM is used to form the gate of the fifth transistor T5 and a part of the structure is used to form the gate of the sixth transistor T6.

It should be understood that the orthographic projection of a certain structure a onto a substrate and another structure B onto a substrate as described in this disclosure can be understood as having the projected outline of B onto the plane of the substrate entirely within the outline of a projected in the same plane.

The first conductive layer 1 may further include a first conductive bump 11, and the orthographic projection of the first conductive bump 11 on the substrate covers the orthographic projection of the third active portion AC3 on the substrate, and the first conductive bump 11 may be used to form the gate of the driving transistor T3 and the first electrode of the storage capacitor Cst.

Further, as shown in fig. 11, in the transition region of the first display region 101 and the second display region 102, the first conductive layer 1 further includes a first enable signal patch line EM 'whose orthographic projection on the substrate extends in the pixel column direction Y, whereby in the same pixel row X0, the enable signal line EM located in the first sub-pixel row X1 is connected to the enable signal line EM in the second sub-pixel row X2 through the first enable signal patch line EM', so that the signals transmitted by the enable signal lines EM located in the same pixel row X0 in the first display region 101 are identical. In the transition region of the first display region 101 and the second display region 102, one end of the first enable signal patch line EM' may be connected to the enable signal line EM in the first pixel driving circuit, and the other end may be connected to the enable signal line EM of the second pixel driving circuit in the same pixel unit, thereby connecting the enable signal lines EM of two sub-pixel rows in the same pixel row.

The display panel disclosed by the disclosure can take the first conductive layer 1 as a mask to conduct conductive treatment on the active layer, namely, the active layer covered by the first conductive layer 1 forms a channel region of a transistor, and the region not covered by the first conductive layer 1 forms a conductor structure.

As shown in fig. 14, in an exemplary embodiment, the second conductive layer 2 may include a second Gate signal line Gate, which may be used to provide the second Gate driving signal terminal gate_n in fig. 1, and a first reset signal line ResetN, the orthographic projection of the second Gate signal line Gate on the substrate may extend in the pixel row direction X and cover the orthographic projection of the second active portion IG2 on the substrate, and a partial structure of the second Gate signal line Gate is used to form the bottom Gate of the second transistor T2. The first Reset signal line ResetN may be used to provide the Reset signal terminal reset_n in fig. 1, and the front projection of the first Reset signal line ResetN on the substrate may cover the front projection of the first active portion IG1 on the substrate, and a portion of the structure of the first Reset signal line ResetN is used to form the bottom gate of the first transistor T1.

The second conductive layer 2 may further include a second conductive bump 22, where a front projection of the second conductive bump 22 on the substrate is located on a front projection of the third active portion AC3 on the substrate, and the second conductive bump 22 may be used to form a second electrode of the storage capacitor Cst.

As shown in fig. 15, in an exemplary embodiment, the second active layer 20 may include a first active portion IG1 for forming a channel region of the first transistor T1 and a second active portion IG2 for forming a channel region of the second transistor T2.

The second active layer 20 may further include eighth to tenth sub-active portions IG8 to IG10, and the eighth sub-active portion IG8 is connected between the first and second active portions IG1 and IG2 to form a first pole of the first transistor T1 and a first pole of the second transistor T2. The ninth sub-active portion IG9 is connected to a side of the first active portion IG1 remote from the eighth sub-active portion IG8, for forming a second pole of the first transistor T1. The tenth sub-active part IG10 is connected to a side of the second active part IG2 remote from the eighth sub-active part IG8, for forming a second pole of the second transistor T2.

The second active layer 20 of the present disclosure may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors.

As shown in fig. 16, in an exemplary embodiment, the third conductive layer 3 may include a fourth gate signal line GateN 'and a second reset signal line ResetN', wherein a front projection of the fourth gate signal line GateN 'on the substrate covers a front projection of the second active portion IG2 on the substrate and is located on a front projection of the second gate signal line GateN on the substrate, and a partial structure of the fourth gate signal line GateN' is used to form a top gate of the second transistor T2. Meanwhile, the second gate signal line GateN and the fourth gate signal line GateN' may be connected through the first bridge portion 41 of the fourth conductive layer 4.

The orthographic projection of the second reset signal line ResetN 'on the substrate may cover the orthographic projection of the first active portion IG1 on the substrate, and a partial structure of the second reset signal line ResetN' may form a top gate of the first transistor T1. The second reset signal line ResetN' and the first reset signal line ResetN may be connected through the second bridge portion 42 of the fourth conductive layer 4.

In addition, as shown in fig. 17, in the transition region of the first display region 101 and the second display region 102, the third conductive layer 3 may further include a fourth gate signal patch cord G4, and the orthographic projection of the fourth gate signal patch cord G4 on the substrate may extend along the pixel column direction Y, so that in the same pixel row X0, the fourth gate signal patch cord G4 is connected to the fourth gate signal lines GateN 'of two sub-pixel rows X0 adjacent to each other in the pixel column direction Y, so that the signals transmitted by the fourth gate signal lines GateN' in the same pixel unit are the same. In the transition region of the first display region 101 and the second display region 102, one end of the fourth gate signal patch cord G4 may be connected to the fourth gate signal line gate ' in the third pixel driving circuit, and the other end may be connected to the fourth gate signal line gate ' in the second pixel driving circuit in the same pixel unit, thereby connecting the fourth gate signal lines gate ' of two sub-pixel rows in the same pixel row.

As shown in fig. 20, the fourth conductive layer 4 may include first to twelfth bridge parts 41 to 412, wherein the first bridge part 41 is connected to the fourth gate signal line gate' of the third conductive layer 3 and the second gate signal line gate of the second conductive layer 2, i.e., the top and bottom gates of the second transistor T2, respectively, through a via hole, and the first bridge part 41 is also connected to one end of the third sub-bridge k3 of the first transfer layer ITO1 through a via hole.

The orthographic projection of the sixth bridge portion 46 on the substrate extends along the pixel row direction X, and the sixth bridge portion 46 may be connected to the fourth gate signal line GateN 'of the third conductive layer 3 and the other end of the third sub-switching line k3 of the first switching layer ITO1 through the via hole, respectively, so as to connect the fourth gate signal lines GateN' in two adjacent sub-pixels in the same row through the third sub-switching line k 3.

The second bridge portion 42 connects the first reset signal line ResetN of the second conductive layer 2 and the second reset signal line ResetN' of the third conductive layer 3, i.e., the bottom gate and the top gate of the first transistor T1, respectively, through the via hole.

The orthographic projection of the third bridge portion 43 on the substrate extends along the pixel column direction Y, and the third bridge portion 43 may connect the eighth sub-active portion IG8 and the first conductive block 11 of the first conductive layer 1 through the via hole, respectively, to connect the first electrode of the first transistor T1 and the first electrode of the second transistor T2 to the gate electrode of the driving transistor T3.

The fourth bridge portion 44 connects the sixth sub-active portion AC16 and the fifth sub-active portion AC15 through vias, respectively, to connect the second pole of the sixth transistor T6 and the first pole of the seventh transistor T7.

The orthographic projection of the fifth bridge portion 45 on the substrate extends along the pixel column direction Y, and one end of the fifth bridge portion 45 is connected to the fourth sub-active portion AC14 through a via hole to connect to the second pole of the fifth transistor T5. The other end of the fifth bridge portion 45 is connected to the first switching portion 51 of the first switching layer ITO1 through a via hole to connect the first power line Vdd of the second switching layer ITO2 through the first switching portion 51, thereby connecting the second pole of the fifth transistor T5 to the first power line Vdd.

The seventh bridge portion 47 may connect the second via portion 52 in the first via layer ITO1 and the third sub-active portion AC13 in the first active layer 10, respectively, through a via hole to connect the second pole of the fourth transistor T4 to the data signal line Vdata in the second via layer ITO 2.

The eighth bridge portion 48 is connected to one end of the first gate signal line gate in the second conductive layer 2 and one end of the first sub-bridge line k1 in the first transfer layer ITO1 through a via hole, respectively, and the ninth bridge portion 49 is connected to the other end of the first gate signal line gate in the second conductive layer 2 and the other end of the first sub-bridge line k1 in the first transfer layer ITO1 through a via hole, respectively, so that the eighth bridge portion 48 in one pixel driving circuit is connected to one end of the first sub-bridge line k1 through a via hole in two adjacent pixel driving circuits in the same sub-pixel row X0, and the ninth bridge portion 49 in the other pixel driving circuit is connected to the other end of the first sub-bridge line k1 through a via hole, thereby connecting the first gate signal line gate in two adjacent pixel driving circuits in the same sub-pixel row X0 through the first sub-bridge line k 1.

The tenth bridge portion 410 connects one end of the enable signal line EM in the first conductive layer 1 and one end of the second sub-bridge line k2 in the first transfer layer ITO1 through the via hole, respectively, and the eleventh bridge portion 411 connects the other end of the enable signal line EM and the other end of the first sub-bridge line k1 through the via hole, respectively, so that the enable signal lines EM in two sub-pixels adjacent in the pixel row direction X are connected via the tenth bridge portion 410, the first sub-bridge line k1, and the eleventh bridge portion 411.

The twelfth bridge part 412 connects the tenth sub-active part IG10 in the second active layer 20 and the second sub-active part AC12 in the first active layer 10 through the via hole, respectively, to connect the first pole of the driving transistor T3 and the second pole of the second transistor T2.

As shown in fig. 20, the fourth conductive layer 4 may further include an initialization signal line Vinit, where the initialization signal line Vinit may be used to provide the initialization signal terminal Vinit in fig. 1, where a front projection of the initialization signal line Vinit on the substrate extends along the pixel row direction X, and one end of the initialization signal line Vinit is connected to the ninth sub-active portion IG9 of the second active layer 20 through a via hole to connect to the second pole of the first transistor T1. The other end of the initialization signal line Vinit may be connected to the seventh sub-active portion AC17 of the first active layer 10 through a via hole to connect the second pole of the seventh transistor T7, thereby connecting the second pole of the first transistor T1 and the second pole of the seventh transistor T7 to the initialization signal line Vinit.

Further, as shown in fig. 21, in the transition region of the first display region 101 and the second display region 102, the fourth conductive layer 4 may further include a third reset signal patch line 415 and a third gate signal patch line 416, wherein the third reset signal patch line 415 connects two second bridge portions 42 adjacent in the pixel row direction X, specifically, in the same pixel row X0, the second bridge portion 42 in the first subpixel row X1 is connected to the second bridge portion 42 in the second subpixel row X2 through the third reset signal patch line 415 (for example, the third reset signal patch line 415 is connected to the second bridge portion 42 in the first pixel driving circuit and the second bridge portion 42 in the second pixel driving circuit, respectively), and because the second bridge portion 42 is connected to the first reset signal line ResetN and the second reset signal line ResetN', the reset signal in the first subpixel row X1 and the reset signal line in the second subpixel row X2 are connected through the third reset signal patch line 415, so that the reset signal in the same pixel row X0 is transmitted.

The third gate signal patch line 416 connects the eighth bridge portion 48 of the first sub-pixel row X1 (for example, the eighth bridge portion 48 of the third pixel driving circuit may be connected) and the ninth bridge portion 49 of the second sub-pixel row X2 (for example, the ninth bridge portion 49 of the second pixel driving circuit of the same pixel unit), and since the eighth bridge portion 48 and the ninth bridge portion 49 are connected to the first gate signal line GateP of the same sub-pixel row X0, it is equivalent to connecting the first gate signal line GateP of the first sub-pixel row X1 and the first gate signal line GateP of the second sub-pixel row X2 of the same pixel row X0 through the third gate signal patch line 416, so that the signals transmitted by the first gate signal line GateP of the same pixel row X0 are the same.

Further, in the exemplary embodiment, the orthographic projection of the third gate signal patch cord 416 on the substrate overlaps with the orthographic projection of the fourth gate signal patch cord G4 on the substrate, and in particular, the orthographic projection of a part of the structure of the third gate signal patch cord 416 on the substrate may be located on the orthographic projection of the fourth gate signal patch cord G4 on the substrate, that is, the third gate signal patch cord 416 passes through from above the fourth gate signal patch cord G4, whereby the influence on the light transmittance may be reduced by the overlapping of the signal cords.

As shown in fig. 23, in an exemplary embodiment, the first switching layer ITO1 may include first to third switching parts 51 to 53, wherein, in conjunction with fig. 27 and 28, the first switching part 51 is connected to the first power line of the second switching layer ITO2 and the fifth bridging part 45 of the fourth conductive layer 4 through vias, respectively, so that the first power line of the second switching layer ITO2 is connected to the second pole of the fifth transistor T5 through the first switching part 51 and the fifth bridging part 45.

Referring to fig. 27 and 28, the second transfer portion 52 connects the seventh bridge portion 47 in the fourth conductive layer 4 and the data signal line Vdata in the second transfer layer ITO2 through the via hole, respectively, to connect the second pole of the fourth transistor T4 to the data signal line.

Referring to fig. 27, the orthographic projection of the third switching portion 53 on the substrate is located on the orthographic projection of the fourth bridging portion 44 on the substrate, and the third switching portion 53 may be connected to the fourth bridging portion 44 through a via hole to connect the second pole of the sixth transistor T6 and the first pole of the seventh transistor T7.

As shown in fig. 23, the first transfer layer ITO1 may further include first to fifth sub-bridge lines k1 to k5 and tenth to fifty sub-bridge lines k10 to k50, wherein:

referring to fig. 27, the orthographic projections of the first sub-bridge line k1 and the tenth sub-bridge line k10 on the substrate extend along the pixel row direction X, the first sub-bridge line k1 is located in the first sub-pixel row X1, one end of the first sub-bridge line k1 is connected to the eighth bridge portion 48 in the fourth conductive layer 4 through a via hole, and the other end is connected to the ninth bridge portion 49 in the adjacent other pixel driving circuit in the same sub-pixel row X0 through a via hole, so as to connect the first gate signal lines GateP in the adjacent two sub-pixels in the first sub-pixel row X1. The tenth sub-bridge line k10 is located in the second sub-pixel row X2, and accordingly, in the second sub-pixel row X2, one end of the tenth sub-bridge line k10 is connected to the eighth bridge portion 48 at the corresponding position through a via hole, and the other end is connected to the ninth bridge portion 49 in the other pixel driving circuit adjacent to the corresponding position through a via hole, thereby connecting the first gate signal lines GateP in the two adjacent sub-pixels in the second sub-pixel row X2.

Referring to fig. 27, the orthographic projections of the second sub-bridge line k2 and the twenty-second sub-bridge line k20 on the substrate are extended in the pixel row direction X, the second sub-bridge line k2 is located in the first sub-pixel row X1, and the second sub-bridge line k2 may be connected to the tenth bridge portion 410 of the first pixel driving circuit and the eleventh bridge portion 411 of the adjacent third pixel driving circuit through the via hole, respectively (the tenth bridge portion 410 and the eleventh bridge portion 411 are connected to the enable signal line EM, respectively), so that the enable signal lines EM of the adjacent two pixel driving circuits in the first sub-pixel row X1 are connected through the second sub-bridge line k 2. Accordingly, the twentieth sub-bridge line k20 is located in the second sub-pixel row X2, one end of the twentieth sub-bridge line k20 is connected to the tenth bridge portion 410 at the corresponding position through a via hole, and the other end is connected to the eleventh bridge portion 411 at the corresponding position through a via hole, thereby connecting the enable signal lines EM in two adjacent pixel driving circuits in the second sub-pixel row X2.

Referring to fig. 27, the orthographic projections of the third sub-bridge line k3 and the thirty-first sub-bridge line k30 on the substrate are extended in the pixel row direction X, the third sub-bridge line k3 is located in the first sub-pixel row X1, one end of the third sub-bridge line k3 is connected to the sixth bridge 46 in the first pixel driving circuit through the via hole to be connected to the fourth gate signal line GateN ' in the first pixel driving circuit through the sixth bridge 46, and the other end of the third sub-bridge line k3 is connected to the first bridge 41 in the adjacent third pixel driving circuit in the first sub-pixel row X1 through the via hole to be connected to the fourth gate signal line GateN ' in the third pixel driving circuit, so that the third sub-bridge line k3 connects the fourth gate signal lines GateN ' in the two adjacent pixel driving circuits in the first sub-pixel row X1. Accordingly, the thirty-first sub-bridge line k30 is located in the second sub-pixel row X2, one end of the thirty-first sub-bridge line k30 is connected to the sixth bridge portion 46 in one of the second pixel driving circuits through a via hole, and the other end is connected to the first bridge portion 41 in the adjacent other of the second pixel driving circuits through a via hole, so as to connect the fourth gate signal lines GateN' in the adjacent two of the second sub-pixel row X2.

Referring to fig. 27, the orthographic projections of the fourth sub-bridge line k4 and the forty sub-bridge line k40 on the substrate extend along the pixel row direction X, the fourth sub-bridge line k4 is located in the first sub-pixel row X1, one end of the fourth sub-bridge line k4 is connected to one end of the initialization signal line Vinit in the first pixel driving circuit through a via hole, and the other end is connected to one end of the initialization signal line Vinit in the adjacent third pixel driving circuit through a via hole, so as to connect the initialization signal lines Vinit in the adjacent two pixel driving circuits in the first sub-pixel row X1. The forty-second sub-bridge line k40 is located in the second sub-pixel row X2, and accordingly, one end of the forty-second sub-bridge line k40 is connected to one end of the initialization signal line Vinit in one second pixel driving circuit through a via hole, and the other end is connected to one end of the initialization signal line Vinit in an adjacent second pixel driving circuit through a via hole, so that the initialization signal lines Vinit in two adjacent pixel driving circuits of the second sub-pixel row X2 are connected.

Referring to fig. 27, orthographic projections of the fifth sub-bridge line k5 and the fifty-second sub-bridge line k50 on the substrate extend along the pixel row direction X, the fifth sub-bridge line k5 is located in the first sub-pixel row X1, one end of the fifth sub-bridge line k5 is connected to the second bridge portion 42 in the first pixel driving circuit through a via hole (the second bridge portion 42 is connected to the first reset signal line ResetN of the second conductive layer 2 and the second reset signal line ResetN' of the third conductive layer 3), and the other end is connected to the second bridge portion 42 in the adjacent third pixel driving circuit through a via hole, so that reset signal lines in two adjacent pixel driving circuits in the first sub-pixel row X1 are connected. The fifty-th sub-bridge line k50 is located in the second sub-pixel row X2, and accordingly, one end of the fifty-th sub-bridge line k50 is connected to the second bridge portion 42 in one second pixel driving circuit through a via hole, and the other end is connected to the second bridge portion 42 in the adjacent other second sub-pixel driving circuit through a via hole, so that reset signal lines in two adjacent pixel driving circuits in the second sub-pixel row X2 are connected.

As shown in fig. 25, in an exemplary embodiment, the second switching layer ITO2 may include a Data signal line Vdata and a first power line Vdd, wherein the Data signal line Vdata may be used to provide the Data signal terminal Data in fig. 1, the orthographic projection of the Data signal line Vdata on the substrate extends along the pixel column direction Y, and in conjunction with fig. 28, the Data signal line Vdata may be connected to the second switching portion 52 in the first switching layer ITO1 through a via hole (the second switching portion 52 is connected to the seventh bridging portion 47 of the fourth conductive layer 4, and the seventh bridging portion 47 is connected to the third sub-active portion AC 13), so that the Data signal line Vdata is connected to the third sub-active portion AC13 in the first active layer 10 via the second switching portion 52 in the first switching layer ITO1 and the seventh bridging portion 47 in the fourth conductive layer 4, i.e., the second electrode of the fourth transistor T4 is connected to the Data signal line Vdata.

The first power lines Vdd may be used to provide the first power terminals Vdd in fig. 1, and the orthographic projection of the first power lines Vdd on the substrate extends along the pixel column direction Y and is distributed at intervals in the pixel column direction Y, i.e., the first power lines Vdd are discontinuously distributed in the pixel column direction Y. Referring to fig. 28, one end of the first power line Vdd may be connected to the first switching portion 51 in the first switching layer ITO1 through a via hole (the first switching portion 51 is connected to the fifth bridging portion 45 of the fourth conductive layer 4, the fifth bridging portion 45 is connected to the fourth sub-active portion AC14, i.e., the second pole of the fifth transistor T5), and the other end of the first power line Vdd may be connected to the thirteenth bridging portion 713 in the fifth conductive layer 5 through a via hole, thereby connecting the respective first power lines Vdd through the thirteenth bridging portion 713 of the fifth conductive layer 5. In the present exemplary embodiment, the first power line Vdd is switched through the fifth conductive layer 5, because the resistance of the fifth conductive layer 5 is low, the impedance of the first power line Vdd can be reduced, thereby reducing the Loading of the first power line Vdd, which is beneficial to reducing the power consumption of the display panel.

In addition, referring to fig. 28, the second transfer layer ITO2 may further include a fourth transfer portion 64, an orthographic projection of the fourth transfer portion 64 on the substrate is located on an orthographic projection of the third transfer portion 53 on the substrate, and the fourth transfer portion 64 may connect the third transfer portion 53 in the first transfer layer ITO1 and the anode transfer portion 714 of the fifth conductive layer 5 through a via hole, thereby connecting the second pole of the sixth transistor T6 and the first pole of the seventh transistor T7 to the anode of the light emitting device.

As shown in fig. 26, in an exemplary embodiment, the fifth conductive layer 5 may include a thirteenth bridge portion 713 and an anode transfer portion 714, wherein an orthographic projection of the thirteenth bridge portion 713 on the substrate extends in the pixel column direction Y, and the thirteenth bridge portion 713 may be connected to the first power line Vdd of the second transfer layer ITO2 through a via hole to connect the broken first power line Vdd. In the case of the same line width, the wire impedance of the fifth conductive layer 5 is smaller than the wire impedance of the second switching layer ITO2, so that the impedance of the first power line Vdd can be reduced by switching at the thirteenth bridge portion 713 of the fifth conductive layer 5, thereby reducing the RC load of the first power line Vdd and further reducing the power consumption of the display panel.

Orthographic projection of anode tab 714 on the substrate is located on orthographic projection of fourth tab 64 on the substrate, anode tab 714 being connected to the anode of the anode layer by a via on the one hand, and anode tab 714 being connected to fourth tab 64 in second tab layer ITO2 by a via on the other hand, whereby the second pole of sixth transistor T6 and the first pole of seventh transistor T7 are connected to the anode of the light emitting device by fourth tab 64 in second tab layer ITO2, third tab 53 in first tab layer ITO1 and fourth bridge 44 of fourth conductive layer 4.

As described above, in other embodiments of the present disclosure, in any adjacent two pixel driving circuits located in the first display area 101 in the same pixel row X0, the driving signal lines partially transmitting the same gate driving signal are connected through the corresponding bridge lines, and the driving signal lines partially transmitting the same gate driving signal are connected through the signal connection lines located in the conductive layer. The scheme is further described below with reference to the accompanying drawings.

Fig. 7 is a structural layout of a display panel according to another embodiment of the present disclosure, fig. 12 is a structural layout of a first conductive layer in fig. 7, fig. 18 is a structural layout of a third conductive layer in fig. 7, and fig. 24 is a structural layout of a first switching layer in fig. 7.

Fig. 8 is a structural layout of a display panel in a transition region of a first display region and a second display region according to another embodiment of the present disclosure, fig. 13 is a structural layout of a first conductive layer in fig. 8, fig. 19 is a structural layout of a third conductive layer in fig. 8, fig. 22 is a structural layout of a fourth conductive layer in fig. 8, fig. 29 is a laminated layout structure of the first conductive layer and the third conductive layer in fig. 8, and fig. 30 is a laminated layout structure of the first conductive layer, the third conductive layer, and the fourth conductive layer in fig. 8.

It should be understood that the layout structure shown in fig. 7 may have all the structures of the first active layer 10, the first conductive layer 1, the second conductive layer 2, the second active layer 20, the third conductive layer 3, the fourth conductive layer 4, the second transfer layer ITO2, and the fifth conductive layer 5 in the layout structure shown in fig. 5, and the present exemplary embodiment will be described only with respect to the differences from the layout structure shown in fig. 5, and the same structures as fig. 5 will not be described in detail herein.

As shown in fig. 7 and 12, in an exemplary embodiment, the first conductive layer may include, in addition to the first gate signal line gate and the enable signal line EM shown in fig. 10, a first gate signal patch line G1 and a second gate signal patch line G2, where the first gate signal patch line G1 is located in the first subpixel row X1, one end of the first gate signal patch line G1 is connected to one end of the first gate signal line gate in the first pixel driving circuit, and the other end is connected to one end of the first gate signal line gate in the third pixel driving circuit adjacent in the pixel row direction X, so that the first conductive layer 1 connects the first gate signal lines gate in each adjacent first pixel driving circuit and third pixel driving circuit in the first subpixel row X1, and accordingly, there is no need to additionally provide a wire bridge for bridging each first gate signal line gate of the first subpixel row X1 in the first patch layer ITO 1.

The second gate signal patch cord G2 is located in the second sub-pixel row X2, and the second gate signal patch cord G2 is respectively connected to the first gate signal lines gate in two adjacent second pixel driving circuits in the pixel row direction X, so that each first gate signal line gate in the second sub-pixel row X2 is connected to the first conductive layer 1, and therefore, bridging of the first gate signal lines gate is performed without separately providing a bridge wire on the first patch layer ITO 1.

Obviously, compared with the embodiment shown in fig. 5, the present exemplary embodiment does not need to additionally provide the first sub-bridge line k1 on the first transfer layer ITO1 to connect each first gate signal line gate of the first sub-pixel row X1 and does not need to additionally provide the tenth sub-bridge line k10 to connect each first gate signal line gate of the second sub-pixel row X2, thereby reducing the number of wirings in the first transfer layer ITO1, so that the space of the first transfer layer ITO1 signal line is effectively increased by using the space of the first conductive layer 1, and the reasonable utilization of the layout space is realized as a whole, which is beneficial to improving the resolution of the display panel.

Further, as shown in fig. 13, in the exemplary embodiment, in the transition region of the first display region 101 and the second display region 102, the first conductive layer 1 may further include a first gate signal bridge line gate 'whose orthographic projection on the substrate extends in the pixel column direction Y, whereby, in the same pixel row X0, the first gate signal line gate located in the first sub-pixel row X1 is connected with the first gate signal line gate in the second sub-pixel row X2 through the first gate signal bridge line gate' so that the signals transmitted by the first gate signal line gate located in the same pixel row X0 in the first display region 101 are the same. In the transition region of the first display region 101 and the second display region 102, one end of the first gate signal bridge line gate' may be connected to the first gate signal line gate in the first pixel driving circuit, and the other end may be connected to the first gate signal line gate in the second pixel driving circuit, thereby connecting the first gate signal lines gate of two sub-pixel rows in the same pixel row.

As shown in fig. 7 and 18, in an exemplary embodiment, the third conductive layer 3 may include the fourth gate signal line gate 'and the second reset signal line ResetN' shown in fig. 16, and the layout structure of the fourth gate signal line gate 'and the second reset signal line ResetN' may correspond to the layout structure shown in fig. 16, and will not be described in detail herein.

As shown in fig. 18, the third conductive layer 3 may further include a first reset signal patch cord R1 and a second reset signal patch cord R2, wherein the first reset signal patch cord R1 is located in the first subpixel row X1, and the first reset signal patch cord R1 is connected to the second reset signal cord ResetN 'in the first pixel driving circuit and the second reset signal cord ResetN' in the third pixel driving circuit, respectively, so as to connect adjacent reset signal cords in the first subpixels.

The second reset signal patch cord R2 is located in the second sub-pixel row X2, and the second reset signal patch cord R2 is respectively connected to the second reset signal lines ResetN' in the two adjacent second pixel driving circuits, so as to connect the reset signal lines in the pixel driving circuits in the second sub-pixel row X2.

Similarly, compared with the layout structure shown in fig. 16, the present exemplary embodiment provides a more abundant layout space for each bridge wire of the first conductive layer ITO1 by providing the corresponding reset signal patch cord in the third conductive layer 3, thereby eliminating the need to additionally provide the fifth sub-bridge wire k5 and the fifty-second sub-bridge wire k50 in the first conductive layer ITO1, and further reducing the number of wires of the first conductive layer ITO 1.

Further, as shown in fig. 19, in the exemplary embodiment, in the transition region of the first display region 101 and the second display region 102, the third conductive layer 3 may further include a fourth reset signal patch line R4, and the fourth reset signal patch line R4 may be located between two adjacent fourth gate signal lines GateN 'in the first subpixel row X1, that is, the fourth reset signal patch line R4 may pass between the two adjacent fourth gate signal lines GateN' in the pixel column direction. The orthographic projection of the fourth reset signal patch cord R4 on the substrate extends along the pixel column direction Y, and thus, in the same pixel row X0, the first reset signal line ResetN located in the first sub-pixel row X1 is connected to the first reset signal line ResetN in the second sub-pixel row X2 through the fourth reset signal patch cord R4, so that signals transmitted by the first reset signal line ResetN located in the same pixel row X0 in the first display area 101 are the same. In the transition region of the first display region 101 and the second display region 102, one end of the fourth reset signal patch cord R4 is connected to the first reset signal patch cord R1 in the first sub-pixel row X1, and the other end is connected to the second reset signal patch cord R2 in the second sub-pixel row X2, so that the first reset signal lines ResetN of the two sub-pixel rows in the same pixel row are connected.

With continued reference to fig. 19, in an exemplary embodiment, in the transition region of the first display region 101 and the second display region 102, the third conductive layer 3 may further include a fifth gate signal patch line G5, and the fifth gate signal patch line G5 may include a first extension portion G51 and a second extension portion G52, where a front projection of the first extension portion G51 on the substrate extends along the pixel column direction, a front projection of the second extension portion G52 on the substrate extends along the pixel row direction, the first extension portion G51 is connected to the fourth gate signal line GateN ' in the first sub-pixel row X1, and the second extension portion G52 is connected to the fourth gate signal line GateN ' in the second sub-pixel row X2, so that the fifth gate signal patch line G5 may avoid the via hole of the interlayer dielectric layer ILD and connect the fourth gate signal lines GateN ' of the two sub-pixel rows in the same pixel row. As can be seen from comparing fig. 17, in the present exemplary embodiment, since the connection paths of the fourth gate signal line GateN 'in the third sub-pixel driving circuit and the fourth gate signal line GateN' in the second pixel driving circuit are blocked by connecting the adjacent first reset signal lines ResetN of the same sub-pixel row through the first reset signal patch R1 and the second reset signal patch R2 of the third conductive layer 3 in the first display area 101, the present exemplary embodiment is different from the scheme shown in fig. 17 in that the fourth gate signal line GateN 'in the first pixel driving circuit and the fourth gate signal line GateN' in the second pixel driving circuit are connected, specifically, one end of the two fourth gate signal lines GateN 'away from the third sub-pixel of the same pixel unit is connected, so that the signals transmitted by the fourth gate signal line GateN' of the same pixel row are the same.

Further, as shown in fig. 13, 19 and 29, in the present exemplary embodiment, the orthographic projection of the fifth gate signal patch cord G5 on the substrate may overlap with the orthographic projection of the first gate signal patch cord ' on the substrate, specifically, the first gate signal patch cord ' may include a third extension portion gap '3 and a fourth extension portion gap '4, the orthographic projection of the third extension portion gap '3 on the substrate extends along the pixel column direction, the orthographic projection of the fourth extension portion gap '4 on the substrate extends along the pixel row direction, the orthographic projection of the first extension portion G51 on the substrate is located on the orthographic projection of the third extension portion gap '3 on the substrate, the orthographic projection of the second extension portion G52 on the substrate is located on the orthographic projection of the fourth extension portion gap '4 on the substrate, whereby the orthographic projection of the fifth gate signal patch cord G5 and the first gate signal patch cord ' form an overlapping portion to further reduce the influence on the transmittance of the first light transmittance 101 in the display region.

As shown in fig. 8 and 22, in an exemplary embodiment, in the transition region of the first display region 101 and the second display region 102, the fourth conductive layer 4 may further include a second enable signal patch line 420, where a front projection of the second enable signal patch line 420 on the substrate extends along the pixel column direction, and in the same pixel row, the second enable signal patch line 420 is connected to the enable signal line EM in the first sub-pixel row X1 and the enable signal line EM in the second sub-pixel row X2, so as to connect the enable signal lines EM of the two sub-pixel rows, so that signals transmitted by the enable signal lines EM in the same pixel row are the same. Illustratively, one end of the second enable signal patch cord 420 is connected to the enable signal line EM of the first pixel driving circuit, and the other end is connected to the enable signal line EM in the second pixel driving circuit.

In this exemplary embodiment, the second enable signal patch cord 420 may include a first component 421 and a second component 422, as shown in fig. 30, where the orthographic projection of the first component 421 on the substrate may be located on the orthographic projection of the first gate signal bridge line gap ' on the substrate, and the orthographic projection of the second component 422 on the substrate is located on the orthographic projection of the first reset signal patch cord R1 in the next pixel row on the substrate, that is, the partial structure of the second enable signal patch cord 420 passes over the first gate signal bridge line gap ', and the partial structure passes over the first reset signal patch cord R1 in the next pixel row, thereby reducing the influence on the light transmittance of the first display area by forming overlapping with the first gate signal bridge line gap ' and the first reset signal cord R1 of the next pixel row, respectively.

As shown in fig. 7 and 24, in an exemplary embodiment, the first transfer layer ITO may include first to third transfer portions 51 to 53 shown in fig. 23, and the first transfer portion 51 is connected to the first power line of the second transfer layer ITO2 and the fifth bridge portion 45 of the fourth conductive layer 4 through the via hole, respectively, so that the first power line of the second transfer layer ITO2 is connected to the second pole of the fifth transistor T5 through the first transfer portion 51 and the fifth bridge portion 45.

The second transfer portion 52 connects the seventh bridge portion 47 in the fourth conductive layer 4 and the data signal line Vdata in the second transfer layer ITO2 through the via hole, respectively, to connect the second pole of the fourth transistor T4 to the data signal line.

The orthographic projection of the third switching portion 53 on the substrate is located on the orthographic projection of the fourth bridging portion 44 on the substrate, and the third switching portion 53 may be connected to the fourth bridging portion 44 through a via hole to connect the second pole of the sixth transistor T6 and the first pole of the seventh transistor T7.

Further, as shown in fig. 24, in an exemplary embodiment, the first transfer layer ITO may further include a second sub-bridge line k2, a twentieth sub-bridge line k20, a third sub-bridge line k3, a thirty-th sub-bridge line k30, a fourth sub-bridge line k4, and a forty sub-bridge line k40, wherein:

the orthographic projections of the second sub-bridge line k2 and the twenty-second sub-bridge line k20 on the substrate extend along the pixel row direction X, the second sub-bridge line k2 is located in the first sub-pixel row X1, and the second sub-bridge line k2 may be connected to the tenth bridge portion 410 of the first pixel driving circuit and the eleventh bridge portion 411 of the adjacent third pixel driving circuit (the tenth bridge portion 410 and the eleventh bridge portion 411 are connected to the enable signal line EM, respectively) through the via holes, so that the enable signal lines EM of the adjacent two pixel driving circuits in the first sub-pixel row X1 are connected through the second sub-bridge line k 2. Accordingly, the twentieth sub-bridge line k20 is located in the second sub-pixel row X2, one end of the twentieth sub-bridge line k20 is connected to the tenth bridge portion 410 at the corresponding position through a via hole, and the other end is connected to the eleventh bridge portion 411 at the corresponding position through a via hole, thereby connecting the enable signal lines EM in two adjacent pixel driving circuits in the second sub-pixel row X2.

The orthographic projections of the third sub-bridge line k3 and the thirty-second sub-bridge line k30 on the substrate are extended along the pixel row direction X, the third sub-bridge line k3 is located in the first sub-pixel row X1, one end of the third sub-bridge line k3 is connected to the sixth bridge 46 in the first pixel driving circuit through the via hole to be connected to the fourth gate signal line GateN ' in the first pixel driving circuit through the sixth bridge 46, and the other end of the third sub-bridge line k3 is connected to the first bridge 41 in the adjacent third pixel driving circuit in the first sub-pixel row X1 through the via hole to be connected to the fourth gate signal line GateN ' in the third pixel driving circuit, so that the third sub-bridge line k3 connects the fourth gate signal line GateN ' in the two adjacent pixel driving circuits in the first sub-pixel row X1. Accordingly, the thirty-first sub-bridge line k30 is located in the second sub-pixel row X2, one end of the thirty-first sub-bridge line k30 is connected to the sixth bridge portion 46 in one of the second pixel driving circuits through a via hole, and the other end is connected to the first bridge portion 41 in the adjacent other of the second pixel driving circuits through a via hole, so as to connect the fourth gate signal lines GateN' in the adjacent two of the second sub-pixel row X2.

The orthographic projections of the fourth sub-bridge line k4 and the forty sub-bridge line k40 on the substrate extend along the pixel row direction X, the fourth sub-bridge line k4 is located in the first sub-pixel row X1, one end of the fourth sub-bridge line k4 is connected with one end of an initialization signal line Vinit in the first pixel driving circuit through a via hole, and the other end of the fourth sub-bridge line k4 is connected with one end of an initialization signal line Vinit in an adjacent third pixel driving circuit through a via hole, so that the initialization signal lines Vinit in two adjacent pixel driving circuits in the first sub-pixel row X1 are connected. The forty-second sub-bridge line k40 is located in the second sub-pixel row X2, and accordingly, one end of the forty-second sub-bridge line k40 is connected to one end of the initialization signal line Vinit in one second pixel driving circuit through a via hole, and the other end is connected to one end of the initialization signal line Vinit in an adjacent second pixel driving circuit through a via hole, so that the initialization signal lines Vinit in two adjacent pixel driving circuits of the second sub-pixel row X2 are connected.

Comparing the layout structure shown in fig. 23 of the above embodiment, it can be seen that in the present exemplary embodiment, the first sub-bridge line k1, the tenth sub-bridge line k10, and the fifth sub-bridge line k5, the fifty-th sub-bridge line k50 are not included any more, wherein the first sub-bridge line k1, the tenth sub-bridge line k10 connects the first gate signal lines GateP in the first sub-pixel row X1 and the second sub-pixel row X2 by the first gate signal switching line G1 and the second gate signal switching line G2 of the first conductive layer, and the fifth sub-bridge line k5, the fifty-th sub-bridge line k50 connects the first reset signal lines ResetN and the second reset signal lines ResetN' of the first sub-pixel row X1 and the second sub-pixel row X2 by the first reset signal switching line R1 and the second reset signal switching line R2 of the third conductive layer 3, thereby reducing the number of first gate signal lines GateP in the first conductive layer 1 and the third conductive layer 3, and thus providing a larger wiring space for the first bridge line ITO 1.

Fig. 31 is a partial cross-sectional view taken along the broken line AA in fig. 5. The display panel may include a first insulating layer 81, a second insulating layer 82, a third insulating layer 83, a fourth insulating layer 84, a fifth insulating layer 85, a first dielectric layer 86, a first planarization layer 87, a first sub-planarization layer 88, a second sub-planarization layer 89, and a second planarization layer 90, wherein the substrate 80, the first insulating layer 81, the first active layer 10, the second insulating layer 82, the first conductive layer 1, the third insulating layer 83, the second conductive layer 2, the fourth insulating layer 84, the second active layer 20, the fifth insulating layer 85, the third conductive layer 3, the first dielectric layer 86, the fourth conductive layer 4, the first planarization layer 87, the first transition layer ITO1, the first sub-planarization layer 88, the second transition layer 2, the second sub-planarization layer 89, the fifth conductive layer 5, and the second planarization layer 90 are sequentially stacked. The first insulating layer 81 and the second insulating layer 82 may be silicon oxide layers, and the first dielectric layer 86 may be a silicon nitride layer. The substrate may include a glass substrate, a barrier layer, and a polyimide layer, which are sequentially stacked, and the barrier layer may be an inorganic material. The material of the first conductive layer 1 and the second conductive layer 2 may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum/titanium alloy or a laminate thereof. The materials of the third conductive layer 3, the fourth conductive layer 4, and the fifth conductive layer 5 may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, and niobium, or an alloy, or a molybdenum/titanium alloy, or a stack, or may be a titanium/aluminum/titanium stack.

In addition, the disclosure further provides a display device, including the display panel and the photosensitive element according to any of the embodiments, where the photosensitive element is located on a non-display surface side of the display panel, and a front projection of the photosensitive element on the display panel at least partially overlaps the first display area.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel, comprising a first display area and a second display area at least partially surrounding the first display area; the first display area comprises a plurality of pixel rows, the pixel rows comprise a first sub-pixel row and a second sub-pixel row, the first sub-pixel row and the second sub-pixel row are not overlapped, and the first sub-pixel row and the second sub-pixel row comprise a plurality of pixel driving circuits; the display panel further includes:

A substrate base;

at least one conductive layer located on one side of the substrate base plate, the conductive layer comprising:

a plurality of driving signal lines extending in a pixel row direction in orthographic projection on the substrate, the driving signal lines for supplying gate driving signals to at least part of the transistors in the pixel driving circuit;

the signal switching lines are positioned in a transition region between the first display region and the second display region and are used for connecting driving signal lines for transmitting the same grid driving signals in a first sub-pixel row and a second sub-pixel row in the same pixel row;

the first transfer layer is positioned on one side of the conducting layer, which is away from the substrate, and the first transfer layer comprises a plurality of bridging lines, the orthographic projections of the bridging lines on the substrate extend along the pixel row direction and are positioned in the first display area, and the bridging lines are connected with gate signal lines for transmitting the same gate driving signals in two adjacent pixel driving circuits in the same sub-pixel row.

2. The display panel according to claim 1, wherein the drive signal lines transmitting the same gate drive signal in any adjacent two of the pixel drive circuits in the first display region are connected by corresponding bridge lines in the same pixel row.

3. The display panel according to claim 1, wherein in any adjacent two pixel driving circuits in the first display region in the same pixel row, driving signal lines partially transmitting the same gate driving signal are connected by corresponding to the bridge lines, and driving signal lines partially transmitting the same gate driving signal are connected by signal connection lines in the conductive layer.

4. The display panel according to claim 1, wherein the plurality of bridge lines includes a first bridge line and a second bridge line, the first bridge line being connected to a drive signal line transmitting the same gate drive signal in two adjacent pixel drive circuits in the first subpixel row, and the second bridge line being connected to a drive signal line transmitting the same gate drive signal in two adjacent pixel drive circuits in the second subpixel row.

5. The display panel according to claim 4, wherein each of the pixel driving circuits includes a plurality of transistors, wherein a gate of the first transistor is connected to the reset signal terminal, a gate of the second transistor is connected to the second gate signal terminal, gates of the fifth transistor and the sixth transistor are both connected to the enable signal terminal, and gates of the fourth transistor and the seventh transistor are both connected to the first gate signal terminal;

The at least one conductive layer includes:

a first conductive layer located at one side of the substrate base plate, the first conductive layer comprising:

an enable signal line having a partial structure for forming a gate of the fifth transistor and a partial structure for forming a gate of the sixth transistor;

a first gate signal line having a partial structure for forming a gate of the fourth transistor and a partial structure for forming a gate of the seventh transistor;

a third conductive layer between the first conductive layer and the first transfer layer, the third conductive layer comprising:

a fourth gate signal line having a partial structure for forming a top gate of the second transistor;

a second reset signal line, part of which is used for forming a top gate of the first transistor;

the orthographic projections of the enabling signal line, the first grid signal line, the fourth grid signal line and the second reset signal line on the substrate are distributed at intervals along the pixel column direction, and the pixel column direction is intersected with the pixel row direction.

6. The display panel of claim 5, further comprising:

a fourth conductive layer between the third conductive layer and the first transfer layer, the fourth conductive layer comprising:

an eighth bridge portion connected to one end of the first gate signal line through a via hole;

a ninth bridge portion connected to the other end of the first gate signal line through a via hole;

the first bridge wire comprises a first sub-bridge wire and a second sub-bridge wire, and the first sub-bridge wire is connected with an eighth bridge part of one pixel driving circuit and a ninth bridge part of the adjacent other pixel driving circuit in a first sub-pixel row through a through hole respectively so as to be connected with the adjacent first grid signal wire; the second sub-bridge wire is connected with the enabling signal wires in the two adjacent pixel driving circuits in the first sub-pixel row through the through holes respectively;

the second bridge wire comprises a tenth sub-bridge wire and a twentieth sub-bridge wire, and the tenth sub-bridge wire is connected with an eighth bridge part of a pixel driving circuit in a second sub-pixel row and a ninth bridge part of an adjacent other pixel driving circuit through a via hole respectively so as to be connected with the adjacent first grid signal wire; the twenty-second sub-bridge wire is connected with the enabling signal wires in the two adjacent pixel driving circuits in the second sub-pixel row through the through holes respectively.

7. The display panel of claim 5, further comprising:

a first bridge portion connected to one end of the fourth gate signal line through a via hole;

the second bridging part is connected with the second reset signal line through a via hole;

a sixth bridge portion connected to the other end of the fourth gate signal line through a via hole;

the first bridge wire further comprises a third sub-bridge wire and a fifth sub-bridge wire, and the third sub-bridge wire is connected with the sixth bridge part of one pixel driving circuit and the first bridge part of the other pixel driving circuit in the first sub-pixel row through a through hole respectively so as to be connected with the fourth grid electrode signal wire in the two pixel driving circuits; the fifth sub-bridge wire is connected with the second bridging part of one pixel driving circuit and the second bridging part of the adjacent other pixel driving circuit in the first sub-pixel row through a through hole respectively so as to be connected with the reset signal wire in the adjacent two pixel driving circuits;

the second bridge line further comprises a thirty-first bridge line and a fifty-second bridge line, wherein the thirty-first bridge line is respectively connected with the sixth bridge part of one pixel driving circuit in a second sub-pixel row and the first bridge part of the other adjacent pixel driving circuit so as to be connected with the fourth grid electrode signal line of the two adjacent pixel driving circuits; the fifty-th sub-bridge line is connected to the second bridge portion of one pixel driving circuit and the second bridge portion of the adjacent other pixel driving circuit in the second sub-pixel row, respectively, so as to connect the reset signal lines in the adjacent two pixel driving circuits.

8. The display panel of claim 5, wherein the first conductive layer further comprises:

a first gate signal patch cord connected to the first gate signal lines in two adjacent pixel driving circuits in a first subpixel row;

and the second grid signal patch cord is connected with the first grid signal lines in two adjacent pixel driving circuits in the second sub-pixel row.

9. The display panel of claim 8, wherein the third conductive layer further comprises:

a first reset signal patch cord connected to the second reset signal lines in two adjacent pixel driving circuits in the first subpixel row;

and the second reset signal patch cord is connected with the reset signal lines in two adjacent pixel driving circuits in the second sub-pixel row.

10. The display panel of claim 9, wherein in the same pixel row, an orthographic projection of a first gate signal patch cord on the substrate overlaps with an orthographic projection portion of the second reset signal patch cord on the substrate;

in any two adjacent pixel rows, the orthographic projection of the second reset signal switching wire of the previous pixel row on the substrate is overlapped with the orthographic projection part of the first grid signal switching wire of the next pixel row on the substrate.

11. The display panel of claim 9, wherein in the same pixel row, an orthographic projection of the second reset signal patch cord on the substrate is located on an orthographic projection of the enable signal cord in a first subpixel row on the substrate;

in any two adjacent pixel rows, the orthographic projection of the first reset signal patch cord of the next pixel row on the substrate is positioned on the orthographic projection of the enabling signal cord of the second sub-pixel row in the previous pixel row on the substrate.

12. The display panel of claim 6, wherein the first conductive layer further comprises:

the first enabling signal switching line is positioned in a transition region between the first display region and the second display region, and orthographic projection of the first enabling signal switching line on the substrate extends along the direction of the pixel columns;

in the same pixel row, the first enabling signal patch cord is respectively connected with the enabling signal line in the first sub-pixel row and the enabling signal line in the second sub-pixel row.

13. The display panel of claim 7, wherein the fourth conductive layer further comprises:

The third reset signal switching line is positioned in a transition area between the first display area and the second display area;

in the same pixel row, the third reset signal patch cord is respectively connected with the second bridging portion in the first sub-pixel row and the second bridging portion in the second sub-pixel row.

14. The display panel of claim 6, wherein the fourth conductive layer further comprises:

the third grid signal switching line is positioned in a transition region between the first display region and the second display region, and orthographic projection of the third grid signal switching line on the substrate extends along the direction of the pixel columns;

in the same pixel row, the third gate signal patch cord is connected to the eighth bridge portion in the first sub-pixel row and the ninth bridge portion in the second sub-pixel row respectively.

15. The display panel of claim 14, wherein the third conductive layer further comprises:

a fourth gate signal patch cord located in a transition region between the first display region and the second display region, wherein a orthographic projection of the fourth gate signal patch cord on the substrate extends along a pixel column direction;

In the same pixel row, the fourth gate signal patch cord is respectively connected with the fourth gate signal line in the first sub-pixel row and the fourth gate signal line in the second sub-pixel row;

the fourth gate signal patch cord is located between two adjacent second reset signal lines in the second sub-pixel row.

16. The display panel of claim 15, wherein an orthographic projection of the fourth gate signal patch cord on the substrate overlaps with an orthographic projection of the third gate signal patch cord on the substrate.

17. The display panel of claim 9, wherein the first conductive layer further comprises:

a first gate signal bridge line located at a transition region between the first display region and the second display region;

in the same pixel row, the first gate signal bridging line is connected to the first gate signal line in the first sub-pixel row and the first gate signal line in the second sub-pixel row respectively.

18. The display panel of claim 17, wherein the third conductive layer further comprises:

a fourth reset signal patch cord located in a transition region between the first display region and the second display region, wherein a orthographic projection of the fourth reset signal patch cord on the substrate extends along a pixel column direction;

In the same pixel row, the fourth reset signal patch cord is respectively connected with the first reset signal patch cord in the first sub-pixel row and the second reset signal patch cord in the second sub-pixel row, and the fourth reset signal patch cord is located between two adjacent fourth gate signal lines in the first sub-pixel row.

19. The display panel of claim 18, wherein the third conductive layer further comprises:

a fifth gate signal patch cord located at a transition region between the first display region and the second display region;

the fifth gate signal patch cord is respectively connected with the fourth gate signal line in the first sub-pixel row and the fourth gate signal line in the second sub-pixel row, and orthographic projection of the fifth gate signal patch cord on the substrate overlaps with orthographic projection of the first gate signal patch cord on the substrate.

20. The display panel of claim 17, wherein the display panel further comprises:

The second enabling signal switching line is positioned in a transition area between the first display area and the second display area;

in the same pixel row, the second enabling signal patch cord is connected with the enabling signal line in the first sub-pixel row and the enabling signal line in the second sub-pixel row through a through hole respectively.

21. The display panel of claim 20, wherein the second enable signal patch cord comprises a first component and a second component, the orthographic projection of the first component on the substrate is located on the orthographic projection of the first gate signal bridge cord on the substrate, and the orthographic projection of the second component on the substrate is located on the orthographic projection of the first reset signal patch cord in the next pixel row on the substrate.

22. The display panel according to claim 5, wherein each pixel driving circuit further comprises a driving transistor, a first electrode of the first transistor being connected to a gate of the driving transistor; the first pole of the second transistor is connected with the grid electrode of the driving transistor, and the second pole of the second transistor is connected with the first pole of the driving transistor; the first electrode of the fourth transistor and the first electrode of the fifth transistor are both connected with the second electrode of the driving transistor, the first electrode of the sixth transistor is connected with the first electrode of the driving transistor, and the first electrode of the seventh transistor is connected with the second electrode of the sixth transistor; the display panel further includes:

A first active layer between the substrate base plate and the first conductive layer, the first active layer comprising:

a third active portion for forming a channel region of the driving transistor;

a fourth active portion for forming a channel region of the fourth transistor;

a fifth active portion for forming a channel region of a fifth transistor;

a sixth active portion for forming a channel region of the sixth transistor;

a seventh active part for forming a channel region of the seventh transistor;

a second conductive layer between the first conductive layer and the third conductive layer, the second conductive layer comprising:

a second gate signal line, the orthographic projection on the substrate covering the orthographic projection of the second active portion on the substrate and being located on the orthographic projection of the fourth gate signal line on the substrate, a part of the second gate signal line being used for forming a bottom gate of the second transistor;

a first reset signal line, wherein the orthographic projection of the first active part on the substrate is covered by the orthographic projection of the first active part on the substrate and overlapped with the orthographic projection part of the second reset signal line on the substrate, and a part of the first reset signal line is used for forming a bottom gate of the first transistor;

A second active layer between the second conductive layer and the third conductive layer, the second active layer comprising:

the first active part is used for forming a channel region of the first transistor;

the second active part is used for forming a channel region of the second transistor;

the enabling signal line, the first grid signal line, the fourth grid signal line and the first reset signal line are sequentially distributed in the direction of pixel columns in orthographic projection mode on the substrate;

the fourth active portion and the fifth active portion are located at one side of the third active portion in the pixel row direction, and the sixth active portion and the seventh active portion are located at the other side of the third active portion in the pixel row direction.

23. The display panel according to claim 22, wherein a second pole of the first transistor and a second pole of the seventh transistor are each connected to an initialization signal line;

the first active layer further includes:

a seventh sub-active portion connected to one side of the seventh active portion for forming a second pole of the seventh transistor;

the second active layer further includes:

a ninth sub-active portion connected to one side of the first active portion for forming a second pole of the first transistor;

The display panel further includes:

a fourth conductive layer between the third conductive layer and the first transfer layer, the fourth conductive layer further comprising:

initializing a signal line, wherein orthographic projection on the substrate extends along the pixel row direction, one end of the initial signal line is connected with the ninth sub-active part through a via hole, and the other end of the initial signal line is connected with the seventh sub-active part through a via hole;

the first bridge wire further comprises a fourth sub-bridge wire, and the fourth sub-bridge wire is connected with the initialization signal wires in two adjacent pixel driving circuits in the first sub-pixel row through the through holes respectively;

the second bridge line further includes a forty-second bridge line, one end of the forty-second bridge line being connected to the initialization signal line in two adjacent pixel driving circuits in the second sub-pixel row through a via hole.

24. A display device comprising the display panel of any one of claims 1-23 and a photosensitive element, wherein the photosensitive element is located on a non-display surface side of the display panel, and wherein an orthographic projection of the photosensitive element on the display panel at least partially overlaps the first display region.