CN116599536A

CN116599536A - Gray code to binary code converter and device comprising same

Info

Publication number: CN116599536A
Application number: CN202310101744.1A
Authority: CN
Inventors: 李赫钟
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-02-11
Filing date: 2023-02-09
Publication date: 2023-08-15

Abstract

Gray code to binary code converters and devices including the same are provided. The Gray code to binary code converter includes: a plurality of merge-and-exit (PIPO) latches, each of the plurality of PIPO latches configured to output a parallel output gray code by latching the parallel input gray code in response to a sampling signal; and a parallel-in serial-out (PISO) circuit including a first set of switches, the PISO circuit configured to: the parallel output gray code latched in the plurality of PIPO latches is converted into a binary code, and bits of the binary code are sequentially output from Least Significant Bits (LSBs) of the binary code to Most Significant Bits (MSBs) of the binary code in units of bits when the arrangement of the first group of switches is changed.

Description

Gray code to binary code converter and device comprising same

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2022-0018462 filed on day 2, month 11 of 2022 and korean patent application No.10-2022-0079026 filed on day 6, month 28 of 2022, each of which is incorporated herein by reference in its entirety.

Technical Field

Some example embodiments of the inventive concepts relate to a gray code to binary code converter including a gray code to binary code converter converting parallel gray codes into parallel binary codes and then sequentially outputting bits of the parallel binary codes from Least Significant Bits (LSBs) of the parallel binary codes to Most Significant Bits (MSBs) of the parallel binary codes in units of bits, and/or an apparatus including the same.

Background

An image sensor is a device that captures an image by using the properties of semiconductor response light. With the development of CMOS technology, CMOS image sensors using CMOS technology are being widely used.

Each CMOS image sensor expects or requires an operation of converting an analog pixel signal output from an Active Pixel Sensor (APS) array into a digital pixel signal. For this conversion, each CMOS image sensor uses an analog-to-digital converter (ADC).

According to the analog-to-digital conversion method, the CMOS image sensor is divided into a CMOS image sensor using a single ADC method and a CMOS image sensor using a column ADC method.

The single ADC method refers to a method of converting analog pixel signals output from all column lines of an APS array into digital pixel signals in a desired (or alternatively predetermined) time by using one ADC that operates at a high speed. The single ADC approach has a reduced chip area to achieve an ADC. However, the single ADC method has high power consumption because the ADC needs to operate at high speed. On the other hand, the column ADC method refers to a method of arranging ADCs having a simple structure in each column, and has lower power consumption than the single ADC method.

The column ADC may comprise a counter. The counter compares a pixel signal output through the APS array with a ramp signal output from a ramp signal generator, and counts a state transition time of a comparison signal corresponding to the comparison result.

Disclosure of Invention

Some example embodiments of the inventive concepts provide an analog-to-digital conversion circuit that converts parallel gray codes into parallel binary codes for high-speed operation and noise reduction, and sequentially outputs bits of the parallel binary codes from LSB of the parallel binary codes to MSB of the parallel binary codes in units of bits when an arrangement of switches is changed, and an apparatus including the analog-to-digital conversion circuit.

According to an example embodiment, a gray code to binary code converter includes: a plurality of parallel-in parallel-out (PIPO) latches, each of the plurality of PIPO latches configured to output parallel output gray codes by latching the parallel input gray codes in response to a sampling signal; and a Parallel Input Serial Out (PISO) circuit including a first set of switches configured to convert the parallel output gray code latched in the plurality of PIPO latches into a binary code, and sequentially output bits of the binary code in units of bits from Least Significant Bits (LSBs) of the binary code to Most Significant Bits (MSBs) of the binary code when an arrangement of the first set of switches is changed.

According to an example embodiment, a Correlated Double Sampling (CDS) circuit includes: a full adder, the full adder comprising a first input; and a gray code-to-binary code converter configured to convert parallel input gray codes into binary codes, and sequentially output bits of the binary codes from Least Significant Bits (LSBs) of the binary codes to Most Significant Bits (MSBs) of the binary codes to the first input terminal of the full adder in units of bits when an arrangement of a first set of switches included in the gray code-to-binary code converter is changed.

According to an example embodiment, an image sensor includes: a pixel array including a plurality of pixels, each of the plurality of pixels configured to generate a pixel signal by performing photoelectric conversion; and an analog-to-digital converter configured to receive the pixel signal output from at least one pixel of the plurality of pixels, wherein the analog-to-digital converter comprises: a ramp signal generator configured to generate a ramp signal; a sampling circuit configured to generate a sampling signal by sampling the pixel signal output from the at least one pixel; and a gray code-to-binary code converter configured to receive parallel input gray codes generated by the gray code generator and convert the parallel input gray codes into binary codes, and sequentially output bits of the binary codes from Least Significant Bits (LSBs) of the binary codes to Most Significant Bits (MSBs) of the binary codes in units of bits when an arrangement of a first set of switches included in the gray code-to-binary code converter is changed.

The Gray code to binary code converter includes: a PIPO latch, each of the PIPO latches outputting a parallel output gray code by latching the parallel input gray code in response to the sampling signal; and a PISO circuit that converts the parallel output gray code latched in the PIPO latch into the binary code, and sequentially outputs the bits of the binary code from the LSB to the MSB when the arrangement of the first group of switches is changed.

The PISO circuit further includes a plurality of exclusive-or gates connected in series, and each of the plurality of exclusive-or gates includes an output connected to the first input of the next stage. The first set of switches connects the second input of the plurality of exclusive-or gates so connected in series to the output of the PIPO latch or to ground, respectively, in response to the switching signals of the first set of switches.

Drawings

The above and other objects and features of the inventive concept will become apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a block diagram of an image sensor including an analog-to-digital converter including a gray code-to-binary code converter that converts parallel gray codes into serial binary codes according to an example embodiment of the inventive concept.

Fig. 2 is a block diagram of a first Correlated Double Sampling (CDS) circuit shown in fig. 1.

Fig. 3 is an example embodiment of a circuit diagram of the first latch shown in fig. 2.

Fig. 4 is a table for describing a switching arrangement of the first switching circuit in order to describe an operation of the parallel gray code to serial binary code conversion circuit shown in fig. 2.

Fig. 5 is a detailed view of the reset memory circuit shown in fig. 2.

Fig. 6 is a table for describing a switching arrangement of the second switching circuit included in the reset memory circuit shown in fig. 5 in a reset sampling operation.

Fig. 7 is a table for describing a switching arrangement of the second switching circuit included in the reset memory circuit shown in fig. 5 in a photosensitive image sampling operation.

Fig. 8 is a timing diagram for describing a process of storing parallel gray codes latched in a merging-out (PIPO) latch of the first CDS circuit shown in fig. 2 in latches included in the reset memory circuit.

Fig. 9 is a timing chart for describing a procedure of adding the parallel gray code latched in the PIPO latch of the first CDS circuit shown in fig. 2 to the parallel binary code stored in the latch included in the reset memory circuit.

Fig. 10 is a timing chart for describing a process of outputting codes stored in latches included in the output memory circuit of the first CDS circuit shown in fig. 2 in units of bits.

Fig. 11 is a timing chart of signals for describing the operation of the first CDS circuit shown in fig. 2.

Fig. 12 is a block diagram of an image sensor including a pixel array implemented in a first semiconductor chip and an analog-to-digital conversion circuit implemented in a second semiconductor chip.

Fig. 13 is a flowchart for describing the operation of the first CDS circuit shown in fig. 2.

Fig. 14 is a block diagram of an image processing apparatus including the image sensor shown in fig. 1.

Detailed Description

Referring to fig. 1, the image sensor 100 includes a pixel array 110, an analog-to-digital converter 115, a first switching signal generator 160, a second switching signal generator 170, and a clock signal generator 180. The analog-to-digital converter 115 includes a ramp signal generator 120, a plurality of comparators 130_1, 130_2 to 130_n (here, 'n' is a natural number greater than or equal to 2), a gray code generator 140, and a plurality of Correlated Double Sampling (CDS) circuits 200_1, 200_2 to 200_n. In some example embodiments, the CDS circuits 200_1 to 200—n may reduce noise in the electrical signal by subtracting a reference voltage of the pixel (e.g., a voltage of the pixel after reset) from a signal voltage of the pixel (e.g., a voltage of the pixel at the end of integration) at the end of each integration period. Correlated double sampling may improve technical operation of image sensor 100 by reducing or eliminating kTC noise (e.g., thermal noise associated with the capacitance of the sensor).

The image sensor 100 may be a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and may be referred to as a "solid-state imaging device".

The pixel array 110 (or APS array) includes a plurality of pixels 111 arranged in a matrix shape, and each of the plurality of pixels 111 outputs a pixel signal (or analog pixel signal) by performing photoelectric conversion.

As shown in fig. 2, the analog-to-digital converter 115 converts parallel input gray codes (G <0>, G <1>, G <2>, and G <3 >) generated by the gray code generator 140 into parallel output gray codes (G <0>, G <1>, G <2>, and G <3 >), converts the parallel output gray codes (G <0>, G <1>, G <2>, and G <3 >) into parallel binary codes (B <0>, B <1>, B <2>, and B <3 >), and sequentially outputs bits of the parallel binary codes (B <0>, B <1>, B <2>, and B <3 >) from LSB to MSB in units of bits through one output terminal by using the first sets of switches SW1 to SW4 and SW1a to SW4 a. In some example embodiments, the use of gray codes may improve the technical operation of the image sensor 100 by reducing or preventing erroneous outputs from electromechanical switches. Gray codes comprise successive values that differ in only one bit, so incrementing each value may involve changing only a single bit, thereby causing fewer electromechanical errors during processing in the image sensor 100.

The RAMP signal generator 120 generates a RAMP signal RAMP having the waveform shown in fig. 11. The ramp signal generator 120 may be a digital-to-analog converter.

The comparators 130_1 to 130—n receive and compare the pixel signals PIX1 to PIXn transmitted through the column lines COL1 to COL (or pixel lines) with the RAMP signal RAMP, and then output comparison signals cds_dcs1 to cds_dcsn, respectively. Each of the pixel signals PIX1 to PIXn may include a reset signal and a photosensitive signal. For example, each of the comparators 130_1 to 130—n may be referred to as a "sampling circuit" that generates sampling signals cds_dcs1 to cds_dcsn by sampling the pixel signals PIX1 to PIXn using the RAMP signal RAMP, respectively.

In fig. 1, it is shown that the RAMP signal RAMP is input to a first input terminal (e.g., an inverting input terminal) of each of the comparators 130_1 to 130—n, and the pixel signals PIX1 to PIXn are input to second input terminals (e.g., non-inverting input terminals) of the comparators 130_1 to 130—n, respectively.

According to some example embodiments, the RAMP signal RAMP may be input to the second input terminal of each of the comparators 130_1 to 130—n, and the pixel signals PIX1 to PIXn may be input to the first input terminals of the comparators 130_1 to 130—n, respectively.

Fig. 11 shows waveforms of the first comparison signal cds_dcs1 at a time point when the RAMP signal RAMP is input to the first input terminal of the first comparator 130_1 and the first pixel signal PIX1 is input to the second input terminal of the first comparator 130_1. However, the waveform of the first comparison signal cds_dcs1 at the time point when the RAMP signal RAMP is input to the second input terminal of the first comparator 130_1 and the first pixel signal PIX1 is input to the first input terminal of the first comparator 130_1 is opposite to the waveform of the first comparison signal cds_dcs1 shown in fig. 11.

Gray code generator 140 generates X-bit parallel input Gray codes (G <0> through G < X-1 >). Here, 'X' is a natural number of 2 or more.

Each of the CDS circuits 200_1 to 200—n receives an X-bit parallel input gray code (G <0> to G < X-1 >). Each of the CDS circuits 200_1 to 200—n is also referred to as a "conversion circuit" or a "counter". Each of the CDS circuits 200_1 to 200—n may compare the RAMP signal RAMP with each of the pixel signals PIX1 to PIXn, may count a state transition time of each of the comparison signals cds_dcs1 to cds_dcsn, and may generate a count value.

Hereinafter, for simplicity of the drawing and convenience of description, it is assumed that the gray code generator 140 of fig. 1 generates 4-bit parallel input gray codes (G <0> to G <3 >), the signal G <0> is LSB of the 4-bit parallel input gray code, and the signal G <3> is MSB of the 4-bit parallel input gray code.

The first switching signal generator 160 generates the first group switching signals SS1 to SS4 and bSS1 to bSS4 by using the operation control signal add_op and the clock signal CLK and outputs the first group switching signals SS1 to SS4 and bSS1 to bSS4 to the analog-to-digital converter 115.

The switching signals SS1 and bSS1, SS2 and bSS2, SS3 and bSS3, and SS4 and bSS4 paired with each other are complementary signals. For example, the switching signals bSS to bSS respectively may be signals generated by inverting the switching signals SS1 to SS4 using inverters.

The second switching signal generator 170 generates the second group switching signals RS1 to RS4 and bRS1 to bRS4 by using the operation control signal add_op and the clock signal CLK, and outputs the second group switching signals RS1 to RS4 and bRS1 to bRS4 to the analog-to-digital converter 115.

The switching signals RS1 and bRS1, RS2 and bRS2, RS3 and bRS3, and RS4 and bRS4 paired with each other are complementary signals. For example, the switching signals bRS1 to bRS4 may be signals generated by inverting the switching signals RS1 to RS4 using inverters, respectively. According to some example embodiments, the first and second switching signal generators 160 and 170 may be implemented as one switching signal generator.

The clock signal generator 180 generates a first clock signal CLK1 to be supplied to the serial binary adder 260 shown in fig. 2, a second group of clock signals clk2_1 to clk2_4 to be supplied to the reset memory circuit 270 shown in fig. 2, and a third group of clock signals clk3_1 to clk3_4 to be supplied to the output memory circuit 280 shown in fig. 2 by using the operation control signal add_op and the clock signal CLK.

Fig. 2 is a block diagram of the first CDS circuit shown in fig. 1.

Referring to fig. 1 and 2, the first CDS circuit (or the first counter 200_1) includes a gray code to binary code converter 210 (which is referred to as a "G2B converter" or a "parallel gray code to serial binary code conversion circuit"), a serial binary adder 260, a reset memory circuit 270, and an output memory circuit 280.

The G2B converter 210 includes a first group of switches SW1 to SW4 and SW1a to SW4a. In addition, the G2B converter 210 converts the parallel output gray codes (G <0> to G <3 >) latched in the merging-out (PIPO) latches 221_1 to 221_4 into parallel binary codes (B <0> to B <3 >) and simultaneously or substantially simultaneously outputs LSBs (B <0 >) of the parallel binary codes (B <0> to B <3 >), and sequentially outputs bits of the parallel binary codes from a next bit B <1> of LSBs (B <0> tob <3 >) of the parallel binary codes (B <0> tob <3 >) to the serial binary adder 260 in units of bits when changing the arrangement of the switches SW1 to SW4 and SW1a to SW4a in the first group.

In other words, the G2B converter 210 sequentially outputs bits of the parallel binary codes (B <0> to B <3 >) from LSB (B <0 >) of the parallel binary codes (B <0> to B <3 >) corresponding to the parallel input gray codes (G <0> to G <3 >) to MSB (B <3 >) of the parallel binary codes (B <0> to B <3 >) in units of bits by using the first set of switches SW1 to SW4 and SW1a to SW4 a.

The G2B converter 210 includes a PIPO circuit 220 and a Parallel In Serial Out (PISO) circuit 230, and the PISO circuit 230 includes a first switch circuit 240 and an exclusive or circuit 250 (which is also referred to as a "selection circuit").

The PIPO circuit 220 includes PIPO latches 221_1 to 221_4, each of which receives and latches parallel input gray codes (G <0> to G <3 >) in response to the first comparison signal cds_dcs1 and then outputs parallel output gray codes (G <0> to G <3 >).

Fig. 3 is an embodiment of a circuit diagram of the first latch shown in fig. 2.

Referring to fig. 2 and 3, the pipo latches 221_1 to 221_4 have the same or substantially the same structure and operation as each other, and thus the structure and operation of the first latch 221_1 will be representatively described with reference to fig. 3.

The structure of each of the latches 272_1 to 272_4 of the reset memory circuit 270 is the same or substantially the same as the structure of the first latch 221_1. For example, the clock signal clk2_1 is input to the control terminal of the first tri-state inverter 223 included in the latch 272_1, and the inverted clock signal/clk2_1 is input to the control terminal of the second tri-state inverter 227 included in the latch 272_1. Further, the clock signal clk2_4 is input to the control terminal of the first tri-state inverter 223 included in the latch 272_4, and the inverted clock signal/clk2_4 is input to the control terminal of the second tri-state inverter 227 included in the latch 272_4.

The structure of each of the latches 280_1 to 280_4 of the output memory circuit 280 is the same or substantially the same as the structure of the first latch 221_1. For example, the clock signal clk3_1 is input to the control terminal of the first tri-state inverter 223 included in the latch 280_1, and the inverted clock signal/clk3_1 is input to the control terminal of the second tri-state inverter 227 included in the latch 280_1. Further, the clock signal clk3_4 is input to the control terminal of the first tri-state inverter 223 included in the latch 280_4, and the inverted clock signal/clk3_4 is input to the control terminal of the second tri-state inverter 227 included in the latch 280_4.

The first latch 221_1 of fig. 3 includes a first tri-state inverter 223, an inverter 225, and a second tri-state inverter 227.

An input of the first tri-state inverter 223 is connected to an input D of the first latch 221_1, which receives the first input gray signal G <0>. An input terminal of the inverter 225 is connected to an output terminal of the first tri-state inverter 223, and an output terminal of the inverter 225 is connected to an output terminal Q of the first latch 221_1, which outputs a first output gray signal G <0>.

An input of the second tri-state inverter 227 is connected to the output Q of the first latch 221_1, and an output of the second tri-state inverter 227 is connected to an input of the inverter 225.

Since the level of the inverted first comparison signal/cds_dcs 1 is low when the level of the first comparison signal cds_dcs1 output from the first comparator 130_1 is high, the first tri-state inverter 223 is enabled and the second tri-state inverter 227 is disabled. Accordingly, the first latch 221_1 outputs a first output gray signal G <0>.

However, since the level of the inverted first comparison signal/cds_dcs 1 is high when the level of the first comparison signal cds_dcs1 output from the first comparator 130_1 is low, the first tri-state inverter 223 is disabled and the second tri-state inverter 227 is enabled. Thus, the first input gray signal (G <0 >) is maintained as it is by inverter 225 and second tri-state inverter 227.

The first switch circuit 240 includes a first group of switches SW1 to SW4 and SW1a to SW4a. Each of the switches SW1 to SW4 and SW1a to SW4a in the first group may be implemented with NMOS transistors.

The first switch SW1 of the first group is connected between the output Q of the first latch 221_1 and the second input of the first exclusive or gate 252_1 (which is also referred to as "output exclusive or gate" or "LSB exclusive or gate"), and the fifth switch SW1a of the first group is connected between the second input of the first exclusive or gate 252_1 and the ground Vss.

The second switch SW2 of the first group is connected between the output Q of the second latch 221_2 and the second input of the second exclusive or gate 252_2, and the sixth switch SW2a of the first group is connected between the second input of the second exclusive or gate 252_2 and ground.

The third switch SW3 of the first group is connected between the output Q of the third latch 221_3 and the second input of the third exclusive or gate 252_3, and the seventh switch SW3a of the first group is connected between the second input of the third exclusive or gate 252_3 and ground.

The fourth switch SW4 of the first group is connected between the output Q of the fourth latch 221_4 and the second input of the fourth exclusive or gate 252_4 (which is also referred to as "control exclusive or gate" or "MSB exclusive or gate"), and the eighth switch SW4a of the first group is connected between the second input of the fourth exclusive or gate 252_4 and ground.

The exclusive or circuit 250 includes a plurality of exclusive or gates 252_1 to 252_4. For example, each of the plurality of exclusive-or gates 252_1 to 252_4 may be a 2-input 1-output exclusive-or gate.

A first input terminal of the fourth exclusive or gate 252_4 receives the control signal RST, and an output terminal of the fourth exclusive or gate 252_4 is connected to a first input terminal of an exclusive or gate (for example, the third exclusive or gate 252_3) of the next stage.

When the image sensor 100 performs a reset sampling operation of sampling a reset signal included in the first pixel signal PIX1, the level of the control signal RST is at a logic high level (H). When the image sensor 100 performs a signal sampling operation of sampling a photosensitive signal included in the first pixel signal PIX1, the level of the control signal RST is at a logic low level (L).

The output terminal of the third exclusive-or gate 252_3 is connected to the first input terminal of the exclusive-or gate (e.g., the second exclusive-or gate 252_2) of the next stage; the output terminal of the second exclusive-or gate 252_2 is connected to the first input terminal of the exclusive-or gate of the next stage (for example, the first exclusive-or gate 252_1); and, the output of the first exclusive-or gate 252_1 is connected to the first input 'a' of the full adder 262.

The first exclusive or gate 252_1 sequentially outputs signals B <0>, B <1>, B <2> and B <3> of the parallel binary codes B <0> to B <3> in units of bits each time the arrangement of the switches SW1 to SW4 and SW1a to SW4a in the first group is changed.

Referring to fig. 2 and (a) of fig. 4, in the first switch arrangement, the switches SW1 to SW4 are turned on in response to the switch signals SS1 to SS4, and the switches SW1a to SW4a are turned off in response to the switch signals bSS to bSS, respectively. At this time, each of the switch pairs SW1 and SW1a, SW2 and SW2a, SW3 and SW3a, and SW4a is designed not to be turned on at the same time.

Here, the switch arrangement means a state in which the switches SW1 to SW4 and SW1a to SW4a are turned on or off in response to the levels of the switch signals SS1 to SS4 and bSS1 to bSS, respectively.

The parallel output gray codes (G <0>, G <1>, G <2>, and G <3 >) latched in the PIPO latches 221_1 through 221_4 are sent to the second inputs of the xor gates 252_1 through 252_4 simultaneously or substantially simultaneously according to the first switch arrangement.

Referring to fig. 11, the control signal RST is at a high level (or logic 1) in the reset sampling operation section of the first ADC Time (1 st ADC Time), and thus the parallel output gray code (rst_g=g <3> G <2> G <1> G <0> =0010) is converted into a parallel binary code (rst_b=b <3> B <2> B <1> B <0> =1100) by the exclusive-or circuit 250.

However, the control signal RST is at a low level (or logic 0) in the signal sampling operation section of the first ADC Time (1 st ADC Time), and thus the parallel output gray code (sig_g=g3 > G <2> G <1> G <0> =1111) is converted into a parallel binary code (sig_b=b <3> B <2> B <1> B <0> =1010) by the exclusive-or circuit 250.

The control signal RST is at a high level (or logic 1) in the reset sampling operation section of the second ADC Time (2 nd ADC Time), and thus the parallel output gray code (rst_g=g <3> G <2> G <1> G <0> =0010) is converted into a parallel binary code (rst_b=b <3> B <2> B <1> B <0> =1100) by the exclusive-or circuit 250.

However, the control signal RST is at a low level (or logic 0) in the signal sampling operation section of the second ADC Time (2 nd ADC Time), and thus the parallel output gray code (sig_g=g3 > G <2> G <1> G <0> =1000) is converted into a parallel binary code (sig_b=b <3> B <2> B <1> B <0> =1111) by the exclusive-or circuit 250.

The fourth exclusive or gate 252_4 outputs a binary signal B <3> by performing an exclusive or operation on the gray signal G <3> and the control signal RST latched in the fourth latch 221_4.

In some example embodiments, when the output signal B <3> of the fourth exclusive or gate 252_4 is expressed as "G <3>" regardless of the level of the control signal RST, the output signals B <0> to B <3> of the exclusive or gates 252_1 to 252_4 are expressed as formula 1.

[ 1]

B<3>＝G<3>

Exclusive or circuit 250 converts LSB (B <0 >) of parallel binary codes (B <3>, B <2>, B <1> and B <0 >) to an output signal OUT <0> for full adder 262.

After the LSBs (B <0 >) of the parallel binary codes (B <3>, B <2>, B <1> and B <0 >) are output to the full adder 262, the first set of switches SW1 to SW4 and SW1a to SW4a then have a second switch arrangement as shown in (B) of fig. 4.

In the second switch arrangement, each of the switches SW2, SW3, SW4 and SW1a is turned ON (ON), while each of the switches SW1, SW2a, SW3a and SW4a is turned OFF (OFF).

Referring to fig. 2 and (b) of fig. 4, the second input of the first exclusive or gate 252_1 is connected to ground according to the second switching arrangement.

When the logic value input to one input terminal of each of the 2-input 1-output exclusive-or gates 252_1 to 252_4 is 0, the logic value of the output terminal of each of the 2-input 1-output exclusive-or gates 252_1 to 252_4 is the same as the logic value input to the other input terminal.

The output signal (OUT <1> =b <1 >) of the exclusive or circuit 250 is represented by equation 2.

[ 2]

The exclusive or circuit 250 outputs the output signal B <1> of the second exclusive or gate 252_2 as the output signal OUT <1> to the full adder 262.

After the second signals B <1> of the parallel binary codes (B <3>, B <2>, B <1> and B <0 >) are output to the full adder 262, the first set of switches SW1 to SW4 and SW1a to SW4a have a third switch arrangement as shown in (c) of fig. 4.

In the third switch arrangement, each of the switches SW3, SW4, SW1a and SW2a is turned on, while each of the switches SW1, SW2, SW3a and SW4a is turned off.

Referring to fig. 2 and (c) of fig. 4, the second input of each of the exclusive or gates 252_1 and 252_2 is connected to ground according to a third switch arrangement.

The output signal (OUT <2> =b <2 >) of the exclusive or circuit 250 is expressed as formula 3 according to the third switch arrangement.

[ 3]

The exclusive or circuit 250 outputs the output signal B <2> of the third exclusive or gate 252_3 as the output signal OUT <2> to the full adder 262.

After the output signal B <2> of the third exclusive or gate 252_3 is output to the full adder 262, the first group of switches SW1 to SW4 and SW1a to SW4a have a fourth switch arrangement as shown in (d) of fig. 4.

In the fourth switch arrangement, each of the switches SW4, SW1a, SW2a and SW3a is turned on, while each of the switches SW1, SW2, SW3 and SW4a is turned off.

Referring to fig. 2 and (d) of fig. 4, the second input of each of the exclusive or gates 252_1, 252_2 and 252_3 is connected to ground according to a fourth switching arrangement.

The output signal (OUT <3> =b <3 >) of the exclusive-or circuit 250 is represented as in equation 4 according to the fourth switch arrangement.

[ 4]

The exclusive or circuit 250 outputs the output signal B <3> (e.g., MSB) of the fourth exclusive or gate 252_4 as the output signal OUT <3 >) to the full adder 262.

As described above with reference to fig. 2 and 4, when the switch arrangements of the switches SW1 to SW4 and SW1a to SW4a in the first group are sequentially changed from the first switch arrangement to the fourth switch arrangement after the parallel input gray codes (G <3>, G <2>, G <1>, and G <0 >) are converted into the parallel binary codes (B <3>, B <2>, B <1>, and B <0 >), bits of the parallel binary codes (B <3>, B <2>, B <1>, and B <0 >) are sequentially output from the LSB (B <0 >) to the MSB (B <3 >) in units of bits.

Returning to fig. 2, serial binary adder 260 includes full adder 262, first flip-flop 264, and second flip-flop 266.

The serial binary adder 260 is a circuit that adds a 1-bit signal input to the first input terminal "a" and a 1-bit signal input to the second input terminal "B". For example, as shown in fig. 11, the serial binary adder 260 adds the serial binary code sig_b generated in the signal sampling operation and the serial binary code rst_b generated in the reset sampling operation.

The full adder 262 includes a first input terminal "a" connected to the output terminal of the first exclusive or gate 252_1, a second input terminal "B" for receiving (or directly receiving) the output signal of the reset memory circuit 270 through the transmission line L1, a carry input terminal Cin, a carry output terminal Co, and a summing terminal "S".

In response to the rising edge of the first clock signal CLK1, the first flip-flop 264 latches the output signal of the summing terminal 'S' of the full adder 262 and then outputs the latched output signal to the reset memory circuit 270.

In response to the rising edge of the first clock signal CLK1, the second flip-flop 266 latches the output signal of the carry output terminal Co of the full adder 262 and then outputs (or feeds back) the latched output signal to the carry input terminal Cin of the full adder 262. Each of flip-flops 264 and 266 may be implemented as a D-flip-flop.

Fig. 5 is a detailed view of the reset memory circuit shown in fig. 2.

Referring to fig. 2 and 5, the reset memory circuit 270 includes a plurality of latches 272_1 to 272_4, a second switch circuit 274, and a plurality of or gates 276_1 to 276_4.

Each of the latches 272_1 to 272_4 latches the output signal of the first flip-flop 264 in response to the clock signals clk2_1 to clk2_4 shown in fig. 8, respectively.

The second switching circuit 274 includes a second group of switches RW1 to RW4 and RW1a to RW4a. Each of the switches RW1 to RW4 and RW1a to RW4a in the second group may be implemented with NMOS transistors.

The first switch RW1 in the second group is connected between the output Q of the first latch 272_1 and the second input of the first or gate 276_1 (which is also referred to as an "output or gate" or "LSB or gate"), and the fifth switch RW1a in the second group is connected between the second input of the first or gate 276_1 and ground Vss.

The second switch RW2 in the second group is connected between the output Q of the second latch 272_2 and the second input of the second or gate 276_2, and the sixth switch RW2a in the second group is connected between the second input of the second or gate 276_2 and ground.

The third switch RW3 in the second group is connected between the output Q of the third latch 272_3 and the second input of the third or gate 276_3, and the seventh switch RW3a in the second group is connected between the second input of the third or gate 276_3 and ground.

The fourth switch RW4 in the second group is connected between the output Q of the fourth latch 272_4 and the second input of the fourth or gate 276_4, and the eighth switch RW4a in the second group is connected between the second input of the fourth or gate 276_4 and ground.

Each of the or gates 276_1 to 276_4 may be a 2-input 1-output or gate.

The output terminals of the plurality of 2-input 1-output or gates 276_2 to 276_4 connected in series are connected to the first input terminals of the next or gates 276_1 to 276_3, respectively, in addition to the first or gate 276_1.

The first input of the fourth OR gate 276_4 is connected to the second input of the fourth OR gate 276_4; the output of the fourth OR gate 276_4 is connected to the first input of the third OR gate 276_3; the output of the third OR gate 276_3 is connected to the first input of the second OR gate 276_2; the output of the second OR gate 276_2 is connected to the first input of the first OR gate 276_1; and, the output of the first or gate 276_1 is connected to the second input "B" of the full adder 262 through the transmission line L1.

The first latch 272_1 latches the LSB, and the fourth latch 272_4 latches the MSB.

Referring to fig. 2, 5, 6 and 8, when the image sensor 100 performs a reset sampling operation, the second group of switches RW1 to RW4 and RW1a to RW4a have a fifth switch arrangement.

According to the fifth switch arrangement, each of the switches RW1a, RW2a, RW3a and RW4a is turned on, while each of the switches RW1, RW2, RW3 and RW4 is turned off. Thus, the second input of each of OR gates 276_1-276_4 is connected to ground, such that each of OR gates 276_1-276_4 outputs a logic 0.

Referring to fig. 2, 5, 7 (a) and 9, according to the sixth switch arrangement of the switches RW1 to RW4 and RW1a to RW4a in the second group, each of the switches RW1, RW2a, RW3a and RW4a is turned ON (ON) and each of the switches RW1a, RW2, RW3 and RW4 is turned OFF (OFF). Thus, the output signal of the first latch 272_1 is sent to the second input of the first OR gate 276_1.

Referring to fig. 2, 5, 7 (b) and 9, according to the seventh switch arrangement of the switches RW1 to RW4 and RW1a to RW4a in the second group, each of the switches RW1a, RW2, RW3a and RW4a is turned ON (ON) and each of the switches RW1, RW2a, RW3 and RW4 is turned OFF (OFF). Accordingly, the output signal of the second latch 272_2 is sent to the second input of the second OR gate 276_2.

Referring to fig. 2, 5, 7 (c) and 9, according to the eighth switch arrangement of the switches RW1 to RW4 and RW1a to RW4a in the second group, each of the switches RW1a, RW2a, RW3 and RW4a is turned ON (ON) and each of the switches RW1, RW2, RW3a and RW4 is turned OFF (OFF). Thus, the output signal of the third latch 272_3 is sent to the second input of the third OR gate 276_3.

Referring to fig. 2, 5, 7 (d) and 9, according to the ninth switching arrangement of the switches RW1 to RW4 and RW1a to RW4a in the second group, each of the switches RW1a, RW2a, RW3a and RW4 is turned ON (ON) and each of the switches RW1, RW2, RW3 and RW4a is turned OFF (OFF). Accordingly, the output signal of the fourth latch 272_4 is sent to the second input of the fourth OR gate 276_4.

Fig. 8 is a timing chart for describing a process of storing parallel gray codes latched in the PIPO latch of the first CDS circuit shown in fig. 2 in latches included in the reset memory circuit.

Referring to fig. 2, 5, 8, and 11, the parallel input gray code (rst_g=g <3> G <2> G <1> G <0> =0010) is latched in the PIPO circuit 220 according to the Gray Code Latch Operation (GCLO) in the reset sampling operation interval of the first ADC Time (1 st ADC Time).

The control signal RST is at a high level, and thus the parallel output gray code (rst_g=g3 > G <2> G <1> G <0> =0010) is converted into a parallel binary code (rst_b=b <3> B <2> B <1> B <0> =1100) by the exclusive-or circuit 250.

LSB (B <0> =0) output according to the first switch arrangement of the switches SW1 to SW4 and SW1a to SW4a in the first group is latched in the first latch 272_1 in response to the clock signal clk2_1; the output signal (B <1> =0) output according to the second switch arrangement of the switches SW1 to SW4 and SW1a to SW4a in the first group is latched in the second latch 272_2 in response to the clock signal clk2_2; the output signal (B <2> =1) output according to the third switch arrangement of the switches SW1 to SW4 and SW1a to SW4a in the first group is latched in the third latch 272_3 in response to the clock signal clk2_3; and an output signal (B <3> =1) output according to the fourth switch arrangement of the switches SW1 to SW4 and SW1a to SW4a in the first group is latched in the fourth latch 272_4 in response to the clock signal clk2_4. In the Reset Latch Operation (RLO), the complement (1100) of 1 of "—3" is latched in the latches 272_1 to 272_4.

Referring to fig. 2, 5, 9, and 11, the parallel input gray code (sig_g=g <3> G <2> G <1> G <0> =1111) is latched in the PIPO circuit 220 according to the Gray Code Latch Operation (GCLO) in the signal sampling operation section of the first ADC Time (1 st ADC Time).

The control signal RST is at a low level, and thus the parallel output gray code (sig_g=g3 > G <2> G <1> G <0> =1111) is converted into a parallel binary code (sig_b=b <3> B <2> B <1> B <0> =1010) by the exclusive-or circuit 250.

The serial binary adder 260 adds bits of the binary code (sig_b=1010) output from the first exclusive or gate 252_1 in units of bits to bits of the binary code (rst_b=1100) output from the first exclusive or gate 276_1 in units of bits (sig_b+rst_b), and then latches the addition result (sig_b+rst_b=1010+1100=0110) in each of the latches 280_1 to 280_4 in response to each of the clock signals clk3_1 to clk3_4.

Referring to fig. 2, 5, 8, 9, and 11, the parallel input gray code (rst_g=g <3> G <2> G <1> G <0> =0010) is latched in the PIPO circuit 220 according to the Gray Code Latch Operation (GCLO) in the reset sampling operation interval of the second ADC Time (2 nd ADC Time).

The parallel input gray code (sig_g=g <3> G <2> G <1> G <0> =1000) is latched in the PIPO circuit 220 according to GCLO in the signal sampling operation interval of the second ADC Time (2 nd ADC Time).

The control signal RST is at a low level, and thus the parallel output gray code (sig_g=g3 > G <2> G <1> G <0> =1000) is converted into a parallel binary code (sig_b=b <3> B <2> B <1> B <0> =1111) by the exclusive-or circuit 250.

The serial binary adder 260 adds bits of the binary code (sig_b=1111) output from the first exclusive or gate 252_1 in units of bits to bits of the binary code (rst_b=1100) output from the first exclusive or gate 276_1 in units of bits (sig_b+rst_b), and then latches the addition result (sig_b+rst_b=1111+1010=0011) in each of the latches 280_1 to 280_4 in response to each of the clock signals clk3_1 to clk3_4.

Referring to fig. 2, 5, 8, 9, 10 and 11, when each of the clock signals clk3_1 to clk3_4 is at a low level, the first latch 280_1 outputs a first signal DATA <0>.

When the second clock signal clk3_2 transitions from the low level to the high level, the first latch 280_1 outputs the second signal DATA <1> latched in the second latch 280_2; when the third clock signal clk3_3 transitions from the low level to the high level, the first latch 280_1 outputs the third signal DATA <2> latched in the third latch 280_3; also, when the fourth clock signal clk3_4 transitions from the low level to the high level, the first latch 280_1 sequentially outputs the fourth signal DATA <3> latched in the fourth latch 280_4 in units of bits.

Referring to fig. 1 and 12, the image sensor 100A includes a first semiconductor chip 310 and a second semiconductor chip 320, the first semiconductor chip 310 including the pixel array 110, and the second semiconductor chip 320 including the analog-to-digital converter 115. The pixel array 110 and the analog-to-digital converter 115 may be integrated in different semiconductor chips 310 and 320, respectively. In an example embodiment, the pixel array 110 and the analog-to-digital converter 115 may be integrated into one semiconductor chip.

Referring to fig. 1 to 13, the first comparator 130_1 generates a first comparison signal cds_dcs1 by comparing the RAMP signal RAMP with the first pixel signal PIX1 output from the first column line COL1 (S110).

The parallel gray code-to-serial binary code conversion circuit 210 latches the parallel input gray codes (G <0> to G <3 >) and outputs the parallel output gray codes (G <0> to G <3 >) in response to the comparison signal cds_dcs1 (S120).

The parallel gray code to serial binary code conversion circuit 210 includes a first group of switches SW1 to SW4 and SW1a to SW4a. In addition, the parallel gray code-to-serial binary code conversion circuit 210 converts the parallel output gray codes (G <0> to G <3 >) latched in the PIPO latches 221_1 to 221_4 into parallel binary codes (B <0> to B <3 >) and outputs LSBs (B <0 >) of the parallel binary codes (B <0> to B <3 >) simultaneously or substantially simultaneously, and sequentially outputs bits of the parallel binary codes (B <0> tob <3 >) to the serial binary adder 260 in units of bits from a next bit B <1> of the LSBs (B <0> to (B <3 >) of the parallel binary codes (B <0> tob <3 >) when changing the arrangement of the switches SW1 to SW4 and SW1a to SW4a of the first group.

Fig. 14 is a block diagram of an image processing apparatus including the image sensor shown in fig. 1. Referring to fig. 14, the image processing apparatus 400 includes a camera module 410, a processor 420, and a display apparatus 430.

The image processing apparatus 400 may be used in a mobile apparatus, a Closed Circuit Television (CCTV) system, a wearable computer, or a car infotainment system, but the example embodiments are not limited thereto.

The image sensor 100 of the camera module 410 captures an object by using the lens 412, generates an image signal corresponding to the captured object, and transmits the image signal to the image signal processor 414. The structure of the image sensor 100 may correspond to the structure of the image sensor 100A described with reference to fig. 12.

The image data processed by the image signal processor 414 may be transmitted to the processor 420, and the processor 420 may display an image corresponding to the processed image data through the display device 430.

The inventive concept has been described with reference to some exemplary embodiments shown in the drawings, but these are merely exemplary embodiments and it is understood that various modifications and other equivalent exemplary embodiments can be made by those skilled in the art from this point.

According to example embodiments of the inventive concepts, an analog-to-digital conversion circuit may convert parallel gray codes into parallel binary codes, and then may directly and sequentially output bits of the parallel binary codes from LSBs of the parallel binary codes to MSBs of the parallel binary codes to a serial binary adder in units of bits when an arrangement of switches is changed, thereby reducing noise at high-speed operation.

It is to be understood that elements and/or their properties described herein as "substantially" identical and/or identical include elements and/or their properties that have a relative difference in magnitude of equal to or less than 10%. Furthermore, whether or not the elements and/or their properties are modified to be "substantially," it is understood that such elements and/or their properties are to be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the elements and/or their properties.

One or more of the elements disclosed above may include or be implemented with the following: one or more processing circuits, such as hardware comprising logic circuits; a hardware/software combination such as a processor running software; or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and the like.

While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the scope of the inventive concept.

Claims

1. A gray code to binary code converter, the gray code to binary code converter comprising:

a plurality of PIPO latches, each of the plurality of PIPO latches configured to output parallel output gray codes by latching the parallel input gray codes in response to a sampling signal, the PIPO latches being incorporated into the merge output latches; and

PISO circuitry comprising a first set of switches, the PISO circuitry being a parallel-in-serial-out circuit, the PISO circuitry configured to:

converting the parallel output gray code latched in the plurality of PIPO latches into a binary code, and

when changing the arrangement of the first group of switches, bits of the binary code are sequentially output in units of bits from LSB of the binary code, which is the least significant bit, to MSB of the binary code, which is the most significant bit.

2. The gray code to binary code converter of claim 1, wherein the PISO circuit further comprises:

a plurality of exclusive-or gates connected in series, each of the plurality of exclusive-or gates comprising a first input and an output,

wherein the output of a current stage is connected to the first input of a next stage among the plurality of exclusive-or gates, and

Wherein the first set of switches connects the second input of the plurality of exclusive-or gates to the output of the plurality of PIPO latches or to ground in response to a switching signal of the first set of switches.

3. The gray code to binary code converter of claim 2, wherein

The sampling signal is a signal generated based on a comparison result of comparing the pixel signal output from the pixel and the ramp signal output from the ramp signal generator,

a first input of an MSB exclusive-or gate of the plurality of exclusive-or gates is configured to receive a control signal,

during a reset sampling interval for a reset signal included in the pixel signal output from the pixel, the control signal is maintained at a high level, and

the control signal is maintained at a low level during a signal sampling interval for a photosensitive signal included in the pixel signal output from the pixel.

4. A gray code to binary code converter according to claim 3, wherein

The next stage of LSB exclusive OR gate in the plurality of exclusive OR gates is a full adder, and

an output of the LSB exclusive or gate is connected to a first input of the full adder, the output of the LSB exclusive or gate being configured to output the bits of the binary code from the LSBs of the binary code to the MSBs of the binary code.

5. A CDS circuit, which is a correlated double sampling circuit, comprising:

a full adder, the full adder comprising a first input; and

a gray code to binary code converter configured to:

converting parallel input Gray code into binary code, and

when changing the arrangement of the first group of switches included in the gray code to binary code converter, bits of the binary code are sequentially output from LSB of the binary code, i.e., least significant bits, to MSB of the binary code, i.e., most significant bits, to the first input terminal of the full adder in units of bits.

6. The CDS circuit of claim 5, wherein the gray code to binary code converter comprises:

a plurality of PIPO latches, each of the plurality of PIPO latches configured to output parallel output gray codes by latching the parallel input gray codes in response to a sampling signal, the PIPO latches being merging in and out latches; and

PISO circuitry, i.e., a merge-string-out circuit, configured to:

converting the parallel output gray codes latched in the plurality of PIPO latches into the binary codes; and

The bits of the binary code are sequentially output from the LSB to the MSB to the first input of the full adder upon changing the arrangement of the first set of switches.

7. The CDS circuit of claim 6, wherein the PISO circuit further comprises:

a plurality of exclusive-or gates connected in series, each of the plurality of exclusive-or gates including a first input terminal and an output terminal, wherein, among the plurality of exclusive-or gates, the output terminal of a current stage is connected to the first input terminal of a next stage, and

8. The CDS circuit according to claim 7, wherein

9. The CDS circuit of claim 6, wherein said full adder comprises said first input terminal, a second input terminal for receiving an output signal of a reset memory circuit, a carry input terminal, a carry output terminal, and a summing terminal,

the CDS circuit further includes:

a first flip-flop configured to output an output signal of the summing terminal to the reset memory circuit; and

and a second flip-flop configured to send an output signal of the carry output terminal to the carry input terminal.

10. The CDS circuit of claim 9, wherein the reset memory circuit comprises:

a plurality of latches, each latch of the plurality of latches configured to latch the output signal of the first flip-flop;

a plurality of or gates connected in series, each of the plurality of or gates including a first input terminal and an output terminal, wherein in the plurality of or gates, the output terminal of a current stage is connected to the first input terminal of a next stage; and

A second set of switches configured to connect a second input of the plurality of OR gates to an output of the plurality of latches or to ground in response to a switching signal of the second set of switches,

wherein a second input of an MSB or gate of the plurality of OR gates is connected to the first input of the MSB or gate, and

wherein an output of an LSB or gate of the plurality of or gates is connected to the second input of the full adder.

11. The CDS circuit of claim 10, further comprising:

a plurality of string-in and string-out latches, each of the plurality of string-in and string-out latches being connected to an output of the first flip-flop.

12. An image sensor, the image sensor comprising:

a pixel array including a plurality of pixels, each of the plurality of pixels configured to generate a pixel signal by performing photoelectric conversion; and

an analog-to-digital converter configured to receive the pixel signal output from at least one of the plurality of pixels,

wherein the analog-to-digital converter comprises

A ramp signal generator configured to generate a ramp signal, a sampling circuit configured to generate a sampling signal by sampling the pixel signal output from the at least one pixel using the ramp signal, and

A gray code to binary code converter configured to:

receiving parallel input Gray codes generated by Gray code generators and converting the parallel input Gray codes into binary codes, and

when changing the arrangement of the first group of switches included in the gray code to binary code converter, bits of the binary code are sequentially output in units of bits from LSB, i.e., least significant bit, of the binary code to MSB, i.e., most significant bit, of the binary code.

13. The image sensor of claim 12, wherein the gray code to binary code converter comprises:

a plurality of PIPO latches, each of the plurality of PIPO latches configured to output a parallel output gray code by latching the parallel input gray code in response to the sampling signal, the PIPO latches being merging in and out latches; and

PISO circuitry, i.e., a merge-string-out circuit, configured to:

converting the parallel output gray code latched in the plurality of PIPO latches into the binary code, and

the bits of the binary code are sequentially output from the LSB to the MSB when the arrangement of the first set of switches is changed.

14. The image sensor of claim 13, wherein the PISO circuit further comprises:

15. The image sensor of claim 14, wherein

during a reset sampling interval for a reset signal included in the pixel signal, the control signal is maintained at a high level, and

the control signal is maintained at a low level during a signal sampling interval for a photosensitive signal included in the pixel signal.

16. The image sensor of claim 15, the image sensor further comprising:

a full adder including a first input connected to the output of the PISO circuit, a second input configured to receive an output signal of a reset memory circuit, a carry input, a carry output, and a summing terminal;

and a second flip-flop configured to output an output signal of the carry output terminal to the carry input terminal.

17. The image sensor of claim 16, wherein the reset memory circuit comprises:

a second set of switches configured to connect a second input of the plurality of OR gates to an output of the plurality of latches or the ground in response to a switching signal of the second set of switches,

18. The image sensor of claim 17, the image sensor further comprising:

19. The image sensor of claim 12, wherein

The pixel array is located on the first semiconductor chip and

the analog-to-digital converter is located on a second semiconductor chip different from the first semiconductor chip.

20. An image processing apparatus, the image processing apparatus comprising:

the image sensor of claim 12; and

a processor configured to control operation of the image sensor.