CN116599509A - Load switching circuit - Google Patents
Load switching circuit Download PDFInfo
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- CN116599509A CN116599509A CN202310672798.3A CN202310672798A CN116599509A CN 116599509 A CN116599509 A CN 116599509A CN 202310672798 A CN202310672798 A CN 202310672798A CN 116599509 A CN116599509 A CN 116599509A
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- 230000000630 rising effect Effects 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 13
- 238000001514 detection method Methods 0.000 claims description 12
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 abstract description 13
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 2
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 2
- 101150107557 SMT-1 gene Proteins 0.000 description 2
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 1
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000006243 chemical reaction Methods 0.000 description 1
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- 230000002035 prolonged effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The application discloses a load switch circuit, comprising: the clock and timing signal generating unit is connected with the enabling signal port and is used for generating multiple paths of non-overlapping clock signals and multiple paths of timing signals according to the input enabling signal; the first end of the power tube is connected with the power port, and the second end of the power tube is connected with the output port; the charge pump unit is connected with the clock and timing signal generating unit and the control end of the power tube and is used for generating a control signal for controlling the power tube according to the multi-path non-overlapping clock signals and the multi-path timing signals, and the conduction time of the power tube is controlled by controlling the rising time of the control signal. The load switch circuit can provide different soft start time to realize different system requirements so as to solve the problem of overlarge surge current of the optical module during hot plug; meanwhile, the load switch circuit has simple structure and low power consumption, and can be widely applied to various power supply systems.
Description
Technical Field
The application belongs to the technical field of integrated circuits, and particularly relates to a load switch circuit.
Background
As connectors and translators for implementing mutual conversion of optical signals and electrical signals, optical modules are widely used in various network architectures such as servers, switches, routers and wireless base station devices, and play an important role in the communication network market and the data center market.
The load switch is an important component in the optical module system, and the main function of the load switch is to connect/disconnect a load; when the optical module is hot plugged, an anti-surge design is needed to prevent equipment damage caused by overlarge surge current. The soft start function of the load switch can provide professional anti-surge protection for the optical module when current is accessed.
Accordingly, in view of the above-described problems, it is necessary to provide a load switching circuit.
Disclosure of Invention
In view of the above, the present application is directed to a load switch circuit to solve the problem of excessive surge current of an optical module during hot plugging.
In order to achieve the above object, an embodiment of the present application provides the following technical solution:
a load switching circuit, the load switching circuit comprising:
the clock and timing signal generating unit is connected with the enabling signal port and is used for generating multiple paths of non-overlapping clock signals and multiple paths of timing signals according to the input enabling signal;
the first end of the power tube is connected with the power port, and the second end of the power tube is connected with the output port;
the charge pump unit is connected with the clock and timing signal generating unit and the control end of the power tube and is used for generating a control signal for controlling the power tube according to the multi-path non-overlapping clock signals and the multi-path timing signals, and the conduction time of the power tube is controlled by controlling the rising time of the control signal.
In one embodiment, the clock and timing signal generating unit is configured to generate four non-overlapping clock signals and two timing signals according to an input enable signal.
In one embodiment, the charge pump unit includes a plurality of PMOS transistors, a plurality of NMOS transistors, a plurality of resistors, and a plurality of capacitors.
In an embodiment, the charge pump unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first resistor, a second resistor, and a capacitor, wherein:
the source electrode of the first PMOS tube is connected with the power supply port, the grid electrode of the first PMOS tube is connected with a first non-overlapping clock signal, and the drain electrode of the first PMOS tube is connected with the first node;
the drain electrode of the first NMOS tube is connected with a first node, the grid electrode of the first NMOS tube is connected with a second non-overlapping clock signal, and the source electrode of the first NMOS tube is connected with a ground port;
the drain electrode of the second NMOS tube is connected with a fourth node, the grid electrode of the second NMOS tube is connected with a third non-overlapping clock signal, and the source electrode of the second NMOS tube is connected with a ground port;
the drain electrode of the third NMOS tube outputs a control signal to the control end of the power tube, the grid electrode of the third NMOS tube is connected with a fourth non-overlapping clock signal, and the source electrode of the third NMOS tube is connected with a fourth node;
the source electrode of the second PMOS tube is connected with the first node, the grid electrode of the second PMOS tube is connected with the first timing signal, and the drain electrode of the second PMOS tube is connected with the second node;
the source electrode of the third PMOS tube is connected with the second node, the grid electrode of the third PMOS tube is connected with the second timing signal, and the drain electrode of the third PMOS tube is connected with the third node;
the first end of the first resistor is connected with the first node, the second end of the first resistor is connected with the second node, the first end of the second resistor is connected with the second node, the second end of the second resistor is connected with the third node, the first end of the capacitor is connected with the third node, and the second end of the capacitor is connected with the fourth node.
In an embodiment, the power tube is a PMOS tube, the first end is a source, the second end is a gate, and the control end is a gate.
In one embodiment, the clock and timing signal generation unit comprises:
the input end of the enabling circuit is connected with the enabling signal port and is used for setting the on threshold value and/or the off threshold value of the input enabling signal;
an oscillator circuit having a first input coupled to the output of the enable circuit for generating a first clock signal and a second clock signal;
a non-overlapping circuit, the input end of which is connected with the first output end of the oscillator circuit and is used for generating four paths of non-overlapping clock signals according to the first clock signal;
and the input end of the timer circuit is connected with the second output end of the oscillator circuit and is used for generating two paths of timing signals according to the second clock signal.
In an embodiment, the load switch circuit further includes a voltage detection circuit connected to the power port, the control end of the power tube, and the second input end of the oscillator circuit, and configured to detect a voltage difference between the power port and the control end of the power tube, and when the voltage difference is greater than or equal to a preset voltage threshold, output a control signal to turn off the oscillator circuit and the charge pump unit.
In one embodiment, the voltage detection circuit comprises a plurality of PMOS tubes, a plurality of resistors and a Schmitt trigger.
In an embodiment, the voltage detection circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a third resistor, a fourth resistor, and a schmitt trigger, wherein:
the drain electrode of the fourth PMOS tube is connected with the control end of the power tube, the grid electrode is in short circuit with the drain electrode, and the source electrode is connected with the sixth node;
the drain electrode of the fifth PMOS tube is connected with the sixth node, the grid electrode is in short circuit with the drain electrode, and the source electrode is connected with the fifth node;
the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube, the source electrode is connected with the power port, and the grid electrode is connected with the fifth node;
the grid electrode of the seventh PMOS tube is connected with the sixth node, and the drain electrode of the seventh PMOS tube is connected with the seventh node;
the first end of the third resistor is connected with the power port, the second end of the third resistor is connected with the fifth node, the first end of the fourth resistor is connected with the ground port, and the second end of the fourth resistor is connected with the seventh node;
the input end of the Schmitt trigger is connected with the seventh node, and the output end of the Schmitt trigger is connected with the second output end of the oscillator circuit.
The application has the following beneficial effects:
the load switch circuit can provide different soft start time to realize different system requirements so as to solve the problem of overlarge surge current of the optical module during hot plug; meanwhile, the load switch circuit has simple structure and low power consumption, and can be widely applied to various power supply systems.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a circuit diagram of a load switching circuit according to an embodiment of the application;
fig. 2 is a timing diagram illustrating the operation of the load switch circuit according to an embodiment of the present application.
Detailed Description
In order to make the technical solution of the present application better understood by those skilled in the art, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
The application discloses a load switch circuit, which comprises:
the clock and timing signal generating unit is connected with the enabling signal port and is used for generating multiple paths of non-overlapping clock signals and multiple paths of timing signals according to the input enabling signal;
the first end of the power tube is connected with the power port, and the second end of the power tube is connected with the output port;
the charge pump unit is connected with the clock and timing signal generating unit and the control end of the power tube and is used for generating a control signal for controlling the power tube according to the multi-path non-overlapping clock signals and the multi-path timing signals, and the conduction time of the power tube is controlled by controlling the rising time of the control signal.
The present application will be described in detail with reference to specific examples.
Referring to fig. 1, the ports of the present embodiment include an enable signal port ON, an output port OUT, a power supply port VIN, a ground port GND, and the load switching circuit includes:
the clock and timing signal generating unit is connected with the enabling signal port ON and is used for generating multiple paths of non-overlapping clock signals and multiple paths of timing signals according to the input enabling signal;
the power tube Q1, the first end of the power tube Q1 links with power port VIN, the second end links with output port OUT;
the charge pump unit (charge pump) is connected with the clock and timing signal generating unit and the control end of the power tube Q1, and is used for generating a control signal NG for controlling the power tube Q1 according to the multi-path non-overlapping clock signal and the multi-path timing signal, and the conduction time of the power tube Q1 is controlled by controlling the rising time of the control signal NG.
Illustratively, the clock and timing signal generating unit in the present embodiment is capable of generating four non-overlapping clock signals S1-S4 and two timing signals T1, T2.
Specifically, the clock and timing signal generation unit in the present embodiment includes:
an enable circuit (EN), the input end of which is connected with the enable signal port ON, and the output end of which is an ENO port and is used for setting the ON threshold value and/or the off threshold value of the input enable signal ON;
an oscillator circuit (OSC) having a first input terminal connected to an output terminal of the enable circuit for generating a first clock signal CLK1 and a second clock signal CLK2 inside the system;
a non-overlapping circuit (nonverlap) having an input coupled to the first output of the oscillator circuit for generating four non-overlapping clock signals S1-S4 based on the first clock signal CLK 1;
the Timer circuit (Timer) has an input terminal connected to the second output terminal of the oscillator circuit, and is configured to generate two timing signals T1 and T2 according to the second clock signal CLK2, and fig. 2 is a waveform diagram of the two timing signals T1 and T2 in the embodiment.
Each module in the clock and timing signal generating unit is a circuit in the prior art, and will not be described here again.
In this embodiment, the power transistor Q1 is a low-impedance PMOS transistor, a first end (source) thereof is connected to the power port VIN, a second end (drain) thereof is connected to the output port OUT, and a control end (gate) thereof is connected to the control signal NG. The starting time of the power tube directly determines the starting time of the optical module product, and meanwhile, the on-resistance R of the power tube DSON The power consumption of the system is directly determined, and the smaller the on-resistance of the power tube is, the better the on-resistance of the power tube is under the condition of area permission, and the magnitude of mΩ can be generally achieved.
The charge pump unit (charge pump) in this embodiment includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a first resistor R1, a second resistor R2, and a capacitor, wherein:
the source electrode of the first PMOS tube MP1 is connected with the power supply port VIN, the grid electrode is connected with the first non-overlapping clock signal S1, and the drain electrode is connected with the first node A;
the drain electrode of the first NMOS tube NM1 is connected with the first node A, the grid electrode is connected with the second non-overlapping clock signal S2, and the source electrode is connected with the ground port GND;
the drain electrode of the second NMOS tube NM2 is connected with the fourth node D, the grid electrode is connected with a third non-overlapping clock signal S3, and the source electrode is connected with the ground port GND;
the drain electrode of the third NMOS tube NM3 outputs a control signal to the control end of the power tube Q1, the grid electrode is connected with a fourth non-overlapping clock signal S4, and the source electrode is connected with a fourth node D;
the source electrode of the second PMOS tube MP2 is connected with the first node A, the grid electrode is connected with the first timing signal T1, and the drain electrode is connected with the second node B;
the source electrode of the third PMOS tube MP3 is connected with the second node B, the grid electrode is connected with the second timing signal T2, and the drain electrode is connected with the third node C;
the first end of the first resistor R1 is connected with the first node A, the second end of the first resistor R1 is connected with the second node B, the first end of the second resistor R2 is connected with the second node B, the second end of the second resistor R2 is connected with the third node C, the first end of the capacitor is connected with the third node C, and the second end of the capacitor is connected with the fourth node D.
In this embodiment, the charge pump unit (charge pump) is a negative-pressure charge pump circuit, and is mainly used for generating a control signal NG for controlling the gate voltage of the power tube Q1, and the rising time of the control signal NG directly determines the on time of the power tube Q1, so as to determine the magnitude of the surge current of the optical module during hot plugging.
The basic working principle of the charge pump unit is as follows:
firstly, under the condition that MP2 and MP3 are both conducted, at the moment, R1 and R2 are short-circuited, the potential of the point A is equal to the potential of the point C, and under the control of non-overlapping clock signals, MP1 and MN2 are conducted in the charging process, MN1 and MN3 are cut off, at the moment, the power supply voltage VIN directly charges the capacitor C1, the voltage of the point C is equal to VIN, and the voltage of the point D is equal to GND; in the discharging process, MP1 and MN2 are cut off, MN1 and MN3 are conducted, the potential at point C is equal to GND, the voltage at point D is equal to-VIN based on the principle that the voltages at two ends of a capacitor cannot be suddenly changed, the voltage is transmitted to NG through MN3, the NG voltage is-VIN, the NG voltage is finally stabilized at-VIN under the control of a clock, and the voltage can ensure that the power tube Q1 is fully conducted.
In addition, in the initial power-up process, under the control of the timing signals T1 and T2, MP2 and MP3 are turned on after waiting for a period of time, i.e. R1 and R2 will be shorted after waiting for a period of time, because of the existence of R1 and R2, the NG voltage starting time is prolonged, different NG signal starting times can be obtained by adjusting the resistance values of R1 and R2 or the turning time of T1 and T2, and finally the requirements of different systems of the optical module product on different soft starting times can be met, and referring to fig. 2, a waveform diagram corresponding to the timing signals T1 and T2 and the output signal OUT is shown.
Preferably, the load switch circuit in this embodiment further includes a voltage detection circuit (ng_sense), connected to the power supply port VIN, the control terminal of the power tube Q1, and the second input terminal of the oscillator circuit, for detecting a voltage difference (VIN-NG) between the power supply port VIN and the control terminal of the power tube Q1, and outputting a control signal to turn off the oscillator circuit and the charge pump unit when the voltage difference (VIN-NG) is greater than or equal to a preset voltage threshold.
Specifically, the voltage detection circuit includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a third resistor R3, a fourth resistor R4, and a schmitt trigger SMT1, wherein:
the drain electrode of the fourth PMOS tube MP4 is connected with the control end of the power tube Q1, the grid electrode is in short circuit with the drain electrode, and the source electrode is connected with the sixth node F;
the drain electrode of the fifth PMOS tube MP5 is connected with the sixth node F, the grid electrode is in short circuit with the drain electrode, and the source electrode is connected with the fifth node E;
the drain electrode of the sixth PMOS tube MP6 is connected with the source electrode of the seventh PMOS tube MP7, the source electrode is connected with the power supply port VIN, and the grid electrode is connected with the fifth node E;
the grid electrode of the seventh PMOS tube MP7 is connected with the sixth node F, and the drain electrode is connected with the seventh node G;
the first end of the third resistor R3 is connected with the power supply port VIN, the second end of the third resistor R3 is connected with the fifth node E, the first end of the fourth resistor R4 is connected with the ground port GND, and the second end of the fourth resistor R4 is connected with the seventh node G;
the input of the schmitt trigger SMT1 is connected to the seventh node G and the output is connected to the second output of the oscillator circuit.
The voltage detection circuit (ng_sense) is mainly used for detecting the voltage difference between VIN and NG, by reasonably setting the device size, when the voltage difference (VIN-NG) is greater than or equal to a preset voltage threshold, the output SENSE signal is turned over to turn off the oscillator circuit (OSC), thereby turning off the charge pump unit (charge pump), and finally, the voltage difference (VIN-NG) can be maintained at a set maximum voltage value, and in this embodiment, the waveform diagram of VIN-NG is shown in fig. 2.
The voltage detection circuit can ensure that when the input voltage VIN is higher, the gate-source voltage of the power tube Q1 does not exceed the breakdown voltage value, and meanwhile, the oscillator circuit and the charge pump unit are turned off, so that the overall power consumption of the load switch is greatly reduced.
It should be understood that the voltage detection circuit is not an essential circuit of the present application, and in other embodiments, the voltage detection circuit may not be provided, and the problem of excessive surge current during hot plugging of the optical module may be solved.
As can be seen from the technical scheme, the application has the following advantages:
the load switch circuit can provide different soft start time to realize different system requirements so as to solve the problem of overlarge surge current of the optical module during hot plug; meanwhile, the load switch circuit has simple structure and low power consumption, and can be widely applied to various power supply systems.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (9)
1. A load switching circuit, the load switching circuit comprising:
the clock and timing signal generating unit is connected with the enabling signal port and is used for generating multiple paths of non-overlapping clock signals and multiple paths of timing signals according to the input enabling signal;
the first end of the power tube is connected with the power port, and the second end of the power tube is connected with the output port;
the charge pump unit is connected with the clock and timing signal generating unit and the control end of the power tube and is used for generating a control signal for controlling the power tube according to the multi-path non-overlapping clock signals and the multi-path timing signals, and the conduction time of the power tube is controlled by controlling the rising time of the control signal.
2. The load switch circuit of claim 1, wherein the clock and timing signal generation unit is configured to generate four non-overlapping clock signals and two timing signals according to an input enable signal.
3. The load switching circuit of claim 1, wherein the charge pump unit comprises a plurality of PMOS transistors, a plurality of NMOS transistors, a plurality of resistors, and a plurality of capacitors.
4. The load switch circuit of claim 2, wherein the charge pump unit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first resistor, a second resistor, and a capacitor, wherein:
the source electrode of the first PMOS tube is connected with the power supply port, the grid electrode of the first PMOS tube is connected with a first non-overlapping clock signal, and the drain electrode of the first PMOS tube is connected with the first node;
the drain electrode of the first NMOS tube is connected with a first node, the grid electrode of the first NMOS tube is connected with a second non-overlapping clock signal, and the source electrode of the first NMOS tube is connected with a ground port;
the drain electrode of the second NMOS tube is connected with a fourth node, the grid electrode of the second NMOS tube is connected with a third non-overlapping clock signal, and the source electrode of the second NMOS tube is connected with a ground port;
the drain electrode of the third NMOS tube outputs a control signal to the control end of the power tube, the grid electrode of the third NMOS tube is connected with a fourth non-overlapping clock signal, and the source electrode of the third NMOS tube is connected with a fourth node;
the source electrode of the second PMOS tube is connected with the first node, the grid electrode of the second PMOS tube is connected with the first timing signal, and the drain electrode of the second PMOS tube is connected with the second node;
the source electrode of the third PMOS tube is connected with the second node, the grid electrode of the third PMOS tube is connected with the second timing signal, and the drain electrode of the third PMOS tube is connected with the third node;
the first end of the first resistor is connected with the first node, the second end of the first resistor is connected with the second node, the first end of the second resistor is connected with the second node, the second end of the second resistor is connected with the third node, the first end of the capacitor is connected with the third node, and the second end of the capacitor is connected with the fourth node.
5. The load switching circuit of claim 1, wherein the power tube is a PMOS tube, the first terminal is a source, the second terminal is a gate, and the control terminal is a gate.
6. The load switching circuit according to claim 2, wherein the clock and timing signal generating unit includes:
the input end of the enabling circuit is connected with the enabling signal port and is used for setting the on threshold value and/or the off threshold value of the input enabling signal;
an oscillator circuit having a first input coupled to the output of the enable circuit for generating a first clock signal and a second clock signal;
a non-overlapping circuit, the input end of which is connected with the first output end of the oscillator circuit and is used for generating four paths of non-overlapping clock signals according to the first clock signal;
and the input end of the timer circuit is connected with the second output end of the oscillator circuit and is used for generating two paths of timing signals according to the second clock signal.
7. The load switch circuit of claim 6, further comprising a voltage detection circuit coupled to the power port, the control terminal of the power tube, and the second input terminal of the oscillator circuit for detecting a voltage difference between the power port and the control terminal of the power tube, and outputting a control signal to turn off the oscillator circuit and the charge pump unit when the voltage difference is greater than or equal to a predetermined voltage threshold.
8. The load switching circuit of claim 7, wherein the voltage detection circuit comprises a plurality of PMOS transistors, a plurality of resistors, and a schmitt trigger.
9. The load switching circuit of claim 7, wherein the voltage detection circuit comprises a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a third resistor, a fourth resistor, and a schmitt trigger, wherein:
the drain electrode of the fourth PMOS tube is connected with the control end of the power tube, the grid electrode is in short circuit with the drain electrode, and the source electrode is connected with the sixth node;
the drain electrode of the fifth PMOS tube is connected with the sixth node, the grid electrode is in short circuit with the drain electrode, and the source electrode is connected with the fifth node;
the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube, the source electrode is connected with the power port, and the grid electrode is connected with the fifth node;
the grid electrode of the seventh PMOS tube is connected with the sixth node, and the drain electrode of the seventh PMOS tube is connected with the seventh node;
the first end of the third resistor is connected with the power port, the second end of the third resistor is connected with the fifth node, the first end of the fourth resistor is connected with the ground port, and the second end of the fourth resistor is connected with the seventh node;
the input end of the Schmitt trigger is connected with the seventh node, and the output end of the Schmitt trigger is connected with the second output end of the oscillator circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310672798.3A CN116599509A (en) | 2023-06-07 | 2023-06-07 | Load switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310672798.3A CN116599509A (en) | 2023-06-07 | 2023-06-07 | Load switching circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116599509A true CN116599509A (en) | 2023-08-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310672798.3A Pending CN116599509A (en) | 2023-06-07 | 2023-06-07 | Load switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116599509A (en) |
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2023
- 2023-06-07 CN CN202310672798.3A patent/CN116599509A/en active Pending
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