CN116598362A - Bottom U-shaped gate-around gate transistor device, manufacturing method, equipment and manufacturing method - Google Patents
Bottom U-shaped gate-around gate transistor device, manufacturing method, equipment and manufacturing method Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention provides a bottom U-shaped gate surrounding gate transistor device, which comprises a substrate, a first source region, a first drain region, a first control gate and a first channel layer, wherein the first source region is formed on the substrate; the first source region and the first drain region are doped with first ions; the first channel layer characterizes the channel layer closest to the substrate; the first control gate characterizes the control gate closest to the substrate; the second source region is formed between the substrate and the first source region, the second drain region is formed between the substrate and the first drain region, and the type of the first ions is different from the type of the second ions; wherein the thickness of the first control gate channel layer along the second direction is higher than the thickness of other control gates along the second direction; the first faces of the second source region and the second drain region are not higher than the bottom face of the first channel layer along the second direction, and the second faces are not lower than the surface of the substrate between the first source region and the second drain region. The technical scheme solves the problem of direct tunneling of source and drain in the surrounding gate transistor device while preventing the leakage of the bottom parasitic channel.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a bottom U-shaped gate surrounding gate transistor device, a manufacturing method, equipment and a manufacturing method.
Background
Compared to FinFET, a wrap Gate (GAA) stacked nano-chip field effect transistor (NSFET) is widely used in terms of integrated technology development and power performance improvement due to its superior electrostatic performance and higher layout efficiency. Device power consumption remains one of the important challenges in device size scaling. One approach to reducing power consumption of a wrap-gate device is to reduce parasitic channel leakage at the bottom. Unlike finfets, GAA nanoplates have a wider tri-gate bottom channel, which means weaker gate control and bottom leakage issues. How to inhibit the direct tunneling of off-state leakage current and source and drain becomes one of the key challenges of the optimization of the surrounding gate device. Currently, bottom leakage current is mainly suppressed by means of anti-punch-through ion implantation (PTS) or Bottom Dielectric Isolation (BDI). However, as devices continue to shrink, the process difficulty of the PTS scheme continues to increase and is very sensitive to process fluctuations. The BDI scheme uses a dielectric to block the bottom parasitic leakage channel, but the introduction of a dielectric layer also brings greater challenges for subsequent processes.
Therefore, the novel gate-surrounding gate transistor structure is provided, so that the suppression effect of leakage current can be enhanced, and meanwhile, the direct tunneling of the source and the drain of the bottom tunneling transistor can be effectively prevented, and the novel gate-surrounding gate transistor structure becomes a technical key point to be solved by the person skilled in the art.
Disclosure of Invention
The invention provides a bottom U-shaped gate surrounding gate transistor device, a manufacturing method, equipment and a manufacturing method, which are used for solving the problem of direct tunneling of source and drain in a mixed conduction mechanism surrounding gate transistor while preventing bottom parasitic channel leakage.
According to a first aspect of the present invention there is provided a bottom U-gate wrap gate transistor device comprising:
the gate-all MOSFET device comprises a substrate, a first source region, a first drain region, a first control gate and a channel layer; the first source region and the first drain region are arranged along a first direction; wherein first ions are doped in the first source region and the first drain region; wherein the first direction characterizes a direction parallel to a surface of the substrate; the channel layer includes a first channel layer; the first channel layer characterizes a channel layer closest to the substrate; the first control gate characterizes the control gate closest to the substrate;
A second source region and a second drain region, the second source region being formed between the substrate and the first source region, the second drain region being formed between the substrate and the first drain region; wherein, the second drain region is doped with first ions, the second source region is doped with second ions, and the type of the first ions is different from the type of the second ions;
wherein the thickness of the first control gate along the second direction is greater than the thickness of the other control gates along the second direction; the heights of the first surfaces of the second source region and the second drain region along the second direction are not higher than the bottom surface of the first channel layer; the second source region and the second drain region have a second face with a height in the second direction not lower than the surface of the substrate therebetween; the second direction is perpendicular to the first direction.
Optionally, the channel length of the bottom U-shaped gate surrounding gate transistor device is 5nm-100nm.
Optionally, the thickness of the first control gate along the second direction is: 5nm-200nm.
Optionally, the thickness of the second source region and/or the second drain region along the second direction is 5nm-50nm.
Optionally, the boom MOSFET device further includes:
the gate dielectric layer wraps part of the surface of the channel layer and covers the surface of the substrate between the second source region and the second drain region; the channel layer is formed between the first source region and the first drain region and is arranged at intervals along the direction away from the substrate; the control gate covers the surface of the gate dielectric layer; wherein the control gate comprises the first control gate; when the control gate covers the surface of the gate dielectric layer, the first control gate covers the surface of the gate dielectric layer on the surface of the substrate at the same time;
the inner side wall is formed between the first source region and the gate dielectric layer and on the surface of the channel layer between the first drain region and the gate dielectric layer;
a source metal layer, a gate metal layer and a drain metal layer; the source electrode metal layer and the drain electrode metal layer are respectively formed on the surfaces of the first source region and the first drain region, and respectively fully wrap the first source region and the second source region and the first drain region and the second drain region; the grid metal layer is formed on the top end of the control grid;
An interlayer dielectric layer covering the source metal layer, the gate metal layer, the drain metal layer and the surface of the inner side wall;
and the metal contact layers penetrate through the interlayer dielectric layer and are respectively connected with the source electrode metal layer, the gate electrode metal layer and the drain electrode metal layer.
According to a second aspect of the present invention, there is provided a method of fabricating a bottom U-gate wrap gate transistor device for fabricating a bottom U-gate wrap gate transistor device according to any of the first aspect of the present invention, comprising:
forming the surrounding gate MOSFET device, the second source region and the second drain region; wherein, the fence MOSFET device includes: the substrate, the first source region, the first drain region, the first control gate and the channel layer; the channel layer includes a first channel layer; the first channel layer characterizes a channel layer closest to the substrate; the first control gate characterizes the control gate closest to the substrate; wherein the first source region and the first drain region are doped with the first ions; the second source region and the second drain region are respectively formed between the substrate and the first source region and between the substrate and the first drain region, wherein the first ions are doped in the second drain region, and the second ions are doped in the second source region;
Wherein the thickness of the first control gate along the second direction is greater than the thickness of the other control gates along the second direction; the heights of the first surfaces of the second source region and the second drain region along the second direction are not higher than the bottom surface of the first channel layer; the second source region and the second drain region have a second face with a height in the second direction not lower than a surface of the substrate therebetween.
Optionally, forming the surrounding gate MOSFET device, the second source region, and the second drain region specifically includes:
providing the substrate;
forming a sacrificial layer and the channel layer; the sacrificial layer and the channel layer are stacked on the substrate at intervals; wherein the thickness of the first sacrificial layer is greater than the thickness of the other sacrificial layers; the first sacrificial layer characterizes the sacrificial layer closest to the substrate;
etching the sacrificial layer and the channel layer to form a fin structure;
forming a dummy gate structure, and etching two ends of the sacrificial layer along the first direction to form an inner side wall cavity;
forming the inner side wall; the inner side wall is formed in the inner side wall cavity;
forming the second source region and the second drain region; the second source region and the second drain region are respectively formed on two sides of the fin structure along the first direction;
Forming the first source region and the first drain region; the first source region and the first drain region are respectively formed at the top ends of the second source region and the second drain region;
removing the dummy gate structure and releasing the channel layer;
and forming the gate dielectric layer, the control gate, the source metal layer, the gate metal layer, the drain metal layer, the interlayer dielectric layer and the metal contact layer.
Optionally, the thickness of the first sacrificial layer is 5-200nm, and the thicknesses of the other sacrificial layers are as follows: 5-50nm.
Optionally, when etching the sacrificial layer and the channel layer to form a fin structure, and the substrate on two sides of the fin structure along the first direction is etched, before forming the second source region and the second drain region, the method further includes:
forming a first epitaxial layer; the first epitaxial layer is formed on two sides of the fin structure along the first direction; the height of the first epitaxial layer along the second direction is not lower than the height of the substrate between the second source region and the second drain region;
the second source region and the second drain region are respectively formed on the surface of the first epitaxial layer.
Optionally, when etching the sacrificial layer and the channel layer to form a fin structure, controlling the thickness of the etched substrate to be: 5nm-100nm.
According to a third aspect of the present invention there is provided an electronic device comprising a bottom U-gate wrap gate transistor device according to any of the first aspects of the present invention.
According to a fourth aspect of the present invention, there is provided a method of manufacturing an electronic device, comprising a method of manufacturing a bottom U-gate wrap gate transistor device according to any of the second aspect of the present invention.
The invention provides a bottom U-shaped gate surrounding gate transistor device, which designs the thickness of a bottom control gate (namely a first control gate) along a second direction as follows: higher than the thickness of other control gates along the second direction; the first surfaces of the second source region and the second drain region are not higher than the bottom surface of the first channel layer along the second direction; the height of the second face of the second source region and the second drain region along the second direction is not lower than the surface of the substrate between the second face and the second drain region; the second direction is perpendicular to the first direction; such that: and in the off state, the second source region, the bottom substrate and the second drain region at the bottom form a P-i-N structure, the off-state leakage current of the TFET channel at the bottom is reverse bias P-i-N current, the parasitic channel leakage at the bottom of the traditional surrounding gate device can be obviously restrained, and the current switching ratio of the device is increased. More important is: in a conventional surrounding gate transistor with extremely small size, the bottom TFET channel may have a source-drain direct tunneling condition, and the design of the U-shaped gate (i.e., the first control gate) can increase the effective channel length to prevent the source-drain direct tunneling. Therefore, according to the technical scheme provided by the invention, the thickness of the first control gate along the second direction is designed as follows while the bottom parasitic channel leakage is prevented: higher than the thickness of other control gates along the second direction; the problem of direct tunneling of source and drain in the mixed conduction mechanism surrounding gate transistor is solved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a schematic view of a device structure fabricated according to a fabrication method of a bottom U-gate wrap gate transistor device according to an embodiment of the present invention;
fig. 2 is a schematic view of a device structure fabricated according to a fabrication method of a bottom U-gate wrap gate transistor device according to another embodiment of the present invention;
fig. 3 is a schematic flow chart of a method for manufacturing a bottom U-gate wrap gate transistor device according to an embodiment of the present invention;
fig. 4 is a schematic view of a device structure at different process stages according to a method for manufacturing a bottom U-gate wrap-gate transistor device according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a second device structure at different process stages according to a method for manufacturing a bottom U-gate wrap-gate transistor device according to an embodiment of the present invention;
Fig. 6 is a schematic diagram of a device structure at different process stages according to a method for manufacturing a bottom U-gate wrap-gate transistor device according to an embodiment of the present invention;
fig. 7 is a schematic view of a device structure at different process stages according to a method for fabricating a bottom U-gate wrap-gate transistor device according to another embodiment of the present invention;
fig. 8 is a schematic diagram of a second device structure at different process stages according to a method for manufacturing a bottom U-gate wrap-gate transistor device according to another embodiment of the present invention;
fig. 9 is a schematic diagram of a device structure at different process stages according to a method for fabricating a bottom U-gate wrap-gate transistor device according to another embodiment of the present invention;
101-a substrate;
102-sacrificial layer
103-a channel layer;
104-an inner side wall;
105-dummy gate structure;
106-a first epitaxial layer;
107-a second source region;
108-a second drain region;
109-a first source region;
110-a first drain region;
111-source metal layer;
112-a drain metal layer;
113-gate metal layer;
114-an interlayer dielectric layer;
115-metal interconnect layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
How to suppress off-state leakage current in a gate-around (GAA) stacked nano-chip field effect transistor (NSFET), and under very small dimensions, source-drain direct tunneling of the bottom TFET may occur, becomes one of the key challenges for gate-around device optimization.
In view of this, the inventors of the present application devised a bottom U-gate wrap gate transistor device having a structure that not only adds an asymmetrically doped bottom source-drain region at the location of the original source-drain over-etch region, but also has a doping type opposite to that of the source region, and a doping type of the bottom drain region is the same as that of the drain region, wherein the bottom substrate is intrinsic silicon to form a tunneling field effect transistor of p-i-n structure in the bottom channel for suppressing bottom leakage current. Meanwhile, in the surrounding gate transistor device provided by the application, the bottom U-shaped gate is arranged between the bottom source region and the bottom drain region, so that the effective channel length is increased, and direct tunneling of the source and the drain can be further prevented.
Therefore, in the technical scheme provided by the application, when in the off state, the off-state leakage current of the bottom TFET channel is reverse bias P-i-N current, so that the bottom parasitic channel leakage problem of the traditional surrounding gate device can be obviously restrained, and the current switching ratio of the device is increased.
Under the extremely small size, the bottom TFET may have the source-drain direct tunneling condition, and the effective channel length can be increased by adopting the design of the U-shaped gate, so that the source-drain direct tunneling is prevented.
The technical scheme of the application is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Referring to fig. 1-9, according to one embodiment of the present application, there is provided a bottom U-gate wrap gate transistor device, comprising:
a boom MOSFET device comprising: a substrate 101, a first source region 109, a first drain region 110, a first control gate, and a channel layer 103; the first source region 109 and the first drain region 110 are arranged along a first direction; wherein first ions are doped in the first source region 109 and the first drain region 110; wherein the first direction characterizes a direction parallel to a surface of the substrate 101; the channel layer 103 includes a first channel layer 103; the first channel layer 103 characterizes the channel layer 103 closest to the substrate 101; the first control gate characterizes the control gate closest to the substrate 101;
A second source region 107 and a second drain region 108, the second source region 107 being formed between the substrate 101 and the first source region 109, the second drain region 108 being formed between the substrate 101 and the first drain region 110; wherein, the second drain region 108 is doped with a first ion, the second source region 107 is doped with a second ion, and the type of the first ion is different from the type of the second ion;
wherein the thickness of the first control gate channel layer 103 along the second direction is greater than the thickness of the other channel layer 103 control gates along the second direction; a height of a first face of the second source region 107 and the second drain region 108 in the second direction is not higher than a bottom face of the first channel layer 103, and a height of a second face of the second source region 107 and the second drain region 108 in the second direction is not lower than a surface of the substrate 101 therebetween; the second direction is perpendicular to the first direction, and the bottom U-shaped gate wrap gate transistor device is as shown in fig. 1 or fig. 2.
The first direction refers to the horizontal direction on the paper surface, and the second direction refers to the vertical direction on the paper surface. The first faces of the second source region 107 and the second drain region 108 refer to: one side of the second source region 107 and the second drain region 108 away from the substrate 101; the second faces of the second source region 107 and the second drain region 108 refer to: the second source region 107 and the second drain region 108 directly contact one side of the substrate 101.
On the other hand, if the second surfaces of the second source region 107 and the second drain region 108 are lower than the surface of the substrate 101 therebetween along the second direction, the length of the bottom effective channel (shown by the dashed path in fig. 1 or 2) becomes shorter, and the direct tunneling of the source and drain cannot be prevented in the case of the minimum size;
on the other hand, if the first surfaces of the second source region 107 and the second drain region 108 are higher than the bottom surface of the first channel layer 103 along the second direction, the bottom second source region 107 and the second drain region 108 may affect the upper channel layer 103, resulting in a decrease in on-state current of the device.
The first direction refers to the horizontal direction on the paper surface, and the vertical direction refers to the vertical direction on the paper surface. The first faces of the second source region 107 and the second drain region 108 refer to: one side of the second source region 107 and the second drain region 108 away from the substrate 101; the second faces of the second source region 107 and the second drain region 108 refer to: directly contacting one side of the substrate 101.
The invention provides a bottom U-shaped gate surrounding gate transistor device, wherein the thickness of a bottom control gate (namely a first control gate) in a mixed conduction mechanism surrounding gate transistor along a second direction is designed as follows: higher than the thickness of other control gates along the second direction; and the second source region 107 and the second drain region 108 are not higher than the bottom surface of the first channel layer 103 in the height in the second direction on the side away from the substrate 101; the second source region 107 and the second drain region 108 have a height in the second direction not lower than the surface of the substrate 101 therebetween on the side close to the substrate 101. In the off state, the bottom second source region 107, the bottom substrate 101 and the second drain region 108 form a P-i-N structure, so that the off-state leakage current of the bottom TFET channel is reverse bias P-i-N current, the bottom parasitic channel leakage problem of the conventional surrounding gate device can be obviously suppressed, and the current switching ratio of the device is increased. More important is: in a conventional mixed turn-on mechanism surrounding gate transistor with a very small size, the bottom TFET channel may have a source-drain direct tunneling condition, and the design of the U-shaped gate (i.e., the first control gate) may increase the effective channel length (the increased channel length is shown as a dotted line box in fig. 1 or fig. 2) to prevent the source-drain direct tunneling.
Therefore, according to the technical scheme provided by the invention, the thickness of the bottom control gate (namely the first control gate) in the conventional mixed conduction mechanism surrounding gate transistor along the second direction is designed as follows: higher than the thickness of other control gates along the second direction; the problem of direct tunneling of source and drain in the mixed conduction mechanism surrounding gate transistor is solved.
The mixed conduction mechanism surrounding gate transistor refers to: a gate-all-around transistor formed after the second source region 107 and the second drain region 108 are added; the transistor forms a reverse bias P-I-N channel at the bottom, and the structure can obviously inhibit the leakage current of the bottom parasitic channel of the traditional surrounding grid MOSFET device, thereby enhancing the current switching ratio of the device. Further, due to the fact that the second source region 107 and the second drain region 108 are additionally arranged, the bottom of the traditional surrounding gate MOSFET device is equivalent to the bottom of the traditional surrounding gate MOSFET device, and the tunneling field effect transistor TFET device structure is connected in parallel, mixed conduction of surrounding gate channel diffusion drift current and bottom channel quantum mechanical band tunneling current can be achieved, and therefore ultra-steep switching characteristics lower than 60mV/dec are achieved. Meanwhile, the surrounding grid MOSFET devices connected in parallel above are conducted, and high current can be provided for the devices.
The technical proposal provided by the invention aims at increasing the effective channel length by arranging the first control gate, thereby preventing the direct tunneling condition of source and drain in the bottom TFET channel from happening in the conventional mixed conduction mechanism surrounding gate transistor under the extremely small size,
In one embodiment, the channel length of the bottom U-shaped gate wrap gate transistor device is 5nm-100nm.
Regarding the absolute thickness of the first control gate, if the thickness of the first control gate is too thin, the device has poor inhibition effect on direct tunneling of the source and the drain, so that leakage current is increased, and meanwhile, the process difficulty in preparing the bottom source and drain region is increased; if the thickness of the first control gate is too thick, the bottom parasitic capacitance increases, and the frequency characteristics of the device deteriorate. Thus, in a preferred embodiment, the thickness of the first control gate in the second direction is: 5nm-200nm.
In one embodiment, the first ion is a P-type ion or an N-type ion.
In one embodiment, the second ion is a P-type ion or an N-type ion.
Specifically, the P-type ions are: the hydride, fluoride or chloride of boron is one or a combination of the following materials: B2H6, B4H10, B6H10, B10H14, B18H22, BF3 or BCl3; the N-type ions are as follows: the hydride and fluoride of phosphorus and arsenic are one or a combination of the following materials: phosphane, arsine, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride or arsenic trifluoride.
The channel region and the bottom Fin region (i.e., substrate 101) are undoped or lightly doped i regions;
Wherein, for N-type devices, the first source region 109 is N-type doped with a doping concentration of about 1E18cm-3 to about 1E22cm-3, and the first drain region 110 is N-type doped with a doping concentration of about
1E18cm-3-1E22cm-3, the second source region 107 is P-type doped with a doping concentration of about 1E18cm-3-1E22cm-3, and the second drain region 108 is N-type doped with a doping concentration of about 1E16cm-3-1E21cm-3;
for P-type devices, the first source region 109 is P-type doped with a doping concentration of about 1E18cm-3 to about 1E22cm-3, the first drain region 110 is P-type doped with a doping concentration of about 1E18cm-3 to about 1E20cm-3, the second source region 107 is N-type doped with a doping concentration of about 1E18cm-3 to about 1E22cm-3, and the second drain region 108 is P-type doped with a doping concentration of about 1E16cm-3 to about 1E21cm-3.
In the bottom U-shaped gate wrap gate transistor device, the thickness of the second source region 107 and the second drain region 108, as well as their doping concentration, are important parameters for device design. The thickness of the second source region 107 or the second drain region 108 is too thin, so that the influence of the bottom tunneling field effect transistor on the total current is small, and the subthreshold swing characteristic of the device is limited; too thick a second source region 107 or second drain region 108 may increase process difficulty, resulting in reduced device uniformity and reliability. The doping concentration of the second source region 107 cannot be too low, which can lead to an increase in the resistance of the second source region 107, and the lower doping reduces the tunneling probability of the bottom tunneling transistor, so that band tunneling is more difficult to occur, and the current is reduced. The doping concentration of the second drain region 108 needs to be controlled within a certain range, and the doping concentration is too low, so that the resistance of the bottom drain region is increased, and the current is reduced; too high doping concentration results in more significant channel bipolar effect of the TFET device. Thus: in a preferred embodiment, the thickness of the second source region 107 and/or the second drain region 108 is 5nm-50nm. In a preferred embodiment, the concentration of doped ions in the second source region 107 and/or the second drain region 108 is 1E16cm-3 to 1E22cm-3.
In one embodiment, the material of the second source region 107 and the material of the second drain region 108 are: binary or ternary compounds of groups II-VI, III-V or IV-IV.
In one embodiment, the material of the second source region 107 and the material of the second drain region 108 are Si, siGe or Ge.
In one embodiment, the wrap gate MOSFET device further comprises:
a gate dielectric layer and a control gate, wherein the gate dielectric layer wraps part of the surface of the channel layer 103 and covers the surface of the substrate 101 between the second source region 107 and the second drain region 108; wherein the channel layer 103 is formed between the first source region 109 and the first drain region 110, and is arranged at intervals in a direction away from the substrate 101; the control gate covers the surface of the gate dielectric layer; wherein the control gate comprises the first control gate; when the control gate covers the surface of the gate dielectric layer, the first control gate simultaneously covers the surface of the gate dielectric layer on the surface of the substrate 101;
an inner sidewall 104 formed between the first source region 109 and the gate dielectric layer, and between the first drain region 110 and the gate dielectric layer on the surface of the channel layer 103;
A source metal layer 111, a gate metal layer 113 and a drain metal layer 112; the source metal layer 111 and the drain metal layer 112 are respectively formed on the surfaces of the first source region 109 and the first drain region 110, and respectively entirely encapsulate the first source region 109 and the second source region 107 and the first drain region 110 and the second drain region 108; the gate metal layer 113 is formed on top of the control gate;
an interlayer dielectric layer 114 covering the source metal layer 111, the gate metal layer 113, the drain metal layer 112 and the surface of the inner sidewall 104;
the metal contact layers 115 penetrate through the interlayer dielectric layer 114 and are respectively connected with the source metal layer 111, the gate metal layer 113 and the drain metal layer 112.
According to an embodiment of the present invention, there is also provided a method for manufacturing a bottom U-gate wrap gate transistor device, for manufacturing a bottom U-gate wrap gate transistor device according to any of the preceding embodiments of the present invention, the method comprising:
s11: forming the wrap-gate MOSFET device, the second source region 107, and the second drain region 108; wherein, the fence MOSFET device includes: the substrate 101, the first source region 109, the first drain region 110, the first control gate and the channel layer 103; the channel layer 103 includes a first channel layer 103; the first channel layer 103 characterizes the channel layer 103 closest to the substrate 101; the first control gate characterizes the control gate closest to the substrate 101; wherein the first source region 109 and the first drain region 110 are doped with the first ions; the second source region 107 and the second drain region 108 are respectively formed between the substrate 101 and the first source region 109, and between the substrate 101 and the first drain region 110, wherein the second drain region 108 is doped with the first ions, and the second source region 107 is doped with the second ions; wherein the thickness of the first control gate channel layer 103 along the second direction is greater than the thickness of the other control gate channel layers 103 along the second direction; the height of the first faces of the second source region 107 and the second drain region 108 in the second direction is not higher than the bottom face of the first channel layer 103; the second source region 107 and the second surface of the second drain region 108 have a height along the second direction not lower than the surface of the substrate 101 therebetween, and a bottom U-shaped gate-surrounding gate transistor device is formed as shown in fig. 1 or 2.
In one embodiment, in step S11, the forming the wrap-gate MOSFET device, the second source region 107, and the second drain region 108 specifically includes:
s111: providing the substrate 101;
s112: forming a sacrificial layer 102 and the channel layer 103; the sacrificial layer 102 is stacked on the substrate 101 with a space from the channel layer 103; wherein the thickness of the first sacrificial layer 102 is greater than the thickness of the other sacrificial layers 102; the first sacrificial layer 102 characterizes the sacrificial layer 102 closest to the substrate 101; namely: the first sacrificial layer 102 is directly formed on the substrate 101; as shown in fig. 4; according to the technical scheme provided by the invention, the thickness of the first sacrificial layer 102 is larger than that of other sacrificial layers 102, so that the following step S118 is realized: after the dummy gate structure 105 is removed and the channel layer 103 is released, the space where the original first sacrificial layer 102 is located can be used as a space for subsequently filling the first control gate, and the space where the original other sacrificial layer 102 is located can be used as a space for subsequently filling other control gates, so that the thickness of the first control gate is greater than that of the other control gates; the sacrificial layer 102 and the channel layer 103 are formed as follows: a Si/SiGe stack having a crystal orientation <100 >;
S113: etching the sacrificial layer 102 and the channel layer 103 to form a fin structure; controlling the length of the device channel to be about 50nm-100nm; the thickness of the over-etched region of the control device is about 5nm to 50nm
S114: forming a dummy gate structure 105, and etching two ends of the sacrificial layer 102 along the first direction to form a cavity of the inner side wall 104; the method of growing the dummy gate structure 105 is selected from one of the following methods: atomic layer deposition, chemical vapor deposition and physical vapor deposition; in one specific example, the thickness of the dummy gate structure 105 is about 50nm
S115: forming the inner side wall 104; the inner side wall 104 is formed in the cavity of the inner side wall 104, and the device structure after step S115 is shown in fig. 5; specifically, the material of the inner sidewall 104 is selected from SiO2, si3N4 or other low K dielectric material; the method of growing the sidewall spacer 104 is selected from one of the following methods: atomic layer deposition, chemical vapor deposition, physical vapor deposition; in a specific example, the inner sidewall 104 is deposited Si3N4 by LPCVD
S116: forming the second source region 107 and the second drain region 108; the second source region 107 and the second drain region 108 are respectively formed at two sides of the fin structure along the first direction; wherein the optional arrangement range of the second source region 107 and the second drain region 108 is defined, which will be specifically explained in the following description of the present invention; in one embodiment, the second drain region 108 is doped with As at a concentration of about 1E18cm-3; in one embodiment, B is doped in the second source region 107 at a concentration of about 1E21cm-3;
In one embodiment, the method of growing the second source region 107 and the second drain region 108 is selected from one of the following methods: in-situ epitaxy, atomic layer deposition, chemical vapor deposition;
in another embodiment, the method of high doping the second source region 107 and the second drain region 108 is selected from one of the following methods: in-situ doping, ion implantation and solid source doping;
s117: forming the first source region 109 and the first drain region 110; the first source region 109 and the first drain region 110 are formed on top of the second source region 107 and the second drain region 108, respectively; in a specific example, the source-drain epitaxial material is selected from SiGe, si, C; in one embodiment, as is doped in the first source region 109 and the first drain region 110 at a concentration of about 1E21cm-3; step S117 further includes: implanting impurities for activation (1050 ℃ C., 10 s);
s118: removing the dummy gate structure 105 and releasing the channel layer 103; the device structure after step S118 is shown in fig. 6; as can be seen from fig. 6, in the technical solution provided by the present invention, the bottom channel length is increased (wherein, the bottom channel length is shown as a dotted path in the figure; and the increased channel length is shown as a dotted frame in the figure);
s119: the gate dielectric layer, the control gate, the source metal layer 111, the gate metal layer 113, the drain metal layer 112, the interlayer dielectric layer 114 and the metal contact layer 115 are formed, and a flow chart of the manufacturing method of steps S111-S119 is shown in fig. 3. The gate dielectric layer material is selected from SiO2, si3N4 or high-K gate dielectric material; the method for growing the gate dielectric layer is selected from one of the following methods: conventional thermal oxidation, nitrogen-doped thermal oxidation, atomic layer deposition or chemical vapor deposition; in a specific example, ALD is adopted to deposit a gate dielectric layer, the gate dielectric layer is HfO2, and the thickness is 1-5 nm; and depositing a control gate material by PEALD, wherein the control gate material is a TiN layer, and the thickness is 50-200 nm.
In one embodiment, in step S112, the thickness of the first sacrificial layer 102 is 5-200nm, and the thicknesses of the other sacrificial layers 102 are: 5-50nm. With respect to step S113, in one embodiment, when the sacrificial layer 102 and the channel layer 103 are etched to form a fin structure, and the substrate 101 on both sides of the fin structure along the first direction is not etched, steps S114 to S119 are performed to form the boom MOSFET device, the second source region 107, and the second drain region 108.
However, in view of the greater difficulty in the process of the foregoing embodiments, the present invention provides another embodiment: in step S113, when the sacrificial layer 102 and the channel layer 103 are etched to form a fin structure, the substrate 101 on both sides of the fin structure in the first direction is etched (as shown in fig. 7),
thus, step S117: the forming of the second source region 107 and the second drain region 108 further includes:
forming a first epitaxial layer 106; the first epitaxial layer 106 is formed on two sides of the fin structure along the first direction; the height of the first epitaxial layer 106 in the second direction is not lower than the height of the substrate 101 between the second source region 107 and the second drain region 108; in a specific example, the material of the first epitaxial layer 106 is: undoped Si;
The second source region 107 and the second drain region 108 are formed on the surface of the first epitaxial layer 106, respectively. Specifically, the material of the first epitaxial layer 106 is Si, which is the same as the material of the substrate 101.
In one embodiment, the height of the first epitaxial layer 106 along the second direction is equal to the height of the substrate 101 between the second source region 107 and the second drain region 108, and the device structure may refer to fig. 5;
in another embodiment, the first epitaxial layer 106 has a height along the second direction that is higher than the height of the substrate 101 between the second source region 107 and the second drain region 108; as shown in fig. 8; when the thicknesses of the second source region 107 and the second drain region 108 are fixed, the epitaxial height of the first epitaxial layer 106 is adapted to the height between the bottom surface of the first channel layer 103 and the substrate 101, that is, the thickness of the first sacrificial layer 102;
in this embodiment, other process steps after the step S113 are similar to the subsequent process steps of the previous embodiment, and the present application is not repeated here. Wherein, the liquid crystal display device comprises a liquid crystal display device,
wherein, corresponding to the embodiment in which the first epitaxial layer 106 is at the same height as the substrate 101, step S118: the device structure after removing the dummy gate structure 105 and releasing the channel layer 103 may refer to fig. 6; (in FIG. 6, the bottom channel length is shown as a dashed path; the increased channel length is shown as a dashed box); the height between the arrows in fig. 6 is the optional arrangement range of the second source region 107 and the second drain region 108, the second source region 107 and the second drain region 108;
Corresponding to the embodiment where the first epitaxial layer 106 is higher than the substrate 101, step S118: the device structure after removing the dummy gate structure 105 and releasing the channel layer 103 is shown in fig. 9; (in FIG. 9, the bottom channel length is shown as a dashed path; the increased channel length is shown as a dashed box); it can be seen that in this embodiment the bottom channel length of the device is longer compared to the first embodiment (as shown in fig. 6). Wherein the height between the arrows in fig. 9 is an optional setting range of the second source region 107 and the second drain region 108;
in one embodiment, when etching the sacrificial layer 102 and the channel layer 103 to form a fin structure, the thickness of the substrate 101 is controlled to be: 5nm-100nm.
Step S116: forming the second source region 107 and the second drain region 108 specifically includes:
s1161: forming a patterned first mask layer; the patterned first mask layer covers the second cavity, the dummy gate structure 105, and the surface of the inner sidewall 104;
s1162: filling the material of the second source region 107 in the first cavity to form the second source region 107, and removing the patterned first mask layer;
S1163: forming a patterned second mask layer; the patterned second mask layer covers the second source region 107, the dummy gate structure 105, and the surface of the inner sidewall 104;
s1164: and depositing and filling the material of the second drain region 108 in the second cavity to form the second drain region 108, and removing the patterned second mask layer.
Next, according to an embodiment of the present invention, there is also provided an electronic device including the bottom U-gate wrap gate transistor device according to any of the preceding embodiments of the present invention.
In addition, according to an embodiment of the present invention, there is further provided a method for manufacturing an electronic device, including a method for manufacturing a bottom U-shaped gate-all-around transistor device according to any one of the preceding embodiments of the present invention.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (12)
1. A bottom U-gate wrap gate transistor device, comprising:
the gate-all MOSFET device comprises a substrate, a first source region, a first drain region, a first control gate and a channel layer; the first source region and the first drain region are arranged along a first direction; wherein first ions are doped in the first source region and the first drain region; wherein the first direction characterizes a direction parallel to a surface of the substrate; the channel layer includes a first channel layer; the first channel layer characterizes a channel layer closest to the substrate; the first control gate characterizes the control gate closest to the substrate;
a second source region and a second drain region, the second source region being formed between the substrate and the first source region, the second drain region being formed between the substrate and the first drain region; wherein, the second drain region is doped with first ions, the second source region is doped with second ions, and the type of the first ions is different from the type of the second ions;
wherein the thickness of the first control gate along the second direction is greater than the thickness of the other control gates along the second direction; the heights of the first surfaces of the second source region and the second drain region along the second direction are not higher than the bottom surface of the first channel layer; the second source region and the second drain region have a second face with a height in the second direction not lower than the surface of the substrate therebetween; the second direction is perpendicular to the first direction.
2. The bottom U-gate wrap gate transistor device of claim 1, wherein a channel length of the bottom U-gate wrap gate transistor device is between 5nm and 100nm.
3. The bottom U-gate wrap gate transistor device of claim 2, wherein the thickness of the first control gate in the second direction is: 5nm-200nm.
4. A bottom U-gate wrap gate transistor device according to claim 3, wherein the thickness of the second source region and/or the second drain region in the second direction is 5nm-50nm.
5. The bottom U-gate wrap gate transistor device of claim 4, wherein the wrap gate MOSFET device further comprises:
the gate dielectric layer wraps part of the surface of the channel layer and covers the surface of the substrate between the second source region and the second drain region; the channel layer is formed between the first source region and the first drain region and is arranged at intervals along the direction away from the substrate; the control gate covers the surface of the gate dielectric layer; wherein the control gate comprises the first control gate; when the control gate covers the surface of the gate dielectric layer, the first control gate covers the surface of the gate dielectric layer on the surface of the substrate at the same time;
The inner side wall is formed between the first source region and the gate dielectric layer and on the surface of the channel layer between the first drain region and the gate dielectric layer;
a source metal layer, a gate metal layer and a drain metal layer; the source electrode metal layer and the drain electrode metal layer are respectively formed on the surfaces of the first source region and the first drain region, and respectively fully wrap the first source region and the second source region and the first drain region and the second drain region; the grid metal layer is formed on the top end of the control grid;
an interlayer dielectric layer covering the source metal layer, the gate metal layer, the drain metal layer and the surface of the inner side wall;
and the metal contact layers penetrate through the interlayer dielectric layer and are respectively connected with the source electrode metal layer, the gate electrode metal layer and the drain electrode metal layer.
6. A method of making a bottom U-gate wrap gate transistor device of any of claims 1-5, comprising:
forming the surrounding gate MOSFET device, the second source region and the second drain region; wherein, the fence MOSFET device includes: the substrate, the first source region, the first drain region, the first control gate and the channel layer; the channel layer includes a first channel layer; the first channel layer characterizes a channel layer closest to the substrate; the first control gate characterizes the control gate closest to the substrate; wherein the first source region and the first drain region are doped with the first ions; the second source region and the second drain region are respectively formed between the substrate and the first source region and between the substrate and the first drain region, wherein the first ions are doped in the second drain region, and the second ions are doped in the second source region;
Wherein the thickness of the first control gate along the second direction is greater than the thickness of the other control gates along the second direction; the heights of the first surfaces of the second source region and the second drain region along the second direction are not higher than the bottom surface of the first channel layer; the second source region and the second drain region have a second face with a height in the second direction not lower than a surface of the substrate therebetween.
7. The method of manufacturing a bottom U-gate wrap gate transistor device of claim 6, wherein forming the wrap gate MOSFET device, the second source region and the second drain region comprises:
providing the substrate;
forming a sacrificial layer and the channel layer; the sacrificial layer and the channel layer are stacked on the substrate at intervals; wherein the thickness of the first sacrificial layer is greater than the thickness of the other sacrificial layers; the first sacrificial layer characterizes the sacrificial layer closest to the substrate;
etching the sacrificial layer and the channel layer to form a fin structure;
forming a dummy gate structure, and etching two ends of the sacrificial layer along the first direction to form an inner side wall cavity;
Forming the inner side wall; the inner side wall is formed in the inner side wall cavity;
forming the second source region and the second drain region; the second source region and the second drain region are respectively formed on two sides of the fin structure along the first direction;
forming the first source region and the first drain region; the first source region and the first drain region are respectively formed at the top ends of the second source region and the second drain region;
removing the dummy gate structure and releasing the channel layer;
and forming the gate dielectric layer, the control gate, the source metal layer, the gate metal layer, the drain metal layer, the interlayer dielectric layer and the metal contact layer.
8. The method for manufacturing a bottom U-gate wrap gate transistor device of claim 7, wherein the thickness of the first sacrificial layer is 5-200nm, and the thicknesses of the other sacrificial layers are: 5-50nm.
9. The method of manufacturing a bottom U-gate wrap gate transistor device of claim 8, wherein when etching the sacrificial layer and the channel layer to form a fin structure, over etching the substrate on both sides of the fin structure along the first direction, forming the second source region and the second drain region further comprises, before:
Forming a first epitaxial layer; the first epitaxial layer is formed on two sides of the fin structure along the first direction; the height of the first epitaxial layer along the second direction is not lower than the height of the substrate between the second source region and the second drain region;
the second source region and the second drain region are respectively formed on the surface of the first epitaxial layer.
10. The method of manufacturing a bottom U-gate wrap gate transistor device of claim 9, wherein when etching the sacrificial layer and the channel layer to form a fin structure, controlling the thickness of the substrate over-etch is: 5nm-100nm.
11. An electronic device comprising a bottom U-gate wrap gate transistor device as claimed in any of claims 1-5.
12. A method of manufacturing an electronic device comprising the method of manufacturing a bottom U-gate wrap gate transistor device according to any of claims 6-10.
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