CN116598266A

CN116598266A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN116598266A
Application number: CN202310466436.9A
Authority: CN
Inventors: 刘志拯
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-04-26
Filing date: 2023-04-26
Publication date: 2023-08-15

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same, wherein the semiconductor structure includes: a base structure having a seal ring region and a device region, including at least one device located in the device region and a first seal ring structure located in the seal ring region and in a closed loop around the device region; a passivation layer over the base structure; an annular groove penetrating the passivation layer and extending to the top surface of the first sealing ring structure; the annular groove is provided with a first side wall and a second side wall which are opposite to each other, the first side wall is close to the device region, and the second side wall is far away from the device region; and a second sealing ring structure at least covering the first side wall and contacting at least part of the top surface of the first sealing ring structure.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background

A guard ring (die) of a chip (die) is a protective barrier for packaging and wafer dicing, and the formation of the guard ring is an important component in the back-end-of-chip process. The guard ring may protect the internal circuitry of the chip from damage caused by the dicing of the wafer into chips, e.g., the guard ring may block impurities and stresses to achieve good chip reliability.

It is a challenge to form a guard ring with better reliability that suppresses or eliminates defects generated in the wafer dicing process, such as forming semiconductor chips with less or no impurities and stresses, which may be caused by chip defects (e.g., semiconductor chips with impurities and stresses) due to the dicing forces of dicing.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same.

According to a first aspect of embodiments of the present disclosure, there is provided a semiconductor structure comprising:

a base structure having a seal ring region and a device region, comprising at least one device located in the device region and a first seal ring structure located in the seal ring region and in a closed loop around the device region;

a passivation layer over the base structure;

an annular groove penetrating the passivation layer and extending to the top surface of the first sealing ring structure; the annular groove is provided with a first side wall and a second side wall which are opposite, the first side wall is close to the device region, and the second side wall is far away from the device region;

and a second sealing ring structure at least covering the first side wall and contacting at least part of the top surface of the first sealing ring structure.

In the above scheme, the first side wall includes a step surface, a third side wall and a fourth side wall, the step surface extends to the bottom surface of the annular groove through the third side wall, and the step surface extends to the top surface of the passivation layer through the fourth side wall;

the second seal ring structure comprises a rerouting layer which is connected with each other and distributed on the step surface, and a second metal layer which is distributed between the rerouting layer and the first seal ring structure; wherein the second metal layer covers the third sidewall and is in contact with the redistribution layer and at least a portion of the top surface of the first seal ring structure;

or alternatively, the process may be performed,

the first side wall extends to the bottom surface of the annular groove and the top surface of the passivation layer;

the second seal ring structure comprises a rerouting layer which is connected with each other and distributed on the passivation layer, and a second metal layer which is distributed between the rerouting layer and the first seal ring structure; wherein the second metal layer covers the first sidewall and is in contact with the redistribution layer and at least a portion of the top surface of the first seal ring structure.

In the above scheme, the redistribution layer and the second metal layer are of an integrated structure.

In the above scheme, the semiconductor structure further comprises a third sealing ring structure, and the third sealing ring structure at least covers part of the second side wall and is in contact with at least part of the top surface of the first sealing ring structure.

In the above scheme, the first sealing ring structure comprises first metal layers and conductive columns which are alternately stacked and connected with each other.

In the above scheme, the base structure further comprises a substrate; the at least one device and the first seal ring structure are located on the substrate; the first seal ring structure also includes a contact plug ring having a bottom contacting the substrate and a top contacting the first metal layer.

In the above scheme, the material of the second sealing ring structure is different from the material of the first metal layer of the first sealing ring structure.

In the above scheme, the material of the second sealing ring structure comprises aluminum or aluminum alloy, and the material of the first metal layer of the first sealing ring structure comprises copper or copper alloy.

In the above solution, the substrate structure further has a scribe line region, and the scribe line region is disposed around the device region; the base structure further includes a dummy pattern metal layer located in the scribe line region.

According to a second aspect of embodiments of the present disclosure, there is provided a method for manufacturing a semiconductor structure, the method comprising:

providing a base structure; the substrate structure is provided with a sealing ring area and a device area, and comprises at least one device positioned in the device area and a first sealing ring structure positioned in the sealing ring area and forming a closed loop around the device area;

forming a passivation layer over the base structure;

forming an annular groove penetrating through the passivation layer along the thickness direction of the substrate structure and extending to the top surface of the first sealing ring structure; the annular groove is provided with a first side wall and a second side wall which are opposite, the first side wall is close to the device region, and the second side wall is far away from the device region;

forming a second seal ring structure at least covering the first sidewall; the second seal ring structure is in contact with at least a portion of the top surface of the first seal ring structure.

In various embodiments of the present disclosure, since the semiconductor structure is formed with the first and second seal ring structures connected to each other, the first and second seal ring structures may serve as a guard ring, which may protect devices within the semiconductor structure from damage caused by the dicing of the wafer into chips, e.g., the guard ring may block impurities and stresses, to achieve good chip reliability.

Drawings

FIG. 1 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

FIGS. 2a and 2b are schematic cross-sectional views of another semiconductor structure provided in an embodiment of the present disclosure;

fig. 3 a-3 c are schematic cross-sectional views of yet another semiconductor structure provided in an embodiment of the present disclosure;

fig. 4 is a flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the disclosure;

fig. 5a to 5g are schematic cross-sectional views illustrating a process for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 6 a-6 d are schematic cross-sectional views illustrating a fabrication process of another semiconductor structure provided in an embodiment of the present disclosure.

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Detailed Description

Exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure.

Dicing lines (also known as scribe lines) exist between the formed chips on the wafer, by which the wafer is diced to separate the wafer into a plurality of chips. In the process of cutting the wafer, impurities, stress and the like are generated, and the chip is easily damaged. In order to protect the chip during dicing of the wafer, a guard ring is typically formed between the chip and the dicing line.

Here and hereinafter, the term "chip" may be understood as a "semiconductor structure" described hereinafter.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure.

Referring to fig. 1, the semiconductor structure 10 includes:

a base structure 100 having a seal ring region A2 and a device region A1, comprising at least one device 124 located in the device region A1 and a first seal ring structure 113 located in the seal ring region A2 and in a closed loop around the device region A1;

A passivation layer 204 over the base structure 100;

a redistribution layer 202 is located over the passivation layer 204.

Here, in the semiconductor structure 10, due to the lack of the seal ring structure in the passivation layer 204, the protection capability of the passivation layer 204 is limited, so that impurities, stress, etc. (for example, moisture) may enter the internal circuit of the semiconductor structure through the passivation layer 204 during the dicing process, which is easy to damage the internal circuit of the semiconductor structure.

In the embodiments of the present disclosure shown in fig. 1, specific details of each structure or component or layer in each schematic cross-sectional view, and processes adopted to implement a method for manufacturing a semiconductor structure, may be understood with reference to the following semiconductor structure and/or a manufacturing process of the semiconductor structure.

Based on this, in order to solve one or more of the above-described problems, according to a first aspect of embodiments of the present disclosure, a semiconductor structure is provided. FIGS. 2a and 2b are schematic cross-sectional views of another semiconductor structure provided in an embodiment of the present disclosure; fig. 3a, 3b, and 3c are schematic cross-sectional views of yet another semiconductor structure provided in embodiments of the present disclosure.

Referring to fig. 2a and 2b, the semiconductor structure 20 includes:

a passivation layer 204 over the base structure 100;

an annular trench extending through the passivation layer 204 to the top surface of the first seal ring structure 113; the annular groove is provided with a first side wall S1 and a second side wall S2 which are opposite, the first side wall S1 is close to the device region A1, and the second side wall S2 is far away from the device region A1;

a second sealing ring structure 203, covering at least the first sidewall S1 and the second sidewall S2, is in contact with at least part of the top surface of the first sealing ring structure 113.

Referring to fig. 3a, 3b, and 3c, the semiconductor structure 30 includes:

a passivation layer 204 over the base structure 100;

A second sealing ring structure 203 covers at least the first sidewall S1 and is in contact with at least part of the top surface of the first sealing ring structure 113.

In some embodiments, referring to fig. 2a and 2b, fig. 3a and 3b, the second seal ring structure 203 is in contact with and electrically connected to the first seal ring structure 113.

In some embodiments, semiconductor structure 30 may be a memory chip or a logic chip. In some embodiments, semiconductor structures 30 may all be the same kind of memory chip. In other embodiments, some of the semiconductor structures 30 may be memory chips, while others are logic chips.

For example, the semiconductor structure 30 may be a volatile memory chip, such as a dynamic random access memory (DRAM, dynamic Random Access Memory) chip and a static random access memory chip, or may be a nonvolatile memory chip, such as a phase change random access memory chip, a magnetoresistive random access memory chip, a ferroelectric random access memory chip, and a resistive random access memory chip. In some example embodiments, semiconductor structure 30 may be a DRAM.

In some embodiments, device 124 may further include functional circuitry 121, insulating layer 122, interconnect layer 123. Wherein the functional circuit 121 comprises at least a transistor. The material of insulating layer 122 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The material of interconnect layer 123 includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof.

Here and hereinafter, the term "annular trench" is understood to mean an outer contour of a closed loop in a direction surrounding the device region A1 in one plane parallel to the top surface of the base structure 100. The outer contour of the annular groove has, for example, a closed contour in the first section, such as a regular closed contour (for example, a circle, an ellipse, a polygon, etc.), and an irregular closed contour. Wherein the first cross section is a plane passing through the annular groove and parallel to the top surface of the base structure.

Here and hereinafter, the present disclosure is illustrated by way of example, but not by way of limitation, of the semiconductor structure 30 shown in fig. 3a and 3b, which includes a redistribution layer 202 and a second metal layer 201 overlying a first sidewall S1. The details of the semiconductor structure 20 including the re-wiring layer 202 and the second metal layer 201 covering the first sidewall S1 and the third seal ring structure 207 covering the second sidewall S2 shown in fig. 2a and 2b and the details of the manufacturing method of the semiconductor structure 20 may be understood by referring to the details of the semiconductor structure 30 and the details of the manufacturing method of the semiconductor structure 30 described below, respectively, and will not be described in detail herein.

As shown in fig. 3a and 3b, in some embodiments, the first sidewall S1 includes a step surface SC, a third sidewall S3, and a fourth sidewall S4, the step surface SC extending to a bottom surface of the annular trench through the third sidewall S3, and the step surface SC extending to a top surface of the passivation layer 204 through the fourth sidewall S4;

the second seal ring structure 203 comprises a re-wiring layer 202 interconnected and distributed over the step surface SC and a second metal layer 201 distributed between the re-wiring layer 202 and the first seal ring structure 113;

wherein the second metal layer 201 covers the third sidewall S3 and is in contact with the redistribution layer 202 and at least part of the top surface of the first seal ring structure 113;

alternatively, as shown in FIG. 3c,

the first sidewall S1 extends to the bottom surface of the annular trench and the top surface of the passivation layer 204;

the second seal ring structure 203 comprises a re-wiring layer 202 interconnected and distributed over the passivation layer 204 and a second metal layer 201 distributed between the re-wiring layer and the first seal ring structure 113; wherein the second metal layer covers the first sidewall S1 and is in contact with the redistribution layer 202 and at least part of the top surface of the first seal ring structure 113.

The protection and sealing of the semiconductor structure 30 is facilitated by the second seal ring structure 203 being able to protect the devices within the semiconductor structure 30 from damage caused by the dicing of the wafer into chips during dicing of the wafer (see fig. 2a and 2 b), where the second seal ring structure 203 comprises the second metal layer 201 covering the first sidewall S1 and the redistribution layer 202 covering the step surface SC, or where the second seal ring structure 203 comprises the second metal layer 201 covering the first sidewall S1 and the redistribution layer 202 on the passivation layer 204, with respect to embodiments having a metal layer on the second sidewall (sidewall in the annular trench close to the dicing street region) and on the top surface of the passivation layer 204 connected to the second sidewall, and with respect to embodiments having a second metal layer covering the first sidewall and the second sidewall (see fig. 2a and 2 b). The second seal ring structure 203 having the stepped structure may better block impurities and stresses during wafer dicing, and may better protect devices within the semiconductor structure 30 from damage during wafer dicing. In addition, the redistribution layer 202 is located at the shoulder of the edge of the passivation layer 204, which effectively prevents cracking at the corners of the passivation layer.

Since the width of the dicing line area is much larger than the width of the annular groove, and the dicing line area is closer to the annular groove, dicing is easily shifted to the annular groove during dicing of the wafer. For embodiments having a metal layer on the second sidewall (sidewall in the annular trench proximate to the dicing street region) and/or on the top surface of the passivation layer 204 connected to the second sidewall, the dicing wafer may cut to the metal layer on the second sidewall and/or on the top surface of the passivation layer 204 connected to the second sidewall, resulting in impurities in the semiconductor structure and/or damage to devices within the semiconductor structure from mechanical, chemical stresses. Here, the passivation layer adjacent to the second sidewall has no metal layer on the top surface, or neither the second sidewall (the sidewall in the annular trench near the scribe line region) nor the passivation layer 204 connected to the second sidewall has a metal layer on the top surface, so that the devices in the semiconductor structure 30 can be better protected from damage during the wafer dicing process.

The redistribution layer 202 connected to the second metal layer 201 may be a dummy redistribution layer, in other words, disconnected from the other redistribution layers 202 located in the device region A1. As shown in fig. 3a, 3b, and 3c, in some embodiments, the redistribution layer 202 and the second metal layer 201 are connected together as an integral structure.

Here, the second sealing ring structure 203 is an integrally formed structure, and in the process of cutting the wafer, the second sealing ring structure 203 will not generate cracks under the condition of being stressed, for example, cracks are generated at the bonding position between the redistribution layer 202 and the second metal layer 201, so that the second sealing ring structure 203 can better realize the protection function.

As shown in fig. 3a, 3b, and 3c, in some embodiments, the third sidewall S3 has a first included angle θ with the bottom surface of the annular groove, and the first included angle θ is greater than or equal to 90 degrees.

Here, the first included angle may be understood as that, in the X-Z section, the third sidewall S3 has a first included angle θ with a first direction, where the first direction is a direction parallel to the top surface of the base structure and directed from the device region A1 to the seal ring region A2, and is illustrated as an X direction in the drawing; the X-Z section is a plane formed by the first direction and the thickness direction of the substrate structure.

In this way, the first included angle θ is greater than or equal to 90 degrees, which can facilitate forming a uniform second metal layer 201 under the condition that the second metal layer 201 achieves protection capability, and can reduce the thickness of the second metal layer 201 as much as possible under the condition that a certain thickness is satisfied, and in the process of forming the second metal layer 201, the metal material with smaller thickness can be etched to obtain the second metal layer 201.

As shown in fig. 3a, 3b, and 3c, in some embodiments, the first included angle θ ranges from 100 degrees to 120 degrees.

Here, the first included angle θ ranges from 100 degrees to 120 degrees, that is, the projection of the second metal layer 201 on the top surface of the base structure is located at a position that can be away from the seal ring area A2; in this way, in the wafer dicing process, the second seal ring structure 203 is relatively far away from the seal ring region A2, so that damage to the second metal layer 201 caused by dicing stress can be further alleviated, the second metal layer 201 can better block damage to the semiconductor structure caused by impurities and stress, and meanwhile, compared with the first included angle θ, the range of the second metal layer 201 is larger than 120 degrees (assuming that the first included angle θ is 135 degrees), the second metal layer 201 does not occupy a larger area of the semiconductor structure; compared with the first included angle θ being smaller than 100 degrees (assuming that the first included angle θ is 90 degrees here), the second metal layer 201 has a certain inclination angle, which can also relieve the stress concentration of the second metal layer to better block impurities and stress, thereby realizing the protection function.

As shown in fig. 3a, 3b, and 3c, in some embodiments, the redistribution layer 202 has a first dimension W2 along a direction parallel to the top surface of the base structure, where the first dimension W2 ranges from 3 μm to 7 μm, and the redistribution layer 202 has a second dimension H2 along a thickness direction of the base structure, and the second dimension H2 ranges from 3 μm to 5 μm;

The second metal layer 201 has a third dimension W1 in a direction parallel to the top surface of the base structure, the third dimension W1 ranges from 2 μm to 5 μm, the second metal layer 201 has a fourth dimension H1 in a thickness direction of the base structure, and the fourth dimension H1 ranges from 3 μm to 5 μm.

Here, a direction parallel to the top surface of the base structure may be understood as a first direction, schematically indicated as X-direction in the drawing.

Here, the specific dimensions of the redistribution layer 202 and the second metal layer 201 may be set to alleviate or avoid stress concentration of the semiconductor structure to better block impurities and stress during wafer dicing, and better implement a function of protecting the semiconductor structure under the condition of implementing protection capability.

As shown in fig. 2a and 2b, in some embodiments, the semiconductor structure further comprises a third seal ring structure 207, the third seal ring structure 207 covering at least the second sidewall S2 and being in contact with at least part of the top surface of the first seal ring structure 113.

In some embodiments, the third seal ring structure 207 extends on the top surface of the first seal ring structure 113 and is in contact with the second seal ring structure 203. Illustratively, the third seal ring structure 207 and the second seal ring structure 203 are an integrally formed structure.

As shown in fig. 3a, in some embodiments, the semiconductor structure further comprises a dielectric layer 205; a gap space is included between the second metal layer 201 and the second sidewall S2, and the dielectric layer 205 fills at least a portion of the gap space.

Here, the second seal ring structure 203 covers at least the first sidewall S1, a gap space is formed between the second seal ring structure 203 and the passivation layer 204 (which may be understood as a gap between the first sidewall S1 and the second sidewall S2 opposite to each other and excluding a space occupied by the second seal ring structure 203, and reference may also be made to a gap space G shown in fig. 3 b), and the dielectric layer 205 fills at least a portion of the gap space.

As shown in fig. 3b, 3c, in some embodiments, a gap space G is included between the second metal layer 201 and the second sidewall S2. In the wafer dicing process, the gap space G provides a stress buffer space for dicing the remaining dicing line area A3, which is beneficial to protecting the device. Illustratively, the interstitial space G is air.

As shown in fig. 3a, 3b, 3c, in some embodiments, the first seal ring structure 113 includes first metal layers 111 and conductive pillars 112 alternately stacked and interconnected.

In some embodiments, the first seal ring structure 113 includes the first metal layer 111 and the conductive pillar 112 alternately stacked and connected to each other, and the top of the first seal ring structure 113 is the first metal layer 111, and the bottom of the first seal ring structure 113 is the conductive pillar 112. Illustratively, the first seal ring structure 113 includes a contact plug ring 103, a zero metal layer 107, a zero conductive post 104, a first metal layer 108, a first conductive post 105, a second metal layer 109, a second conductive post 106, and a third metal layer 110 stacked in this order, wherein the first metal layer 111 includes the zero metal layer 107, the first metal layer 108, the second metal layer 109, and the third metal layer 110, and the conductive post 112 includes the contact plug ring 103, the zero conductive post 104, the first conductive post 105, and the second conductive post 106.

Here, the first metal layers 111 and the conductive pillars 112 alternately stacked and connected to each other may be formed simultaneously with the at least one device 124.

As shown in fig. 3a, 3b, 3c, in some embodiments, the base structure 100 further comprises a substrate 101; the at least one device 124 and the first seal ring structure 113 are located on the substrate 101; the first seal ring structure 113 further comprises a contact plug ring 103, the bottom of the contact plug ring 103 contacting the substrate 101, the top of the contact plug ring 103 contacting the first metal layer (zero metal layer 107 as shown in fig. 3a and 3 b).

The presence of the contact plug ring 103 in effect connects the first seal ring structure 113 with the substrate 101, thus enabling the first seal ring structure 113 to provide better electrostatic protection of the internal circuitry of the internally enclosed semiconductor structure.

As shown in fig. 3a and 3b, in some embodiments, the first seal ring structure has a first width in a direction parallel to the top surface of the base structure; the first width is in the range of 2 μm to 5 μm.

Here, a direction parallel to the top surface of the base structure may be understood as a first direction, schematically indicated as X-direction in the drawing. In this way, the first seal ring structure has a first width of 2 μm to 5 μm along the first direction, so that the first seal ring structure 113 plays a role in blocking stress during dicing, thereby avoiding damage to the chip caused by stress.

In some embodiments, the redistribution layer 202 is spaced from the edge of the device region A1 by a distance of about 10 μm, so as to further block the stress during dicing and prevent the chip from being damaged by the stress.

In some embodiments, the semiconductor structure further includes a pad (pad) (not shown in fig. 3a, 3b, and 3 c), both of which are formed in a metal layer patterning process. In some embodiments, after forming the pad and the second seal ring structure 203, a passivation layer having an opening is formed on top of the semiconductor structure, the passivation layer having an opening exposing a top surface of the pad (pad) and a top surface of the second seal ring structure 203 on a top surface of the semiconductor structure. In other embodiments, the passivation layer having the opening may also expose the second metal layer from the passivation layer.

In some embodiments, the material of the second seal ring structure 203 is different from the material of the first metal layer of the first seal ring structure 113; the material of the second seal ring structure 203 includes a metal material such as aluminum or aluminum alloy that is easy to be directly lithographically patterned, and the material of the first metal layer of the first seal ring structure 113 includes copper or copper alloy. Copper or copper alloys are good in conductivity but difficult to photolithographic patterning, and this embodiment is optionally prepared using a damascene process.

As shown in fig. 3a, 3b, 3c, in some embodiments, the base structure 100 further has a scribe line region A3, the scribe line region A3 being disposed around the device region; the base structure 100 further includes dummy pattern metal layers 130-133 located in the scribe line region A3.

In some embodiments, the substrate structure 100 further includes a dummy pattern structure 134 located at the scribe line region A3; the dummy pattern structure 134 includes dummy pattern metal layers 130-133 located in the insulating layer 122 and spaced apart by the insulating layer 122.

Here, the dummy pattern structure 134 can relieve internal stress caused during the formation of the semiconductor structure.

In some embodiments, the dimension of the cut line area A3 in the first direction is 50 μm to 100 μm.

In various embodiments of the present disclosure, since the semiconductor structure is formed with the first and second seal ring structures 113 and 113 connected to each other, the first and second seal ring structures may serve as a guard ring, which may protect devices within the semiconductor structure from damage caused by a process of dicing a wafer into chips, for example, the guard ring may block impurities and stresses, to achieve good chip reliability.

The semiconductor structure provided by the above embodiments of the present disclosure is similar to the semiconductor structure manufactured by the method for manufacturing the following semiconductor structure, and for the technical features of the above embodiments of the present disclosure that are not fully disclosed, reference is made to the method for manufacturing the following semiconductor structure for understanding, and details are not repeated here.

Fig. 4 is a flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the disclosure. As shown in fig. 4, according to a second aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a semiconductor structure, the method comprising the steps of:

s401, providing a substrate structure; the substrate structure is provided with a sealing ring area and a device area, and comprises at least one device positioned in the device area and a first sealing ring structure positioned in the sealing ring area and forming a closed loop around the device area;

s402, forming a passivation layer above the substrate structure;

s403, forming an annular groove penetrating through the passivation layer along the thickness direction of the substrate structure and extending to the top surface of the first sealing ring structure; the annular groove is provided with a first side wall and a second side wall which are opposite, the first side wall is close to the device region, and the second side wall is far away from the device region;

S404, forming a second sealing ring structure at least covering the first side wall; the second seal ring structure is in contact with at least a portion of the top surface of the first seal ring structure. Optionally, the second seal ring structure is electrically connected with the first seal ring structure.

It should be understood that the steps shown in fig. 4 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 4 can be sequentially adjusted according to actual requirements.

Here and hereinafter, the first direction is a direction parallel to the top surface of the base structure and directed by the device region toward the seal ring region; the first direction and the second direction are represented as two orthogonal directions parallel to the top surface of the base structure; the third direction is a direction parallel to the thickness of the substrate, and can be understood as a stacking direction of the process layers formed. Illustratively, the first direction is represented as the X-direction in the drawings; the second direction is denoted as the Y direction in the drawing; the third direction is denoted as Z-direction in the drawing.

Fig. 5a to 5g are schematic cross-sectional views illustrating a process for fabricating a semiconductor structure according to an embodiment of the present disclosure. Fig. 6 a-6 d are schematic cross-sectional views illustrating a fabrication process of another semiconductor structure provided in an embodiment of the present disclosure. The following describes in detail the method for manufacturing the semiconductor structure provided in the embodiment of the present disclosure with reference to fig. 4, 5a to 5g, and fig. 6a to 6 d.

It should be noted that fig. 5a to 5g, each of fig. 6a to 6d show schematic cross-sectional views of the same region of the semiconductor structure in at least one process step; as an example, each of fig. 5a to 5g only shows a partial device region A1 immediately adjacent to the seal ring region A2, and a partial cut line region A3 immediately adjacent to the seal ring region A2.

Step S401 is performed to provide a base structure.

Referring to fig. 5a, the base structure 100 has a seal ring region A2 and a device region A1, comprising at least one device 124 located in the device region A1 and a first seal ring structure 113 located in the seal ring region A2 and in a closed loop around the device region A1.

Referring to fig. 5a, in some embodiments, the base structure 100 further comprises a substrate 101; the at least one device 124 and the first seal ring structure 113 are located on the substrate 101, the method further comprising:

providing the substrate 101;

forming the at least one device 124 and the first seal ring structure 113 on the substrate 101; wherein the first seal ring structure 113 includes first metal layers 111 and conductive pillars 112 alternately stacked and connected to each other.

In some embodiments, the substrate 101 may be a package substrate or a printed circuit board, such as a stack base formed as a stack of multiple thin layers (or stacks) of polymeric material, such as Bismaleimide Triazine (BT), FR-4, ABF, and the like. However, any other suitable substrate may be utilized, such as a silicon interposer, a silicon substrate, an organic substrate, a ceramic substrate, and the like.

In some embodiments, the substrate 101 may comprise silicon germanium, gallium arsenide, or other suitable semiconductor material. The substrate 101 may further include doped regions such as P-wells, N-wells, and/or doped active regions such as P + doped active regions. In one aspect, the doped active region may be located in other regions.

In some embodiments, the substrate 101 may also include other components, such as buried oxide layers, and/or epitaxial layers. In addition, the substrate 101 may be a semiconductor-on-insulator, such as silicon-on-insulator. In other embodiments, the substrate 101 may include a doped epitaxial layer, a graded semiconductor layer, and/or may also include a semiconductor layer overlying other different types of semiconductor layers, such as a silicon layer on a silicon germanium layer. In other examples, the substrate 101 may include a compound semiconductor structure that may also include multiple layers.

The substrate 101 may further comprise isolation structures, such as shallow trench isolation 102 features or silicon selective oxidation (LOCOS, local Oxidation of Silicon) features formed in the substrate 101, for isolating the active region from other regions of the substrate 101. In one example, the active region may be configured as an NMOS device or a PMOS device.

The substrate 101 may further include dummy gates and/or gate structures (not shown in fig. 5 a) overlying the substrate 101, which may be formed from various metal layers and by various etching and/or patterning techniques for various regions of the substrate 101.

The device 124 may further include functional circuitry 121, an insulating layer 122, an interconnect layer 123.

Here, the functional circuit 121 includes at least a transistor. The material of insulating layer 122 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The material of interconnect layer 123 includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof.

In some embodiments, the semiconductor structure includes a DRAM, which includes a plurality of repeated functional circuits 121 for storing data in an insulating layer 122, the functional circuits 121 including a memory cell array (not shown in fig. 5 a) and peripheral circuits (not shown in fig. 5 a) located at the periphery of the memory cell array. The array unit and the peripheral circuit are coupled through the interconnection layer 123, and the peripheral circuit includes a peripheral circuit for controlling the memory cell array to implement data read/write operation.

In some embodiments, the first seal ring structure 113 includes first metal layers 111 and conductive pillars 112 alternately stacked and interconnected. As shown in fig. 5a, the first metal layer 111 includes a zero metal layer 107, a one metal layer 108, a two metal layer 109, and a three metal layer 110, and the conductive pillars 112 include a zero conductive pillar 104, a one conductive pillar 105, and a two conductive pillar 106.

Here, the material of the first seal ring structure 113 includes copper and copper alloy.

A plurality of first metal layers and conductive pillars stacked in a semiconductor structure are shown in the embodiments of the present disclosure, but the number of first metal layers and conductive pillars stacked in a semiconductor structure is not limited thereto. For example, one, two or more (e.g., ten) layers of the first metal layer and the conductive pillars may be stacked in the semiconductor structure.

Although the number of through holes each layer of conductive posts has is shown in the present exemplary embodiment, the number of through holes each layer of conductive posts has is not limited thereto. For example, one, three, or more (e.g., ten) vias may be provided per layer of conductive pillars.

In some embodiments, the first seal ring structure 113 further comprises a contact plug ring 103, the bottom of the contact plug ring 103 contacting the substrate 101, the top of the contact plug ring 103 contacting the first metal layer (zero metal layer 107 as shown in fig. 5 a).

Here, the material contacting the plug ring 103 includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof.

In some embodiments, the first seal ring structure 113 has a dimension in the first direction (X direction in fig. 5 a) in the range of 2 μm to 5 μm.

Steps S402 and S403 are performed to form a passivation layer and a ring-shaped trench.

Referring to fig. 5b, a passivation layer 204 may be formed over the substrate structure 100 by a chemical vapor deposition (CVD, chemical Vapor Deposition) process, spin-on technique, or the like. The material of the passivation layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Illustratively, the passivation layer 204 thickness has a sum of a fourth dimension H1 and a second dimension H2.

Referring to fig. 5 b-5 d, in some embodiments, forming the annular trench T2 includes:

as shown in fig. 5b, a first pattern mask layer 301 having a first opening OP1 is formed on the passivation layer 204;

using the first pattern mask layer 301 as a mask, forming an initial annular trench T1 by etching a part of the passivation layer;

as shown in fig. 5c, removing a portion of the first pattern mask layer on at least one of two sides of the first opening to form a second pattern mask layer 302 having a second opening OP 2;

as shown in fig. 5c and 5d, the second pattern mask layer 302 is used as a mask to etch the initial annular trench T1 (as shown in fig. 5 c) and form an annular trench T2 (as shown in fig. 5 d) by using part of the passivation layer;

the first sidewall S1 includes a step surface SC, a third sidewall S3, and a fourth sidewall S4, the step surface SC extends to the bottom surface of the annular trench T2 through the third sidewall S3, and the step surface SC extends to the top surface of the passivation layer 204 through the fourth sidewall S4.

Here, the first pattern mask layer 301 and the second pattern mask layer 302 may be obtained by performing exposure and development on the same pattern mask material layer (not shown in fig. 5 b) twice, and after performing the first etching and the second etching with the first pattern mask layer 301 and the second pattern mask layer 302 as masks, the annular trench T2 may be formed, and the passivation layer 204 may have a step structure.

Here, a dimension W4 of the second opening OP2 in the first direction is larger than a dimension W3 of the first opening OP1 in the first direction.

In some embodiments, the dimension of the initial annular groove T1 in the third direction may be smaller than the dimension of the annular groove T2 in the third direction.

Here, the annular trench T2 has a first sidewall S1 and a second sidewall S2, the first sidewall S1 being close to the device region A1, the second sidewall S2 being distant from the device region A1.

Thus, since the first sidewall S1 has the stepped surface SC, the passivation layer 204 has a stepped structure, and as shown in fig. 5d, the passivation layer 204 has a planar structure including three planar structures extending along the X-Y plane, such as a top surface of the passivation layer 204, the stepped surface SC, and a bottom surface of the annular trench T2, the top surface of the passivation layer 204 extends to the stepped surface SC through the fourth sidewall S4, and the stepped surface SC extends to the bottom surface of the annular trench T2 through the third sidewall S3.

Referring to fig. 5d, in some embodiments, the third sidewall S3 has a first angle θ with the bottom surface of the annular trench T2, and the first angle θ ranges from 100 degrees to 120 degrees.

Here, the first direction (X direction in fig. 5 d) is a direction parallel to the top surface of the base structure and directed from the device region A1 to the seal ring region A2, and the cross section is a plane (X-Z cross section in fig. 5 d) formed by the first direction and the thickness direction of the base structure.

The side wall (the first side wall S1 or the second side wall S2) of the annular groove T2 in the X-Z section has a first included angle theta with the first direction, and the first included angle theta ranges from 100 degrees to 120 degrees.

As shown in fig. 5d, the specific morphology and size of the annular trench T2 are controlled, for example: the step surface SC of the annular groove T2 is controlled to have a dimension along the first direction and a dimension along the third direction, and/or the side wall (the third side wall S3 or the second side wall S2) of the annular groove T2 is controlled to have an included angle θ with the first direction, so as to prepare for forming the second seal ring structure with a specific shape and dimension in the subsequent process.

Step S404 is performed to form a second seal ring structure.

Referring to fig. 5 e-5 f, in some embodiments, the second seal ring structure 203 includes a re-wiring layer 202 and a second metal layer 201, forming the second seal ring structure 203 includes:

Referring to fig. 5e, a metal material layer 203 '(including a conductive material layer 205' covering the top surface of the passivation layer 204 and conductive material layers 201', 202' covering at least the first sidewall S1) covering the sidewalls, the bottom surface and the top surface of the passivation layer 204 of the annular trench is formed;

referring to fig. 5e to 5f, a portion of the metal material layer 203' is removed, forming a re-wiring layer 202 (refer to fig. 5 f) covering the stepped surface SC and the fourth sidewall S4 and a second metal layer 201 (refer to fig. 5 f) covering the third sidewall S3;

wherein the redistribution layer 202 is interconnected with the second metal layer 201, the second metal layer 201 being in contact with at least a portion of the top surface of the first seal ring structure 113. Optionally, the second metal layer 201 is in contact and electrically connected with at least a portion of the top surface of the first seal ring structure 113.

Note that fig. 5f only shows the second seal ring structure 203 formed to cover the first sidewall S1. The topography of the second seal ring structure forming the cap over the first sidewall S1 and the second sidewall S2 can be understood with particular reference to the second seal ring structure 203 (comprising the re-wiring layer 202 and the second metal layer 201) and the third seal ring structure 207 in fig. 2 b.

As shown in fig. 5e, the metal material layer 203' covering the sidewalls, bottom surface and top surface of the passivation layer 204 of the annular trench T2 may be formed by a physical vapor deposition (PVD, physical Vapor Deposition) process, CVD process, or the like.

Here, the material of the metal material layer 203' includes aluminum and aluminum alloy.

As shown in fig. 5f, a portion of the metal material layer may be removed by a photolithography-etching process (illustratively, at least the metal material layer 203 'on the top surface of the passivation layer 204 and the metal material layer 203' covering the second sidewall S2 are removed), forming a re-wiring layer 202 covering the step surface SC and the fourth sidewall S4 and a second metal layer 201 covering the third sidewall S3 (refer to fig. 5 f).

In some embodiments, the material of the second seal ring structure 203 is different from the material of the top of the first seal ring structure 113, as shown in fig. 5 f. In some embodiments, the material of the second seal ring structure 203 comprises aluminum or an aluminum alloy, and the material of the top of the first seal ring structure 113 (e.g., the three metal layers 110 of the first seal ring structure 113) comprises copper or a copper alloy.

With continued reference to fig. 5 e-5 f, in some embodiments, portions of the metal material layer 203' are removed, the method further comprising:

as shown in fig. 5e to 5f, removing the metal material layer on the top surface of the passivation layer 204 to obtain a metal material layer covering the sidewall and the bottom surface of the annular trench;

forming a patterned masking layer (not shown in fig. 5 f); the pattern mask layer includes a metal material layer 203' (as shown in fig. 5 f) covering the first sidewall S1;

As shown in fig. 5f to fig. 5f, the metal material layer 203' not covered by the pattern mask layer is etched away; the layer of metal material that is not removed includes a second seal ring structure 203 (as shown in fig. 5 f).

Here, since the specific morphology and size of the annular trench T2 are controlled in the foregoing process, for example: the dimension of the stepped surface SC of the annular trench T2 in the first direction and the dimension thereof in the third direction are controlled, and/or the included angle θ of the sidewall (the third sidewall S3 or the second sidewall S2) of the annular trench T2 with respect to the first direction is controlled, whereby the re-wiring layer 202 formed in the annular trench T2 has a specific shape and dimension similar to those of the second metal layer 201.

Thus, the redistribution layer 202 and the second metal layer 201 are formed as an integral structure.

In some embodiments, the third sidewall S3 has a first angle θ with the bottom surface of the annular trench, and the first angle θ is greater than or equal to 90 degrees. In some embodiments, the first included angle θ ranges from 100 degrees to 120 degrees, as shown in FIG. 5 f.

As shown in fig. 5f, in some embodiments, the redistribution layer 202 has a first dimension W2 along a first direction, the first dimension W2 ranges from 3 μm to 7 μm, the redistribution layer 202 has a second dimension H2 along a thickness direction of the base structure, and the second dimension H2 ranges from 3 μm to 5 μm;

The second metal layer 201 has a third dimension W1 at a maximum distance from the second sidewall S2 in the first direction, the third dimension W1 ranges from 2 μm to 5 μm, the second metal layer 201 has a fourth dimension H1 in the thickness direction of the base structure, and the fourth dimension H1 ranges from 3 μm to 5 μm.

As shown in fig. 5f, in some embodiments, after forming the second seal ring structure 203, the fabrication method further includes: a dielectric layer 205 is formed to cover the sidewalls of the re-wiring layer 202 and to cover the sidewalls of the second metal layer 201 and to fill the gap space G (refer to fig. 3 a). Wherein the top surface of dielectric layer 205 is flush with the top surface of redistribution layer 202. Here, the material of the dielectric layer 205 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the material of dielectric layer 205 and the material of passivation layer 204 may be the same.

As shown in fig. 5g, in some embodiments, the base structure 100 also has a scribe line region A3, the scribe line region A3 being used to isolate the semiconductor structure from other semiconductor structures; the base structure 100 further includes a dummy pattern structure 134 located at the scribe line region A3; the dummy pattern structure 134 includes dummy pattern metal layers 130-133 located in the insulating layer 122 and spaced apart by the insulating layer 122, and after forming the second seal ring structure 203, the method of fabricating the semiconductor structure further includes:

A scribe line region A3 may exist between semiconductor structures formed on the wafer, and the wafer is divided into a plurality of semiconductor structures by dicing the wafer through the scribe line region A3.

Here, since the semiconductor structure is formed with the first and second seal ring structures 113 and 203 connected to each other, the first and second seal ring structures 113 and 203 may serve as a guard ring, which may protect the devices 124 within the semiconductor structure from damage caused by the dicing of the wafer into chips, for example, the guard ring may block impurities and stress, to achieve good chip reliability.

Fig. 6 a-6 d are schematic cross-sectional views illustrating a fabrication process of another semiconductor structure provided in an embodiment of the present disclosure. In fig. 6a to 6d, the same reference numerals as in fig. 5a to 5g are used to denote the same or similar elements, components, regions, layers or portions, and the manufacturing methods of manufacturing the same or similar elements, components, regions, layers or portions may be understood with reference to the relevant portions in fig. 5a to 5g, and will not be repeated herein.

Referring to fig. 6a, the base structure 100 has a seal ring region A2 and a device region A1, comprising at least one device 124 located in the device region A1 and a first seal ring structure 113 located in the seal ring region A2 and in a closed loop around the device region A1.

Referring to fig. 6b, a first passivation layer 204' may be formed over the base structure 100 by a chemical vapor deposition process, spin-on technique, or the like. The material of the first passivation layer 204' includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Illustratively, the thickness of the first passivation layer 204' has a fourth dimension H1.

As shown in fig. 6b, a first pattern mask layer 301 having a third opening OP3 is formed on the first passivation layer 204'; the size of the third opening OP3 can be understood with reference to the third dimension W1 in fig. 5 f.

The first etched portion of the passivation layer forms a ring-shaped trench T3 using the first pattern mask layer 301 as a mask.

Referring to fig. 6b, in some embodiments, the first sidewall S1 has a first angle θ with the bottom surface of the annular groove T3, and the first angle θ ranges from 100 degrees to 120 degrees.

The opening size of the annular trench T3 has a third size W1, and the depth size of the annular trench T3 has a fourth size H1 (as understood with reference to the fourth size H1 in fig. 6 b), the fourth size H1 being in the range of 3 μm to 7 μm.

Here, the specific morphology, dimensions of the annular trench T3 are controlled, for example: the control of the dimension of the annular groove T3 along the first direction and the dimension along the third direction, and/or the control of the included angle θ between the sidewall (the first sidewall S1 or the second sidewall S2) of the annular groove T3 and the first direction, provides for the formation of a second seal ring structure with a specific shape and dimension in the subsequent process.

Referring to fig. 6 c-6 d, in some embodiments, the second seal ring structure 203 includes a re-wiring layer 202 and a second metal layer 201, forming the second seal ring structure 203 includes:

referring to fig. 6c, a metal material layer 203' (including a conductive material layer 205' covering the top surface of the first passivation layer 204' and conductive material layers 201', 207' covering at least the first and second sidewalls S1, S2) covering the sidewalls, the bottom surface, and the top surface of the annular trench is formed;

referring to fig. 6c to 6d, a portion of the metal material layer (a portion of the conductive material layer 205', the conductive material layer 207 ') is removed, forming a re-wiring layer 202 (refer to fig. 6 d) covering the top surface of the first passivation layer 204' and a second metal layer 201 (refer to fig. 6 d) covering the first sidewall S1;

As shown in fig. 6c, the metal material layer 203 'covering the sidewalls, bottom surface and top surface of the first passivation layer 204' of the annular trench T3 may be formed by a PVD process, a CVD process, or the like.

As shown in fig. 6d, a portion of the metal material layer may be removed by a photolithography-etching process (illustratively, a portion of the conductive material layer 205 'on the top surface of the first passivation layer 204' is removed and a portion of the metal material layer 207 'covering the second sidewall S2 is removed), forming a re-wiring layer 202 covering a portion of the top surface of the first passivation layer 204' and a second metal layer 201 covering the first sidewall S1; wherein the redistribution layer 202 is located in the device region A1 and/or the seal ring region A2, and the second metal layer 201 is located in the seal ring region A2 or in the device region A1 and the seal ring region A2.

In some embodiments, the wafer is diced by dicing line area A3, separating the wafer into a plurality of semiconductor structures (see fig. 3 c).

The semiconductor structure manufactured by the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure is similar to the semiconductor structure in the above embodiment, and for technical features that are not fully disclosed in the embodiment of the present disclosure, reference is made to the above embodiment for understanding, and details are not repeated here.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.

Claims

1. A semiconductor structure, the semiconductor structure comprising:

a passivation layer over the base structure;

2. The semiconductor structure of claim 1, wherein the first sidewall comprises a stepped surface, a third sidewall, and a fourth sidewall, the stepped surface extending through the third sidewall to a bottom surface of the annular trench, the stepped surface extending through the fourth sidewall to a top surface of the passivation layer;

Or alternatively, the process may be performed,

3. The semiconductor structure of claim 2, wherein the redistribution layer is an integral structure with the second metal layer.

4. The semiconductor structure of claim 1, further comprising a third seal ring structure covering at least a portion of the second sidewall and in contact with at least a portion of a top surface of the first seal ring structure.

5. The semiconductor structure of claim 1, wherein the first seal ring structure comprises alternating stacked and interconnected first metal layers and conductive pillars.

6. The semiconductor structure of claim 5, wherein the base structure further comprises a substrate; the at least one device and the first seal ring structure are located on the substrate; the first seal ring structure also includes a contact plug ring having a bottom contacting the substrate and a top contacting the first metal layer.

7. The semiconductor structure of claim 5, wherein a material of the second seal ring structure is different from a material of the first metal layer of the first seal ring structure.

8. The semiconductor structure of claim 7, wherein the material of the second seal ring structure comprises aluminum or an aluminum alloy and the material of the first metal layer of the first seal ring structure comprises copper or a copper alloy.

9. The semiconductor structure of claim 1, wherein the base structure further has a scribe line region disposed around the device region; the base structure further includes a dummy pattern metal layer located in the scribe line region.

10. A method of fabricating a semiconductor structure, the method comprising:

forming a passivation layer over the base structure;