CN116598202A - Zener diode and manufacturing method thereof - Google Patents

Zener diode and manufacturing method thereof Download PDF

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Publication number
CN116598202A
CN116598202A CN202310640708.2A CN202310640708A CN116598202A CN 116598202 A CN116598202 A CN 116598202A CN 202310640708 A CN202310640708 A CN 202310640708A CN 116598202 A CN116598202 A CN 116598202A
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zener diode
type
buried layer
type buried
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方明旭
陈华伦
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66098—Breakdown diodes
    • H01L29/66106—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a zener diode and a manufacturing method thereof, comprising the steps of providing a substrate, and forming an N-type buried layer and a P-type buried layer on the substrate; forming an epitaxial layer over the N-type buried layer and the P-type buried layer; forming a shallow trench isolation structure in the epitaxial layer; photoetching and ion implantation are carried out on the epitaxial layer to form an N-type well and a P-type well; depositing a gate oxide layer and polysilicon and etching to form a polysilicon gate; forming PLDD regions in the epitaxial layers between the polysilicon gates by using the polysilicon gates as masks and adopting a lightly doped ion implantation process; and (3) carrying out source-drain ion implantation to form an N+ region and a P+ region, wherein the N+ region and the PLDD region in the PLDD region form a PN junction of the zener diode. The invention adopts the lightly doped ion implantation technology to form the PLDD region in the epitaxial layer, and forms the N+ region positioned in the PLDD region when carrying out source-drain ion implantation, thereby solving the problem of overhigh mask technology cost of the traditional zener diode and reducing the parasitic capacitance of the zener diode.

Description

Zener diode and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a zener diode and a manufacturing method thereof.
Background
The zener diode (zeneriode), which may be called a zener diode, uses a reverse breakdown state of the PN junction, that is, when the PN junction breaks down in reverse, a current variation range is very large, but the voltage is basically unchanged, and the voltage maintained at this time is called a breakdown voltage (Breakdown Voltage, BV), which is also called a stabilized voltage, so as to perform a voltage stabilizing function. Zener diodes have found wide application in the integrated circuit field, mainly as voltage regulators and voltage reference devices.
In the prior art, the reverse breakdown voltage of the zener diode is generally determined by the longitudinal PN junction. That is, the P region and the N region of the vertical stack are required to form the PN junction, and thus, the doping depth of one of the P region and the N region is larger, that is, the doping depth is larger than that of the other doped region, so that an additional mask (mask) and a corresponding masking step are required to distinguish the region with the large doping depth from the other doped region, which results in an increase in process cost.
Disclosure of Invention
In view of the above, the present invention provides a zener diode and a method for manufacturing the same, which are used for reducing the cost of the existing zener diode with too high mask process and reducing the parasitic capacitance.
The invention provides a manufacturing method of a zener diode, which comprises the following steps:
providing a substrate, and forming an N-type buried layer and a P-type buried layer on the substrate;
step two, forming an epitaxial layer above the N-type buried layer and the P-type buried layer;
step three, forming a shallow trench isolation structure in the epitaxial layer;
step four, photoetching and ion implantation are carried out on the epitaxial layer to form an N-type well and a P-type well;
depositing a gate oxide layer and polysilicon and etching to form a polysilicon gate;
step six, forming PLDD regions in the epitaxial layers between the polysilicon gates by using the polysilicon gates as masks and adopting a lightly doped ion implantation process;
and seventhly, performing source-drain ion implantation to form an N+ region and a P+ region, wherein the N+ region positioned in the PLDD region and the PLDD region form a PN junction of the zener diode.
Preferably, in the first step, the substrate is a P-type substrate.
Preferably, in the second step, the epitaxial layer is formed by an epitaxial growth process.
Preferably, in the third step, a trench is formed in the epitaxial layer by utilizing photoetching and etching, and then silicon dioxide is filled in the trench, and chemical mechanical polishing is performed to form the shallow trench isolation structure.
Preferably, in the fourth step, the N-type well and the P-type well include: first and second N-type wells spaced apart from each other above the N-type buried layer; first and second P-type wells disposed in spaced relation to each other between the N-type wells; and a P-type well over the P-type buried layer.
Preferably, in the fifth step, the polysilicon gate includes a polysilicon gate located at the upper right of the first P-type well and a polysilicon gate located at the upper left of the second P-type well.
Preferably, the operating voltage of the lightly doped ion implantation process in the step six is 5V.
Preferably, in the seventh step, the p+ region is connected to the polysilicon gate.
Preferably, the method further comprises a step of forming a side wall after the fifth step and before the sixth step.
The present invention also provides a zener diode comprising:
a substrate;
an N-type buried layer and a P-type buried layer which are positioned above the substrate;
an epitaxial layer located above the N-type buried layer and the P-type buried layer;
the shallow trench isolation structure, the PLDD region, the N+ region and the P+ region are positioned in the epitaxial layer;
the P-type wells are positioned at two sides of the PLDD region and connected with the N-type buried layer, the N-type wells are positioned at the outer sides of the P-type wells and connected with the N-type buried layer, and the P-type wells are positioned above the P-type buried layer; and
the polysilicon gate is positioned above the epitaxial layer and comprises a gate oxide layer, polysilicon and a side wall;
wherein an n+ region located in the PLDD region forms a PN junction of a zener diode with the PLDD region.
According to the invention, the PLDD region is formed in the epitaxial layer by adopting an ion implantation process, and the N+ region positioned in the PLDD region is formed at the same time of carrying out source-drain ion implantation, so that the PN junction of the zener diode is formed, the process is simple, the problem of overhigh mask process cost of the existing zener diode is solved, and the parasitic capacitance of the formed zener diode is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic structural diagram of a zener diode of the prior art;
fig. 2 is a flowchart showing a method for manufacturing a zener diode according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a zener diode according to an embodiment of the present invention;
fig. 4 shows a Breakdown Voltage (BV) test curve of a zener diode according to an embodiment of the present invention.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, the words "comprise," "comprising," and the like throughout the application are to be construed as including but not being exclusive or exhaustive; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
Fig. 1 is a schematic structural diagram of a zener diode of the prior art. As shown in fig. 1, the conventional Zener diode is generally implemented by adding a Zener implant, which requires adding an additional mask (mask) and a corresponding masking step, resulting in an increase in process cost, and a complicated and cumbersome implementation process. Therefore, the invention provides a novel zener diode and a manufacturing method thereof. The technical scheme of the invention is further described below by the specific embodiments with reference to the accompanying drawings.
Fig. 2 is a flowchart illustrating a method for manufacturing a zener diode according to an embodiment of the present invention. As shown in fig. 2, the manufacturing method of the zener diode in the embodiment of the invention includes the following steps:
providing a substrate, and forming an N-type buried layer and a P-type buried layer on the substrate.
The substrate may be any suitable substrate material, such as silicon, silicon-on-insulator, germanium, silicon carbide, silicon germanium, etc., or may be a substrate material having a semiconductor epitaxial layer such as silicon carbide epitaxially grown on a base. In the embodiment of the invention, the substrate is a P-type substrate.
In the embodiment of the invention, an N-type buried layer (NBL) injection region is defined through a photomask, and antimony (Sb) injection is performed; after the injection is finished, performing high-temperature push trap to form an N-type buried layer; then, a P-type buried layer (PBL) implantation region is defined by a photomask, boron (B) implantation is performed, and a P-type buried layer is formed by Rapid Thermal Annealing (RTA) treatment. The P-type buried layer is positioned on two sides of the N-type buried layer and surrounds the N-type buried layer.
And step two, forming an epitaxial layer above the N-type buried layer and the P-type buried layer.
And forming an epitaxial layer above the N-type buried layer and the P-type buried layer through an epitaxial growth process. Here, the epitaxial layer is a P-type epitaxial layer. The concentration and thickness of the epitaxial layer are determined by the withstand voltage of the device and the withstand voltage required for the isolation of the drain terminal.
And thirdly, forming a shallow trench isolation structure in the epitaxial layer.
In the embodiment of the invention, a groove is formed in an epitaxial layer by photoetching and etching, silicon dioxide is filled in the groove, and chemical mechanical polishing is carried out to form a shallow groove isolation structure. Specifically, depositing SiN, defining an active region through a photomask, etching SiN on the active region, etching Shallow Trench Isolation (STI), filling silicon dioxide (HTO), polishing by Chemical Mechanical Polishing (CMP), and removing SiN to form a shallow trench isolation structure.
And fourthly, photoetching and ion implantation are carried out on the epitaxial layer to form an N-type well and a P-type well.
And defining an N Well (NW) implantation region through a photomask, implanting phosphorus (P), pushing the well at high temperature after the implantation is completed to form an N well, defining a P Well (PW) implantation region through the photomask, and implanting boron to form a P well. The ion doping concentration of the well region needs to be reasonably designed according to the voltage withstand requirement and the on-resistance requirement of the device. In an embodiment of the present invention, an N-type well and a P-type well include: first and second N-type wells disposed above the N-type buried layer and spaced apart from each other, first and second P-type wells disposed between the N-type wells and spaced apart from each other, and a P-type well disposed above the P-type buried layer. It should be noted that the formation distribution of each region in the epitaxial layer in the embodiment of the present invention is only one of them, and may be other distributed epitaxial layers, which is not limited by the present invention.
And fifthly, depositing a gate oxide layer and polysilicon and etching to form a polysilicon gate.
In the embodiment of the invention, a gate oxide layer (GOX) can be grown through a thermal oxidation process, then polysilicon is deposited through a chemical vapor deposition process and the like, and then etching is performed. The formed polysilicon gate comprises a polysilicon gate positioned at the upper right of the first P-type well and a polysilicon gate positioned at the upper left of the second P-type well.
And step six, forming PLDD regions in the epitaxial layers between the polysilicon gates by using the polysilicon gates as masks and adopting a lightly doped ion implantation process.
In the embodiment of the invention, the working voltage of the lightly doped ion implantation process is 5V, the implantation energy of LDD ion implantation is 2-120KeV, the implantation dosage is 1E13-5E15Atom/cm < 3 >, and the implanted ions are P-type ions B, BF or In.
In the embodiment of the invention, the method further comprises a step of forming the side wall after the fifth step and before the sixth step.
And seventhly, performing source-drain ion implantation to form an N+ region and a P+ region, wherein the N+ region and the PLDD region in the PLDD region form a PN junction of the zener diode.
In the embodiment of the invention, source and drain ion implantation is carried out to form the N+ region and the P+ region of the source and drain ion implantation region, the N+ region and the PLDD region in the PLDD region form the PN junction of the zener diode, and the P+ region is connected with the polysilicon gate, so that the parasitic capacitance of the zener diode is reduced.
Fig. 3 is a schematic diagram of a zener diode according to an embodiment of the present invention. As shown in fig. 3, the zener diode of the embodiment of the present invention includes: the semiconductor device comprises a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, a Shallow Trench Isolation (STI), a P-type well, an N-type well, a PLDD region, an N+ region and a P+ region, and a polysilicon gate, wherein the N-type buried layer and the P-type buried layer are arranged above the substrate, the epitaxial layer is arranged above the N-type buried layer and the P-type buried layer, the Shallow Trench Isolation (STI), the P-type well, the N-type well, the PLDD region, the N+ region and the P+ region are arranged in the epitaxial layer, and the polysilicon gate is arranged above the epitaxial layer. The P-type well and the N-type well comprise P-type wells which are positioned at two sides of the PLDD region and connected with the N-type buried layer, N-type wells which are positioned at the outer sides of the P-type wells and connected with the N-type buried layer, and P-type wells positioned above the P-type buried layer. The polysilicon gate comprises a gate oxide layer, polysilicon and a side wall. In the embodiment of the invention, the N+ region and the PLDD region in the PLDD region form the PN junction of the zener diode, and the P+ region is connected with the polysilicon gate, so that the parasitic capacitance of the zener diode is reduced. As shown in fig. 4, a Breakdown Voltage (BV) test curve of the zener diode according to the embodiment of the present invention is shown. As can be seen from the figure, the test BV value of the zener diode formed by the method is about 5.55V, that is, the embodiment of the invention can realize the manufacture of the zener diode.
In summary, the PLDD region is formed in the epitaxial layer by adopting the ion implantation process, the source drain ion implantation is carried out to form the source drain region, and the N+ region positioned in the PLDD region is formed at the same time, so that the problem of overhigh mask process cost of the conventional zener diode is solved, and the manufacturing of the zener diode can be realized under the condition of simple process, so that the process can be simplified, and the method has great value.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method of manufacturing a zener diode, comprising the steps of:
providing a substrate, and forming an N-type buried layer and a P-type buried layer on the substrate;
step two, forming an epitaxial layer above the N-type buried layer and the P-type buried layer;
step three, forming a shallow trench isolation structure in the epitaxial layer;
step four, photoetching and ion implantation are carried out on the epitaxial layer to form an N-type well and a P-type well;
depositing a gate oxide layer and polysilicon and etching to form a polysilicon gate;
step six, forming PLDD regions in the epitaxial layers between the polysilicon gates by using the polysilicon gates as masks and adopting a lightly doped ion implantation process;
and seventhly, performing source-drain ion implantation to form an N+ region and a P+ region, wherein the N+ region positioned in the PLDD region and the PLDD region form a PN junction of the zener diode.
2. The method of manufacturing a zener diode of claim 1 wherein in step one the substrate is a P-type substrate.
3. The method of manufacturing a zener diode of claim 1, wherein the epitaxial layer is formed by an epitaxial growth process in step two.
4. The method of fabricating a zener diode as claimed in claim 1, wherein in step three, a trench is formed in the epitaxial layer by photolithography and etching, and then the trench is filled with silicon dioxide and chemically and mechanically polished to form the shallow trench isolation structure.
5. The method of manufacturing a zener diode of claim 1, wherein the N-type well and the P-type well in the fourth step comprise: first and second N-type wells spaced apart from each other above the N-type buried layer; first and second P-type wells disposed in spaced relation to each other between the N-type wells; and a P-type well over the P-type buried layer.
6. The method of manufacturing a zener diode of claim 5 wherein the polysilicon gate in step five comprises a polysilicon gate located at the upper right of the first P-well and a polysilicon gate located at the upper left of the second P-well.
7. The method of fabricating a zener diode of claim 1, wherein the operating voltage of the lightly doped ion implantation process in the sixth step is 5V.
8. The method of manufacturing a zener diode of claim 1 wherein in step seven the p+ region is connected to the polysilicon gate.
9. The method of manufacturing a zener diode of claim 1 further comprising the step of forming a sidewall after step five and before step six.
10. A zener diode formed by the method of manufacturing a zener diode according to any one of claims 1 to 9, comprising:
a substrate;
an N-type buried layer and a P-type buried layer which are positioned above the substrate;
an epitaxial layer located above the N-type buried layer and the P-type buried layer;
the shallow trench isolation structure, the PLDD region, the N+ region and the P+ region are positioned in the epitaxial layer;
the P-type wells are positioned at two sides of the PLDD region and connected with the N-type buried layer, the N-type wells are positioned at the outer sides of the P-type wells and connected with the N-type buried layer, and the P-type wells are positioned above the P-type buried layer; and
the polysilicon gate is positioned above the epitaxial layer and comprises a gate oxide layer, polysilicon and a side wall;
wherein an n+ region located in the PLDD region forms a PN junction of a zener diode with the PLDD region.
CN202310640708.2A 2023-05-31 2023-05-31 Zener diode and manufacturing method thereof Pending CN116598202A (en)

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Application Number Priority Date Filing Date Title
CN202310640708.2A CN116598202A (en) 2023-05-31 2023-05-31 Zener diode and manufacturing method thereof

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Application Number Priority Date Filing Date Title
CN202310640708.2A CN116598202A (en) 2023-05-31 2023-05-31 Zener diode and manufacturing method thereof

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CN116598202A true CN116598202A (en) 2023-08-15

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