CN116597763A - Display panel and display device - Google Patents

Abstract

The application provides a display panel and a display device, wherein a grid driving circuit of the display panel comprises a plurality of grid driving modules which are sequentially cascaded; each gate driving module comprises a first gate driving unit and a second gate driving unit; the second gate driving unit comprises a first switch piece, a first end of the first switch piece is connected with a low-level signal of the display panel, a second end of the first switch piece is connected with a corresponding pixel unit row to output a current-stage gate driving signal, a control end of the first switch piece receives a first starting signal, and the first starting signal is the current-stage gate driving signal provided by a later-stage gate driving module separated by one stage. The application reduces the size of the display device while guaranteeing the row driving capability of the display panel, effectively reduces the product cost and improves the user experience.

Description

Display panel and display device

Technical Field

The application relates to the technical field of screen display, in particular to a display panel and a display device.

Background

With the continuous development of electronic devices, the requirements of people on display pictures are also higher and higher, and an electric display screen is used as a light-emitting device for high-performance display; and the use of display devices with display panels is becoming more and more widespread. People put forward higher requirements on the performances of the display panel in various aspects such as size, definition and stability while the application of the display panel is more diversified.

In the course of conception and implementation of the present application, the inventors found that at least the following problems exist: the edge of the display panel needs to be provided with a gate driving circuit. For example, when each row of pixels of the display panel is scanned, a set of gate driving units with the same complexity are respectively arranged in the peripheral areas of two sides of each row of pixels by the gate driving circuit so as to charge the pixels of the corresponding row. With wider application range of display products with narrow frames, the excessive size of the gate driving circuit can restrict the further development of narrower frames of the display panel.

Disclosure of Invention

In view of the above technical problems, the present application provides a display panel, including a display area and a peripheral area surrounding the display area;

the display area comprises a plurality of pixel unit rows; a grid driving circuit is arranged in the peripheral area and comprises a plurality of grid driving modules which are sequentially cascaded;

each gate driving module comprises a first gate driving unit and a second gate driving unit, and each pixel unit row is connected between the first gate driving unit and the second gate driving unit;

the first grid driving unit comprises an input circuit, a pull-down circuit, an output circuit and a stabilizing circuit; the second gate driving unit comprises a first switch piece, a first end of the first switch piece is connected with a low-level signal of the display panel, a second end of the first switch piece is connected with a corresponding pixel unit row to output a current-stage gate driving signal, a control end of the first switch piece receives a first starting signal, and the first starting signal is the current-stage gate driving signal provided by a later-stage gate driving module separated by one stage.

Optionally, the second gate driving unit further includes a second switching element, a third switching element, and a fourth switching element;

the control end of the second switch piece is connected with the second end of the first switch piece and the second end of the third switch piece, the first end of the second switch piece is connected with the first end of the third switch piece and the first end of the fourth switch piece, and the second end of the second switch piece is connected with the control end of the third switch piece and the control end of the fourth switch piece so as to be connected with a high-level signal of a display panel; the second end of the fourth switch element is connected with the first end of the first switch element so as to access the low-level signal.

Optionally, the output circuit includes a fifth switch element and a first capacitor, and the first capacitor is connected between a control end and a second end of the fifth switch element;

the control end of the fifth switch element is connected with the input circuit through a first node, the first end of the fifth switch element is connected with a first clock signal, and the second end of the fifth switch element outputs the gate driving signal of the current stage.

Optionally, the input circuit includes a sixth switch element and a seventh switch element;

The control end and the first end of the sixth switch element receive the first starting signal; the first end of the seventh switch element is connected with a second clock signal, the control end of the seventh switch element receives a second starting signal, and the second starting signal is a current-stage gate driving signal provided by a previous-stage gate driving module separated by one stage;

the second end of the sixth switching element and the second end of the seventh switching element are connected with the first node.

Optionally, the pull-down circuit includes an eighth switch and a ninth switch;

the control ends of the eighth switch element and the ninth switch element are connected with the first node;

the first end of the eighth switch element and the first end of the ninth switch element are connected with the low-level signal, the second end of the eighth switch element is connected with the stabilizing circuit through a second node, and the second end of the ninth switch element is connected with the stabilizing circuit through a third node.

Optionally, the stabilizing circuit includes a tenth switch, an eleventh switch, a fourteenth switch and a fifteenth switch,

the first ends of the tenth switch element and the eleventh switch element are connected with the first node, and the second ends of the tenth switch element and the eleventh switch element are connected with the low-level signal;

The control end of the tenth switch piece is connected with the second node, and the control end of the eleventh switch piece is connected with the third node;

the control end and the second end of the fourteenth switching element are connected with the first control signal, the control end and the second end of the fifteenth switching element are connected with the second control signal, the first end of the fourteenth switching element is connected with the second node, and the first end of the fifteenth switching element is connected with the third node.

Optionally, the stabilizing circuit further includes a twelfth switching element and a thirteenth switching element, a control end of the twelfth switching element is connected to a first control signal, a control end of the thirteenth switching element is connected to a second control signal, a first end of the twelfth switching element is connected to the second node, a first end of the thirteenth switching element is connected to the third node, and a second end of the twelfth switching element and a second end of the thirteenth switching element are connected to the low-level signal.

Optionally, the stabilizing circuit further comprises a sixteenth switching element and a seventeenth switching element;

the first ends of the sixteenth switching element and the seventeenth switching element are connected with the current-stage grid driving signal, and the second ends of the sixteenth switching element and the seventeenth switching element are connected with the low-level signal;

The control end of the sixteenth switch element is connected with the second node, and the control end of the seventeenth switch element is connected with the third node.

Optionally, the output circuit further comprises a twentieth switching element; the control end of the twentieth switching element is connected with the first node, the first end of the twentieth switching element is connected with the first clock signal, and the second end of the twentieth switching element outputs a transmission signal.

Optionally, the stabilizing circuit further includes an eighteenth switch element and a nineteenth switch element;

the first ends of the eighteenth switching element and the nineteenth switching element are connected with the second end of the twentieth switching element, and the second ends of the eighteenth switching element and the nineteenth switching element are connected with the low-level signal;

the control end of the eighteenth switch element is connected with the second node, and the control end of the nineteenth switch element is connected with the third node.

Optionally, the first gate driving unit corresponding to each pixel unit row is disposed in a peripheral area on a first side of the display panel, and the second gate driving unit corresponding to each pixel unit row is disposed in a peripheral area on a second side of the display panel, where the first side and the second side are disposed opposite to each other on two sides of the display area.

Optionally, in the peripheral region of the first side of the display panel, the first gate driving units and the second gate driving units are alternately arranged in a preset alternating order;

in the peripheral area of the second side of the display panel, the first gate driving units and the second gate driving units are alternately arranged in an order corresponding to the preset alternating order, so that two sides of each pixel unit row respectively correspond to the first gate driving units and the second gate driving units.

Optionally, the preset alternating sequence is a one-to-one alternating mode, or the alternating sequence is a two-to-two alternating mode.

The present application also provides a display device including:

a data driving circuit for providing a plurality of gray-scale data;

the display area of the display panel has a plurality of pixel units arranged in an array and a plurality of gate lines and a plurality of data lines,

the display panel according to the above, wherein the gate driving circuit is capable of providing a plurality of gate driving signals;

the display panel receives the plurality of gate driving signals via the plurality of gate lines to select the plurality of pixel cells in a row, and receives the plurality of gray scale data in a column via the plurality of data lines to be supplied to the selected pixel cells to realize image display.

As described above, the display panel and the display device of the present application, by designing the first gate driving unit and the second gate driving unit corresponding to each pixel unit row, respectively correspond to the main charging circuit and the auxiliary charging circuit as the pixel unit rows, so that each row of pixels can mutually assist through different gate driving unit circuits, thereby effectively reducing the size of the display device while ensuring the row driving capability of the display panel, effectively reducing the product cost, and improving the user experience.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic diagram of a display panel according to an embodiment of the application.

Fig. 2 is a schematic diagram of an n-th stage gate driving module of a gate driving circuit according to an embodiment of the application.

Fig. 3 is a schematic circuit diagram of a second gate driving unit according to an embodiment of the application.

Fig. 4 is a schematic diagram of a first gate driving unit according to an embodiment of the application.

Fig. 5 is a schematic diagram of a first gate driving unit according to an embodiment of the application.

Fig. 6 is a schematic diagram of a first gate driving unit according to an embodiment of the application.

Fig. 7 is a schematic diagram of a first gate driving unit according to an embodiment of the application.

FIG. 8 is a timing diagram illustrating an embodiment of a gate driving circuit according to the present application.

Fig. 9 is a schematic diagram of a layout of a display panel according to an embodiment of the application.

Fig. 10 is a schematic diagram of a layout of a display panel according to an embodiment of the application.

Fig. 11 is a schematic diagram of a layout of a display panel according to an embodiment of the application.

The achievement of the objects, functional features and advantages of the present application will be further described with reference to the accompanying drawings, in conjunction with the embodiments. Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the application may have the same meaning or may have different meanings, the particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope herein. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context. Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, steps, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, steps, operations, elements, components, items, categories, and/or groups. The terms "or", "and/or", "including at least one of", and the like, as used herein, may be construed as inclusive, or mean any one or any combination. For example, "including at least one of: A. b, C "means" any one of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; a and B and C ", again as examples," A, B or C "or" A, B and/or C "means" any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; a and B and C). An exception to this definition will occur only when a combination of elements, functions, steps or operations are in some way inherently mutually exclusive.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

In the following description, suffixes such as "module", "part" or "unit" for representing elements are used only for facilitating the description of the present application, and have no specific meaning per se. Thus, "module," "component," or "unit" may be used in combination.

The following description will be given taking a mobile terminal as an example, and those skilled in the art will understand that the configuration according to the embodiment of the present application can be applied to a fixed type terminal in addition to elements particularly used for a moving purpose.

First embodiment

In view of the above technical problems, the present application provides a display panel, and fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application.

As shown in fig. 1, in an embodiment, the display panel PNL includes a display area AA and a peripheral area BB surrounding the display area.

The display area includes a plurality of pixel unit rows. In the display area AA, a pixel array and a pixel driving circuit PDC for driving the pixel array are provided. Each pixel in the pixel array may be a liquid crystal light valve or a self-luminous element. Each pixel emits light independently under the control of the pixel driving circuit PDC, thereby enabling the display panel PNL to display an image.

The display panel PNL may be a liquid crystal display panel or an LED display panel, for example. Taking a liquid crystal panel as an example, the liquid crystal display panel comprises an array substrate and a color film substrate which are correspondingly arranged, and liquid crystal molecules are filled in a liquid crystal box formed by the array substrate and the color film substrate, so that each pixel can be a liquid crystal unit serving as a light valve. Each liquid crystal cell comprises two electrodes for controlling the electric field and liquid crystals that deflect under the control of the electric field. One of the two electrodes may be a pixel electrode that supplies a pixel signal, and the other may be a common electrode. The common electrodes of the liquid crystal cells may be electrically connected to each other to commonly apply a common voltage. The pixel driving circuit PDC may be electrically connected to each pixel electrode in a one-to-one correspondence, so as to adjust an electric field of a region corresponding to the pixel electrode by controlling a voltage on the pixel electrode, thereby controlling a deflection degree of the liquid crystal of the region corresponding to the pixel electrode. Therefore, the light transmittance of each liquid crystal unit can be controlled by the PNL of the display panel under the cooperation of the upper polaroid and the lower polaroid. In another embodiment, the display panel PNL may be a display panel having self-luminous elements, which may be selected from OLED, PLED, QLED, Q-OLED, micro LED, mini LED, etc. The display panel PNL may include a substrate base plate BP, a driving layer, and a pixel layer, which are sequentially stacked. The light emitting element is disposed in the pixel layer as a sub-pixel, and a pixel driving circuit PDC for driving each pixel is disposed in the driving layer. The pixel driving circuit PDC can control the magnitude of the current flowing through the light emitting element, and thus control the light emitting luminance of the light emitting element.

And a grid driving circuit is arranged in the peripheral area and comprises a plurality of grid driving modules which are sequentially cascaded.

With continued reference to fig. 1, the display panel PNL may be further provided with scan lines GL extending in the row direction DH and driving data lines extending in the column direction DV, and the pixel driving circuit PDC may be electrically connected to the scan lines GL and the driving data lines. The pixel driving circuit PDC may receive driving data loaded on the driving data line under control of a scanning signal on the scanning line GL, and further control brightness of the sub-pixels according to the received driving data. For example, the pixel driving circuit PDC may include a data writing transistor having a control terminal electrically connected to the scan line GL and an input terminal electrically connected to the driving data line. When a scanning signal is applied to the scanning line GL, the data writing transistor is turned on, so that the driving data applied to the driving data line is written into the capacitor of the pixel driving circuit PDC. When the scanning line GL is not loaded with a scanning signal, the data writing transistor is electrically turned off, so that the driving data loaded on the driving data line cannot be written into the capacitor of the pixel driving circuit PDC.

Referring to fig. 1, a gate driving circuit GDC may be disposed at a peripheral region around the display region AA for loading scan signals to the respective scan lines GL. Alternatively, the gate driving circuit GDC is disposed on one side of the display area AA along the row direction DH, and may include a plurality of gate driving modules GOA cascaded in sequence, and each scan line GL may be electrically connected to an output terminal of one gate driving module GOA. Thus, when the shift register unit GOA outputs a scan signal, the scan signal may be loaded to the scan line GL. In the related art, the respective gate driving modules GOA in the gate driving circuit GDC are identical and are sequentially arranged in the column direction DV. However, this arrangement may cause a larger area occupied by the gate driving circuit GDC, and further may cause an increase in the frame of the display panel PNL, which is not beneficial to the narrowing of the frame of the display panel PNL.

Referring to fig. 1, in an embodiment, each gate driving module includes a first gate driving unit and a second gate driving unit, and each pixel unit row is connected between the first gate driving unit and the second gate driving unit.

By arranging the gate driving circuit GDC with two different gate driving units, namely a first gate driving unit GOAA and a second gate driving unit GOAB. Illustratively, the first gate driving units GOAA and the second gate driving units GOAB are spaced apart from each other in a cascade relationship.

Fig. 2 is a schematic diagram of an n-th stage gate driving module of a gate driving circuit according to an embodiment of the application.

Referring to fig. 2, the first gate driving unit GOAA includes an input circuit, a pull-down circuit, an output circuit and a stabilizing circuit; the second gate driving unit GOAB includes a first switch element T1, a first end of the first switch element T1 is connected to a low-level signal VGL of the display panel, a second end of the first switch element T1 is connected to a corresponding pixel unit row to output a current-stage gate driving signal Gn, a control end of the first switch element T1 receives a first start signal gn+2, and the first start signal is the current-stage gate driving signal provided by a post-stage gate driving module separated by one stage.

The first gate driving unit GOAA may have a conventional input circuit, pull-down circuit, output circuit and stabilizing circuit, thus having a rich and stable driving function, and also having a relatively large number of transistors for performing a main charging function for a corresponding pixel row. The second gate driving circuit GOAB is provided with a transistor as a first switch element for performing auxiliary charging for the corresponding pixel row. Therefore, by setting the main charging unit and the auxiliary charging unit for each column of pixel units, the first gate driving unit GOAA can be utilized to have rich functions and stabilizing effects brought by more switching elements, and the total number of switching elements required by the driving circuit GDC can be reduced by setting the second gate driving unit GOAB. The second gate driving unit GOAB can simultaneously inhibit noise of the first gate driving unit GOAA, so that stability of the current-stage gate driving signal Gn output by the gate driving module GOA is improved. The first grid driving unit is used for improving the working stability of the first grid driving unit, so that the problem of insufficient functions when the second grid driving unit GOAB is adopted is avoided. Therefore, each row of pixels can be mutually assisted through different grid driving unit circuits, the row driving capability of the display panel is guaranteed, the size of the display device is effectively reduced, the product cost is effectively reduced, and the user experience is improved.

Referring to fig. 2, the gate driving circuit of an embodiment includes a plurality of stages of gate driving modules as shown in fig. 2, and an nth stage of gate driving module is used for driving a corresponding gate line on the display panel. As shown in fig. 2, the first gate driving unit GOAA of the gate driving module of each stage includes a front stage signal input terminal 11, a rear stage signal input terminal 12, a second clock signal input terminal 13, a low level signal input terminal 14, and a present stage signal output terminal 15. The front-back stage signal input terminal 11 may be configured to receive the present stage gate driving signal and the present stage transfer signal of the front k stage or the back k stage gate driving unit, where k is a positive integer. In other embodiments, the front and rear signal inputs 11 may also be used to receive the enable signal. The first clock signal input 12 and the second clock signal input 13 may be used for receiving clock signals. The low level signal input terminal 14 is used for receiving the low level signal VGL. The present stage signal output terminal 15 is used for outputting the present stage gate driving signal Gn and the present stage transfer signal Zn. The present stage gate driving signal Gn is used for driving a gate line of a pixel row correspondingly connected to the nth stage gate driving display panel, and the present stage transfer signal Zn is used for controlling the precharge process of the next stage gate driving module.

In the first gate driving unit GOAA, an input circuit is connected to the front and rear stage signal input terminals 11 in fig. 2 for receiving the front k stage Gn-k or the rear k stage driving signal gn+k and the front k stage transfer signal Zn-k or the rear k stage transfer signal Zn-k, etc., as an example. The output end of the input circuit is connected with the first node Q and is used for precharging the first node Q according to the front and rear stage transmission signals of the front and rear stage driving signal stage. In one embodiment, the input circuit also receives the second clock signal CLK2 at the same time.

With continued reference to fig. 2, an output circuit is illustratively connected to the first node Q and the first clock signal input terminal 12 for outputting the received first clock signal CLK1 as the gate driving signal Gn and the transfer signal Zn according to the control voltage of the first node Q.

Illustratively, the pull-down circuit is connected to the first node Q, the low-level signal input terminal 14, and the stabilizing circuit to receive the control voltage of the first node Q and the low-level signal VGL, respectively, for providing the low-level signal VGL to the stabilizing circuit according to the control voltage of the first node Q.

The stabilizing circuit is connected to the control signal input terminal and the low level signal input terminal, and alternately supplies the low level signal VGL to the first node Q, the gate driving signal output terminal of the present stage, and the transfer signal output terminal of the present stage according to the control of the control signal.

Fig. 3 is a schematic circuit diagram of a second gate driving unit according to an embodiment of the application.

Referring to fig. 3, the second gate driving unit GOAB may further include a second switching element T2, a third switching element T3, and a fourth switching element T4.

The control end of the second switching element T2 is connected with the second end of the first switching element T1 and the second end of the third switching element T3, the first end of the second switching element T2 is connected with the first end of the third switching element T3 and the first end of the fourth switching element T4, and the second end of the second switching element T2 is connected with the control end of the third switching element T3 and the control end of the fourth switching element T4 so as to be connected with a high-level signal of the display panel; the second terminal of the fourth switching element T4 is connected to the first terminal of the first switching element T1 to switch in a low level signal.

The second switching element T2, the third switching element T3, and the fourth switching element T4 form a pull-down circuit of the second gate driving unit GOAB, which can enhance and suppress noise of the first gate driving unit GOAA, improve stability of the present-stage gate driving signal Gn output by the gate driving module GOA, and improve high-temperature stability of the gate driving module GOA, so that the product can adapt to a stricter high-temperature reliability test.

Fig. 4 is a schematic diagram of a first gate driving unit according to an embodiment of the application.

Referring to fig. 4, the output circuit optionally includes a fifth switch T5 and a first capacitor C. The first capacitor C is connected between the control terminal and the second terminal of the fifth switching element T5.

The control end of the fifth switch element T5 is connected with the input circuit through a first node, the first end of the fifth switch element T5 is connected with the first clock signal CLK1, and the second end of the fifth switch element T5 outputs the gate driving signal Gn of the current stage.

The first capacitor C is a parasitic capacitor between the control terminal and the second terminal of the fifth switch T5. It will be appreciated that in another embodiment, an independent capacitor may be provided between the control terminal and the second terminal of the fifth switching element T5, where the first capacitor C is the sum of the parasitic capacitor and the independent storage capacitor between the control terminal and the second path terminal of the fifth switching element T5. Referring to fig. 3, the output circuit is connected to the first node Q and the first clock signal input terminal 12 to output the gate driving signal Gn according to the control voltage of the first node Q and the received first clock signal CLK 1.

With continued reference to fig. 4, the input circuit optionally includes a sixth switch T6 and a seventh switch T7.

The control end and the first end of the sixth switch element T6 receive the first starting signal Gn-2; the first end of the seventh switch element T7 is connected with a second clock signal CLK2, the control end of the seventh switch element T7 receives a second starting signal Gn+2, and the second starting signal Gn+2 is a current stage gate driving signal provided by a previous stage gate driving module separated by one stage;

The second terminal of the sixth switching element T6 and the second terminal of the seventh switching element T7 are connected to the first node Q.

Illustratively, the input circuit has an input terminal receiving the first enable signal Gn-2, the second enable signal gn+2, and the second clock signal CLK2, and an output terminal coupled to the first node Q for precharging the first node Q in accordance with the first enable signal Gn-2, the second enable signal gn+2, and the second clock signal CLK 2.

With continued reference to fig. 4, the pull-down circuit may optionally include an eighth switch T8 and a ninth switch T9.

The control ends of the eighth switching element T8 and the ninth switching element T9 are connected to the first node Q.

The first end of the eighth switching element T8 and the first end of the ninth switching element T9 are connected to the low-level signal VGL, the second end of the eighth switching element T8 is connected to the stabilizing circuit through the second node QB2, and the second end of the ninth switching element T9 is connected to the stabilizing circuit through the third node QB 3.

Illustratively, the pull-down circuit pulls down the potential of the first node Q by connecting the second node QB2 and the third node QB3, thereby providing the low level signal VGL to the first node Q according to the control voltages of the second node QB2 and the third node QB 3.

With continued reference to fig. 4, the stabilizing circuit optionally includes a tenth switch T10, an eleventh switch T11, a fourteenth switch T14, and a fifteenth switch T15.

The first ends of the tenth and eleventh switching elements T10 and T11 are connected to the first node Q, and the second ends of the tenth and eleventh switching elements T10 and T11 are connected to the low-level signal VGL.

The control end of the tenth switching element T10 is connected to the second node QB2, and the control end of the eleventh switching element T11 is connected to the third node QB3.

The control end and the second end of the fourteenth switching element T14 are connected with a first control signal V1, the control end and the second end of the fifteenth switching element T15 are connected with a second control signal V2, the first end of the fourteenth switching element T14 is connected with a second node QB2, and the first end of the fifteenth switching element T15 is connected with a third node QB3.

Fig. 5 is a schematic diagram of a first gate driving unit according to an embodiment of the application.

Referring to fig. 5, the stabilizing circuit may further include a twelfth switching element T12 and a thirteenth switching element T13, for example. The control end of the twelfth switching element T12 is connected to the first control signal V1, the control end of the thirteenth switching element T13 is connected to the second control signal V2, the first end of the twelfth switching element T12 is connected to the second node QB2, the first end of the thirteenth switching element T13 is connected to the third node QB3, and the second ends of the twelfth switching element T12 and the thirteenth switching element T13 are connected to the low-level signal VGL.

The stabilizing circuit may supply the low level signal VGL to the first node Q according to the first control signal V2 and the second control signal V3 to stabilize the signal of the first node Q.

Fig. 6 is a schematic diagram of a first gate driving unit according to an embodiment of the application.

Referring to fig. 6, the stabilizing circuit may further include a sixteenth switching element T16 and a seventeenth switching element T17.

The first ends of the sixteenth and seventeenth switching elements T16 and T17 are connected to the gate driving signal Gn of the present stage, and the second ends of the sixteenth and seventeenth switching elements T16 and T17 are connected to the low level signal VGL.

The control terminal of the sixteenth switching element T16 is connected to the second node QB2, and the control terminal of the seventeenth switching element T17 is connected to the third node QB3.

Illustratively, the stabilizing circuit supplies the low level signal VGL to the gate driving signal Gn of the present stage according to the first control signal V2 and the second control signal V3 through the sixteenth switching element T16 and the seventeenth switching element T17 to stabilize the signal of the gate driving signal Gn of the present stage.

Fig. 7 is a schematic diagram of a first gate driving unit according to an embodiment of the application.

As shown in fig. 7, the output circuit may optionally further include a twentieth switching element T20. The control end of the twentieth switching element T20 is connected to the first node Q, the first end of the twentieth switching element T20 is connected to the first clock signal CLK1, and the second end of the twentieth switching element T20 outputs the transfer signal Zn.

The output circuit receives the first clock signal through the twentieth switching element T20, and outputs the pass signal Zn according to the control voltage of the first node Q, for example.

Optionally, the stabilizing circuit further comprises an eighteenth switching element T18 and a nineteenth switching element T19.

The first ends of the eighteenth and nineteenth switching elements T18 and T19 are connected to the second end of the twentieth switching element T20, and the second ends of the eighteenth and nineteenth switching elements T18 and T19 are connected to the low-level signal VGL.

The control terminal of the eighteenth switching element T18 is connected to the second node QB2, and the control terminal of the nineteenth switching element T19 is connected to the third node QB3.

Illustratively, the stabilizing circuit outputs the low level signal VGL to the second terminal of the twentieth switching element T20 according to the control signals of the second node QB2 and the third node QB3 through the eighteenth switching element T18 and the nineteenth switching element T19 to stabilize the output signal of the pass signal Zn.

With continued reference to fig. 7, alternatively, the eighth switching element T8, the ninth switching element T9, the tenth switching element T10, the eleventh switching element T11, the twelfth switching element T12 and the thirteenth switching element T13 may be replaced by the predetermined voltage signal VSQ instead of the low level signal VGL. Exemplary, the preset voltage signal VSQ may be a negative voltage.

FIG. 8 is a timing diagram illustrating an embodiment of a gate driving circuit according to the present application.

As shown in fig. 8, the first clock signal CLK1 and the second clock signal CLK2 are square wave signals. The system may also set the third clock signal CLK3 and the fourth clock signal CLK4 as required by the system. Illustratively, the clock period is 4T and the duty cycle is 1/2.T is a predetermined clock period, such as the minimum clock period or an integer multiple of the minimum clock period of the system clock signal. The first clock signal CLK1 is 1/4T earlier than the second clock signal CLK 2. The first control signal V1 is a high-low level signal, and the second control signal V2 is a high-low level signal, wherein the first control signal V1 and the second control signal V2 change simultaneously and the changing directions are opposite.

According to the grid driving circuit, through sequential cascading, when one grid driving module charges a pixel row, the pixels separated by one stage are precharged, the number of grid lines which are opened simultaneously is reduced, overlapping periods of waveforms output by adjacent grid driving units are reduced, the phenomenon of transverse lines in display can be avoided, and the display quality of a display panel is improved.

The first to twentieth switching elements T1 to T20 may be implemented by using switching elements such as amorphous silicon TFTs, oxide TFTs, or low-temperature polysilicon N-TFTs, as the case may be. For example, in the embodiment of the present application, the first to twentieth switching elements T1 to T20 may be N-type thin film transistors, and the drain and gate of each transistor may be interchanged, but the present application is not limited thereto.

In this embodiment, by designing the first gate driving unit and the second gate driving unit corresponding to each pixel unit row, the main charging circuit and the auxiliary charging circuit corresponding to each pixel unit row are respectively used, so that each row of pixels can mutually assist through different gate driving unit circuits, the row driving capability of the display panel is ensured, the size of the display device is effectively reduced, the product cost is effectively reduced, and the user experience is improved.

Second embodiment

The application further provides a layout mode of the display panel on the basis of the first embodiment. Fig. 9 is a schematic diagram of a layout of a display panel according to an embodiment of the application.

Optionally, the first gate driving units corresponding to each pixel unit row are disposed in a peripheral area on the first side of the display panel, and the second gate driving units corresponding to each pixel unit row are disposed in a peripheral area on the second side of the display panel, where the first side and the second side are disposed opposite to each other on two sides of the display area.

As shown in fig. 9, alternatively, the first gate driving unit corresponding to each pixel unit row is a unit a, and is disposed in the peripheral area on the left side of the display panel, and the second gate driving unit corresponding to each pixel unit row is a unit B, and is disposed in the peripheral area on the right side of the display panel. As can be seen from the first embodiment, since the components of the unit B are fewer, the occupied area of the unit B can be smaller, so that the area of the peripheral area on the second side of the display panel can be effectively reduced, which is beneficial to the narrow-edge design of the display device.

Alternatively, the first gate driving units and the second gate driving units are alternately arranged in a preset alternating order in the peripheral region of the first side of the display panel.

In the peripheral region of the second side of the display panel, the first gate driving units and the second gate driving units are alternately arranged in an order corresponding to a preset alternating order, so that both sides of each pixel unit row respectively correspond to the first gate driving units and the second gate driving units.

Fig. 10 is a schematic diagram of a layout of a display panel according to an embodiment of the application. Fig. 11 is a schematic diagram of a layout of a display panel according to an embodiment of the application.

Referring to fig. 10, alternatively, the preset alternating sequence is a one-to-one alternating manner. Referring to fig. 11, alternatively, the alternating sequence is a two-by-two alternating manner.

The unit A and the unit B are arranged alternately in sequence by presetting the alternating sequence, so that the circuit characteristics of the unit A and the unit B can be effectively combined, and the combination design is a layout mode which saves layout area more, thereby effectively reducing the peripheral area of the display panel and being beneficial to the narrow-edge design of the display device. It should be noted that the present application is not limited to these arrangements, but may be other arrangements of a plurality of switch elements, and the display panel may be selected in an appropriate alternating order according to the specific situation.

Third embodiment

The present application also provides a display device including:

and the data driving circuit is used for providing a plurality of gray-scale data.

The display area of the display panel has a plurality of pixel units arranged in an array, a plurality of gate lines and a plurality of data lines.

The display panel according to the above, wherein the gate driving circuit is capable of providing a plurality of gate driving signals.

The display panel receives a plurality of gate driving signals via a plurality of gate lines to select a plurality of pixel cells in a row, and receives a plurality of gray scale data in a column via a plurality of data lines to be supplied to the selected pixel cells to realize image display.

In the display device provided by the application, the grid driving circuit can work by two clock signals and two control signals, so that the number of signal wires and the load of the signal wires are reduced, the required wiring area is reduced, the design of a narrow frame is facilitated, and the power consumption of the circuit is reduced.

In the display device provided by the application, the transmission signal of the gate driving circuit and the gate driving signal are output through different terminals, so that the influence of signal transmission on gate driving is reduced, and the output capacity of the gate driving unit is high.

In a preferred embodiment of the display device, a gate driving circuit capable of bidirectional scanning is provided, which has two modes of forward scanning and backward scanning, and can increase the degree of freedom of use of the display panel, and provide an elastic driving mode for the display device.

As described above, the display panel and the display device of the present application, by designing the first gate driving unit and the second gate driving unit corresponding to each pixel unit row, respectively correspond to the main charging circuit and the auxiliary charging circuit as the pixel unit rows, so that each row of pixels can mutually assist through different gate driving unit circuits, thereby effectively reducing the size of the display device while ensuring the row driving capability of the display panel, effectively reducing the product cost, and improving the user experience.

The foregoing is merely a reference example, and in order to avoid redundancy, it is not necessary to use any combination in practical development or application, but any combination belongs to the technical solution of the present application, and is covered in the protection scope of the present application.

It can be understood that the above scenario is merely an example, and does not constitute a limitation on the application scenario of the technical solution provided by the embodiment of the present application, and the technical solution of the present application may also be applied to other scenarios. For example, as one of ordinary skill in the art can know, with the evolution of the system architecture and the appearance of new service scenarios, the technical solution provided by the embodiment of the present application is also applicable to similar technical problems.

The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The units in the device of the embodiment of the application can be combined, divided and deleted according to actual needs.

In the present application, the same or similar term concept, technical solution and/or application scenario description will be generally described in detail only when first appearing and then repeatedly appearing, and for brevity, the description will not be repeated generally, and in understanding the present application technical solution and the like, reference may be made to the previous related detailed description thereof for the same or similar term concept, technical solution and/or application scenario description and the like which are not described in detail later.

In the present application, the descriptions of the embodiments are emphasized, and the details or descriptions of the other embodiments may be referred to.

The technical features of the technical scheme of the application can be arbitrarily combined, and all possible combinations of the technical features in the above embodiment are not described for the sake of brevity, however, as long as there is no contradiction between the combinations of the technical features, the application shall be considered as the scope of the description of the application.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as above, comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, a controlled terminal, or a network device, etc.) to perform the method of each embodiment of the present application.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable devices. The computer instructions may be stored in a storage medium or transmitted from one storage medium to another storage medium, for example, from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.) means. The storage media may be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains an integration of one or more available media. Usable media may be magnetic media (e.g., floppy disks, storage disks, magnetic tape), optical media (e.g., DVD), or semiconductor media (e.g., solid State Disk (SSD)), among others.

The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims (10)

1. A display panel comprising a display area and a peripheral area surrounding the display area;

the display area comprises a plurality of pixel unit rows; a grid driving circuit is arranged in the peripheral area and comprises a plurality of grid driving modules which are sequentially cascaded;

each gate driving module comprises a first gate driving unit and a second gate driving unit, and each pixel unit row is connected between the first gate driving unit and the second gate driving unit;

the first grid driving unit comprises an input circuit, a pull-down circuit, an output circuit and a stabilizing circuit; the second gate driving unit comprises a first switch piece, a first end of the first switch piece is connected with a low-level signal of the display panel, a second end of the first switch piece is connected with a corresponding pixel unit row to output a current-stage gate driving signal, a control end of the first switch piece receives a first starting signal, and the first starting signal is the current-stage gate driving signal provided by a later-stage gate driving module separated by one stage.

2. The display panel of claim 1, wherein the second gate driving unit further comprises a second switching element, a third switching element, and a fourth switching element;

the control end of the second switch piece is connected with the second end of the first switch piece and the second end of the third switch piece, the first end of the second switch piece is connected with the first end of the third switch piece and the first end of the fourth switch piece, and the second end of the second switch piece is connected with the control end of the third switch piece and the control end of the fourth switch piece so as to be connected with a high-level signal of a display panel; the second end of the fourth switch element is connected with the first end of the first switch element so as to access the low-level signal.

3. The display panel of claim 2, wherein the output circuit comprises a fifth switching element and a first capacitor, the first capacitor being connected between a control terminal and a second terminal of the fifth switching element,

the control end of the fifth switch element is connected with the input circuit through a first node, the first end of the fifth switch element is connected with a first clock signal, and the second end of the fifth switch element outputs the gate driving signal of the current stage; and/or

The input circuit comprises a sixth switch element and a seventh switch element, and a control end and a first end of the sixth switch element receive the first starting signal; the first end of the seventh switch element is connected with a second clock signal, the control end of the seventh switch element receives a second starting signal, and the second starting signal is a current-stage gate driving signal provided by a previous-stage gate driving module separated by one stage;

the second end of the sixth switch element and the second end of the seventh switch element are connected with the first node; and/or

The pull-down circuit comprises an eighth switch piece and a ninth switch piece, the control ends of the eighth switch piece and the ninth switch piece are connected with the first node, the first end of the eighth switch piece and the first end of the ninth switch piece are connected with the low-level signal, the second end of the eighth switch piece is connected with the stabilizing circuit through a second node, and the second end of the ninth switch piece is connected with the stabilizing circuit through a third node.

4. The display panel of claim 3, wherein the stabilizing circuit includes a tenth switching element, an eleventh switching element, a fourteenth switching element, and a fifteenth switching element,

The first ends of the tenth switch element and the eleventh switch element are connected with the first node, and the second ends of the tenth switch element and the eleventh switch element are connected with the low-level signal;

the control end of the tenth switch piece is connected with the second node, and the control end of the eleventh switch piece is connected with the third node;

the control end and the second end of the fourteenth switching element are connected with a first control signal, the control end and the second end of the fifteenth switching element are connected with a second control signal, the first end of the fourteenth switching element is connected with the second node, and the first end of the fifteenth switching element is connected with the third node.

5. The display panel of claim 4, wherein the stabilizing circuit further comprises a twelfth switching element and a thirteenth switching element, a control terminal of the twelfth switching element being connected to the first control signal, a control terminal of the thirteenth switching element being connected to the second control signal, a first terminal of the twelfth switching element being connected to the second node, a first terminal of the thirteenth switching element being connected to the third node, a second terminal of the twelfth switching element and the thirteenth switching element being connected to the low level signal; and/or the number of the groups of groups,

The stabilizing circuit further comprises a sixteenth switching element and a seventeenth switching element, wherein first ends of the sixteenth switching element and the seventeenth switching element are connected with the current-stage gate driving signal, and second ends of the sixteenth switching element and the seventeenth switching element are connected with the low-level signal;

the control end of the sixteenth switch element is connected with the second node, and the control end of the seventeenth switch element is connected with the third node.

6. The display panel of claim 5, wherein,

the output circuit further includes a twentieth switching element; the control end of the twentieth switching element is connected with the first node, the first end of the twentieth switching element is connected with the first clock signal, and the second end of the twentieth switching element outputs a transmission signal.

7. The display panel of claim 6, wherein,

the stabilizing circuit further comprises an eighteenth switch element and a nineteenth switch element;

the first ends of the eighteenth switching element and the nineteenth switching element are connected with the second end of the twentieth switching element, and the second ends of the eighteenth switching element and the nineteenth switching element are connected with the low-level signal;

The control end of the eighteenth switch element is connected with the second node, and the control end of the nineteenth switch element is connected with the third node.

8. The display panel of any one of claims 1-7, wherein the first gate drive unit corresponding to each pixel cell row is disposed in a peripheral region of a first side of the display panel, and the second gate drive unit corresponding to each pixel cell row is disposed in a peripheral region of a second side of the display panel, wherein the first side is disposed opposite the second side on both sides of the display region; and/or the number of the groups of groups,

the first grid driving units and the second grid driving units are alternately arranged in a preset alternating sequence in a peripheral area of the first side of the display panel;

in the peripheral area of the second side of the display panel, the first gate driving units and the second gate driving units are alternately arranged in an order corresponding to the preset alternating order, so that two sides of each pixel unit row respectively correspond to the first gate driving units and the second gate driving units.

9. The display panel of claim 8, wherein the predetermined alternating sequence is one-to-one alternating or the alternating sequence is two-by-two alternating.

10. A display device, characterized in that the display device comprises:

a data driving circuit for providing a plurality of gray-scale data;

the display area of the display panel has a plurality of pixel units arranged in an array and a plurality of gate lines and a plurality of data lines,

the display panel according to any one of claims 1-9, wherein the gate driving circuit is capable of providing a plurality of gate driving signals;

the display panel receives the plurality of gate driving signals via the plurality of gate lines to select the plurality of pixel cells in a row, and receives the plurality of gray scale data in a column via the plurality of data lines to be supplied to the selected pixel cells to realize image display.