CN116594715A - FPGA-based data processing and unloading method, FPGA, CPU and system - Google Patents

FPGA-based data processing and unloading method, FPGA, CPU and system Download PDF

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Publication number
CN116594715A
CN116594715A CN202310870029.4A CN202310870029A CN116594715A CN 116594715 A CN116594715 A CN 116594715A CN 202310870029 A CN202310870029 A CN 202310870029A CN 116594715 A CN116594715 A CN 116594715A
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data packet
cpu
fpga
data
packet
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CN116594715B (en
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田源
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China Telecom Corp Ltd
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China Telecom Corp Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44594—Unloading
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The disclosure provides a data processing and unloading method based on an FPGA, the FPGA, a CPU and a data processing and unloading system based on the FPGA, and belongs to the technical field of communication. In the method, when a first data packet sent by a CPU is received in the FPGA, the first data packet can be encrypted by the FPGA under the condition that the first data packet is of a first packet type, and the first packet type is obtained by changing the type of the data packet under the condition that the CPU accords with a first hardware unloading condition, so that the FPGA can unload a first data packet related processing task of the first packet type to hardware for execution, the load pressure of the CPU in the data processing process is effectively reduced in a soft-hard combination mode, the occupation of resources can be reasonably distributed, the task processing time is reduced, and the communication efficiency of the whole data network is further improved.

Description

FPGA-based data processing and unloading method, FPGA, CPU and system
Technical Field
The disclosure belongs to the technical field of communication, and particularly relates to a data processing and unloading method based on an FPGA, the FPGA, a CPU and a data processing and unloading system based on the FPGA.
Background
The HTTP/3 protocol (HyperText Transfer Protocol/3, third generation hypertext transfer protocol) adopts QUIC (Quick UDP Internet Connections, fast UDP network connection) protocol based on UDP protocol (User Datagram Protocol ), and single data stream transmitted under multiplexing condition can ensure orderly delivery without affecting transmission of other data streams, thereby avoiding problem of blocking head of subsequent data stream when single data stream transmission based on TCP protocol of HTTP/2 protocol is retransmitted, and effectively improving data stream transmission efficiency.
However, the QUIC protocol based data transmission under the HTTP/3 protocol avoids blocking the queue head, and also causes high load operation of the CPU, which results in high resource occupation, and may increase task processing time, thereby affecting overall data network communication efficiency.
Disclosure of Invention
The embodiment of the disclosure aims to provide a data processing and unloading method based on an FPGA, the FPGA, a CPU and a data processing and unloading system based on the FPGA, which can asynchronously and dynamically unload data processing of a QUIC protocol to the FPGA, so that the load pressure of the CPU is relieved, the occupation of resources can be reasonably distributed, the task processing time is reduced, and the communication efficiency of an overall data network is further improved.
In order to solve the above technical problems, the present disclosure is implemented as follows:
in a first aspect, the present disclosure provides a method for FPGA-based data processing offloading, the method being applied to a field programmable gate array FPGA, the method may include: receiving a first data packet sent by a CPU, wherein the CPU communicates based on a QUIC protocol; and carrying out encryption processing on the first data packet under the condition that the first data packet is of a first packet type, wherein the first packet type is obtained by modifying the CPU under the condition that the first hardware unloading condition is met.
Optionally, before receiving the first data packet sent by the CPU, the method further includes: and when the CPU is determined to establish the QUIC connection, sending a notification parameter to the CPU, wherein the notification parameter is used for indicating that the unloading of the FPGA is available.
Optionally, the method further comprises: receiving a second data packet; under the condition that the second data packet is an encrypted data packet and meets a second hardware unloading condition, decrypting the second data packet and changing the second data packet into a second packet type; and sending the decrypted second data packet to the CPU.
Optionally, the first hardware offload condition includes at least one of:
the first data packet is configured to be forcibly offloaded;
the load of the CPU is greater than or equal to the offload threshold.
Optionally, the first hardware offload condition further includes:
offloading of the FPGA is available.
In a second aspect, the present disclosure further provides a data processing offloading method based on an FPGA, the method being applicable to a CPU, the method may include: changing the first data packet to a first packet type if the first hardware unloading condition is met; and sending a first data packet to the FPGA, and communicating by the CPU based on the QUIC protocol.
Optionally, before changing the first data packet to the first packet type if the hardware offload condition is met, further comprises: upon receiving the notification parameters, it is determined that offloading of the FPGA is available.
Optionally, the method further comprises: receiving a second data packet sent by the FPGA; and in the case that the second data packet is a decryption data packet and the second data packet is of a second packet type, performing unpacking processing on the second data packet.
In a third aspect, the present disclosure also provides an FPGA, which may include: the first data receiving module is used for receiving a first data packet sent by the CPU, and the CPU communicates based on the QUIC protocol; the first data unloading module is used for carrying out encryption processing on the first data packet under the condition that the first data packet is of a first packet type, and the first packet type is obtained by the CPU through modification under the condition that the first hardware unloading condition is met.
Optionally, the FPGA may further include a second data sending module, configured to send a notification parameter to the CPU when it is determined that the CPU establishes the quitc connection, where the notification parameter is used to indicate that unloading of the FPGA is available.
Optionally, the first data receiving module is further configured to receive a second data packet;
the first data unloading module is further configured to decrypt the second data packet and change the second data packet to be of a second packet type when the second data packet is an encrypted data packet and meets a second hardware unloading condition;
The second data sending module is further used for sending the decrypted second data packet to the CPU.
Optionally, the first hardware offload condition includes at least one of:
the first data packet is configured to be forcibly offloaded;
the load of the CPU is greater than or equal to the offload threshold.
Optionally, the first hardware offload condition further includes:
offloading of the FPGA is available.
In a fourth aspect, the present disclosure also provides a CPU, which may include: the second data unloading module is used for changing the first data packet into a first packet type under the condition that the first hardware unloading condition is met; and the first data transmission module is used for transmitting a first data packet to the FPGA, and the CPU is communicated based on the QUIC protocol.
Optionally, the CPU may further include a second data receiving module configured to determine that unloading of the FPGA is available if the notification parameter is received.
Optionally, the second data receiving module is further configured to receive a second data packet sent by the FPGA;
and the second data receiving module is further used for unpacking the second data packet when the second data packet is a decryption data packet and the second data packet is of a second packet type.
In a fifth aspect, the present disclosure also provides an FPGA-based data processing offload system that may include an FPGA in communication with a CPU that is based on a QUIC protocol, wherein the CPU includes: the second data unloading module is used for changing the first data packet into a first packet type under the condition that the first hardware unloading condition is met; the first data sending module is used for sending a first data packet to the FPGA;
The FPGA comprises: the first data receiving module is used for receiving a first data packet sent by the CPU; the first data unloading module is used for carrying out encryption processing on the first data packet under the condition that the first data packet is of a first packet type, and the first packet type is obtained by the CPU through modification under the condition that the first hardware unloading condition is met.
In a sixth aspect, the present disclosure provides an electronic device comprising a processor, a memory, and a program or instruction stored on the memory and executable on the processor, which when executed by the processor, implements the steps of the FPGA-based data processing offload method as previously described.
In a seventh aspect, the present disclosure provides a readable storage medium having stored thereon a program or instructions which when executed by a processor perform the steps of the FPGA-based data processing offload method described above.
In an eighth aspect, the present disclosure provides a chip comprising a processor and a communication interface, the communication interface being coupled to the processor for running programs or instructions implementing the steps of the FPGA-based data processing offload method as described above.
In a ninth aspect, the present disclosure provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the steps of implementing the FPGA-based data processing offload method as described above.
The data processing and unloading method based on the FPGA is applied to the FPGA, when the first data packet sent by the CPU is received, the first data packet can be encrypted by the FPGA under the condition that the first data packet is of a first packet type, the first packet type is obtained by changing the type of the data packet under the condition that the CPU accords with a first hardware unloading condition, so that the FPGA can unload a first data packet related processing task of the first packet type to hardware for execution, the load pressure of the CPU in a data processing process is effectively reduced in a mode of combining soft and hard, the occupation of resources can be reasonably distributed, the task processing time is reduced, and the communication efficiency of the whole data network is further improved.
Drawings
Fig. 1 is one of the step flowcharts of the FPGA-based data processing offloading method provided in the embodiment of the present disclosure.
Fig. 2 is a second flowchart of steps of an FPGA-based data processing offloading method according to an embodiment of the present disclosure.
FIG. 3 is a third flowchart illustrating steps of an FPGA-based data processing offloading method according to an embodiment of the present disclosure.
Fig. 4 is an interactive flowchart of an FPGA-based data processing offloading method according to an embodiment of the present disclosure.
Fig. 5 is a block diagram of an FPGA according to an embodiment of the present disclosure.
Fig. 6 is a block diagram of a CPU according to an embodiment of the present disclosure.
Fig. 7 is a schematic diagram of an example of a collaboration flow of data transmission in an FPGA-based data processing offload system according to an embodiment of the present disclosure.
Fig. 8 is a schematic diagram of an example of a collaboration flow of initialization data in an FPGA-based data processing and offloading system according to an embodiment of the present disclosure.
Fig. 9 is a schematic diagram of a collaboration flow of data reception in an FPGA-based data processing offload system according to an embodiment of the present disclosure.
Fig. 10 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.
Fig. 11 is a hardware schematic of an electronic device according to an embodiment of the disclosure.
Detailed Description
The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, where appropriate, such that embodiments of the disclosure may be practiced in sequences other than those illustrated and described herein, and that the objects identified by "first," "second," etc. are generally of the same type and are not limited to the number of objects, e.g., the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The QUIC protocol mentioned in the disclosure has different standards in application at present, and the problem of larger performance difference of a connection library, especially the QUIC protocol also internally realizes the TLS1.3 encryption protocol, so that data packets almost need encryption and decryption in transmission, and the problem of higher load pressure of a CPU is caused. In the background of increasing network service demands, the data stream transmission amount is increased, and higher requirements are also put on the efficiency and performance of the CPU.
Therefore, the present disclosure provides a data processing and offloading method (Field Programmable Gate Array ) based on an FPGA, an FPGA supporting the method, a CPU, and a system including the FPGA and the CPU, in which the FPGA dynamically offload a quitc protocol based on a packet type provided by the CPU in a soft-hard combination manner, so as to reasonably reduce CPU consumption, improve data transmission efficiency, and enhance communication network quality.
The data processing and unloading method based on the FPGA provided by the embodiment of the disclosure is described in detail below through specific embodiments and application scenes thereof with reference to the accompanying drawings.
Fig. 1 is one of the step flowcharts of the FPGA-based data processing offloading method provided in the embodiment of the present disclosure. The method can be applied to an FPGA.
The FPGA is an integrated circuit with programmable characteristics, can flexibly meet design requirements, can better adapt to the development process of a communication network, meets the standardized current situation of the QUIC protocol, and can be reused in a production environment and has low cost due to the matching of the change of the protocol.
As shown in fig. 1, the method may include the following steps 101 to 102.
And step 101, receiving a first data packet sent by the CPU, wherein the CPU communicates based on the QUIC protocol.
In the embodiment of the disclosure, the FPGA may offload the task of performing data processing on the CPU based on the QUIC protocol communication, where the data processing may include encryption and decryption of the data packet, or unpacking and packing. The FGPA may receive the first data packet sent by the CPU and further determine whether the first data packet is being processed at the FGPA.
Step 102, performing encryption processing on the first data packet when the first data packet is of a first packet type, wherein the first packet type is obtained by modifying the first data packet when the first hardware unloading condition is met by the CPU.
In the embodiment of the disclosure, the packets with different processing manners may be distinguished by the packet type, for example, when the first packet is of the first packet type, the FGPA performs offloading, may perform encryption processing on the first packet, and when the first packet is of another packet type, the FGPA may perform other actions, or may not perform processing on the first packet.
The first packet type is obtained by modifying a CPU under the condition that the first hardware offload condition is met, the first hardware offload condition may be an independent or comprehensive evaluation condition for various parameters such as a CPU state, a communication state, a data type, etc., and under the condition that the first hardware offload condition is met, it is indicated that performing offload on the first data packet by the FGPA can improve overall communication efficiency, so that the CPU may modify the packet type of the first data packet into the first packet type, so that the FGPA, when receiving the first data packet, can determine to perform offload according to the packet type of the first data packet, and encrypt the first data packet and then send out the first data packet.
In an optional method embodiment of the present disclosure, during a data transmission process between network nodes, when the FGPA configured by the transmitting end sends out an encrypted first data packet, a packet type of the first data packet may be further changed, so that when the FGPA configured by the receiving end receives the first data packet, it may be determined that unloading is performed on the first data packet, and decryption processing is performed by the FGPA configured by the receiving end.
In the embodiment of the disclosure, the first data packet may not meet the first hardware unloading condition, and at this time, performing unloading by using FGPA may not improve the overall communication efficiency or may cause efficiency reduction, or may also cause an influence such as an increase in energy consumption. At this time, the CPU may encrypt the first data packet and does not change the packet type of the first data packet, so that when the FGPA receives the first data packet that has the packet type that is the initial packet type and is encrypted, the first data packet may be directly sent out, without performing offloading to process the first data packet.
Fig. 2 is a second flowchart of steps of an FPGA-based data processing offloading method according to an embodiment of the present disclosure. The method may be applied to an FPGA, as shown in fig. 2, and may include the following steps 201 to 206:
step 201, when it is determined that the CPU establishes the quitc connection, a notification parameter is sent to the CPU, where the notification parameter is used to indicate that unloading of the FPGA is available.
In the embodiment of the disclosure, the network node configured with the CPU may perform data transmission with another network node based on the quench protocol, and when a communication connection is established between the network nodes, the CPU may initiate a flow of quench connection establishment to the other network node, and at this time, the FPGA configured with the network node may transmit related data packets of quench connection. The FPGA does not process the relevant data packets of the QUIC connection, but may determine that the CPU establishes the QUIC connection based on the relevant data packets of the QUIC connection, thereby triggering the sending of notification parameters to the CPU to indicate to the CPU that offloading of the FPGA is available.
In the embodiment of the disclosure, in practical application, there may be a case that the network node is not configured with the FPGA and cannot execute the hardware offloading function, so that a notification parameter may be sent by the FPGA when the quitc connection is established, so that the CPU may determine whether the offloading of the FPGA is available. When hardware uninstallation of the QUIC protocol is available, the CPU can timely start related functions to integrally improve communication efficiency; when hardware is changed by the network node to cause unavailability of hardware uninstallation of the QUIC protocol, CPU execution logic is not required to be modified, data processing can be normally performed on the basis of determining unavailability of hardware uninstallation, and efficiency of hardware replacement and upgrading of the network node is improved.
For example, the FPGA may check the packet Type (Package Type) of the connection initialization Init packet when receiving the connection initialization Init packet. Upon determining that the packet type indicates that the CPU establishes a QUIC connection, but not other protocol connection or non-connection initialization data packets, a notification parameter is sent to the CPU.
Step 202, receiving a first data packet sent by a CPU, wherein the CPU communicates based on a QUIC protocol.
In the embodiment of the disclosure, step 202 may correspond to the related description of step 101, and is not repeated here.
Step 203, performing encryption processing on the first data packet when the first data packet is of a first packet type, wherein the first packet type is obtained by the CPU through modification when the first hardware unloading condition is met.
In the embodiment of the disclosure, step 203 may correspond to the related description of step 102, and is not repeated here.
In an alternative method embodiment of the present disclosure, the first hardware offload condition may include at least one of:
the first data packet is configured to be forcibly offloaded.
The load of the CPU is greater than or equal to the offload threshold.
In the embodiment of the disclosure, the first hardware unloading condition may be an independent condition, may be a plurality of conditions synthesized, may be set based on a CPU state, or may be set based on a data type. For example, the first hardware unloading condition may be that the first data packet is configured to be forcibly unloaded, for example, for a more complex request or response, the first data packet may be unloaded to the FPGA to be processed so as to reduce the load pressure of the CPU, and at this time, the first data packet of the request or response may be configured to be forcibly unloaded so as to be unloaded to the FPGA to be processed in any state of the CPU; the load of the CPU may be greater than or equal to an offloading threshold, where the offloading threshold may be a maximum load threshold that is set according to a network node configuration parameter, communication quality, and the like, where the CPU operates at a desired efficiency, and it may be considered that when the load of the CPU exceeds the offloading threshold, the overall communication efficiency will be affected, and thus the offloading threshold may be different in size under different network nodes, different configuration parameters, and different communication services. The magnitude of the unloading threshold value should not be too large, so as to avoid the problems of high energy consumption and low efficiency caused by the fact that the CPU is possibly in higher load operation, and the overall communication quality is influenced; the efficiency of the FPGA in local and repetitive data processing is higher, and the processing efficiency may be affected in other data processing, so that the hardware energy consumption is increased, and therefore, the unloading threshold should not be too small, so that tasks unsuitable for FPGA processing are unloaded to FPGA processing, and in particular, the actual measurement configuration may be performed according to the application environment, service requirements, and the like.
In an alternative method embodiment of the present disclosure, the first hardware offload condition may further include:
offloading of the FPGA is available.
In the embodiment of the disclosure, because the network environment is complex and may be in a change, the network node may be configured with an intelligent network card (SmartNIC), and the unloading of the quit protocol to the CPU is supported by the FPGA built in the intelligent network card, or the intelligent network card may not be configured, so that the data processing unloading function of the FPGA is not supported. Therefore, when the CPU establishes QUIC connection, whether the unloading of the FPGA is available can be determined by whether the notification parameters actively sent by the FPGA are received, and the first hardware unloading condition is preliminarily determined to be met under the condition that the unloading of the FPGA is available. On this basis, the CPU may further determine the CPU load status, whether the first packet is forcibly unloaded, etc.
In an alternative method embodiment of the present disclosure, the method may further comprise:
step 204, receiving the second data packet.
In an embodiment of the disclosure, the FPGA may further receive a second data packet sent by the other end in the network node, where the second data packet is sent based on the QUIC protocol.
And step 205, under the condition that the second data packet is an encrypted data packet and the second hardware unloading condition is met, performing decryption processing on the second data packet, and changing the second data packet into a second packet type.
And 206, sending the decrypted second data packet to the CPU.
In the embodiment of the present disclosure, the second hardware unloading condition may be that the packet type of the second data packet indicates to be unloaded to the FPGA to perform decryption processing, the CPU load is greater than or equal to the unloading threshold, etc., and the description related to the foregoing first hardware unloading condition may be referred to, so that no further description is given here for avoiding repetition.
In the embodiment of the disclosure, when the second data packet is an encrypted data packet and meets the second hardware unloading condition, it is indicated that the FGPA performs unloading to decrypt the second data packet, so that overall communication efficiency can be improved, and therefore the FGPA can decrypt the second data packet and change the packet type of the first data packet into the second packet type, so that when the CPU receives the second data packet, it can determine that the decryption work has been unloaded to the FGPA according to the second packet type of the second data packet.
The data processing and unloading method based on the FPGA is applied to the FPGA, when the first data packet sent by the CPU is received, the first data packet can be encrypted by the FPGA under the condition that the first data packet is of a first packet type, the first packet type is obtained by changing the type of the data packet under the condition that the CPU accords with a first hardware unloading condition, so that the FPGA can unload a first data packet related processing task of the first packet type to hardware for execution, the load pressure of the CPU in a data processing process is effectively reduced in a mode of combining soft and hard, the occupation of resources can be reasonably distributed, the task processing time is reduced, and the communication efficiency of the whole data network is further improved.
FIG. 3 is a third flowchart illustrating steps of an FPGA-based data processing offloading method according to an embodiment of the present disclosure. The method may be applied to a CPU, as shown in fig. 3, and may include:
step 301, changing the first data packet to a first packet type if the first hardware offload condition is met.
In the embodiment of the present disclosure, the CPU may determine whether the first data packet meets the first hardware unloading condition by determining the state of the CPU itself, determining whether the first data packet is configured to be forcibly unloaded, determining whether the unloading of the FPGA is available, and the like, and modifying the packet type of the first data packet to be the first packet type if the first hardware unloading condition is met, and may specifically refer to the foregoing description related to fig. 1 to 2, and will not be repeated here.
For example, after the CPU packages the first data packet based on the QUIC protocol, it may first determine whether fpga_flow_ready (FPGA offload available) is True, determine that the offload of the FPGA is available when fpga_flow_ready is True, and then change the packet type of the first data packet to the first packet type when the first data packet is configured to be forcedly offloaded or the load of the CPU exceeds an offload threshold.
In a method embodiment of the present disclosure, step 301 is preceded by the further step of a:
And step A, under the condition that the notification parameter is received, determining that the unloading of the FPGA is available.
In the embodiment of the disclosure, when the CPU establishes the quitc connection, the notification parameter sent by the FPGA may be received, so as to determine that the unloading of the FPGA is available according to the notification parameter, and in particular, reference may be made to the foregoing description related to fig. 1 to 2, which is not repeated herein.
For example, when the CPU receives a notification parameter that the unloading of the FPGA is available, the fpga_offlow_ready is set to True.
Step 302, a first data packet is sent to the FPGA, and the CPU communicates based on the QUIC protocol.
In this embodiment of the present disclosure, the CPU may send the first data packet to the FPGA, so that the FPGA encrypts the first data packet based on the first packet type corresponding to the first data packet, and in particular, reference may be made to the foregoing description related to fig. 1 to fig. 2, which is not repeated herein.
When the first data packet does not meet the first hardware unloading condition, the CPU may encrypt the first data packet and send the encrypted first data packet to the FPGA, where the packet type of the first data packet is the initial packet type.
In a method embodiment of the present disclosure, the method may further include the following steps B1 to B2:
And B1, receiving a second data packet sent by the FPGA.
And B2, unpacking the second data packet under the condition that the second data packet is a decryption data packet and the second data packet is of a second packet type.
In the embodiment of the disclosure, the second data packet may be an encrypted data packet received by the FPGA, and after the CPU receives the second data packet sent by the FPGA, the second data packet may or may not be decrypted. Under the condition that the second data packet is a decryption data packet and is of a second packet type, the second data packet is unloaded to the FGPA for decryption, and at the moment, the CPU can carry out unpacking processing to obtain a payload (payload) in the second data packet; alternatively, in a case where the second packet is in an encrypted state, the CPU may perform decryption processing on the second packet.
The FPGA-based data processing and unloading method is applied to the CPU, when the first data packet is sent, the first data packet is changed into the first packet type when the first hardware unloading condition is met, and the first data packet is sent to the FPGA, and the CPU is communicated based on the QUIC protocol, so that the FPGA can unload the first data packet related processing task of the first packet type to the hardware for execution, the load pressure of the CPU in the data processing process is effectively reduced in a soft-hard combination mode, the resource occupation can be reasonably distributed, the task processing time is reduced, and the overall data network communication efficiency is further improved.
Fig. 4 is an interactive flow diagram of an FPGA-based data processing offloading method according to an embodiment of the present disclosure, as shown in fig. 4, where the method may be applied to HOST (HOST configured with CPU), FPGA on HOST (FPGA configured on HOST), and PEER (other end network node), and the interactive flow is shown in the following steps C1 to CX:
and C1, initiating a QUIC connection establishment flow to the PEER by HOST, and establishing a QUIC connection between HOST and the PEER.
And C2, the FPGA on HOST sends notification parameters to HOST to indicate that unloading of the FPGA is available.
And C3, HOST is unloaded by using the FPGA based on the notification parameter setting.
And C4, HOST packages the first data packet, and changes the packet type of the first data packet into a first packet type under the condition that the first hardware unloading condition is met.
And C5, transmitting the first data packet to the FPGA on HOST by the HOST.
And C6, checking the first data packet by the FPGA on HOST, and carrying out encryption processing on the first data packet when the first data packet is of a first packet type.
And C7, the FPGA on HOST sends the first data packet after encryption processing to PEER.
And C8, the PEER decrypts the first data packet and acquires the effective load from the first data packet.
And C9, PEER packages the second data packet, and encrypts the second data packet.
And C10, the PEER sends the encrypted second data packet to the FPGA on HOST.
And C11, under the condition that the second data packet is an encrypted data packet and the second hardware unloading condition is met, the FPGA on HOST decrypts the second data packet and changes the packet type of the second data packet into a second packet type.
And C12, the FPGA on HOST sends the decrypted second data packet to HOST.
And C13, performing unpacking processing on the second data packet to obtain the effective load when the second data packet is a decryption data packet and the second data packet is of a second packet type.
The FPGA-based data processing and unloading method is applied to the interaction flow of the CPU and the FPGA, when the CPU sends the first data packet, the first data packet is changed into the first packet type when the first hardware unloading condition is met, the first data packet is sent to the FPGA, when the FPGA receives the first data packet sent by the CPU, the first data packet can be encrypted under the condition that the first data packet is of the first packet type, so that the FPGA can unload the first data packet related processing task of the first packet type to the hardware for execution, the load pressure of the CPU in the data processing process is effectively reduced in a soft-hard combination mode, the occupation of resources can be reasonably distributed, the task processing time is reduced, and the communication efficiency of the whole data network is further improved.
Fig. 5 is a block diagram of an FPGA 500 according to an embodiment of the disclosure, as shown in fig. 5, the FPGA 500 may include:
the first data receiving module 501 is configured to receive a first data packet sent by a CPU, where the CPU communicates based on the QUIC protocol.
The first data offloading module 502 is configured to encrypt a first data packet if the first data packet is of a first packet type, where the first packet type is obtained by the CPU by modification if the first hardware offloading condition is met.
In an embodiment of the present disclosure, the FPGA 500 may further include a second data sending module configured to send a notification parameter to the CPU when it is determined that the CPU establishes the QUIC connection, where the notification parameter is used to indicate that unloading of the FPGA is available.
In an embodiment of the present disclosure, the first data receiving module 501 is further configured to receive a second data packet;
the first data offloading module 502 is further configured to decrypt the second data packet and change the second data packet to be of a second packet type when the second data packet is an encrypted data packet and meets a second hardware offloading condition;
the second data sending module is further used for sending the decrypted second data packet to the CPU.
In an embodiment of the present disclosure, the first hardware offload condition includes at least one of:
The first data packet is configured to be forcibly offloaded;
the load of the CPU is greater than or equal to the offload threshold.
In an embodiment of the present disclosure, the first hardware offload condition further includes:
offloading of the FPGA is available.
According to the FPGA provided by the disclosure, when the first data packet sent by the CPU is received, the FPGA can encrypt the first data packet under the condition that the first data packet is of the first packet type, and the first packet type is obtained by changing the type of the data packet under the condition that the CPU accords with the first hardware unloading condition, so that the FPGA can unload the first data packet related processing task of the first packet type to hardware for execution, the load pressure of the CPU in the data processing process is effectively reduced in a soft-hard combination mode, the occupation of resources can be reasonably distributed, the task processing time is reduced, and the communication efficiency of the whole data network is further improved.
Fig. 6 is a block diagram of a CPU 600 according to an embodiment of the present disclosure, as shown in fig. 6, the CPU 600 may include:
the second data offloading module 601 is configured to change the first data packet to a first packet type if the first hardware offloading condition is met.
And the first data sending module 602 is used for sending a first data packet to the FPGA, and the CPU communicates based on the QUIC protocol.
Optionally, the CPU may further include a second data receiving module configured to determine that unloading of the FPGA is available if the notification parameter is received.
Optionally, the second data receiving module is further configured to receive a second data packet sent by the FPGA;
and the second data receiving module is further used for unpacking the second data packet when the second data packet is a decryption data packet and the second data packet is of a second packet type.
According to the unloading method for the data processing of the CPU, when the first data packet is sent, the first data packet is changed into the first packet type when the first hardware unloading condition is met, and the first data packet is sent to the FPGA, and the CPU is communicated based on the QUIC protocol, so that the FPGA can unload the first data packet related processing task of the first packet type to the hardware for execution, the load pressure of the CPU in the data processing process is effectively reduced in a soft-hard combination mode, the occupation of resources can be reasonably distributed, the task processing time is reduced, and the overall data network communication efficiency is further improved.
In an embodiment of the present disclosure, there is further provided an FPGA-based data processing offload system, where the system may include an FPGA and a CPU, where the CPU communicates based on a QUIC protocol, where the CPU may include: the second data unloading module is used for changing the first data packet into a first packet type under the condition that the first hardware unloading condition is met; the first data sending module is used for sending a first data packet to the FPGA;
The FPGA comprises: the first data receiving module is used for receiving a first data packet sent by the CPU; the first data unloading module is used for carrying out encryption processing on the first data packet under the condition that the first data packet is of a first packet type, and the first packet type is obtained by the CPU through modification under the condition that the first hardware unloading condition is met.
Fig. 7 is a schematic diagram of a collaboration flow of data transmission in an FPGA-based data processing offload system according to an embodiment of the present disclosure, where the system includes a CPU and an FPGA. As shown in fig. 7, at the Start (Start), the CPU packs the first packet (Pack data) and determines the CPU load (system cpu_load) of the system; further, the CPU determines whether FPGA offload is available (whether FPGA_offflow_ready is true), and whether the CPU load is greater than or equal to an offload threshold (system CPU_load is greater than or equal to 70%) or whether the first data packet is configured as a forced offload (FPGA_offflow_force);
when the judgment is yes, changing the packet type (Update Packet Type) of the first data packet into the first packet type, and sending the first data packet to the FPGA;
if no (N) is determined, the first packet is encrypted (encrypted) and sent to the FPGA.
When the FPGA receives the first data packet, checking the packet type of the first data packet to determine whether the first data packet needs to be unloaded to the FPGA for encryption processing (Check Packet Type if need encrypt);
if the determination is yes (Y), encrypting the first data packet (encryption packet), changing the packet type of the encrypted first data packet (Update Packet Type), and transmitting the first data packet to the other end of the quitc connection (Send packet);
if no (N) is determined, the first packet is transmitted to the other end of the quitc connection (Send packet).
In an optional system embodiment of the disclosure, the FPGA may further include a second data sending module configured to send a notification parameter to the CPU when it is determined that the CPU establishes the QUIC connection, where the notification parameter is used to indicate that unloading of the FPGA is available.
The CPU may further comprise a second data receiving module for determining that offloading of the FPGA is available in case of receiving the notification parameter.
Fig. 8 is a schematic diagram of a collaborative flow of initialization data in an FPGA-based data processing offload system according to an embodiment of the present disclosure, where the system includes a CPU and an FPGA. As shown in fig. 8, when the FPGA receives the Init packet (Receive Init Package), it determines the packet type of the Init packet (Check Packet Type Init), and sends notification parameters to the CPU on the basis of determining that the CPU establishes a quench connection;
The CPU receives the notification parameter, determines that FPGA offloading is available, and sets FPGA offloading available (fpga_offflow_ready=true).
In an optional system embodiment of the disclosure, the first data receiving module is further configured to receive a second data packet;
the first data unloading module is further configured to decrypt the second data packet and change the second data packet to be of a second packet type when the second data packet is an encrypted data packet and meets a second hardware unloading condition;
the second data sending module is further used for sending the decrypted second data packet to the CPU.
The second data receiving module is further used for receiving a second data packet sent by the FPGA;
and the second data receiving module is further used for unpacking the second data packet when the second data packet is a decryption data packet and the second data packet is of a second packet type.
Fig. 9 is an exemplary diagram of a collaboration flow for data reception in an FPGA-based data processing offload system according to an embodiment of the present disclosure, where the system includes a CPU and an FPGA. As shown in fig. 9, after the FPGA receives the second packet (receive packet) from the other end of the quitc connection and determines the CPU load (system cpu_load) of the system, it checks whether the second packet is an encrypted packet (Is encrypted packet) and whether the CPU load is greater than or equal to the offload threshold (system cpu_load is greater than or equal to 70%);
If the determination is yes (Y), decrypting the second packet, changing the type of the decrypted second packet (Update Packet Type) to the second packet type, and transmitting the first packet to the CPU;
if no (N) is determined, the second packet is transmitted to the CPU.
The CPU receives the second data packet and checks the packet type of the second data packet to determine whether encryption processing is required (Check Packet encrypt type);
if the determination is yes (Y), decrypting the second packet, and unpacking the decrypted second packet to obtain the payload;
if no (N) is determined, the second packet after decryption is unpacked (unpackage data) to obtain the payload.
The FPGA-based data processing and unloading system comprises a CPU and an FPGA, when the CPU sends a first data packet, the first data packet is changed into a first packet type when the first data packet meets the first hardware unloading condition, the first data packet is sent to the FPGA, when the FPGA receives the first data packet sent by the CPU, the first data packet can be encrypted under the condition that the first data packet is of the first packet type, so that the FPGA can unload the first data packet related processing task of the first packet type to hardware for execution, the load pressure of the CPU in the data processing process is effectively reduced in a soft-hard combination mode, the occupation of resources can be reasonably distributed, the task processing time is reduced, and the communication efficiency of the whole data network is further improved.
Fig. 10 is a schematic structural diagram of an electronic device 1000 according to an embodiment of the present disclosure, as shown in fig. 10, the electronic device 1000 may include a processor 1001, a memory 1002, and a program or an instruction stored in the memory 1002 and capable of being executed on the processor 1001, where the program or the instruction implements each process of the FPGA-based data processing unloading method embodiment described in any one of fig. 1 to 4,7 to 9 when executed by the processor 1001, and the process may achieve the same technical effects, and will not be repeated herein.
It should be noted that, the electronic device 1000 shown in fig. 10 is only an example, and should not impose any limitation on the functions and the application scope of the embodiments of the present disclosure.
Fig. 11 is a hardware schematic diagram of an electronic device 1100 according to an embodiment of the present disclosure, as shown in fig. 11, the electronic device 1100 includes a central processing unit (Central Processing Unit, CPU) 1101, which may perform various appropriate actions and processes according to a program stored in a ROM (Read Only Memory) 1102 or a program loaded from a storage portion 1108 into a RAM (Random Access Memory ) 1103. In the RAM 1103, various programs and data required for system operation are also stored. The CPU 1101, ROM 1102, and RAM 1103 are connected to each other by a bus 1104. An I/O (Input/Output) interface 1105 is also connected to bus 1104.
The following components are connected to the I/O interface 1105: an input section 1106 including a keyboard, a mouse, and the like; an output portion 1107 including a CRT (Cathode Ray Tube), an LCD (Liquid Crystal Display ), and the like, a speaker, and the like; a storage section 1108 including a hard disk or the like; and a communication section 1109 including a network interface card such as a LAN (Local Area Network, wireless network) card, a modem, or the like. The communication section 1109 performs communication processing via a network such as the internet. The drive 1110 is also connected to the I/O interface 1105 as needed. Removable media 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like, is installed as needed in drive 1110, so that a computer program read therefrom is installed as needed in storage section 1108.
In particular, according to embodiments of the present disclosure, the processes described below with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the FPGA-based data processing offload method as described in any of figures 1-4, 7-9. In such an embodiment, the computer program can be downloaded and installed from a network via the communication portion 1109, and/or installed from the removable media 1111. When executed by a central processing unit (CPU 1101), performs the various functions defined in the system of the present application.
The embodiment of the present disclosure further sends a readable storage medium, where a program or an instruction is stored, where the program or the instruction implements each process of the FPGA-based data processing and offloading method embodiment described in any one of fig. 1 to 4,7 to 9 when executed by a processor, and the process can achieve the same technical effects, so that repetition is avoided and redundant description is omitted here.
The processor is a processor in the electronic device in the above embodiment. A readable storage medium includes a computer readable storage medium such as ROM, RAM, magnetic or optical disk, etc.
The embodiment of the disclosure further provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to run a program or an instruction, implement each process of the FPGA-based data processing and offloading method embodiment described in any one of fig. 1 to 4,7 to 9, and achieve the same technical effect, so that repetition is avoided and redundant description is omitted here.
It should be understood that the chips referred to in the embodiments of the present disclosure may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.
Embodiments of the present disclosure provide a computer program product containing instructions, which when executed on a computer, cause the computer to perform the steps of the FPGA-based data processing offloading method as described in any one of fig. 1 to 4,7 to 9, and achieve the same technical effects, and are not repeated herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present disclosure is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present disclosure may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk), including several instructions for causing a terminal (which may be a mobile phone, a computer, an electronic device, an air conditioner, or a network device, etc.) to perform the method of the embodiments of the present disclosure.
The embodiments of the present disclosure have been described above with reference to the accompanying drawings, but the present disclosure is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the disclosure and the scope of the claims, which are all within the protection of the present disclosure.

Claims (11)

1. A method for data processing and offloading based on an FPGA, the method being applied to a field programmable gate array FPGA, the method comprising:
receiving a first data packet sent by a CPU, wherein the CPU communicates based on a QUIC protocol;
and carrying out encryption processing on the first data packet under the condition that the first data packet is of a first packet type, wherein the first packet type is obtained by changing the CPU under the condition that a first hardware unloading condition is met.
2. The method of claim 1, wherein prior to receiving the first data packet sent by the CPU, the method further comprises:
and when the QUIC connection with the CPU is determined to be established, sending a notification parameter to the CPU, wherein the notification parameter is used for indicating that the unloading of the FPGA is available.
3. The method according to claim 1, wherein the method further comprises:
receiving a second data packet;
under the condition that the second data packet is an encrypted data packet and meets a second hardware unloading condition, carrying out decryption processing on the second data packet and changing the second data packet into a second packet type;
and sending the decrypted second data packet to the CPU.
4. The method of claim 1, wherein the first hardware offload condition comprises at least one of:
the first data packet is configured to be forcibly offloaded;
the load of the CPU is greater than or equal to an unloading threshold.
5. The method of claim 4, wherein the first hardware offload condition further comprises:
offloading of the FPGA is available.
6. A method for data processing offloading based on an FPGA, the method being applied to a CPU, the method comprising:
changing the first data packet to a first packet type if the first hardware unloading condition is met;
and sending the first data packet to an FPGA, wherein the CPU communicates based on a QUIC protocol.
7. The method of claim 6, wherein before modifying the first data packet to the first packet type if the hardware offload condition is met, further comprising:
Upon receiving the notification parameter, determining that offloading of the FPGA is available.
8. The method of claim 6, wherein the method further comprises:
receiving a second data packet sent by the FPGA;
and in the case that the second data packet is a decryption data packet and the second data packet is a second packet type, unpacking the second data packet.
9. An FPGA, the FPGA comprising:
the first data receiving module is used for receiving a first data packet sent by a CPU, and the CPU is communicated based on a QUIC protocol;
and the first data unloading module is used for carrying out encryption processing on the first data packet under the condition that the first data packet is of a first packet type, and the first packet type is obtained by the CPU through modification under the condition that the first hardware unloading condition is met.
10. A CPU, the CPU comprising:
the second data unloading module is used for changing the first data packet into a first packet type under the condition that the first hardware unloading condition is met;
and the first data sending module is used for sending the first data packet to the FPGA, and the CPU is communicated based on a QUIC protocol.
11. An FPGA-based data processing offload system, the system comprising an FPGA in communication with a CPU, the CPU being based on a QUIC protocol, wherein the CPU comprises:
The second data unloading module is used for changing the first data packet into a first packet type under the condition that the first hardware unloading condition is met;
the first data sending module is used for sending the first data packet to the FPGA;
the FPGA comprises:
the first data receiving module is used for receiving a first data packet sent by the CPU;
and the first data unloading module is used for carrying out encryption processing on the first data packet under the condition that the first data packet is of a first packet type, and the first packet type is obtained by the CPU through modification under the condition that the first hardware unloading condition is met.
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