CN116583151A - Display panel, preparation method thereof and display device - Google Patents
Display panel, preparation method thereof and display device Download PDFInfo
- Publication number
- CN116583151A CN116583151A CN202310679068.6A CN202310679068A CN116583151A CN 116583151 A CN116583151 A CN 116583151A CN 202310679068 A CN202310679068 A CN 202310679068A CN 116583151 A CN116583151 A CN 116583151A
- Authority
- CN
- China
- Prior art keywords
- layer
- edge
- open hole
- hole area
- flat layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 113
- 239000002184 metal Substances 0.000 claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 239000010410 layer Substances 0.000 claims description 234
- 239000000463 material Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 description 30
- 239000011148 porous material Substances 0.000 description 15
- 239000007769 metal material Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/87—Passivation; Containers; Encapsulations
- H10K59/871—Self-supporting sealing arrangements
- H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present disclosure provides a display panel, including: a substrate base; a first metal trace disposed on the substrate; the first flat layer is positioned on one side of the first metal wire and is arranged to cover the first metal wire; the second metal wire is positioned on one side of the first flat layer and in the flat area of the first flat layer, and the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area is smaller than the distance between the edge of the second metal wire, which is close to the open hole area, and the edge of the open hole area; the second flat layer is arranged on one side of the second metal wire and covers the second metal wire, and the distance between the edge of the second flat layer, which is close to the open hole area, and the edge of the open hole area is greater than the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area; the third flat layer is positioned on one side of the second flat layer, and the distance between the edge of the third flat layer, which is close to the open hole area, and the edge of the open hole area is larger than the distance between the edge of the second flat layer, which is close to the open hole area, and the edge of the open hole area.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of display, in particular to a display panel, a preparation method thereof and a display device.
Background
With the increasing demand of users for products and the intense competitive environment in the industry, most mobile phone factories are pursuing higher screen occupation ratio so as to bring more dazzling visual impact to users and win market competition. However, the development of higher screen ratios for cameras and some sensors is limited, and placing cameras and some sensors in the screen is of great interest in the industry.
When some sensors such as cameras are placed in a screen, holes are usually needed to be formed in the screen, and moisture, oxygen or the like is easy to invade the display panel in the process, so that the display panel is in packaging failure.
Disclosure of Invention
The embodiment of the disclosure provides a display panel, a preparation method thereof and a display device.
In a first aspect, embodiments of the present disclosure provide a display panel including:
a substrate including an open area and a display area surrounding the open area;
on the substrate, in the area between the edge of the open area close to the display area and the edge of the display area close to the open area, the following steps are sequentially arranged: the first metal wire, the first flat layer, the second metal wire, the second flat layer and the third flat layer;
the first metal wire is positioned on the substrate base plate;
the first flat layer is positioned on one side of the first metal wire away from the substrate base plate and covers the first metal wire;
the second metal wire is positioned on one side of the first flat layer, which is away from the substrate base plate, and is positioned in a flat area of the first flat layer, and the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area is smaller than the distance between the edge of the second metal wire, which is close to the open hole area, and the edge of the open hole area;
the second flat layer is positioned on one side of the second metal wire away from the substrate base plate and covers the second metal wire, and the distance between the edge of the second flat layer, which is close to the open hole area, and the edge of the open hole area is greater than the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area;
the third flat layer is positioned on one side, away from the substrate, of the second flat layer, and the distance between the edge, close to the open hole area, of the third flat layer and the edge of the open hole area is larger than the distance between the edge, close to the open hole area, of the second flat layer and the edge of the open hole area.
In some embodiments, at least one isolation pillar is further disposed on a side of the first planar layer adjacent to the open area.
In some embodiments, a dam structure is further provided on a side of the spacer column adjacent to the open area.
In some embodiments, the isolation pillars are formed in the same layer and material as the first metal traces.
In some embodiments, the dike structure includes a first dike layer, a second dike layer, and a third dike layer;
the first dyke layer is located on the substrate, the second dyke layer is located on one side of the first dyke layer, which is away from the substrate, and covers the first dyke layer, and the third dyke layer is located on one side of the second dyke layer, which is away from the substrate, and covers the second dyke layer.
In some embodiments, the first bank layer is formed in the same layer and material as the first planar layer, the second bank layer is formed in the same layer and material as the second planar layer, and the third bank layer is formed in the same layer and material as the third planar layer.
In some embodiments, an interlayer insulating layer is further disposed between the first metal trace and the substrate base.
In some embodiments, a first gate wire, a first gate insulating layer, a second gate wire, and a second gate insulating layer are further disposed between the interlayer insulating layer and the substrate base plate;
the first grid electrode wiring is positioned on the substrate base plate;
the first grid insulation layer is positioned on one side of the first grid wiring away from the substrate base plate and is arranged to cover the first grid wiring;
the second grid wiring is positioned on one side of the first grid insulating layer, which is away from the substrate base plate;
the second gate insulating layer is positioned on one side of the second gate wire away from the substrate base plate and covers the second gate wire.
In some embodiments, a buffer layer is further disposed between the first gate trace and the substrate base.
In a second aspect, embodiments of the present disclosure provide a display device including the display panel described above.
In a third aspect, an embodiment of the present disclosure provides a method for manufacturing a display panel, including:
providing a substrate, wherein the substrate comprises an open hole area and a display area surrounding the open hole area;
forming a first metal wire on the substrate in a region between the edge of the open hole region close to the display region and the edge of the display region close to the open hole region;
forming a first flat layer on one side of the first metal wire away from the substrate, wherein the first flat layer covers the first metal wire;
forming a second metal wire on one side of the first flat layer, which is away from the substrate, wherein the second metal wire is positioned in a flat area of the first flat layer, and the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area is smaller than the distance between the edge of the second metal wire, which is close to the open hole area, and the edge of the open hole area;
forming a second flat layer on one side of the second metal wire away from the substrate, wherein the second flat layer covers the second metal wire, and the distance between the edge of the second flat layer, which is close to the open hole area, and the edge of the open hole area is larger than the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area;
and forming a third flat layer on one side of the second flat layer, which is away from the substrate, wherein the distance between the edge of the third flat layer, which is close to the open hole area, and the edge of the open hole area is larger than the distance between the edge of the second flat layer, which is close to the open hole area, and the edge of the open hole area.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the disclosure;
FIG. 2 is a schematic diagram of a first metal trace, a second metal trace, and a spacer in an embodiment of the disclosure;
fig. 3 is a schematic structural view of a dam structure in an embodiment of the present disclosure;
FIG. 4 is a schematic top view of a display panel according to an embodiment of the disclosure;
fig. 5 is a flow chart of a method for manufacturing a display panel according to an embodiment of the disclosure.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the technical solutions of the display panel, the manufacturing method thereof, and the display device provided by the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure.
Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements/structures, these elements/structures should not be limited by these terms. These terms are only used to distinguish one element/structure from another element/structure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure, where the embodiment of the present disclosure provides a display panel, as shown in fig. 1, including:
the substrate 11, the substrate 11 includes an opening area (AA Hole) HH and a display area AA surrounding the opening area HH.
On the substrate 11, in a region FF between an edge of the aperture region HH near the display region AA and an edge of the display region AA near the aperture region HH, there are sequentially provided: a first metal trace 12, a first Planarization Layer (PLN) 13, a second metal trace 14, a second Planarization Layer (PLN) 15, and a third Planarization Layer (PLN) 16.
Wherein, the first metal wire 12 is located on the substrate 11; the first flat layer 13 is positioned on one side of the first metal wire 12 away from the substrate 11 and is arranged to cover the first metal wire 12; the second metal wire 14 is positioned on one side of the first flat layer 13 away from the substrate 11 and is positioned in a flat area of the first flat layer 13, and the distance between the edge of the first flat layer 13, which is close to the open pore area HH, and the edge of the open pore area HH is smaller than the distance between the edge of the second metal wire 14, which is close to the open pore area HH, and the edge of the open pore area HH; the second flat layer 15 is located on one side of the second metal wire 14 away from the substrate 11 and covers the second metal wire 14, and the distance between the edge of the second flat layer 15, which is close to the open pore region HH, and the edge of the open pore region HH is greater than the distance between the edge of the first flat layer 13, which is close to the open pore region HH, and the edge of the open pore region HH; the third flat layer 16 is located on one side of the second flat layer 15 away from the substrate 11, and the distance between the edge of the third flat layer 16 close to the open pore region HH and the edge of the open pore region HH is greater than the distance between the edge of the second flat layer 15 close to the open pore region HH and the edge of the open pore region HH.
In the embodiment of the present disclosure, the first metal trace 12 and the second metal trace 14 are Source Drain (SD) metal traces of transistors (not shown) in the display area AA.
In the embodiment of the disclosure, on the one hand, the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area is smaller than the distance between the edge of the second metal wire, which is close to the open hole area, and the edge of the open hole area, so that the second metal wire, which is positioned on one side of the first flat layer, which is away from the substrate, is arranged in the flat area of the first flat layer, thereby effectively preventing the second metal wire from breaking off, causing the display panel to have poor bright lines and reducing the occurrence of poor bright lines; in another aspect, the distance between the edge of the second flat layer near the open area and the edge of the open area is greater than the distance between the edge of the first flat layer near the open area and the edge of the open area, the distance between the edge of the third flat layer near the open area and the edge of the open area is greater than the distance between the edge of the second flat layer near the open area and the edge of the open area, and the edge of the third flat layer near the open area is further away from the isolation pillars between the flat layer and the open area, thereby increasing the opening of the grooves formed between the flat layer and the isolation pillars, facilitating the reduction of organic material residues of the flat layer (PLN) or the Pixel Defining Layer (PDL), and further facilitating the improvement of GDSH (Growing Dark Spot (AA Hole), the growth of black specks) poor (vapor oxidation of the open area due to poor cracking, scratches, top damage, etc. caused by encapsulation or external forces).
In some embodiments, at least one isolation column 17 is further disposed on a side of the first planarization layer 13 adjacent to the open area HH, and the isolation column 17 is disposed to facilitate blocking moisture and oxygen from entering the display area AA from the open area HH.
In some embodiments, the isolation pillars 17 are formed in the same layer and material as the first metal traces 12, i.e., the isolation pillars 17 are formed simultaneously with the first metal traces 12 in a single manufacturing process.
In some embodiments, the first metal trace 12 may be formed by sequentially stacking three metal structures, and the second metal trace 14 may be formed by sequentially stacking three metal structures, and the isolation post 17 may be formed by sequentially stacking three metal structures.
Fig. 2 is a schematic structural diagram of a first metal trace, a second metal trace, and a spacer in an embodiment of the disclosure, in some embodiments, as shown in fig. 2, the first metal trace 12 includes a first metal layer 121, a second metal layer 122, and a third metal layer 123 stacked in sequence, the first metal layer 121 is located above the substrate 11, the second metal layer 122 is located on a side of the first metal layer 121 facing away from the substrate 11, and the third metal layer 123 is located on a side of the second metal layer 123 facing away from the substrate 11, where the first metal layer 121, the second metal layer 122, and the third metal layer 123 may be made of metal materials, for example, the first metal layer 121 and the third metal layer 123 may be made of titanium metal materials, and the second metal layer 122 may be made of aluminum metal materials.
In some embodiments, as shown in fig. 2, the second metal trace 14 includes a fourth metal layer 141, a fifth metal layer 142, and a sixth metal layer 143 sequentially stacked, the fourth metal layer 141 is located above the first flat layer 13, the fifth metal layer 142 is located on a side of the fourth metal layer 141 facing away from the first flat layer 13, and the sixth metal layer 143 is located on a side of the fifth metal layer 142 facing away from the first flat layer 13, where the fourth metal layer 141, the fifth metal layer 142, and the sixth metal layer 143 may be made of a metal material, for example, the fourth metal layer 141 and the sixth metal layer 143 may be made of a titanium metal material, and the fifth metal layer 142 may be made of an aluminum metal material.
In some embodiments, as shown in fig. 2, the isolation column 17 includes a first isolation layer 171, a second isolation layer 172, and a third isolation layer 173 stacked in this order, the first isolation layer 171 is located above the substrate 11, the first isolation layer 171 is formed with the same layer and the same material as the first metal layer 121, the second isolation layer 172 is located at a side of the first isolation layer 171 facing away from the substrate 11, the second isolation layer 172 is formed with the same layer and the same material as the second metal layer 122, and the third isolation layer 173 is located at a side of the second isolation layer 173 facing away from the substrate 11, wherein the first isolation layer 171, the second isolation layer 172, and the third isolation layer 173 may be made of a metal material, for example, the first isolation layer 171 and the third isolation layer 173 may be made of a titanium metal material, and the second isolation layer 172 may be made of an aluminum metal material.
In some embodiments, a dam structure 18 is also provided on the side of the spacer 17 adjacent to the open area HH, the dam structure 18 being provided to facilitate prevention of ink jet outflow when an organic material film layer (e.g., a flat layer) is prepared using the ink jet printing technique (IJP).
Fig. 3 is a schematic structural view of a dike structure in an embodiment of the present disclosure, and in some embodiments, as shown in fig. 3, the dike structure 18 includes a first dike layer 181, a second dike layer 182, and a third dike layer 183; wherein the first bank layer 181 is located above the substrate 11, the second bank layer 182 is located at a side of the first bank layer 181 facing away from the substrate 11 and is disposed to cover the first bank layer 181, and the third bank layer 183 is located at a side of the second bank layer 182 facing away from the substrate 11 and is disposed to cover the second bank layer 181.
In some embodiments, the first bank layer 181 is formed with the first flat layer 13 and the same material, the second bank layer 182 is formed with the second flat layer 15 and the same material, and the third bank layer 183 is formed with the third flat layer 16 and the same material, which means that the same material is used in one manufacturing process and the same material is used for manufacturing.
In some embodiments, as shown in fig. 1, an interlayer Insulating Layer (ILD) 19 is also provided between the first metal trace 12 and the substrate base 11.
In some embodiments, a passivation layer (PVX) is also provided between the interlayer insulating layer 19 and the first metal trace 12.
In some embodiments, as shown in fig. 1, between the interlayer insulating layer 19 and the substrate base plate 11, a first Gate wiring (Gate) 20, a first Gate insulating layer (GI) 21, a second Gate wiring (Gate) 22, and a second Gate insulating layer (GI) 23 are further provided.
Wherein, the first gate wire 20 is located on the substrate 11; a first gate insulating layer 21, which is located at a side of the first gate trace 20 away from the substrate 11 and is disposed to cover the first gate trace 20; a second gate trace 22 located on a side of the first gate insulating layer 21 facing away from the substrate 11; the second gate insulating layer 23 is located on a side of the second gate trace 22 away from the substrate 11, and is disposed to cover the second gate trace 22.
In some embodiments, as shown in fig. 1, a Buffer layer (Buffer) 24 is further disposed between the first gate trace 20 and the substrate 11.
In some embodiments, a Barrier layer (Barrier) is also provided between the buffer layer 24 and the substrate base plate 11.
In some embodiments, the substrate (PI) 11 is a flexible substrate, made of a flexible material.
Fig. 4 is a schematic top view of a display panel according to an embodiment of the disclosure, as shown in fig. 4, in some embodiments, as shown in fig. 4, a plurality of isolation columns 17 are further disposed on a side of the dam structure 18 near the open pore region HH, the number of the isolation columns 17 disposed on the side of the dam structure 18 near the open pore region HH is not particularly limited, and the number of the isolation columns 17 may be disposed as needed, for example, on the side of the dam structure 18 near the open pore region HH, and 7 isolation columns 17 as shown in fig. 4 are further disposed.
Note that fig. 1 is a schematic longitudinal sectional view of the display panel shown in fig. 4, and fig. 1 and 4 are only schematic views illustrating a structure of a region FF between an edge of the opening region HH near the display region AA and an edge of the display region AA near the opening region HH on the display panel, and the display region AA and the opening region HH are not illustrated.
In an embodiment of the present disclosure, the display panel may be an OLED (Organic Light-Emitting Diode) display panel, and accordingly, the display area AA may include a plurality of pixel units on a substrate, each pixel unit including a plurality of sub-pixels.
The plurality of pixel units can be arranged in an array, and the plurality of sub-pixels in each pixel unit can also be arranged in an array. The display area AA further includes a plurality of gate lines extending in a row direction and a plurality of data lines extending in a column direction, wherein the gate lines and the data lines are disposed to cross each other and define sub-pixels. The grid lines are used for providing grid scanning signals for the corresponding connected sub-pixels, and the data lines are used for providing required data signals for the corresponding connected sub-pixels.
The display area AA further includes a plurality of power traces extending along the column direction, where each column of sub-pixels may be correspondingly provided with a power trace, and the power trace is configured to provide a required power voltage to the corresponding connected sub-pixels.
In the display area AA, each sub-pixel may include a pixel driving circuit and a light emitting device, wherein the pixel driving circuit is connected to a corresponding gate line, a corresponding data line, a corresponding power trace, and a corresponding light emitting device, and is capable of providing a driving current to the light emitting device according to a data signal provided by the data line and a power voltage provided by the power trace to drive the light emitting device to emit light; the light Emitting device may be a current driven light Emitting device, for example, an OLED light Emitting device or an AMOLED (Active-Matrix Organic Light-Emitting Diode) light Emitting device, or the like.
The embodiment of the disclosure also provides a display device, which comprises the display panel provided by any one of the embodiments.
The display device may be a device with a display panel, such as a mobile phone, a tablet computer, a notebook computer, an electronic watch, etc., which is not specifically described herein.
The specific description of the display panel may refer to the related description of the display panel in the above embodiment, and will not be repeated here.
Fig. 5 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure, where the method for manufacturing a display panel, as shown in fig. 5, includes:
step S41, providing a substrate, wherein the substrate comprises an open area and a display area surrounding the open area.
Step S42, forming a first metal wire on the substrate in a region between the edge of the opening area close to the display area and the edge of the display area close to the opening area.
In step S43, a first planarization layer is formed on a side of the first metal trace facing away from the substrate, where the first planarization layer covers the first metal trace.
In step S44, a second metal trace is formed on a side of the first flat layer facing away from the substrate, where the second metal trace is located in a flat area of the first flat layer, and a distance between an edge of the first flat layer, which is close to the open hole area, and an edge of the open hole area is smaller than a distance between an edge of the second metal trace, which is close to the open hole area, and an edge of the open hole area.
In step S45, a second flat layer is formed on a side of the second metal trace away from the substrate, the second flat layer covers the second metal line, and a distance between an edge of the second flat layer, which is close to the open hole area, and an edge of the open hole area is greater than a distance between an edge of the first flat layer, which is close to the open hole area, and an edge of the open hole area.
In step S46, a third flat layer is formed on a side of the second flat layer facing away from the substrate, where a distance between an edge of the third flat layer, which is close to the open area, and an edge of the open area is greater than a distance between an edge of the second flat layer, which is close to the open area, and an edge of the open area.
The method for preparing a display panel provided by the embodiments of the present disclosure is used for preparing the display panel provided by the foregoing embodiments, and specific description of the display panel may be referred to the description of the foregoing embodiments, which is not repeated herein.
It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.
Claims (11)
1. A display panel, comprising:
a substrate including an open area and a display area surrounding the open area;
on the substrate, in the area between the edge of the open area close to the display area and the edge of the display area close to the open area, the following steps are sequentially arranged: the first metal wire, the first flat layer, the second metal wire, the second flat layer and the third flat layer;
the first metal wire is positioned on the substrate base plate;
the first flat layer is positioned on one side of the first metal wire away from the substrate base plate and covers the first metal wire;
the second metal wire is positioned on one side of the first flat layer, which is away from the substrate base plate, and is positioned in a flat area of the first flat layer, and the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area is smaller than the distance between the edge of the second metal wire, which is close to the open hole area, and the edge of the open hole area;
the second flat layer is positioned on one side of the second metal wire away from the substrate base plate and covers the second metal wire, and the distance between the edge of the second flat layer, which is close to the open hole area, and the edge of the open hole area is greater than the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area;
the third flat layer is positioned on one side, away from the substrate, of the second flat layer, and the distance between the edge, close to the open hole area, of the third flat layer and the edge of the open hole area is larger than the distance between the edge, close to the open hole area, of the second flat layer and the edge of the open hole area.
2. The display panel of claim 1, wherein at least one spacer is further provided on a side of the first planar layer adjacent to the open area.
3. The display panel according to claim 2, wherein a dam structure is further provided at a side of the barrier ribs adjacent to the open hole area.
4. The display panel of claim 2, wherein the spacer is formed of the same material and in the same layer as the first metal trace.
5. The display panel according to claim 3, wherein the bank structure includes a first bank layer, a second bank layer, and a third bank layer;
the first dyke layer is located on the substrate, the second dyke layer is located on one side of the first dyke layer, which is away from the substrate, and covers the first dyke layer, and the third dyke layer is located on one side of the second dyke layer, which is away from the substrate, and covers the second dyke layer.
6. The display panel according to claim 5, wherein the first bank layer is formed of the same layer and the same material as the first flat layer, the second bank layer is formed of the same layer and the same material as the second flat layer, and the third bank layer is formed of the same layer and the same material as the third flat layer.
7. The display panel according to claim 1, wherein an interlayer insulating layer is further provided between the first metal wiring and the substrate base.
8. The display panel according to claim 7, wherein a first gate wiring, a first gate insulating layer, a second gate wiring, and a second gate insulating layer are further provided between the interlayer insulating layer and the substrate base plate;
the first grid electrode wiring is positioned on the substrate base plate;
the first grid insulation layer is positioned on one side of the first grid wiring away from the substrate base plate and is arranged to cover the first grid wiring;
the second grid wiring is positioned on one side of the first grid insulating layer, which is away from the substrate base plate;
the second gate insulating layer is positioned on one side of the second gate wire away from the substrate base plate and covers the second gate wire.
9. The display panel according to claim 8, wherein a buffer layer is further provided between the first gate wire and the substrate.
10. A display device comprising the display panel according to any one of claims 1-9.
11. A method for manufacturing a display panel, the method comprising:
providing a substrate, wherein the substrate comprises an open hole area and a display area surrounding the open hole area;
forming a first metal wire on the substrate in a region between the edge of the open hole region close to the display region and the edge of the display region close to the open hole region;
forming a first flat layer on one side of the first metal wire away from the substrate, wherein the first flat layer covers the first metal wire;
forming a second metal wire on one side of the first flat layer, which is away from the substrate, wherein the second metal wire is positioned in a flat area of the first flat layer, and the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area is smaller than the distance between the edge of the second metal wire, which is close to the open hole area, and the edge of the open hole area;
forming a second flat layer on one side of the second metal wire away from the substrate, wherein the second flat layer covers the second metal wire, and the distance between the edge of the second flat layer, which is close to the open hole area, and the edge of the open hole area is larger than the distance between the edge of the first flat layer, which is close to the open hole area, and the edge of the open hole area;
and forming a third flat layer on one side of the second flat layer, which is away from the substrate, wherein the distance between the edge of the third flat layer, which is close to the open hole area, and the edge of the open hole area is larger than the distance between the edge of the second flat layer, which is close to the open hole area, and the edge of the open hole area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202310679068.6A CN116583151A (en) | 2023-06-08 | 2023-06-08 | Display panel, preparation method thereof and display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202310679068.6A CN116583151A (en) | 2023-06-08 | 2023-06-08 | Display panel, preparation method thereof and display device |
Publications (1)
Publication Number | Publication Date |
---|---|
CN116583151A true CN116583151A (en) | 2023-08-11 |
Family
ID=87543231
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202310679068.6A Pending CN116583151A (en) | 2023-06-08 | 2023-06-08 | Display panel, preparation method thereof and display device |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN116583151A (en) |
-
2023
- 2023-06-08 CN CN202310679068.6A patent/CN116583151A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11916087B2 (en) | Array substrate and organic light-emitting display including the same | |
US10038163B2 (en) | Display device | |
US10580836B2 (en) | OLED touch display panel with baffles on a TFT back plate, method for manufacturing the same and touch display device | |
KR102668184B1 (en) | Display device | |
KR102541447B1 (en) | organic light emitting display device | |
KR102111562B1 (en) | Thin film semiconductor device and organic light emitting display | |
JP7079803B2 (en) | Display device | |
EP3457437B1 (en) | Display apparatus | |
KR102315889B1 (en) | Display panel | |
US20240179942A1 (en) | Display apparatus | |
US20200357877A1 (en) | Display device | |
US12016211B2 (en) | Display device | |
US20240196689A1 (en) | Display panel, display module, and display device | |
CN116583151A (en) | Display panel, preparation method thereof and display device | |
CN110783368B (en) | Display panel, manufacturing method thereof and display terminal | |
EP4089734A1 (en) | Display device | |
CN219999921U (en) | Display substrate | |
US20240224631A1 (en) | Display Device | |
CN116940175A (en) | Display substrate | |
KR20240016651A (en) | Display panel and display device including the same | |
KR20220106261A (en) | Display apparatus and manufacturing the same | |
CN114447033A (en) | Display device | |
CN115918292A (en) | Display panel and display device | |
CN115240558A (en) | First substrate, display panel and display device | |
CN114447037A (en) | Display device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |