CN116581102A

CN116581102A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Info

Publication number: CN116581102A
Application number: CN202310097476.0A
Authority: CN
Inventors: 后藤聪; 青池将之; 筒井孝幸; 佐佐木健次
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2022-02-09
Filing date: 2023-02-08
Publication date: 2023-08-11

Abstract

The invention provides a semiconductor device, which ensures heat dissipation and is difficult to generate characteristic degradation and oscillation of a high-frequency wave amplifying circuit in a structure of jointing different components. The second face of the second member is opposite the first face of the first member. The second part includes a high-frequency amplifying circuit. The first member and the second member are joined by a conductive joining member disposed between the first surface and the second surface. The high-frequency amplifying circuit includes: at least one power stage transistor; an input wiring connected to the power stage transistor and supplying an input signal to the power stage transistor; and an input side circuit unit connected to the input wiring and including at least one of a passive element, an active element, and an external connection terminal. The joint member includes a first conductor pattern including a power stage transistor in a plan view, and the input side circuit unit is arranged outside the first conductor pattern in a plan view.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Technical Field

The present invention relates to a semiconductor device.

Background

Patent document 1 below discloses a semiconductor device having a substrate formed by bonding two substrates having different thermal conductivities, for example, a GaAs substrate and a Si substrate. As an example, two substrates are bonded via a bonding layer composed of a metal provided in the entire region of a bonding interface. A high frequency amplifying circuit is formed on one substrate. The heat generated in the transistor of the high-frequency amplifying circuit is transferred to the other substrate through the bonding layer, thereby securing heat radiation.

Patent document 1: japanese patent laid-open publication No. 2021-2644

Parasitic capacitance is generated between a wiring, a circuit element, and a bonding layer made of metal formed in a high-frequency amplification circuit of one substrate. The parasitic capacitance and the bonding layer may cause interference in the high-frequency amplification circuit, and may deteriorate characteristics or cause oscillation.

Disclosure of Invention

The invention aims to provide a semiconductor device, which ensures heat dissipation in a structure for jointing different components and is difficult to generate degradation and oscillation of characteristics of a high-frequency amplifying circuit.

According to one aspect of the present invention, there is provided a semiconductor device including:

a first component having a first face;

a second member having a second surface facing the first surface and including a high-frequency amplifying circuit; and

a conductive bonding member disposed between the first surface and the second surface for bonding the first member and the second member,

the high-frequency amplifying circuit includes:

at least one power stage transistor;

an input wiring connected to the power stage transistor and supplying an input signal to the power stage transistor; and

an input side circuit unit connected to the input wiring and including at least one of a passive element, an active element, and an external connection terminal,

The bonding part includes a first conductor pattern including the power stage transistor in a plan view,

the input side circuit unit is arranged outside the first conductor pattern in a plan view.

According to another aspect of the present invention, there is provided a semiconductor device including:

a semiconductor component including a compound semiconductor;

a high-frequency amplifying circuit formed on the semiconductor device; and

a conductor member disposed on one surface of the semiconductor member,

the high-frequency amplifying circuit includes:

at least one power stage transistor;

an input wiring for supplying an input signal to the power stage transistor; and

the conductor part comprises at least one conductor pattern,

the power stage transistor is included in at least one conductor pattern of the conductor member when the surface on which the conductor member is arranged is viewed in plan, and the input side circuit unit is arranged outside the conductor pattern including the power stage transistor.

Since the first conductor pattern of the bonding member includes a plurality of power stage transistors in a plan view, heat dissipation from the power stage transistors to the heat dissipation path of the first member via the bonding member is not impaired. The input side circuit unit is arranged outside the first conductor pattern in a plan view, so that coupling between the plurality of power stage transistors and the input side circuit unit via the first conductor pattern is reduced. This suppresses degradation of characteristics and oscillation of the high-frequency amplification circuit.

Drawings

Fig. 1 is a schematic top view of a semiconductor device according to a first embodiment.

Fig. 2A is a cross-sectional view of the semiconductor device according to the first embodiment, and fig. 2B is a cross-sectional view of the first member and the second member showing an example in which a natural oxide film is formed on the second surface of the second member.

Fig. 3 is a cross-sectional view of one of the power stage transistors included in the second component.

Fig. 4 is a plan view of the power stage transistors included in the second component, and the input side circuit unit arranged for each power stage transistor.

Fig. 5 is an equivalent circuit diagram of the high-frequency amplifying circuit.

Fig. 6 is a block diagram of a high-frequency amplifying circuit of the semiconductor device according to the first embodiment.

Fig. 7 is a schematic top view of a semiconductor device according to a second embodiment.

Fig. 8 is a schematic top view of a semiconductor device according to a third embodiment.

Fig. 9 is a schematic top view of a semiconductor device according to a fourth embodiment.

Fig. 10 is a schematic top view of a semiconductor device according to a fifth embodiment.

Fig. 11 is a schematic top view of a semiconductor device according to a sixth embodiment.

Fig. 12 is a schematic top view of a semiconductor device according to a seventh embodiment.

Fig. 13 is a schematic top view of a semiconductor device according to an eighth embodiment.

Fig. 14 is a schematic top view of a semiconductor device according to a ninth embodiment.

Fig. 15 is a schematic top view of a semiconductor device according to a tenth embodiment.

Fig. 16 is a schematic top view of a semiconductor device according to an eleventh embodiment.

Fig. 17 is a schematic top view of a semiconductor device according to a twelfth embodiment.

Fig. 18 is a schematic top view of a second component of the semiconductor device according to the thirteenth embodiment.

Fig. 19 is a block diagram of a semiconductor device according to a thirteenth embodiment.

Fig. 20 is a schematic plan view of a second component of the semiconductor device according to the fourteenth embodiment.

Fig. 21 is a schematic plan view of a second component of the semiconductor device according to the fifteenth embodiment.

Fig. 22 is a schematic plan view of a second component of the semiconductor device according to the sixteenth embodiment.

Fig. 23 is a schematic top view of a second component of the semiconductor device according to the seventeenth embodiment.

Fig. 24 is a schematic plan view of a second member of the semiconductor device according to the eighteenth embodiment.

Fig. 25 is a schematic top view of a second component of the semiconductor device according to the nineteenth embodiment.

Fig. 26 is a schematic plan view of a semiconductor device according to a twentieth embodiment.

Fig. 27 is a block diagram of a semiconductor device according to a twentieth embodiment.

Fig. 28 is a schematic top view of a semiconductor device according to a twenty-first embodiment.

Fig. 29 is a block diagram of a semiconductor device according to a twenty-first embodiment.

Fig. 30 is a schematic top view of a second component of the semiconductor device according to the twenty-second embodiment.

Fig. 31 is a schematic top view of a second component of a semiconductor device according to a twenty-third embodiment.

Fig. 32 is a schematic plan view of a second component of the semiconductor device according to the twenty-fourth embodiment.

Fig. 33 is a schematic top view of a second component of the semiconductor device according to the twenty-fifth embodiment.

Fig. 34 is a schematic plan view of a second component of the semiconductor device according to the twenty-sixth embodiment.

Fig. 35 is a schematic plan view of a second component of the semiconductor device according to the twenty-seventh embodiment.

Fig. 36 is a schematic top view of a second component of the semiconductor device according to the twenty-eighth embodiment.

Fig. 37 is a schematic top view of a semiconductor device according to a twenty-ninth embodiment.

Fig. 38 is a schematic top view of a semiconductor device according to a thirty-third embodiment.

Fig. 39 is a schematic top view of a semiconductor device according to a thirty-first embodiment.

Fig. 40 is a top view of a power stage transistor of a semiconductor device according to a thirty-first embodiment.

Fig. 41 is a schematic top view of a semiconductor device according to a thirty-second embodiment.

Fig. 42 is a schematic top view of a semiconductor device according to a thirty-third embodiment.

Fig. 43A is a schematic top view of a semiconductor device according to a thirty-fourth embodiment, and fig. 43B and 43C are schematic cross-sectional views at dash-dot lines 43B-43B and 43C-43C, respectively, of fig. 43A.

Fig. 44A is a schematic top view of a semiconductor device according to a thirty-fifth embodiment, and fig. 44B and 44C are schematic cross-sectional views at the dash-dot lines 44B-44B and the dash-dot lines 44C-44C, respectively, of fig. 44A.

Fig. 45 is a schematic top view of a semiconductor device according to a thirty-sixth embodiment.

Fig. 46 is a cross-sectional view of a portion of the semiconductor device shown in fig. 45.

Fig. 47 is a schematic top view of a semiconductor device according to a thirty-seventh embodiment.

Fig. 48 is a cross-sectional view of a portion of the semiconductor device shown in fig. 47.

Fig. 49 is a schematic top view of a semiconductor device according to a thirty-eighth embodiment.

Fig. 50 is a schematic plan view of a semiconductor device according to a modification of the thirty-eighth embodiment.

Fig. 51 is a schematic plan view of a semiconductor device according to another modification of the thirty-eighth embodiment.

Fig. 52 is a schematic plan view of a semiconductor device according to still another modification of the thirty-eighth embodiment.

Fig. 53 is a schematic plan view of a semiconductor device according to still another modification of the thirty-eighth embodiment.

Fig. 54 is a schematic plan view of a semiconductor device according to still another modification of the thirty-eighth embodiment.

Fig. 55 is a schematic top view of a semiconductor device according to a thirty-ninth embodiment.

Fig. 56 is a schematic plan view of a semiconductor device according to a modification of the thirty-ninth embodiment.

Fig. 57 is a schematic top view of a semiconductor device according to a fortieth embodiment.

Fig. 58 is a schematic top view of a semiconductor device according to a forty-first embodiment.

Fig. 59 is a schematic top view of a semiconductor device according to a forty-second embodiment.

Fig. 60 is a schematic top view of a semiconductor device according to a forty-third embodiment.

Fig. 61 is a schematic plan view of a semiconductor device according to a modification of the forty-third embodiment.

Fig. 62 is a schematic plan view of a semiconductor device according to another modification of the forty-third embodiment.

Fig. 63 is a schematic plan view of a semiconductor device according to still another modification of the forty-third embodiment.

Fig. 64 is a schematic plan view of a semiconductor device according to still another modification of the forty-third embodiment.

Fig. 65 is a schematic plan view of a semiconductor device according to still another modification of the forty-third embodiment.

Fig. 66 is a schematic plan view of a semiconductor device according to still another modification of the forty-third embodiment.

Fig. 67 is a schematic plan view of a semiconductor device according to still another modification of the forty-third embodiment.

Fig. 68 is a schematic top view of a semiconductor device according to a forty-fourth embodiment.

Fig. 69 is a schematic top view of a semiconductor device according to a forty-fifth embodiment.

Fig. 70 is a schematic plan view of a semiconductor device according to a modification of the forty-fifth embodiment.

Fig. 71 is a schematic plan view of a semiconductor device according to another modification of the forty-fifth embodiment.

Fig. 72 is a schematic top view of a semiconductor device according to a forty-sixth embodiment.

Fig. 73 is a schematic plan view of a semiconductor device according to a modification of the forty-sixth embodiment.

Fig. 74 is a schematic plan view of a semiconductor device according to another modification of the forty-sixth embodiment.

Fig. 75 is a schematic top view of a semiconductor device according to a forty-seventh embodiment.

Fig. 76 is a schematic plan view of a semiconductor device according to a modification of the forty-seventh embodiment.

Fig. 77 is a schematic plan view of a semiconductor device according to another modification of the forty-seventh embodiment.

Fig. 78 is a schematic top view of a semiconductor device according to a forty-eighth embodiment.

Fig. 79 is a schematic plan view of a semiconductor device according to a modification of the forty-eighth embodiment.

Description of the reference numerals

10 … first part; 10a … first side; 10B … support substrate; 10I … insulating layer; 10S … semiconductor layers; 10W … multilayer wiring layers; 11 … wiring; 12 … via holes; 15 … first-member-side engagement members; 15A, 15A1, 15A11, 15A12, 15A2, 15A21, 15A22, 15B1, 15B2, 15B21, 15B22, 15B3, 15B4, 15BI1, 15BI2, 15BO1, 15BO2, 15C, 15D, 15E, 15F, 15G, 15GL … conductor patterns; 16 … control circuitry; 20 … second part; 20B … second side; 20I … natural oxide film; 21 … semiconductor film; 21a … subcollector layer; 21B … element separation region; 25 … second-member-side engagement members; 25A, 25A1, 25A11, 25A12, 25A2, 25A21, 25A22, 25B1, 25B2, 25B3, 25B4, 25C, 25D, 25E, 25F1, 25F2, 25F21, 25F22, 25FI1, 25FI2, 25FO1, 25FO2, 25G, 25GL, 25H … conductor patterns; 31 … power stage transistor; 31B … base layer; 31BM … base mesa; 31C … collector layer; 31E … emitter layer; 31EM … emitter mesa; 31P … cap layer; 31T … contact layer; 32a … alloyed region; 32B … base electrode; 32C … collector; 32E … emitter electrode; 33BB … bias wiring; 33C … collector wiring; 33E … emitter wiring; 34E … emitter wiring; 34I … signal input wiring (capacitor upper electrode); 35 … input wiring; 36 … input capacitor; 36U … to the lower electrode of the capacitor; 37 … ballast resistor element; 38A, 38B, 38C, 38D … blocks of power stage transistors; 40 … input side circuit unit; 41. 41A, 41A1, 41A2, 41B1, 41B2 … input terminals; 42. 42A, 42B … bias terminals; 45 … ground terminals; 51 … drive stage transistor; 56 … input capacitor; a 60 … power stage high frequency amplifying circuit; 61 … drive stage bias circuits; 62 … power stage bias circuit; a 63 … driver stage high frequency amplifying circuit; a 64 … double-stage structure high-frequency amplifying circuit; 65 … input terminals; 66 … battery voltage terminal; 67 … drive stage bias control terminal; 68 … power stage bias control terminal; 70 … input matching circuit; 71 … inter-stage matching circuit; 72C … capacitor; 72L … inductor; 75. 76, 77, 78 … inter-component connection wiring; 80. 80A, 80B, 80C, 80D … output terminals; 81 and … terminals for external connection; 85. 85A, 85A1, 85A2, 85B1, 85B2, 86A, 86B …;87 … pad; 88 … conductor projections connected to the first member; 90. 91 … insulating film; 100 … first part; the lower part of the conductor protuberance on the first component of 100A …;100B …

A conductor projection upper portion on the first member; 101 … conductor-bump base patterns; 105 … can configure the location of the conductor protrusions on the first component; 110 … circular; 111 …;120 … semiconductor component; 125 … conductor parts.

Detailed Description

First embodiment

A semiconductor device according to a first embodiment will be described with reference to the drawings of fig. 1 to 6.

Fig. 1 is a schematic top view of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment includes a first member 10 and a second member 20. The first member 10 is a substrate including a single semiconductor layer, for example, an SOI substrate, and the second member 20 is a film-like member including a compound semiconductor film, for example, a GaAs film. As will be described later with reference to fig. 2A, the second member 20 is joined to the first surface 10A of the first member 10. In fig. 1, only a part of the first member 10 is shown, and the broken line representing the first member 10 in fig. 1 does not show the outer shape of the first member 10. The shape of the second member 20 is square or rectangular when the first surface 10A is viewed in plan (hereinafter, may be simply referred to as "plan view").

The second component 20 contains a high frequency amplification circuit 60 of a power stage. The high-frequency amplification circuit 60 of the power stage includes: a plurality of power stage transistors 31, a plurality of input wirings 35 connected to respective bases of the power stage transistors 31, a plurality of input capacitors 36 connected to the respective input wirings 35, an input terminal 41, a bias terminal 42, and the like. The passive element connected to the input wiring 35, the external connection terminal, and the wiring for connecting these are referred to as an input side circuit unit 40.

The plurality of power stage transistors 31 are arranged in a row and are arranged symmetrically with respect to the center of the arrangement direction. The plurality of power stage transistors 31 are separated into two blocks at the center of the transistor column. For example, in the high power operation, the power stage transistors 31 of two blocks are operated, and in the low power operation, only the power stage transistor 31 of one block is operated. The input-side circuit unit 40 is arranged on one side (lower side in fig. 1) of a straight line passing through the plurality of power stage transistors 31 in parallel with an arrangement direction of the plurality of power stage transistors 31 (hereinafter, may be simply referred to as an "arrangement direction") in a plan view.

For example, the arrangement direction of the plurality of power stage transistors 31 is parallel to one edge of the second member 20. An input side circuit unit 40 is arranged between one edge of the second member 20 arranged at an interval in a direction orthogonal to the arrangement direction with respect to the transistor array of the power stage transistors 31 and the transistor array. The input side circuit unit 40 is not arranged between the transistor array and the other edge parallel to the arrangement direction. The input side circuit unit 40 may be disposed between the edge of the second member 20 intersecting a straight line extending the transistor array in the arrangement direction and the transistor array. The positional relationship of the input side circuit unit 40 and the transistor array is the same in the embodiment described later. Here, the term "orthogonal to the alignment direction" does not need to be strictly geometrically orthogonal, and may deviate from the orthogonal relationship. In the present specification, the orthogonal relationship allowing such a deviation is referred to as "substantially orthogonal". The term "parallel to the alignment direction" does not need to be strictly geometrically parallel, and may deviate from the parallel relationship. The parallel relationship allowing such deviation is referred to as "substantially parallel".

In some cases, a protection element, a diode-connected transistor constituting a bias circuit, a wiring for feedback from an output side to an input side, and the like are arranged in a space between two blocks. In addition, there are cases where wiring, circuit components, and the like are not arranged in the space between the two blocks.

Base biases are supplied from the two bias terminals 42 to the power stage transistors 31 of the two blocks via the bias wiring 33BB, respectively (description of the ballast resistor elements described later with reference to fig. 4 and 5 is omitted in fig. 1). A high-frequency signal is input from the input terminal 41 to the base of the power stage transistor 31 via the plurality of input capacitors 36 and the input wiring 35. The control of the base bias may be either current control or voltage control.

A collector wiring 33C is connected to collectors of the plurality of power stage transistors 31. The collector wiring 33C has a comb-tooth shape in a plan view, and a plurality of comb-tooth portions are arranged between the plurality of power stage transistors 31. The common portion of the portions connecting the plurality of comb teeth is arranged on the opposite side of the input side circuit unit 40 as viewed from the power stage transistor 31. The collector wiring 33C may be separated for each block of the power stage transistor 31 or may be shared for two blocks.

The output terminal 80 formed of a conductive bump such as a bump is connected to the collector wiring 33C. The output signals amplified by the plurality of power stage transistors 31 are output from the output terminal 80. For example, collector voltages are applied to the plurality of power stage transistors 31 via the choke coil, the output terminal 80, and the collector wiring 33C. The output terminal 80 is connected to an external impedance matching circuit, for example. In addition to the output terminal 80, a plurality of external connection terminals 81 each including a conductor protrusion such as a bump are arranged. The plurality of external connection terminals 81 include, for example, terminals for connection to external circuits, dummy terminals for ensuring flatness and parallelism in flip-chip bonding to a module substrate or the like.

The high-frequency signal is input to the plurality of power stage transistors 31 from the input side circuit unit 40 disposed on one side of a straight line passing through the plurality of power stage transistors 31 in a plan view and parallel to the arrangement direction, and is output from the output terminal 80 via the collector wiring 33C disposed on the opposite side. In this way, the high-frequency signal is transmitted mainly in one direction from the input-side circuit unit 40 toward the output terminal 80.

Inter-member connection wirings 85, 86 for connecting the terminals provided on the second member 20 and the terminals provided on the first member 10 are arranged. An input signal is supplied to the input terminal 41 through the inter-component connection wiring 85. Bias voltages are supplied to the two bias terminals 42 through the other two inter-component connection wirings 86, respectively.

A conductive bonding member 25 is disposed between the first surface 10A of the first member 10 and the second member 20. The first member 10 and the second member 20 are joined via a joining member 25. The conductor pattern 25A of the bonding member 25 is configured to include a plurality of power stage transistors 31 in a plan view. In the first embodiment, the joint member 25 includes a series of conductor patterns 25A. In this specification, a plurality of conductor patterns separated from each other may be collectively referred to as a "conductor pattern".

In fig. 1, the conductor pattern 25A is hatched. The conductor pattern 25A has a shape symmetrical with respect to a symmetry axis passing through the center of the arrangement direction of the plurality of power stage transistors 31 and orthogonal to the arrangement direction in plan view. The conductor pattern of the joining member 15 on the first member 10 side is arranged so as to substantially overlap with the conductor pattern 25A. In the present specification and other drawings, although the conductor pattern of the joining member 15 on the first member 10 side is not clearly shown in some cases, the conductor pattern on the first member 10 side is arranged so as to overlap with the conductor pattern of the joining member 25 on the second member 20 side. The conductor pattern on the first member 10 side is arranged on the collector wiring 33C and the output terminal 80 side more widely than the input side circuit unit 40 side as viewed from the plurality of power stage transistors 31 in the direction orthogonal to the arrangement direction of the plurality of power stage transistors 31.

The conductor pattern 25A does not overlap the input side circuit unit 40 in a plan view. That is, the input side circuit unit 40 is arranged outside the conductor pattern 25A including the plurality of power stage transistors 31 in a plan view. For example, the conductor pattern 25A partially overlaps the collector wiring 33C arranged on the opposite side of the input side circuit unit 40 as viewed from the plurality of power stage transistors 31. In the present specification, "outside of a certain portion" means an area outside of the peripheral line of the certain portion in plan view, and "inside of a certain portion" means an area inside of the peripheral line of the certain portion in plan view.

The conductor-bump base pattern 101 is arranged on the first surface 10A of the first member 10 outside the second member 20 in a plan view. The first component upper conductor bump 100 is arranged inside the conductor bump base pattern 101 in a plan view.

Fig. 2A is a cross-sectional view of the semiconductor device according to the first embodiment. In addition, fig. 2A does not show a specific cross-sectional structure of the semiconductor device according to the first embodiment, but shows a cross-sectional structure of each of a plurality of constituent elements of the semiconductor device focusing on each constituent element. First, the structure of the first member 10 will be described.

The first component 10 includes a silicon-on-insulator (SOI) substrate and a multilayer wiring layer 10W disposed thereon. The SOI substrate includes a support substrate 10B, an insulating layer 10I, and a semiconductor layer 10S. Instead of the SOI substrate, a normal single silicon substrate or the like may be used. A plurality of driving stage transistors 51 are formed in the semiconductor layer 10S. In fig. 2A, the driving stage transistor 51 is indicated by a broken line. The driving stage transistor 51 is, for example, a CMOS transistor.

The second member 20 is bonded to a partial region of the first surface 10A, which is the upper surface of the multilayer wiring layer 10W. The second face 20B of the second member 20 is opposite to the first face 10A of the first member 10. The joint member 15 is disposed in a partial region of the first surface 10A of the first member 10. The conductor pattern 25A of the joint member 25 is disposed in a partial region of the second surface 20B of the second member 20. The engaging member 25 on the second member 20 side is brought into close contact with the engaging member 15 of the first member 10, so that the second member 20 is engaged with the first member 10.

The joining member 25 on the second member 20 side and the joining member 15 on the first member 10 side have substantially the same shape in plan view, and substantially overlap. In fig. 1, the joint member 15 is not explicitly shown, but the joint member 15 is disposed so as to substantially overlap with the joint member 25 on the second member 20 side. The joining member 25 on the second member 20 side and the joining member 15 on the first member 10 side may be formed in different shapes, and one may be larger than the other. However, the bonding member 15 on the first member 10 side bonded to the bonding member 25 is shaped and sized so as not to overlap the input side circuit unit 40 (fig. 1) in a plan view. The difference in shape and size between the two is preferably small enough to absorb the alignment error at the time of bonding.

The joining member 15 and the joining member 25 are formed of Au, for example, and can be joined to the first member 10 by bringing them into close contact and pressing them. In addition, the bonding of the second member 20 to the first member 10 may be by van der Waals bonding, hydrogen bonding, electrostatic force, covalent bonding, eutectic alloy bonding, or the like. A gap corresponding to the total thickness of the joining member 15 on the first member 10 side and the joining member 25 on the second member 20 side is formed between the first surface 10A and the second surface 20B.

The plurality of power stage transistors 31 formed in the second component 20 are shown in dashed lines. An input terminal 41 and a ground terminal 45 are disposed on a surface (hereinafter, sometimes referred to as an "upper surface") of the second member 20 opposite to the second surface. The input terminal 41 and the ground terminal 45 are formed of the uppermost metal film of the second member 20. The ground terminal 45 is arranged at a position overlapping the plurality of power stage transistors 31 in a plan view. In fig. 1, the description of the ground terminal 45 is omitted.

A rewiring layer is disposed on the first surface 10A of the first member 10 and on the upper surface of the second member 20 via an insulating film 90. The rewiring layer includes a plurality of pads 87 each made of a metal pattern, inter-component connection wirings 85, and first-component upper-conductor-bump lower portions 100A. A conductive bump base pattern 101 is arranged between the first component upper conductive bump lower portion 100A and the multilayer wiring layer 10W. The conductor-protrusion base pattern 101 is formed by the same process as the joining member 15 on the first member 10 side. Although not shown in fig. 2A, the inter-component connection wiring 86 (fig. 1) connected to the bias terminal 42 is also included in the rewiring layer. The input terminal 41 is connected to the driver transistor 51 via the inter-component connection wiring 85, the wiring 11 in the multilayer wiring layer 10W, and the via hole 12. An inter-stage impedance matching circuit including a capacitor, an inductor, and the like may be arranged between the input terminal 41 and the driving stage transistor 51. Alternatively, an inter-stage impedance matching circuit may be disposed between the input terminal 41 and the power stage transistor 31.

One pad 87 of the plurality of pads 87 is connected to the ground terminal 45 provided to the second member 20. The plurality of pads 87, the inter-component connection wiring 85, and the first-component upper-conductor-projection lower portion 100A are covered with an insulating film 91. The insulating film 91 is provided with openings reaching the upper surfaces of the plurality of pads 87 and the first-component upper-conductor-bump lower portions 100A in the cross section shown in fig. 2A. These openings are included in each of the plurality of pads 87 and the conductor bump lower portion 100A on the first member in a plan view. A conductor projection 88 connected to the pad 87 and a first-component-upper conductor projection upper portion 100B connected to the first-component-upper conductor projection lower portion 100A are disposed in each opening and on the insulating film 91. The conductor protrusions 88 serve as connection terminals for face-down mounting to a module substrate or the like. The output terminal 80 (fig. 1) and the external connection terminal 81 (fig. 1) are constituted by these conductor projections 88. The first-member upper-conductor-projection lower portion 100A and the first-member upper-conductor-projection upper portion 100B are referred to as first-member upper-conductor projections 100. In order to distinguish it from the first-member-upper-conductor projection 100, the conductor projection 88 serving as the terminal 81 for external connection is sometimes referred to as a terminal-conductor projection.

Fig. 2B is a cross-sectional view of the first member 10 and the second member 20 showing an example in which the natural oxide film 20I is formed on the second surface 20B of the second member 20. After the second surface 20B of the second member 20 is formed into the bonding member 25, a natural oxide film 20I may be formed on the second surface 20B of the second member 20 before bonding with the first member 10. When the thickness of the natural oxide film 20I is substantially equal to the total thickness of the bonding member 15 on the first member 10 side and the bonding member 25 on the second member 20 side, almost no gap is formed between the first member 10 and the second member 20.

Fig. 3 is a cross-sectional view of one of the power stage transistors 31 included in the second component 20. The second member 20 includes a semiconductor thin film 21. One surface of the semiconductor thin film 21 corresponds to a second surface 20B facing the first member 10. The second surface 20B is formed with a joint member 25. The semiconductor thin film 21 is formed of a compound semiconductor such as GaAs, and is divided into a sub-collector layer 21A of n-type conductivity and an insulating element separation region 21B. Power stage transistor 31 is formed on subcollector layer 21A.

The power stage transistor 31 includes: a base mesa 31BM formed on the subcollector layer 21A, and an emitter mesa 31EM formed on a partial region of the upper surface of the base mesa 31 BM. The base mesa 31BM includes: a collector layer 31C, a base layer 31B, and an emitter layer 31E are stacked in this order from the subcollector layer 21A. That is, the collector layer 31C, the base layer 31B, and the emitter layer 31E are laminated in this order from the side close to the first member 10 (fig. 2A). The emitter mesa 31EM includes a cap layer 31P and a contact layer 31T disposed on the cap layer.

As an example, the collector layer 31C is formed of n-type GaAs, the base layer 31B is formed of p-type GaAs, and the emitter layer 31E is formed of n-type InGaP. The cap layer 31P is formed of n-type GaAs, and the contact layer 31T is formed of n-type InGaAs. The power stage transistor 31, which is composed of a base mesa 31BM and an emitter mesa 31EM, is a Heterojunction Bipolar Transistor (HBT). When the power stage transistor 31 operates, heat is mainly generated in the collector layer 31C directly below the emitter mesa 31 EM.

A collector 32C is disposed on a region of the subcollector layer 21A where the base mesa 31BM is not disposed. For example, in the cross section of fig. 3, collectors 32C are disposed on both sides of the base mesa 31 BM. The first layer collector wirings 33C are disposed on the collectors 32C, respectively. In fig. 3, description of a specific structure of an interlayer insulating film between wiring layers is omitted. The collector wiring 33C is electrically connected to the collector layer 31C via the collector 32C and the subcollector layer 21A. The collector wiring 33C in the cross section shown in fig. 3 corresponds to a portion of the comb teeth of the collector wiring 33C of fig. 1. A plurality of power stage transistors 31 may be arranged on a series of subcollector layers 21A, and one collector 32C may be shared between two power stage transistors 31 adjacent to each other.

A base electrode 32B is disposed on a region of the emitter layer 31E where the emitter mesa 31EM is not disposed. The base electrode 32B includes portions arranged on both sides of the emitter mesa 31EM in the cross section of fig. 3. The base electrode 32B penetrates the emitter layer 31E in the thickness direction and is electrically connected to the base layer 31B via the alloying region 32A reaching the base layer 31B.

An emitter electrode 32E is disposed on the emitter mesa 31 EM. The emitter electrode 32E is electrically connected to the emitter layer 31E via the contact layer 31T and the cap layer 31P. The emitter layer 31E located directly below the emitter mesa 31EM substantially functions as an emitter region.

A first layer emitter wiring 33E is disposed on the emitter electrode 32E, and a second layer emitter wiring 34E is disposed thereon. The second layer emitter wiring 34E is electrically connected to the emitter electrode 32E via the first layer emitter wiring 33E. At least one ground terminal 45 is arranged on the second layer emitter wiring 34E (fig. 2A). The ground terminal 45 is electrically connected to the emitter layer 31E of the power stage transistor 31.

Fig. 4 is a plan view of the power stage transistors 31 included in the second member 20, and the input capacitors 36 arranged for each power stage transistor 31. In fig. 4, a relatively thick upper right hatching is added to the emitter electrode 32E, the base electrode 32B, and the collector electrode 32C, and a relatively thin lower right hatching is added to the emitter wiring 33E, the collector wiring 33C, the input wiring 35, and the bias wiring 33 BB.

An emitter electrode 32E and a base electrode 32B are arranged inside a base mesa 31BM having a shape (for example, a rectangle) long in one direction in a plan view. The emitter electrode 32E is also rectangular in shape in plan view and longer in one direction. The base electrode 32B has a U-shape formed of portions arranged at intervals from the two long sides and one short side of the emitter electrode 32E. The two collectors 32C are arranged at intervals in the short side direction (width direction) from the base mesa 31 BM. The plurality of power stage transistors 31 (fig. 1) are arranged in the width direction of the emitter electrode 32E. One collector 32C may also be shared between two adjacent power stage transistors 31.

The first layer emitter wiring 33E is arranged to overlap the emitter electrode 32E in a plan view. The first layer collector wiring 33C is arranged to overlap the collector 32C in a plan view. The first layer collector wiring 33C extends from a position overlapping the collector 32C in one direction substantially orthogonal to the arrangement direction of the power stage transistors 31. The direction in which the collector wiring 33C extends and the arrangement direction of the power stage transistors 31 need not be strictly geometrically orthogonal, but may deviate from the orthogonal relationship.

The second layer emitter wiring 34E is arranged to overlap the first layer plurality of emitter wirings 33E in a plan view. The second layer emitter wiring 34E extends in a direction substantially parallel to the arrangement direction of the power stage transistors 31, and is connected to the plurality of first layer emitter wirings 33E.

One end of the input wiring 35 overlaps the base electrode 32B and is connected to the base electrode 32B. The input wiring 35 extends from a position overlapping the base electrode 32B in one direction substantially orthogonal to the arrangement direction of the power stage transistors 31. The direction in which the input wiring 35 extends is the opposite direction to the direction in which the collector wiring 33C extends.

A lower electrode 36U of the input capacitor 36 is connected to the tip of the input wiring 35. The signal input wiring 34I is arranged to overlap with the lower electrode 36U of the input capacitor 36 in a plan view. The signal input wiring 34I in the region overlapping with the lower electrode 36U functions as an upper electrode of the input capacitor 36. The signal input wiring 34I extends in a direction substantially parallel to the arrangement direction of the power stage transistors 31, and overlaps with a plurality of lower electrodes 36U of each of the power stage transistors connected to the plurality of power stage transistors 31.

The input wiring 35 is connected to one end of the ballast resistor element 37 via a lower electrode 36U of the input capacitor 36. The other end of the ballast resistor element 37 is connected to the bias wiring 33 BB. In fig. 1, descriptions of the second layer emitter wiring 34E, the signal input wiring 34I, the ballast resistor element 37, and the like are omitted. The "conductor pattern 25A of the bonding member 25 includes the power stage transistor 31 in a plan view" described with reference to fig. 1 means specifically that the conductor pattern 25A includes the base mesa 31BM in a plan view.

One power stage transistor 31 shown in fig. 3 and 4 has a single emitter configuration including one emitter mesa 31 EM. As another example, a multi-emitter structure may be employed in which a plurality of emitter mesas 31EM are arranged on one base mesa 31BM in the short side direction thereof. In the single emitter structure, the base electrode 32B may be arranged only on one side in the short side direction of the emitter mesa 31EM, and the base electrode 32B may be L-shaped in a plan view.

In fig. 4, the ballast resistor element 37 is arranged at a position distant from the input capacitor 36 as viewed from the power stage transistor 31, but the ballast resistor element 37 may be arranged between the power stage transistor 31 and the input capacitor 36.

Fig. 5 is an equivalent circuit diagram of the high-frequency amplifying circuit 60 of the power stage. The power stage high frequency amplifying circuit 60 includes a plurality of power stage transistors 31. The collectors of the plurality of power stage transistors 31 are connected to a common collector wiring 33C. The common collector wiring 33C is connected to the output terminal 80. The emitters of the plurality of power stage transistors 31 are connected to a common emitter wiring 34E. The bases of the plurality of power stage transistors 31 are connected to a common signal input wiring 34I via input capacitors 36, respectively. The signal input wiring 34I is connected to the input terminal 41.

The plurality of power stage transistors 31 are divided into two blocks, and for each block, the bases of the plurality of power stage transistors 31 are connected to the common bias wiring 33BB via the ballast resistor element 37, respectively. The bias wirings 33BB provided for each block are connected to the bias terminals 42, respectively.

Fig. 6 is a block diagram of a high-frequency amplifying circuit 64 of a 2-stage structure including a high-frequency amplifying circuit 60 of a power stage of the semiconductor device according to the first embodiment. The high-frequency amplifying circuit 64 shown in fig. 6 includes a high-frequency amplifying circuit 63 of a driving stage and a high-frequency amplifying circuit 60 of a power stage. The driver-stage high-frequency amplification circuit 63 includes a driver-stage transistor 51, and the power-stage high-frequency amplification circuit 60 includes a power-stage transistor 31. The high-frequency signal RFin is input to the driving stage transistor 51 via the input matching circuit 70. The high-frequency signal amplified by the driving stage transistor 51 is input to the power stage transistor 31 via the inter-stage matching circuit 71 and the input terminal 41. The high-frequency signal amplified by the power stage transistor 31 is output from the output terminal 80 as an output signal RFout. The output terminal 80 is connected to a load via an impedance matching circuit mounted on a module board, for example.

For example, the power supply voltage Vcc1 is supplied to the driving stage transistor 51 via an external connection terminal. The power supply voltage Vcc2 is supplied to the power stage transistor 31 via the external connection terminal 81. In addition, the output terminal 80 (fig. 5) may also be used as a terminal for supplying the power supply voltage Vcc2. The battery voltage Vbatt is supplied to the driving stage bias circuit 61 and the power stage bias circuit 62. The driving stage bias circuit 61 supplies a base bias to the driving stage transistor 51 based on the driving stage bias control signal Vbias 1. The power stage bias circuit 62 supplies base bias voltages to the respective power stage transistors 31 (fig. 5) of the two blocks via the bias terminals 42 based on the power stage bias control signals Vbias2, vbias 3.

Next, the excellent effects of the first embodiment will be described.

In the first embodiment, heat generated in the power stage transistor 31 is transferred to the first member 10 through the bonding member 25 (fig. 2A), the bonding member 15 on the first member 10 side, and is transferred to the module substrate or the like through the emitter wirings 33E, 34E (fig. 3), the pad 87, the conductor protrusion 88 (fig. 2A). Since the bonding member 25 includes the power stage transistor 31 in a plan view, heat dissipation from the power stage transistor 31 to the first member 10 is not impaired as compared with a structure in which the bonding member 25 is disposed over the entire second surface 20B.

In order to further improve the heat dissipation from the power stage transistor 31, a via hole and a wire extending from the bonding member 15 to the semiconductor layer 10S may be disposed in the multilayer wiring layer 10W of the first member 10. These via holes and wirings function as thermal paths, and thermal resistance from the bonding member 15 to the semiconductor layer 10S can be reduced.

Also, in the first embodiment, as shown in fig. 1, the joint member 25 does not overlap with the input side circuit unit 40 in a plan view. The parasitic capacitance between the input side circuit unit 40 and the conductor pattern 25A of the joint member 25 is smaller than that of the structure in which the both overlap. Therefore, the coupling between the power stage transistor 31 and the input side circuit unit 40 via the joint member 25 becomes weak. As a result, the deterioration of the characteristics of the high-frequency amplification circuit 60 of the power stage is suppressed. In particular, a decrease in gain of the high-frequency amplifying circuit 60 of the power stage is suppressed. As a result, the output of the power-stage high-frequency amplifier circuit 60 is suppressed from being reduced, and the efficiency is suppressed from being reduced. Further, since the coupling strength from the output side circuit of the power stage transistor 31 to the input side circuit unit 40 is small, oscillation due to positive feedback from the output side circuit to the input side circuit unit 40 can be suppressed.

Second embodiment

Next, a semiconductor device according to a second embodiment will be described with reference to fig. 7. Hereinafter, a structure common to the semiconductor device according to the first embodiment described with reference to the drawings of fig. 1 to 6 will be omitted.

Fig. 7 is a schematic top view of a semiconductor device according to a second embodiment. In the first embodiment (fig. 1), the conductor pattern 25A including the plurality of power stage transistors 31 in plan view is arranged in an inner region distant from the edge of the second member 20. In contrast, in the second embodiment, the conductor pattern 25A extends from the region overlapping the plurality of power stage transistors 31 in a direction other than the direction toward the region where the input side circuit unit 40 is arranged, to the edge of the second member 20. In the second embodiment, the input side circuit unit 40 is also arranged outside the conductor pattern 25A in a plan view.

Next, the excellent effects of the second embodiment will be described. In the second embodiment, the area of the conductor pattern 25A is wider than that in the first embodiment. Therefore, the joining strength of the second member 20 and the first member 10 can be improved. Even if the conductor pattern 25A is expanded, the conductor pattern 25A does not overlap the input side circuit unit 40 in a plan view. Therefore, the deterioration of characteristics, such as the decrease in gain of the high-frequency amplifying circuit 60 of the power stage, and the oscillation can be suppressed as in the first embodiment.

Third embodiment

Next, a semiconductor device according to a third embodiment will be described with reference to fig. 8. Hereinafter, a structure common to the semiconductor device according to the first embodiment described with reference to the drawings of fig. 1 to 6 will be omitted.

Fig. 8 is a schematic top view of a semiconductor device according to a third embodiment. In the first embodiment (fig. 1), the joint member 25 is constituted by only one conductor pattern 25A. In contrast, in the third embodiment, the joint member 25 includes another conductor pattern 25B in addition to the conductor pattern 25A. The conductor pattern 25B is disposed along a part of the edge of the second member 20. Here, the term "conductor pattern 25B along the edge of the second member 20" includes both a structure in which the contour line of the outer peripheral side of the conductor pattern 25B coincides with the edge of the second member 20 in plan view, and a structure in which the contour line of the outer peripheral side of the conductor pattern 25B is disposed inside the edge of the second member 20 with a gap formed therebetween.

Regarding the transmission direction (up-down direction in fig. 8) of the high-frequency signal transmitted from the input side circuit unit 40 toward the output terminal 80, the conductor pattern 25B is arranged along the edge of the second member 20 in the range where the input side circuit unit 40 is not arranged. For example, the conductor pattern 25B has a U-shape that opens from the power stage transistor 31 toward the input side circuit unit 40 in a plan view.

The joining member 15 (fig. 2) on the first member 10 side also includes a conductor pattern that substantially overlaps the conductor pattern 25B in a plan view. The conductor pattern of the joining member 15 on the first member 10 side and the conductor pattern 25B on the second member 20 side are joined in contact with each other. In other embodiments described later, the joining member 15 on the first member 10 side is similarly arranged in a region overlapping with the region on the second member 20 side where the joining member 25 is arranged.

Next, the excellent effects of the third embodiment will be described. In the third embodiment, the bonding member 25 includes the conductor pattern 25B along the edge of the second member 20 in addition to the conductor pattern 25A including the plurality of power stage transistors 31 in plan view, and therefore the bonding strength of the first member 10 and the second member 20 can be improved as compared with the first embodiment (fig. 1). Further, since neither of the conductor patterns 25A and 25B of the joint member 25 overlaps the input side circuit unit 40 in a plan view, characteristic degradation and oscillation such as a gain reduction of the high-frequency amplifying circuit 60 of the power stage can be suppressed as in the first embodiment.

Fourth embodiment

Next, a semiconductor device according to a fourth embodiment will be described with reference to fig. 9. Hereinafter, a description of a structure common to the semiconductor device (fig. 8) according to the third embodiment will be omitted.

Fig. 9 is a schematic top view of a semiconductor device according to a fourth embodiment. In the third embodiment (fig. 8), the conductor pattern 25B of the joint member 25 is arranged along a part of the edge of the second member 20, but in the fourth embodiment, the conductor pattern 25B is arranged without a gap along the entire area of the edge of the second member 20 in a plan view. Neither of the conductor patterns 25A, 25B of the joint member 25 overlaps the input side circuit unit 40 in a plan view.

Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment, the area of one conductor pattern 25B of the joint member 25 is wider than that of the third embodiment (fig. 8). Therefore, the joining strength of the second member 20 and the first member 10 becomes further high. Further, since the one conductor pattern 25B of the joint member 25 is disposed along the entire region of the edge of the second member 20 in a plan view, the second member 20 can be stably supported.

In the fourth embodiment, neither of the two conductor patterns 25A and 25B of the joint member 25 overlaps the input side circuit unit 40 in a plan view. Therefore, degradation of characteristics and oscillation such as gain reduction due to coupling of the output-side circuit of the power stage transistor 31 and the input-side circuit unit 40 can be suppressed.

Fifth embodiment

Next, a semiconductor device according to a fifth embodiment will be described with reference to fig. 10. Hereinafter, a description of a structure common to the semiconductor device (fig. 9) according to the fourth embodiment will be omitted.

Fig. 10 is a schematic top view of a semiconductor device according to a fifth embodiment. In the fourth embodiment (fig. 9), one conductor pattern 25B of the joint member 25 is arranged without a gap along the entire area of the edge of the second member 20 in a plan view. In contrast, in the fifth embodiment, a slit of the conductor pattern 25B is provided at a position intersecting the inter-component connection wiring 85 connected to the input terminal 41, and the inter-component connection wiring 85 does not overlap with the conductor pattern 25B. Similarly, the joint member 15 (fig. 2A) on the first member 10 side is provided with a slit at the same position.

Next, the excellent effects of the fifth embodiment will be described. In the fourth embodiment (fig. 9), the inter-component connection wiring 85 connected to the input terminal 41 overlaps the conductor pattern 25B in a plan view, and thus parasitic capacitance is generated therebetween. Further, the conductor pattern 25B overlapping the inter-component connection wiring 85 is separated from the conductor pattern 25A including the power stage transistor 31, and thus the coupling between the circuit on the output side of the power stage transistor 31 and the circuit unit 40 on the input side is sufficiently reduced. In the fifth embodiment, since parasitic capacitance between the inter-component connection wiring 85 and the conductor pattern 25B hardly occurs, coupling of the output-side circuit of the power stage transistor 31 and the input-side circuit unit 40 can be further reduced.

Sixth embodiment

Next, a semiconductor device according to a sixth embodiment will be described with reference to fig. 11. Hereinafter, a description of a structure common to the semiconductor device (fig. 10) according to the fifth embodiment will be omitted.

Fig. 11 is a schematic top view of a semiconductor device according to a sixth embodiment. In the fifth embodiment (fig. 10), the inter-member connection wiring 86 connected to the bias terminal 42 overlaps the conductor pattern 25B of the joint member 25 in a plan view. In contrast, in the sixth embodiment, a slit of the conductor pattern 25B is provided at a position where the conductor pattern 25B and the inter-component connection wiring 86 intersect, and the conductor pattern 25B is separated into two conductor patterns. Therefore, the conductor pattern 25B does not overlap the bias terminal 42 in a plan view.

Next, the excellent effects of the sixth embodiment will be described. In the sixth embodiment, parasitic capacitance between the inter-component connection wiring 86 connected to the bias terminal 42 and the conductor pattern 25B hardly occurs. Therefore, the influence of the output signal of the power stage transistor 31 on the bias circuit can be further reduced.

Next, a modification of the sixth embodiment will be described. In the sixth embodiment, one gap is provided in the conductor pattern 25B for the two inter-component connection wirings 86, but two gaps may be provided that overlap with each of the two inter-component connection wirings 86. That is, the conductor pattern 25B is separated into three conductor patterns by the inter-component connection wiring 85 and the two inter-component connection wirings 86. For example, in the case where the interval between the two members connecting wiring 86 is wide at the crossing position with the edge of the second member 20, the structure of the present modification in which the conductor pattern 25B is separated into three conductor patterns may be adopted.

Seventh embodiment

Next, a semiconductor device according to a seventh embodiment will be described with reference to fig. 12. Hereinafter, a description of a structure common to the semiconductor device (fig. 11) according to the sixth embodiment will be omitted.

Fig. 12 is a schematic top view of a semiconductor device according to a seventh embodiment. In the sixth embodiment (fig. 11), one conductor pattern 25A includes two blocks of a plurality of power stage transistors 31. In contrast, in the seventh embodiment, the conductor pattern 25A is separated into two conductor patterns 25A1 and 25A2, and the conductor patterns 25A1 and 25A2 are arranged for the two blocks, respectively. The plurality of power stage transistors 31 of one block are included in one conductor pattern 25A1 in a plan view, and the plurality of power stage transistors 31 of the other block are included in the other conductor pattern 25A2 in a plan view.

Next, the excellent effects of the seventh embodiment will be described. In the sixth embodiment (fig. 11), the conductor pattern 25A functions as a thermal path between the plurality of power stage transistors 31 of one block and the plurality of power stage transistors 31 of another block. Thus, one block is susceptible to thermal influences from another block. In the seventh embodiment, the conductor pattern 25A1 of the plurality of power stage transistors 31 including one block and the conductor pattern 25A2 of the plurality of power stage transistors 31 including another block are separated from each other in a plan view, and thus the thermal coupling strength between the blocks is weakened. Therefore, the thermal influence between blocks is weakened.

For example, when the plurality of power stage transistors 31 of one block constitute a carrier amplifier of the doherty power amplifier and the plurality of power stage transistors 31 of the other block constitute a peak amplifier of the doherty power amplifier, the amount of heat generated from the plurality of power stage transistors 31 constituting the carrier amplifier is relatively large.

If a series of conductor patterns 25A (fig. 11) are arranged for two blocks, the thermal influence of the power stage transistors 31 constituting both ends of the carrier amplifier is unbalanced. As in the seventh embodiment, if the conductor pattern 25A1 and the conductor pattern 25A2 are separated, imbalance in thermal influence on the plurality of power stage transistors 31 constituting the carrier amplifier is alleviated. This enables the doherty power amplifier to operate with high efficiency.

Eighth embodiment

Next, a semiconductor device according to an eighth embodiment will be described with reference to fig. 13. Hereinafter, a description of a structure common to the semiconductor device (fig. 10) according to the fifth embodiment will be omitted.

Fig. 13 is a schematic top view of a semiconductor device according to an eighth embodiment. In the fifth embodiment (fig. 10), the plurality of power stage transistors 31 are separated into two blocks, and a space is ensured between the blocks. In contrast, in the eighth embodiment, the plurality of power stage transistors 31 are not separated into blocks, and all the power stage transistors 31 are arranged at equal intervals. In a top view, all the power stage transistors 31 are included in one conductor pattern 25A of the joint member 25.

In the fifth embodiment (fig. 10), two bias terminals 42 are arranged corresponding to the number of blocks of the plurality of power stage transistors 31, but in the eighth embodiment, one bias terminal 42 is arranged. Base bias is supplied to all power stage transistors 31 from one bias terminal 42.

Next, the excellent effects of the eighth embodiment will be described. As in the eighth embodiment, a plurality of power stage transistors 31 may be arranged equally from one end to the other. In this configuration as well, as in the fifth embodiment (fig. 10), the coupling between the plurality of power stage transistors 31 and the input side circuit unit 40 can be reduced without impairing the heat radiation from the plurality of power stage transistors 31 to the first member 10.

Next, a modification of the eighth embodiment will be described. In the eighth embodiment, one bias terminal 42 is provided for the plurality of power stage transistors 31, but two bias terminals 42 may be provided as in the semiconductor device (fig. 10) according to the fifth embodiment.

Ninth embodiment

Next, a semiconductor device according to a ninth embodiment will be described with reference to fig. 14. Hereinafter, a description of a structure common to the semiconductor device (fig. 10) according to the fifth embodiment will be omitted.

Fig. 14 is a schematic top view of a semiconductor device according to a ninth embodiment. In the fifth embodiment (fig. 10), a plurality of power stage transistors 31 are arranged along a straight line. In contrast, in the ninth embodiment, the plurality of power stage transistors 31 are arranged in an interleaved manner. Specifically, when a serial number is added to the plurality of power stage transistors 31 in the arrangement direction in one block, the odd-numbered power stage transistors 31 are arranged along one straight line, and the even-numbered power stage transistors 31 are also arranged along one straight line, and the even-numbered power stage transistors 31 are offset from the odd-numbered power stage transistors 31 in a direction substantially orthogonal to the arrangement direction.

The input side circuit unit 40 is parallel to the direction in which the plurality of power stage transistors 31 are arranged, and is disposed on a single side of a straight line passing through at least one power stage transistor 31. As the straight line passing through the at least one power stage transistor 31, for example, a straight line passing through the odd-numbered power stage transistors 31 may be employed, or a straight line passing through the even-numbered power stage transistors 31 may be employed.

The conductor pattern 25A of the joint member 25 is configured to include a smallest including quadrangle including the plurality of power stage transistors 31 in plan view.

Next, the excellent effects of the ninth embodiment will be described. When the plurality of power stage transistors 31 are arranged in a staggered manner, the distribution density of the plurality of heat sources becomes less dense than a configuration in which the plurality of power stage transistors are arranged along a straight line. Therefore, the heat dissipation effect from the plurality of power stage transistors 31 can be improved.

In the ninth embodiment, the area including the minimum quadrangle of the plurality of power stage transistors 31 in plan view is larger than in the configuration in which the plurality of power stage transistors 31 are arranged along one straight line as in the fifth embodiment (fig. 10) under the same size, interval, and number of power stage transistors 31 in plan view of each power stage transistor 31. The conductor pattern 25A of the joint member 25 is configured to include a smallest including quadrangle including the plurality of power stage transistors 31 in plan view, and therefore, the thermal resistance of the thermal path from the plurality of power stage transistors 31 toward the first member 10 can be reduced. As a result, heat dissipation to the first member 10 can be improved.

Tenth embodiment

Next, a semiconductor device according to a tenth embodiment will be described with reference to fig. 15. Hereinafter, a structure common to the semiconductor device according to the first embodiment described with reference to the drawings of fig. 1 to 6 will be omitted.

Fig. 15 is a schematic top view of a semiconductor device according to a tenth embodiment. In the tenth embodiment, the conductor pattern 25A of the bonding member 25 provided to the semiconductor device (fig. 1) according to the first embodiment expands in a direction other than the direction toward the region where the input side circuit unit 40 is arranged, reaching the edge of the second member 20. In the tenth embodiment, the input side circuit unit 40 is also arranged outside the conductor pattern 25A including the plurality of power stage transistors 31 in a plan view.

Further, along the edge of the second member 20 which is not in contact with the conductor pattern 25A including the plurality of power stage transistors 31, another conductor pattern 25B is arranged. The conductor pattern 25B does not overlap the input side circuit unit 40 in a plan view. The conductor pattern 25B is separated from the conductor pattern 25A including the plurality of power stage transistors 31.

Next, the excellent effects of the tenth embodiment will be described. In the tenth embodiment, the area of the conductor pattern 25A including the plurality of power stage transistors 31 is larger in plan view than in the first embodiment (fig. 1). Therefore, the heat dissipation by the thermal path from the plurality of power stage transistors 31 to the first component 10 via the conductor pattern 25A is improved. In the tenth embodiment, the total area of the conductor patterns 25A and 25B constituting the joint member 25 is wider than that of the first embodiment (fig. 1). Therefore, the joining strength of the second member 20 and the first member 10 can be improved.

The inter-component connection wiring 85 connected to the input terminal 41 overlaps the conductor pattern 25B in plan view, but the conductor pattern 25B is separated from the conductor pattern 25A including the plurality of power stage transistors 31 in plan view. Therefore, the coupling between the inter-component connection wiring 85 on the input side and the plurality of power stage transistors 31 is not reinforced.

Eleventh embodiment

Next, a semiconductor device according to an eleventh embodiment will be described with reference to fig. 16. Hereinafter, a description of a structure common to the semiconductor device according to the tenth embodiment (fig. 15) will be omitted.

Fig. 16 is a schematic top view of a semiconductor device according to an eleventh embodiment. In the tenth embodiment (fig. 15), the joint member 25 includes the conductor patterns 25A, 25B, and neither of the conductor patterns 25A, 25B overlaps the input side circuit unit 40 in a plan view. In contrast, in the eleventh embodiment, the joint member 25 includes a plurality of conductor patterns 25C in addition to the conductor patterns 25A, 25B. The plurality of conductor patterns 25C are dispersed in a region surrounded by the two conductor patterns 25A, 25B. A part of the plurality of conductor patterns 25C overlaps at least a part of the input side circuit unit 40 in a plan view.

Next, the excellent effects of the eleventh embodiment will be described. In the eleventh embodiment, the joint member 25 includes a plurality of conductor patterns 25C in addition to the conductor patterns 25A, 25B. Therefore, the joining strength of the second member 20 and the first member 10 can be improved. A part of the conductor pattern 25C overlaps at least a part of the input side circuit unit 40 in a plan view, but the conductor pattern 25C is separated from the conductor pattern 25A including the plurality of power stage transistors 31 in a plan view. Accordingly, the effect of weakening the coupling between the plurality of power stage transistors 31 and the input side circuit unit 40 is maintained.

Twelfth embodiment

Next, a semiconductor device according to a twelfth embodiment will be described with reference to fig. 17. Hereinafter, a description of a structure common to the semiconductor device according to the tenth embodiment (fig. 15) will be omitted.

Fig. 17 is a schematic top view of a semiconductor device according to a twelfth embodiment. In the tenth embodiment (fig. 15), the conductor pattern 25B that does not overlap the plurality of power stage transistors 31 in plan view does not overlap the input side circuit unit 40 either. In contrast, in the twelfth embodiment, the conductor pattern 25B overlaps at least a part of the input-side circuit unit 40 in a plan view. Further, as in the tenth embodiment (fig. 15), the conductor pattern 25B is separated from the conductor pattern 25A including the plurality of power stage transistors 31.

Next, the excellent effects of the twelfth embodiment will be described. In the twelfth embodiment, the total area of the conductor patterns 25A and 25B included in the joint member 25 is larger than that in the tenth embodiment (fig. 15). Therefore, the joining strength of the second member 20 and the first member 10 can be improved. The conductor patterns 25A, 25B are separated from each other, and therefore the effect of reducing the coupling of the plurality of power stage transistors 31 via the joint member 25 with the input side circuit unit 40 is maintained.

Thirteenth embodiment

Next, a semiconductor device according to a thirteenth embodiment will be described with reference to fig. 18 and 19. Hereinafter, a structure common to the semiconductor device according to the first embodiment described with reference to the drawings of fig. 1 to 6 will be omitted.

Fig. 18 is a schematic top view of a second member 20 of the semiconductor device according to the thirteenth embodiment. In the first embodiment (fig. 1), the plurality of power stage transistors 31 of the high frequency amplifying circuit 60 constituting the power stage of the high frequency amplifying circuit 64 (fig. 6) of the 2-stage structure are formed in the second member 20, and the plurality of driving stage transistors 51 (fig. 6) constituting the high frequency amplifying circuit 63 of the driving stage are formed in the first member 10 (fig. 2A). In contrast, in the thirteenth embodiment, both the plurality of power stage transistors 31 and the plurality of driving stage transistors 51 are formed in the second member 20. The plurality of driving stage transistors 51 are electrically connected to the plurality of power stage transistors 31. A plurality of input capacitors 36 are provided for each of the plurality of power stage transistors 31 and an input capacitor 56 is provided for each of the plurality of drive stage transistors 51. In addition, the plurality of power stage transistors 31 may be equally arranged without being divided into two blocks as in the semiconductor device of the eighth embodiment (fig. 13).

The second member 20 is further provided with a driving stage bias circuit 61, a power stage bias circuit 62, a plurality of capacitors 72C, a plurality of inductors 72L, an input terminal 65, a battery voltage terminal 66, a driving stage bias control terminal 67, and a power stage bias control terminal 68. Some of the plurality of capacitors 72C may be disposed at positions overlapping the conductor projections 88.

The input side circuit unit 40 of the plurality of power stage transistors 31 includes a plurality of passive elements such as an input capacitor 36, a plurality of driving stage transistors 51, an input capacitor 56, a driving stage bias circuit 61, a power stage bias circuit 62, an input terminal 65, a capacitor 72C, and an inductor 72L. In this way, the input side circuit unit 40 may include active elements such as the driver stage transistor 51. The input terminal 65, battery voltage terminal 66, drive stage bias control terminal 67, and power stage bias control terminal 68 are formed of the same conductor protrusions as conductor protrusions 88 (fig. 2A). The terminal conductor protrusions constituting the input terminal 65, the battery voltage terminal 66, the driving stage bias control terminal 67, and the power stage bias control terminal 68 are included in the input side circuit unit 40.

The joint member 25 includes two conductor patterns 25A, 25D. As in the first embodiment (fig. 1), one conductor pattern 25A includes a plurality of power stage transistors 31 in plan view. The input-side circuit unit 40 is arranged outside the conductor pattern 25A in a plan view. The other conductor pattern 25D is arranged at a position including the driver stage transistor 51 in a plan view.

Fig. 19 is a block diagram of a semiconductor device according to a thirteenth embodiment. The circuit structure of the semiconductor device according to the thirteenth embodiment is the same as the circuit structure (fig. 6) of the semiconductor device according to the first embodiment. In fig. 19, the input capacitors 36 and 56 are not shown. In the first embodiment, the input matching circuit 70, the plurality of driving stage transistors 51, the inter-stage matching circuit 71, the plurality of power stage transistors 31, the driving stage bias circuit 61, and the power stage bias circuit 62 are provided to the first component 10 or the module substrate or the like, but in the thirteenth embodiment, they are provided to the second component 20.

The input terminal 65 is connected to the input matching circuit 70, and a high-frequency signal RFin is input to the input terminal 65. The high-frequency signal output from the driving stage transistor 51 is input to the power stage transistor 31 via the inter-stage matching circuit 71. The input matching circuit 70 and the inter-stage matching circuit 71 are constituted by a plurality of capacitors 72C and inductors 72L (fig. 18). The output terminal 80 is connected to the power stage transistor 31, and an output signal RFout is output from the output terminal 80. The power supply voltages Vcc1 and Vcc2 are applied to the driving stage transistor 51 and the power stage transistor 31 via each of the two terminals 81 for external connection. Further, the power supply voltage Vcc2 may be applied via the output terminal 80.

The battery voltage terminal 66 is connected to the driving stage bias circuit 61 and the power stage bias circuit 62, and the battery voltage Vbatt is supplied to the battery voltage terminal 66. The driving stage bias control terminal 67 is connected to the driving stage bias circuit 61, and the driving stage bias control signal Vbias1 is input to the driving stage bias control terminal 67. The two power stage bias control terminals 68 are connected to the power stage bias circuit 62, and the power stage bias control signals Vbias2 and Vbias3 are input to the two power stage bias control terminals 68, respectively.

Next, the excellent effects of the thirteenth embodiment will be described. In the thirteenth embodiment as well, as in the first embodiment (fig. 1), the plurality of power stage transistors 31 are included in one conductor pattern 25A of the joint member 25 in a plan view, and therefore the heat radiation from the plurality of power stage transistors 31 to the first member 10 is not impaired. Further, since the plurality of driving stage transistors 51 are included in the other conductor pattern 25D of the joint member 25 in a plan view, heat dissipation from the plurality of driving stage transistors 51 can be ensured.

Further, since the input-side circuit unit 40 of the power stage transistor 31 does not overlap with the conductor pattern 25A including the power stage transistor 31 in plan view, the coupling between the power stage transistor 31 and the input-side circuit unit 40 via the joint member 25 can be reduced as in the first embodiment (fig. 1).

Fourteenth embodiment

Next, a semiconductor device according to a fourteenth embodiment is described with reference to fig. 20. Hereinafter, a description of a structure common to the semiconductor device (fig. 18 and 19) according to the thirteenth embodiment will be omitted.

Fig. 20 is a schematic plan view of a second member 20 of the semiconductor device according to the fourteenth embodiment. In the thirteenth embodiment (fig. 18), one conductor pattern 25D of the joint member 25 includes the driving stage transistor 51 in a plan view. In contrast, in the fourteenth embodiment, one conductor pattern 25B is arranged along the edge of the second member 20 sandwiching the input side circuit unit 40 together with the power stage transistor 31 in a plan view. The input-side circuit unit 40 and any of the conductor patterns 25A and 25B of the joint member 25 do not overlap in plan view.

Next, the excellent effects of the fourteenth embodiment will be described. In the fourteenth embodiment, as in the thirteenth embodiment, the coupling between the power stage transistor 31 and the input side circuit unit 40 via the joint member 25 can be reduced without impairing the heat radiation from the power stage transistor 31 to the first member 10. Further, since the two conductor patterns 25A and 25B of the joint member 25 are arranged so as to sandwich the region where the input side circuit unit 40 is arranged, the second member 20 can be supported more stably.

Fifteenth embodiment

Next, a semiconductor device according to a fifteenth embodiment will be described with reference to fig. 21. Hereinafter, a description of a structure common to the semiconductor device (fig. 18 and 19) according to the thirteenth embodiment will be omitted.

Fig. 21 is a schematic plan view of a second member 20 of the semiconductor device according to the fifteenth embodiment. In the fifteenth embodiment, the bonding part 25 includes a conductor pattern 25B in addition to the two conductor patterns 25A, 25D included in the bonding part 25 of the semiconductor device according to the thirteenth embodiment (fig. 18).

Next, the excellent effects of the fifteenth embodiment will be described. In the fifteenth embodiment, as in the thirteenth embodiment (fig. 19), the coupling between the power stage transistor 31 and the input side circuit unit 40 via the joint member 25 can be reduced without impairing the heat radiation from the power stage transistor 31 and the driving stage transistor 51 to the first member 10. Further, the second member 20 can be supported more stably as in the fourteenth embodiment (fig. 20).

Sixteenth embodiment

Next, a semiconductor device according to a sixteenth embodiment will be described with reference to fig. 22. Hereinafter, a description of a structure common to the semiconductor device (fig. 18 and 19) according to the thirteenth embodiment will be omitted.

Fig. 22 is a schematic plan view of a second member 20 of the semiconductor device according to the sixteenth embodiment. In the sixteenth embodiment, the bonding member 25 includes four conductor patterns 25E arranged at four corners of the second member 20 in addition to the two conductor patterns 25A, 25D included in the bonding member 25 of the semiconductor device according to the thirteenth embodiment (fig. 18).

Next, the excellent effects of the sixteenth embodiment will be described. In the sixteenth embodiment, the bonding strength of the second member 20 and the first member 10 can be improved as compared with the semiconductor device according to the thirteenth embodiment. The four conductor patterns 25E do not overlap with any of the power stage transistor 31 and the input side circuit unit 40 in a plan view. Therefore, even if the conductor pattern 25E is newly added to the semiconductor device of the thirteenth embodiment (fig. 18), the effect of reducing the coupling between the power stage transistor 31 and the input side circuit unit 40 via the joint member 25 is not impaired.

Seventeenth embodiment

Next, a semiconductor device according to a seventeenth embodiment will be described with reference to fig. 23. Hereinafter, a description of a structure common to the semiconductor device (fig. 18 and 19) according to the thirteenth embodiment will be omitted.

Fig. 23 is a schematic top view of a second member 20 of the semiconductor device according to the seventeenth embodiment. In the seventeenth embodiment, the bonding part 25 includes a conductor pattern 25B arranged along an edge of the second member 20 in addition to the two conductor patterns 25A, 25D included in the bonding part 25 of the semiconductor device according to the thirteenth embodiment (fig. 18). The conductor pattern 25B has a seamless annular shape in plan view, and is disposed over the entire periphery of the second member 20.

Next, the excellent effects of the seventeenth embodiment will be described. In the seventeenth embodiment, the bonding member 25 includes the conductor pattern 25B arranged along the edge of the second member 20, and therefore the bonding strength of the second member 20 and the first member 10 can be further improved compared to the semiconductor device according to the thirteenth embodiment (fig. 18). The conductor pattern 25B does not overlap with any of the power stage transistor 31 and the input side circuit unit 40 in a plan view. Therefore, even if the conductor pattern 25B is newly added to the semiconductor device of the thirteenth embodiment (fig. 18), the effect of reducing the coupling between the power stage transistor 31 and the input side circuit unit 40 via the joint member 25 is not impaired.

Eighteenth embodiment

Next, a semiconductor device according to an eighteenth embodiment will be described with reference to fig. 24. Hereinafter, a description of a structure common to the semiconductor device (fig. 23) according to the seventeenth embodiment will be omitted.

Fig. 24 is a schematic plan view of a second member 20 of the semiconductor device according to the eighteenth embodiment. In the seventeenth embodiment (fig. 23), no slit is provided in the conductor pattern 25B along the edge of the second member 20, and the conductor pattern 25B has a closed loop shape. In contrast, in the eighteenth embodiment, the conductor pattern 25B (fig. 23) of the seventeenth embodiment is separated into a conductor pattern 25B1 on the region side where the plurality of power stage transistors 31 and the output terminals 80 are arranged and a conductor pattern 25B2 on the region side where the input side circuit unit 40 is arranged.

Next, the excellent effects of the eighteenth embodiment will be described. In the eighteenth embodiment, since the conductor patterns 25B1, 25B2 along the edge of the second member 20 are separated, the coupling between the plurality of power stage transistors 31 and the input side circuit unit 40 via the joint member 25 can be further weakened as compared with the seventeenth embodiment (fig. 23).

Nineteenth embodiment

Next, a semiconductor device according to a nineteenth embodiment will be described with reference to fig. 25. Hereinafter, a description of a structure common to the semiconductor device (fig. 24) according to the eighteenth embodiment will be omitted.

Fig. 25 is a schematic top view of a second member 20 of the semiconductor device according to the nineteenth embodiment. In the eighteenth embodiment (fig. 24), the plurality of power stage transistors 31 are separated into two blocks for which one conductor pattern 25A is arranged. In contrast, in the nineteenth embodiment, as in the seventh embodiment (fig. 12), conductor patterns 25A1 and 25A2 are arranged for each block, and are separated from each other.

Next, the excellent effects of the nineteenth embodiment will be described. In the nineteenth embodiment, as in the seventh embodiment, the thermal influence between blocks of the plurality of power stage transistors 31 is reduced. When the doherty power amplifier is configured by the plurality of power stage transistors 31, the thermal influence between the carrier amplifier and the peak amplifier is reduced, and the doherty power amplifier can operate with high efficiency.

Twentieth embodiment

Next, a semiconductor device according to a twentieth embodiment will be described with reference to fig. 26 and 27. Hereinafter, a description of a structure common to the semiconductor device (fig. 24) according to the eighteenth embodiment will be omitted.

Fig. 26 is a schematic plan view of a semiconductor device according to a twentieth embodiment. The second member 20 is joined to the first member 10. In the eighteenth embodiment, the battery voltage terminal 66, the driving stage bias control terminal 67, and the two power stage bias control terminals 68 are constituted by conductor protrusions for connection with an external circuit. In contrast, in the twentieth embodiment, the inter-component connection wiring 76 is connected to the battery voltage terminal 66, the inter-component connection wiring 77 is connected to the driving stage bias control terminal 67, and the two inter-component connection wirings 78 are connected to the two power stage bias control terminals 68, respectively.

The inter-component connection wirings 76, 77, 78 connect the circuit formed in the first component 10 and the circuit formed in the second component 20, similarly to the inter-component connection wiring 86 (fig. 2) of the semiconductor device of the first embodiment. These inter-component connection wirings 76, 77, 78 are connected to a control circuit formed in the first component 10. The inter-component connection wirings 76, 77, 78 intersect the conductor pattern 25B2 in a plan view, and overlap the conductor pattern 25B2 at the intersection position.

Fig. 27 is a block diagram of a semiconductor device according to a twentieth embodiment. The structures of the power stage transistor 31, the driving stage transistor 51, the driving stage bias circuit 61, the power stage bias circuit 62, the input matching circuit 70, and the inter-stage matching circuit 71 formed in the second member 20 are the same as those of the semiconductor device (fig. 19) of the thirteenth embodiment. A control circuit 16 is formed in the first member 10.

The control circuit 16 is supplied with the power supply voltage VIO1, the control signal SDATA1, and the clock signal SCLK1. The control circuit 16 supplies the driving stage bias control signal Vbias1 to the driving stage bias circuit 61 via the inter-component connection wiring 77 and the driving stage bias control terminal 67 based on the control signal SDATA 1. Then, based on the control signal SDATA1, the control circuit 16 supplies the power stage bias control signals Vbias2 and Vbias3 to the power stage bias circuit 62 via the inter-component connection wiring 78 and the power stage bias control terminal 68. The battery voltage Vbatt is supplied from the first component 10 to the driving stage bias circuit 61 and the power stage bias circuit 62 via the inter-component connection wiring 76 and the battery voltage terminal 66.

Next, the excellent effects of the twentieth embodiment will be described. In the twentieth embodiment, as in the eighteenth embodiment (fig. 24), the coupling between the power stage transistor 31 and the input side circuit unit 40 via the joint member 25 can be reduced without impairing the heat radiation from the power stage transistor 31 to the first member 10.

In the eighteenth embodiment (fig. 24), the battery voltage terminal 66, the driving stage bias control terminal 67, the power stage bias control terminal 68 are connected to a module substrate or the like, and are connected to a control circuit via wiring in the module substrate. In contrast, in the twentieth embodiment, the battery voltage terminal 66, the driving-stage bias control terminal 67, and the two power-stage bias control terminals 68 can be connected to the control circuit 16 in the semiconductor device of the twentieth embodiment without via the wiring in the module substrate.

Twenty-first embodiment

Next, a semiconductor device according to a twenty-first embodiment will be described with reference to fig. 28 and 29. Hereinafter, a description of a structure common to the semiconductor device according to the twentieth embodiment (fig. 26 and 27) will be omitted.

Fig. 28 is a schematic top view of a semiconductor device according to a twenty-first embodiment. In the twentieth embodiment (fig. 26), the input terminal 65 is constituted by a conductor protrusion. A high-frequency signal is input to the input terminal 65 from the module substrate protruding from the connection conductor. In contrast, in the twenty-first embodiment, the inter-component connection wiring 75 is connected to the input terminal 65.

The conductor pattern 25B2 of the semiconductor device (fig. 26) according to the twentieth embodiment is separated into two conductor patterns 25B21, 25B22 at a position intersecting the inter-component connection wiring 75. That is, the inter-component connection wiring 75 does not overlap any of the conductor patterns 25A, 25B1, 25B21, 25B22, 25D of the joint member 25 in a plan view.

Fig. 29 is a block diagram of a semiconductor device according to a twenty-first embodiment. The high-frequency signal RFin is input from the first component 10 to the input terminal 65 of the second component 20 via the inter-component connection wiring 75.

Next, the excellent effects of the twenty-first embodiment will be described. In the twenty-first embodiment, a high-frequency signal is input from the circuit formed in the first member 10 to the input terminal 65 of the second member 20 without via wiring of a module substrate or the like. Further, a switch for selecting one node from a plurality of nodes for supplying a high-frequency signal may be formed in the first member 10, and the selected node may be connected to the input terminal 65 via the inter-member connection wiring 75. For example, in the case where the first component 10 is formed with a mixer that up-converts an intermediate frequency signal into a high frequency signal, in the semiconductor device according to the twenty-first embodiment, the high frequency signal RFin can be supplied from the mixer to the second component 20.

Since the inter-component connection wiring 75 for transmitting the high-frequency signal RFin and the bonding member 25 do not overlap in plan view, an increase in parasitic capacitance between the inter-component connection wiring 75 and the bonding member 25 is suppressed. This can further improve the effect of suppressing the feedback of the output signal from the power stage transistor 31 to the inter-component connection wiring 75.

[ twenty-second embodiment ]

Next, a semiconductor device according to a twenty-second embodiment will be described with reference to fig. 30. Hereinafter, a description of a structure common to the semiconductor device (fig. 23) according to the seventeenth embodiment will be omitted.

Fig. 30 is a schematic top view of a second member 20 of a semiconductor device according to a twenty-second embodiment. In the seventeenth embodiment (fig. 23), the conductor pattern 25B arranged along the edge of the second member 20 has a closed loop shape. In contrast, in the twenty-second embodiment, a plurality of conductor patterns 25F are arranged at intervals in the circumferential direction along the edge of the second member 20.

Next, the excellent effects of the twenty-second embodiment will be described. In the twenty-second embodiment, as in the seventeenth embodiment (fig. 23), the coupling between the power stage transistor 31 and the input side circuit unit 40 via the joint member 25 can be reduced without impairing the heat radiation from the power stage transistor 31 to the first member 10. Further, in the twenty-second embodiment, the circuit units arranged in the vicinity of the edge of the second member 20 are suppressed from being coupled to each other via the conductor pattern 25B arranged along the edge of the second member 20.

[ twenty-third embodiment ]

Next, a semiconductor device according to a twenty-third embodiment will be described with reference to fig. 31. Hereinafter, a description of a structure common to the semiconductor device (fig. 23) according to the seventeenth embodiment will be omitted.

Fig. 31 is a schematic top view of a second member 20 of a semiconductor device according to a twenty-third embodiment. In the seventeenth embodiment (fig. 23), the conductor pattern 25B arranged along the edge of the second member 20 surrounds the region inside the second member 20 in a plan view. In contrast, in the twenty-third embodiment, the conductor patterns 25BO, 25BI arranged along the edge of the second member 20 double-surround the region inside the second member 20 in a plan view. One conductor pattern 25BO is disposed on the outer peripheral side of the other conductor pattern 25BI, and a gap is secured therebetween. In addition, each of the conductor patterns 25BO, 25BI has a closed loop shape without gaps.

Next, the excellent effects of the twenty-third embodiment will be described. In the twenty-second embodiment, as in the seventeenth embodiment (fig. 23), the coupling between the power stage transistor 31 and the input side circuit unit 40 via the joint member 25 can be reduced without impairing the heat radiation from the power stage transistor 31 to the first member 10. In addition, in the twenty-third embodiment, the same degree of joint strength as in the seventeenth embodiment (fig. 23) can be ensured.

[ twenty-fourth embodiment ]

Next, a semiconductor device according to a twenty-fourth embodiment will be described with reference to fig. 32. Hereinafter, a description of a structure common to the semiconductor device (fig. 31) according to the twenty-third embodiment will be omitted.

Fig. 32 is a schematic top view of a second member 20 of a semiconductor device according to a twenty-fourth embodiment. In the twenty-third embodiment (fig. 31), the conductor patterns 25BO, 25BI doubly arranged along the edge of the second member 20 each have a closed loop-like shape without gaps. In contrast, in the twenty-fourth embodiment, instead of the closed conductor pattern 25BI (fig. 31) on the inner peripheral side, two conductor patterns 25BI1, 25BI2 separated in the circumferential direction are arranged. One conductor pattern 25BI1 surrounds the region where the plurality of power stage transistors 31 and the output terminal 80 are arranged in a U shape from three directions. The other conductor pattern 25BI2 surrounds the region where the input-side circuit unit 40 is arranged in a U-shape from three directions.

Next, the excellent effects of the twenty-fourth embodiment will be described. In the present embodiment, since the conductor patterns 25BI1, 25BI2 on the inner peripheral side arranged along the edge of the second member 20 are separated from each other, the coupling between the power stage transistor 31 and the input side circuit unit 40 via the joint member 25 can be further reduced as compared with the twenty-third embodiment (fig. 31).

[ twenty-fifth embodiment ]

Next, a semiconductor device according to a twenty-fifth embodiment will be described with reference to fig. 33. Hereinafter, a description of a structure common to the semiconductor device (fig. 32) according to the twenty-fourth embodiment will be omitted.

Fig. 33 is a schematic top view of the second member 20 of the semiconductor device according to the twenty-fifth embodiment. In the twenty-fourth embodiment (fig. 32), two conductor patterns 25BI1, 25BI2 are arranged along the edge of the second member 20 on the inner peripheral side, and one conductor pattern 25BO is arranged on the outer peripheral side. In contrast, in the twenty-fifth embodiment, two conductor patterns 25BO1 and 25BO2 separated in the circumferential direction are arranged instead of the conductor pattern 25BO on the outer circumferential side of the twenty-fourth embodiment (fig. 32). The two conductor patterns 25BO1 and 25BO2 on the outer peripheral side are separated at substantially the same positions in the circumferential direction as the positions at which the conductor patterns 25BI1 and 25BI2 on the inner peripheral side are separated. The separation positions of the outer conductor patterns 25BO1 and 25BO2 and the separation positions of the inner conductor patterns 25BI1 and 25BI2 may be shifted in the circumferential direction.

Next, the excellent effects of the twenty-fifth embodiment will be described. In the twenty-fifth embodiment, not only the conductor patterns 25BI1, 25BI2 on the inner peripheral side and the conductor patterns 25BO1, 25BO2 on the outer peripheral side arranged along the edge of the second member 20 are also separated from each other, and therefore, the coupling between the power stage transistor 31 and the input side circuit unit 40 via the joint member 25 can be further reduced as compared with the twenty-fourth embodiment (fig. 32).

[ twenty-sixth embodiment ]

Next, a semiconductor device according to a twenty-sixth embodiment will be described with reference to fig. 34. Hereinafter, a description of a structure common to the semiconductor device (fig. 18 and 19) according to the thirteenth embodiment will be omitted.

Fig. 34 is a schematic plan view of a second member 20 of a semiconductor device according to a twenty-sixth embodiment. In the thirteenth embodiment (fig. 18), the conductor pattern 25A including the plurality of power stage transistors 31 is arranged at a distance from the edge of the second member 20 in a plan view. In contrast, in the twenty-sixth embodiment, the conductor pattern 25A including the plurality of power stage transistors 31 in plan view extends in a direction not overlapping the input side circuit unit 40 to reach the edge of the second member 20.

The conductor pattern 25B is arranged along the edge of the second member 20 so as to surround the input-side circuit unit 40 in a U-shape from three directions. The conductor pattern 25B has substantially the same shape as the conductor pattern 25B2 of the semiconductor device (fig. 24) of the eighteenth embodiment in a plan view, and is disposed at substantially the same position.

Next, the excellent effects of the twenty-sixth embodiment will be described. Since the conductor pattern 25A of the semiconductor device according to the twenty-sixth embodiment is larger than the conductor pattern 25A of the semiconductor device (fig. 18) according to the thirteenth embodiment, heat dissipation from the plurality of power stage transistors 31 to the first member 10 can be improved. Even if the conductor pattern 25A including the plurality of power stage transistors 31 in a plan view is expanded, the conductor pattern 25A does not overlap with the input side circuit unit 40 in a plan view, and therefore the effect of reducing the coupling between the plurality of power stage transistors 31 and the input side circuit unit 40 via the joint member 25 is not impaired.

Twenty-seventh embodiment

Next, a semiconductor device according to a twenty-seventh embodiment will be described with reference to fig. 35. Hereinafter, a description of a structure common to the semiconductor device (fig. 34) according to the twenty-sixth embodiment will be omitted.

Fig. 35 is a schematic plan view of a second member 20 of a semiconductor device according to a twenty-seventh embodiment. The bonding part 25 of the semiconductor device according to the twenty-seventh embodiment includes a plurality of conductor patterns 25G in addition to the conductor patterns 25A, 25B, 25D of the semiconductor device (fig. 34) according to the twenty-sixth embodiment. The plurality of conductor patterns 25G are dispersed in the region where the input side circuit unit 40 is arranged. However, the plurality of conductor patterns 25G are arranged so as not to overlap the inductor 72L of the input side circuit unit 40 in a plan view.

Next, the excellent effects of the twenty-seventh embodiment will be described. In the twenty-seventh embodiment, since a plurality of conductor patterns 25G are arranged in addition to the conductor patterns 25A, 25B, 25D of the twenty-sixth embodiment (fig. 34), the bonding strength between the second member 20 and the first member 10 can be further improved. Since the conductor pattern 25G does not overlap the inductor 72L in a plan view, the high-frequency magnetic field generated in the inductor 72L is not shielded by the conductor pattern 25G. Therefore, the conductor pattern 25G has less influence on the inductance of the inductor 72L.

Twenty-eighth embodiment

Next, a semiconductor device according to a twenty-eighth embodiment will be described with reference to fig. 36. Hereinafter, a description of a structure common to the semiconductor device (fig. 35) according to the twenty-seventh embodiment will be omitted.

Fig. 36 is a schematic top view of the second member 20 of the semiconductor device according to the twenty-eighth embodiment. In the twenty-seventh embodiment (fig. 35), the plurality of conductor patterns 25G are arranged so as not to overlap the inductor 72L in a plan view. In contrast, in the twenty-eighth embodiment, the conductor pattern 25GL is arranged in a region overlapping the spiral inductor 72L in a plan view. The conductor pattern 25GL overlapping the inductor 72L in a plan view has a shape that is longer than the other conductor patterns 25G.

Next, the excellent effects of the twenty-eighth embodiment will be described. In the twenty-eighth embodiment, since the conductor pattern 25GL is also arranged at the position overlapping the inductor 72L, the bonding strength between the second member 20 and the first member 10 can be further improved as compared with the twenty-seventh embodiment (fig. 35). Further, since the conductor pattern 25GL disposed at a position overlapping the inductor 72L has an elongated shape, it is difficult for eddy current caused by the high-frequency magnetic field generated by the inductor 72L to flow. Therefore, the influence given to the inductance of the inductor 72L is lessened.

Twenty-ninth embodiment

Next, a semiconductor device according to a twenty-ninth embodiment will be described with reference to fig. 37. Hereinafter, a description of a structure common to the semiconductor device (fig. 10) according to the fifth embodiment will be omitted.

Fig. 37 is a schematic top view of a semiconductor device according to a twenty-ninth embodiment. In the fifth embodiment (fig. 10), the plurality of power stage transistors 31 of two blocks are arranged entirely along a straight line. In contrast, in the twenty-ninth embodiment, a plurality of power stage transistors 31 arranged in two rows in substantially parallel constitute one block, and two of the blocks are arranged. The two blocks are arranged in a direction substantially orthogonal to the arrangement direction of the power stage transistors 31.

In each block, an input wiring 35 extends from each of the plurality of power stage transistors 31 of the two columns toward the outside of the transistor column, and an input capacitor 36 is connected to each input wiring 35. A column of input capacitors 36 is formed corresponding to each column of the power stage transistors 31. A collector wiring 33C is arranged between the two transistor columns.

Extending in a direction parallel to the direction in which the two blocks are arranged (left-right direction in fig. 37), an input terminal 41 is arranged on one side of a band-shaped region of the plurality of power stage transistors 31 including the two blocks, and an output terminal 80 is arranged on the other side. And, two bias terminals 42 are arranged. The collector wiring 33C of one block and the collector wiring 33C of the other block are connected to each other on the side where the output terminal 80 is arranged, and further connected to the output terminal 80. The collector wiring 33C of one block, the collector wiring 33C of the other block, and the portion connecting the two are constituted by one conductor pattern.

The signal input wiring 34I is configured to overlap each capacitor column including a plurality of input capacitors 36. The signal input wirings 34I extend to the side where the input terminals 41 are arranged, respectively, and are connected to the input terminals 41. The inter-component connection wiring 85 is connected to the input terminal 41, and the two inter-component connection wirings 86 are connected to the two bias terminals 42, respectively.

The high-frequency signal inputted to the input terminal 41 is outputted to the output terminal 80 through the signal input wiring 34I, the plurality of input capacitors 36, the plurality of power stage transistors 31, and the collector wiring 33C.

The bonding member 25 includes conductor patterns 25A1, 25A2, 25B. The conductor pattern 25A1 includes a plurality of power stage transistors 31 of one block in plan view, and the conductor pattern 25A2 includes a plurality of power stage transistors 31 of another block. The input side circuit unit 40 including the plurality of input capacitors 36 and the input terminals 41 is arranged outside the conductor patterns 25A1, 25A2 in a plan view.

The conductor pattern 25B is arranged along the edge of the second member 20 in a plan view. A slit is provided in the conductor pattern 25B. The slit is disposed at a position crossing the inter-component connection wiring 85 connected to the input terminal 41.

Next, the excellent effects of the twenty-ninth embodiment will be described. In the twenty-ninth embodiment, as in the fifth embodiment, since the conductor patterns 25A1 and 25A2 including the plurality of power stage transistors 31 in plan view are provided, heat dissipation from the plurality of power stage transistors 31 to the first member 10 is not impaired. Further, since the coupling between the output-side circuit of the plurality of power stage transistors 31 and the input-side circuit unit 40 via the joint member 25 becomes weak, degradation of characteristics such as gain reduction due to interference between the two and oscillation can be suppressed. Further, since the conductor pattern 25B is arranged along the edge of the second member 20, the bonding strength of the second member 20 to the first member 10 can be improved.

(thirty-third embodiment)

Next, a semiconductor device according to a thirty-first embodiment is described with reference to fig. 38. Hereinafter, a description of a structure common to the semiconductor device (fig. 37) according to the twenty-ninth embodiment will be omitted.

Fig. 38 is a schematic top view of a semiconductor device according to a thirty-third embodiment. In the twenty-ninth embodiment (fig. 37), the conductor patterns 25A1 and 25A2 of the plurality of power stage transistors 31 including the two blocks, respectively, are separated from each other in a plan view. In contrast, in the thirty-first embodiment, one conductor pattern 25A includes two blocks of the plurality of power stage transistors 31 in a plan view. Even in this case, the one conductor pattern 25A does not overlap the input side circuit unit 40 in a plan view.

Next, the excellent effects of the thirty-first embodiment will be described. In the thirty-first embodiment, the area of the conductor pattern 25A including the plurality of power stage transistors 31 is wider in plan view than in the twenty-ninth embodiment (fig. 37). Accordingly, heat dissipation from the plurality of power stage transistors 31 to the first component 10 is improved.

Thirty-first embodiment

Next, a semiconductor device according to a thirty-first embodiment will be described with reference to fig. 39 and 40. Hereinafter, a description of a structure common to the semiconductor device (fig. 37) according to the twenty-ninth embodiment will be omitted.

Fig. 39 is a schematic top view of a semiconductor device according to a thirty-first embodiment, and fig. 40 is a top view of an enlarged power stage transistor. In the twenty-ninth embodiment (fig. 37), as shown in fig. 4 of the first embodiment, the emitter electrode 32E, the base electrode 32B, and the collector electrode 32C connected to the power stage transistor 31 each have a shape longer in one direction in plan view, and are arranged so that the longitudinal directions of the electrodes are substantially parallel.

In contrast, in the thirty-first embodiment, as shown in fig. 40, the emitter electrode 32E surrounds the base electrode 32B which is circular in plan view, and the collector electrode 32C surrounds the emitter electrode 32E. In fig. 40, base electrode 32B, emitter electrode 32E, and collector electrode 32C are hatched.

The input wiring 35 extends from the base electrode 32B in one direction (left direction in fig. 40). Slits are provided in the emitter electrode 32E and the collector electrode 32C so that the emitter electrode 32E and the collector electrode 32C do not contact the input wiring 35. The base mesa 31BM of the power stage transistor 31 is configured to include the base electrode 32B and the emitter electrode 32E in plan view, and does not overlap the collector electrode 32C.

In fig. 40, the emitter electrode 32E has a C-shaped configuration in which a part of the annular shape is cut out in a plan view, but may have a U-shaped configuration. In this case, the base mesa 31BM may have a shape formed of a semicircular portion and a rectangular portion connected to the edge of the straight line of the semicircular portion. As another configuration example, the shape of the base electrode 32B may be a polygon such as a regular octagon. In this case, the inner peripheral side and outer peripheral side edges of the emitter electrode 32E and the inner peripheral side edge of the collector electrode 32C may be shaped to reflect the outer shape of the base electrode 32B.

The collector 32C extends in a direction opposite to the direction in which the input wiring 35 extends (rightward in fig. 35), and is connected to the collector wiring 33C at the front end. The emitter electrode 32E is connected to an emitter wiring 33E overlapping the emitter electrode 32E in a plan view.

The input wiring 35 is connected to a lower electrode 36U of the input capacitor 36. The signal input wiring 34I is arranged to overlap the lower electrode 36U in a plan view. The signal input line 34I functions as an upper electrode of the input capacitor 36.

As shown in fig. 39, the joint member 25 includes three conductor patterns 25A1, 25A2, 25B. The conductor pattern 25A1 is configured as a plurality of power stage transistors 31 including one block, and the conductor pattern 25A2 is configured as a plurality of power stage transistors 31 including another block. The conductor pattern 25B is arranged along the edge of the second member 20 in a plan view.

The plurality of input capacitors 36, the input terminal 41, and the signal input wiring 34I connecting the input capacitors 36 and the input terminal 41 are included in the input side circuit unit 40 of the plurality of power stage transistors 31. The input side circuit unit 40 is arranged outside the conductor patterns 25A1 and 25A2 including the plurality of power stage transistors 31 in plan view.

Next, the excellent effects of the thirty-first embodiment will be described. In the thirty-first embodiment, as in the twenty-ninth embodiment (fig. 37), the coupling between the output-side circuit of the plurality of power stage transistors 31 and the input-side circuit unit 40 can be reduced without impairing the heat radiation from the plurality of power stage transistors 31 to the first member 10.

Thirty-second embodiment

Next, a semiconductor device according to a thirty-second embodiment is described with reference to fig. 41. Hereinafter, a description of a structure common to the semiconductor device (fig. 10) according to the fifth embodiment will be omitted.

Fig. 41 is a schematic top view of a semiconductor device according to a thirty-second embodiment. The second member 20 is joined to the first member 10. In the fifth embodiment (fig. 10), the plurality of power stage transistors 31 are separated into two blocks. In contrast, in the thirty-second embodiment, the plurality of power stage transistors 31 are separated into four blocks 38A, 38B, 38C, 38D. The plurality of power stage transistors 31 constitute a differential doherty power amplifier.

For example, the plurality of power stage transistors 31 of the blocks 38A and 38C constitute a doherty amplifier for non-inverted signals, and the plurality of power stage transistors 31 of the blocks 38B and 38D constitute a doherty amplifier for inverted signals. The plurality of power stage transistors 31 of blocks 38A, 38B operate as carrier amplifiers of the doherty power amplifier, and the plurality of power stage transistors 31 of blocks 38C, 38D operate as peak amplifiers of the doherty power amplifier.

The input terminals 41A1, 41A2, 41B1, 41B2 are connected to inter-component connection wirings 85A1, 85A2, 85B1, 85B2, respectively. The two bias terminals 42A are connected to the two inter-component connection wirings 86B, respectively, and the two bias terminals 42B are connected to the two inter-component connection wirings 86B, respectively.

The non-inversion signal is input to the input terminals 41A1, 41B1 via each inter-component connection wiring 85A1, 85B 1. The inversion signal is input to the input terminals 41A2, 41B2 via each inter-component connection wiring 85A2, 85B 2. The non-inversion signal may be input to the input terminals 41A1 and 41B2 via each of the inter-component connection wirings 85A1 and 85B2, and the inversion signal may be input to the input terminals 41A2 and 41B1 via each of the inter-component connection wirings 85A2 and 85B 1. The non-inverted signal inputted to the two input terminals 41A1, 41B1 is inputted to the plurality of power stage transistors 31 of the blocks 38A, 38C via the input capacitor 36 and the input wiring 35. The inversion signals input to the other two input terminals 41A2, 41B2 are input to the plurality of power stage transistors 31 of the blocks 38B, 38D via the input capacitor 36 and the input wiring 35.

Four output terminals 80A, 80B, 80C, 80D are arranged corresponding to the four blocks 38A, 38B, 38C, 38D. The output signals amplified by the plurality of power stage transistors 31 of the respective four blocks 38A, 38B, 38C, 38D are output from the corresponding output terminals 80A, 80B, 80C, 80D.

A plurality of input capacitors 36, four input terminals 41A1, 41A2, 41B1, 41B2, wirings connecting these input terminals and the input capacitors 36, two sets of bias terminals 42A, 42B, and the like are included in the input side circuit unit 40 of the plurality of power stage transistors 31. The collector wiring 33C connected to the plurality of power stage transistors 31 of each of the four blocks 38A, 38B, 38C, 38D, the four output terminals 80A, 80B, 80C, 80D, and the like constitute a circuit on the output side of the power stage transistors 31.

The total four bias terminals 42A, 42B correspond to the four blocks 38A, 38B, 38C, 38D, respectively. The bias voltages supplied to the bias terminals 42A, 42B are supplied to the plurality of power stage transistors 31 of the corresponding block.

The joint member 25 includes conductor patterns 25A1, 25A2, 25B1, 25B2, 25B3, and 25B4. The conductor pattern 25A1 includes a plurality of power stage transistors 31 of the blocks 38A and 38B in plan view. The conductor pattern 25A2 includes a plurality of power stage transistors 31 of the blocks 38C and 38D in plan view. That is, the conductor pattern 25A1 includes a plurality of power stage transistors 31 that operate as carrier amplifiers of the doherty power amplifier in a plan view, and the conductor pattern 25A2 includes a plurality of power stage transistors 31 that operate as peak amplifiers of the doherty power amplifier in a plan view.

The conductor patterns 25B1, 25B2, 25B3, and 25B4 are arranged along the edge of the second member 20 in a plan view, and are separated from each other at positions where the inter-member connection wirings 85A1, 85A2, 85B1, and 85B2 are respectively arranged. Therefore, the inter-component connection wirings 85A1, 85A2, 85B1, and 85B2 connected to the input terminals 41A1, 41A2, 41B1, and 41B2, respectively, do not overlap with any of the conductor patterns of the joint member 25 in a plan view.

Next, excellent effects of the semiconductor device according to the thirty-second embodiment will be described. In the thirty-second embodiment, as in the fifth embodiment (fig. 10), the coupling between the plurality of power stage transistors 31 and the input side circuit unit 40 can be reduced without impairing the heat radiation from the plurality of power stage transistors 31 to the first member 10.

The conductor pattern 25A1 of the plurality of power stage transistors 31 including the blocks 38A and 38B operating as carrier amplifiers in a plan view and the conductor pattern 25A2 of the plurality of power stage transistors 31 including the blocks 38C and 38D operating as peak amplifiers in a plan view are separated from each other. According to this configuration, the thermal influence between the carrier amplifier and the peak amplifier is reduced, and the thermal balance of the carrier amplifier can be maintained, thereby realizing a high-efficiency operation.

Thirty-third embodiment

Next, a semiconductor device according to a thirty-third embodiment is described with reference to fig. 42. Hereinafter, a description of a structure common to the semiconductor device (fig. 41) according to the thirty-second embodiment will be omitted.

Fig. 42 is a schematic top view of a semiconductor device according to a thirty-third embodiment. In the thirty-second embodiment (fig. 41), one conductor pattern 25A1 includes a plurality of power stage transistors 31 of two blocks 38A, 38B in plan view. In contrast, in the thirty-third embodiment, the conductor patterns 25a11, 25a12, 25a21, 25a22 are arranged for each block 38A, 38B, 38C, 38D. The plurality of power stage transistors 31 of the four blocks 38A, 38B, 38C, 38D are respectively included in the conductor patterns 25a11, 25a12, 25a21, 25a22 in plan view.

The conductor pattern 25a11 of the plurality of power stage transistors 31 including the carrier amplifier for non-inverted signals and the conductor pattern 25a12 of the plurality of power stage transistors 31 including the carrier amplifier for inverted signals are separated from each other. Similarly, the conductor patterns 25a21 of the plurality of power stage transistors 31 including the peak amplifier for the non-inverted signal and the conductor patterns 25a22 of the plurality of power stage transistors 31 including the peak amplifier for the inverted signal are separated from each other.

Next, the excellent effects of the thirty-third embodiment will be described. In the thirty-third embodiment, the thermal influence between the carrier amplifier for the non-inverted signal and the carrier amplifier for the inverted signal is reduced. Further, the thermal influence between the peak amplifier for the non-inverted signal and the peak amplifier for the inverted signal is reduced. The thermal balance of each of the non-inverted signal and the inverted signal carrier amplifiers can be maintained, and a high-efficiency operation can be realized.

Thirty-fourth embodiment

Next, a semiconductor device according to a thirty-fourth embodiment is described with reference to fig. 43A, 43B, and 43C. Hereinafter, a structure common to the semiconductor device according to the first embodiment described with reference to the drawings of fig. 1 to 6 will be omitted.

Fig. 43A is a schematic top view of a semiconductor device according to a thirty-fourth embodiment, and fig. 43B and 43C are schematic cross-sectional views at dash-dot lines 43B-43B and 43C-43C, respectively, of fig. 43A. The semiconductor device according to the first embodiment (fig. 1, 2A) includes a first member 10 and a second member 20 formed of different materials. In contrast, the semiconductor device according to the thirty-fourth embodiment includes: a semiconductor component 120 made of a compound semiconductor, a high-frequency amplification circuit 60 formed at a power stage of the semiconductor component 120, and a conductor component 125.

The structure of the power stage high-frequency amplification circuit 60 is the same as that of the power stage high-frequency amplification circuit 60 of the semiconductor device (fig. 1) according to the first embodiment. Specifically, the high-frequency amplification circuit 60 of the power stage includes: a plurality of power stage transistors 31, a plurality of input wirings 35, a plurality of input capacitors 36, an input terminal 41, two bias terminals 42, a collector wiring 33C, an output terminal 80, and the like. The input capacitor 36, the input terminal 41, wiring connecting the two, the bias terminal 42, and the like are included in the input side circuit unit 40 of the plurality of power stage transistors 31.

The input terminal 41 and the bias terminal 42 are pads for connection wiring, and serve as terminals for connecting the inter-component connection wirings 85, 86 (fig. 1) similarly to the input terminal 41 and the bias terminal 42 of the semiconductor device (fig. 1) according to the first embodiment, for example.

The conductor member 125 is disposed on a surface of the semiconductor member 120 opposite to a surface on which the power stage high-frequency amplification circuit 60 is formed. In fig. 43A, the conductor member 125 is hatched. The conductor member 125 serves as a bonding layer for bonding with other members, for example, as in the bonding member 25 of the first embodiment (fig. 1, 2A).

The conductor member 125 is configured to include a plurality of power stage transistors 31 in plan view. The input side circuit unit 40 is arranged outside the conductor member 125 in a plan view. The same material as the joint member 25 of the first embodiment (fig. 1) is used for the conductor member 125, for example.

The other external connection terminals 81 are arranged on the surface of the semiconductor component 120 on which the power stage high-frequency amplifier circuit 60 is formed. The output terminal 80 and the external connection terminal 81 are constituted by conductor projections 88 (fig. 2A).

Next, the excellent effects of the thirty-fourth embodiment will be described. The conductor member 125 including the plurality of power stage transistors 31 constitutes a part of a heat dissipation path from the plurality of power stage transistors 31 in plan view. When the conductor member 125 is joined to other members as in the first embodiment (fig. 1, 2A, 2B), heat is radiated from the power stage transistor 31 to the other members through the conductor member 125.

The conductor member 125 including the plurality of power stage transistors 31 in a plan view does not overlap the input side circuit unit 40 in a plan view, and thus coupling between the plurality of power stage transistors 31 and the input side circuit unit 40 via the conductor member 125 is reduced.

Thirty-fifth embodiment

Next, a semiconductor device according to a thirty-fifth embodiment is described with reference to fig. 44A, 44B, and 44C. Hereinafter, a description of a structure common to the semiconductor device according to the thirty-fourth embodiment (fig. 43A, 43B, and 43C) will be omitted.

Fig. 44A is a schematic top view of a semiconductor device according to a thirty-fifth embodiment, and fig. 44B and 44C are schematic cross-sectional views at the dash-dot lines 44B-44B and the dash-dot lines 44C-44C, respectively, of fig. 44A. In the thirty-fourth embodiment, the input terminal 41 and the bias terminal 42 are terminals for connecting the inter-member connection wirings 85, 86 (fig. 1), and the like. In contrast, in the thirty-fifth embodiment, the input terminal 41 and the bias terminal 42 are constituted by conductor protrusions 88 (fig. 2A) such as bumps.

The semiconductor device according to the thirty-fifth embodiment is flip-chip bonded to a module substrate or the like, whereby an input signal is input from the module substrate to the input terminal 41 and a bias voltage is supplied to the bias terminal 42.

Next, the excellent effects of the thirty-fifth embodiment will be described. In the thirty-fifth embodiment, as in the thirty-fourth embodiment (fig. 43A, 43B, and 43C), when the conductor member 125 is joined to another member, heat is radiated from the power stage transistor 31 to the other member through the conductor member 125. Further, the coupling between the plurality of power stage transistors 31 and the input side circuit unit 40 via the conductor member 125 is reduced.

Thirty-sixth embodiment

Next, a semiconductor device according to a thirty-sixth embodiment will be described with reference to fig. 45 and 46. Hereinafter, a structure common to the semiconductor device according to the first embodiment described with reference to the drawings of fig. 1 to 6 will be omitted.

Fig. 45 is a schematic top view of a semiconductor device according to a thirty-sixth embodiment. Fig. 1 and 2A showing a semiconductor device according to a first embodiment show a plurality of conductor protrusions 88 constituting an output terminal 80 and a terminal 81 for external connection. Several conductor protrusions 88 are connected to the pads 87 provided on the second member 20, and the remaining plurality of conductor protrusions 88 are connected to the pads 87 provided on the first member 10.

In the thirty-sixth embodiment, two first-member upper conductor projections 100 are provided in addition to these conductor projections 88. The number of the conductor protrusions 100 on the first member may be one or three or more. The first-member upper-conductor protrusion 100 is arranged outside the second member 20 in a plan view and protrudes from the first surface 10A of the first member 10. For example, the two first-component-upper-conductor protrusions 100 are arranged on an extension line extending the columns of the plurality of power stage transistors 31 and at positions sandwiching the plurality of power stage transistors 31. A conductive bump base pattern 101 is arranged between the first surface 10A and the first component-side conductive bump 100. In fig. 45, the same hatching as the joint members 15 and 25 is added to the conductor-protrusion base pattern 101.

Fig. 46 is a partial cross-sectional view of the semiconductor device shown in fig. 45. A conductive protrusion base pattern 101 is disposed in a region of the first surface 10A of the first member 10 where the second member 20 is not disposed. The conductor-protrusion base pattern 101 is formed by the same process as the process of forming the joining member 15 on the first member 10 side. That is, the conductor-bump base pattern 101 is formed of the same conductive material as the bonding member 15 on the first member 10 side.

An insulating film 90 is disposed on the conductor-bump base pattern 101. An opening exposing the conductor-bump base pattern 101 is provided in the insulating film 90, and a first-member upper-conductor-bump lower portion 100A is disposed in the opening. The first component upper conductor bump lower portion 100A is formed by the same process as the process of forming the pad 87. An insulating film 91 is disposed on the first member upper conductor projection lower portion 100A and the insulating film 90. The insulating film 91 is provided with an opening exposing the lower portion 100A of the first-member upper conductor protrusion, and the upper portion 100B of the first-member upper conductor protrusion is disposed in the opening. The conductor projection upper portion 100B on the first member is formed by the same process as the process of forming the conductor projection 88 for the terminal. The first-member upper-conductor-projection lower portion 100A and the first-member upper-conductor-projection upper portion 100B constitute the first-member upper-conductor projection 100. That is, the first-member upper conductor bump 100 is connected to the first member 10 via the conductive conductor-bump base pattern 101. The first member upper conductor projection 100 projects upward from the upper surface of the insulating film 91 as in the conductor projection 88.

Next, the excellent effects of the thirty-sixth embodiment will be described.

In the thirty-sixth embodiment, as in the first embodiment, the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed without reducing the heat conduction characteristics from the power stage transistor 31 provided in the second member 20 to the first member 10.

In the thirty-sixth embodiment, in the structure in which the first component-upper conductor protrusion 100 is mounted on the module substrate or the like, as shown by thick arrows in fig. 46, heat conducted from the power stage transistor 31 to the first component 10 is conducted to the module substrate via the first component-upper conductor protrusion 100. Therefore, the heat dissipation from the second member 20, particularly the power stage transistor 31, can be improved.

Next, a preferred positional relationship between the conductor protrusion 100 on the first member and the second member 20 will be described with reference to fig. 45.

The high-frequency signal amplified by the power stage transistor 31 is input to the second member 20 from the direction in which the input side circuit unit 40 is arranged (the direction toward the lower side in fig. 45) as viewed from the power stage transistor 31. The high-frequency signal amplified by the power stage transistor 31 is output in a direction opposite to a direction in which the input side circuit unit 40 is arranged as viewed from the power stage transistor 31 (a direction toward the upper side in fig. 45).

Accordingly, a transmission line and a high-frequency circuit element for a high-frequency signal are disposed on the side from which the high-frequency signal is input and the side from which the high-frequency signal is output as viewed from the second member 20. The first-member upper-conductor bump 100 is preferably arranged so as to avoid a region where a transmission line for a high-frequency signal or a high-frequency circuit element is arranged. For example, it is preferable that the first component upper conductor bump 100 is arranged in a direction extending a column constituted by a plurality of power stage transistors 31 as viewed from the power stage transistors 31.

In order to reduce the thermal resistance of the heat conduction path from the power stage transistor 31 to the module substrate via the first component-side conductor bump 100, the first component-side conductor bump 100 is preferably disposed close to the second component 20.

As an example, when the dimension of the shape of the conductor projection 100 on the first member in a plan view is denoted by D, and the shortest distance from the conductor projection 100 on the first member to the second member 20 in a plan view is denoted by G, it is preferable that the shortest distance G be 2 times or less the dimension D. When the shape of the first-member upper-conductor projection 100 in a plan view is circular, the dimension D is equal to the diameter of the first-member upper-conductor projection 100. When the conductor protrusion 100 on the first member has an elongated strip shape in a plan view, the width of the strip shape may be used as the dimension D. In general, the minimum interval of two parallel lines sandwiching the conductor protrusion 100 on the first member with two parallel lines tangential from both sides in a plan view can be defined as a dimension D.

Further, since the power stage transistor 31 disposed in the second member 20 serves as a main heat source, the conductor bump 100 on the first member is preferably disposed as close to the power stage transistor 31 as possible. For example, the second member 20 may have a convex polygonal shape (preferably a convex quadrangular shape, more preferably a rectangular shape or a square shape) in a plan view, and the geometric center C of the region where the power stage transistor 31 is arranged may be set as the center, and at least a part of the conductor protrusion 100 on the first member may overlap with the region inside the circle 110 passing through the corner of the second member 20 closest to the geometric center C. As the geometric center C of the region where the power stage transistors 31 are arranged, a geometric center containing a minimum quadrangle including a plurality of power stage transistors 31, for example, the base mesa 31BM (fig. 3) in a plan view may be employed.

In addition, it is preferable to suppress the variation in temperature of the plurality of power stage transistors 31. For example, it is preferable to ensure symmetry of the heat dissipation path. As an example, it is preferable that the first component-upper conductor bumps 100 are each disposed at a position that is line-symmetrical with respect to a straight line 111 passing through the geometric center C of the region where the power stage transistors 31 are disposed and orthogonal to the arrangement direction of the power stage transistors 31 in a plan view. By suppressing the variation in the temperatures of the plurality of power stage transistors, deterioration of the characteristics of the transistors and damage due to thermal runaway can be suppressed.

Next, a modification of the thirty-sixth embodiment will be described.

In the thirty-sixth embodiment, the first-component-upper conductor projections 100 are arranged on the extension lines extending the columns of the plurality of power stage transistors 31, but the first-component-upper conductor projections 100 may be arranged at other positions. For example, the inter-component connection wiring 85 may be disposed on both sides of the second component 20. For example, the conductor protrusions 100 on the first member may be disposed at positions 105 indicated by broken lines in fig. 45.

Thirty-seventh embodiment

Next, a semiconductor device according to a thirty-seventh embodiment is described with reference to fig. 47. Hereinafter, a description of a structure common to the semiconductor device (fig. 8) according to the third embodiment will be omitted.

In the third embodiment (fig. 8), two conductor patterns constituting the joining member 15 (fig. 2A) on the first member 10 side are substantially overlapped with the conductor patterns 25A, 25B of the joining member 25 on the second member 20 side, respectively. In contrast, in the thirty-seventh embodiment, the conductor pattern 15B on the first member 10 side overlapped with the conductor pattern 25B having the U-shape opened from the power stage transistor 31 toward the input side circuit unit 40 protrudes from the inside to the outside of the second member 20 in a plan view. Further, the other conductor pattern 15A on the first member 10 side substantially overlaps the conductor pattern 25A on the second member 20 side.

In fig. 47, the conductor patterns 15A and 15B on the first member 10 side are hatched. The same applies to the drawings subsequent to fig. 49. In the present specification, a conductor pattern that protrudes from the inside to the outside of the second member 20 in a plan view of a plurality of conductor patterns that constitute the joint member 15 on the first member 10 side is sometimes referred to as an "protruding conductor pattern". In the thirty-seventh embodiment, the conductor pattern 15B is a protruding conductor pattern.

In the thirty-seventh embodiment, two first-member upper-conductor protrusions 100 are arranged in the same manner as in the thirty-sixth embodiment (fig. 45). In the thirty-sixth embodiment (fig. 45), the conductor-projection base pattern 101 to which the conductor projections 100 on the first member are connected is not connected to the second member 20 in a plan view. In contrast, in the thirty-seventh embodiment, the first-member upper conductor protrusion 100 is arranged at the protruding portion that protrudes from the conductor pattern 15B. That is, the protruding conductor pattern 15B is used as the conductor-bump base pattern 101 (fig. 45).

Fig. 48 is a cross-sectional view of a portion of the semiconductor device shown in fig. 47. The conductor pattern 15B on the first member 10 side protrudes from the region directly below the second member 20 to the outside of the second member 20. The protruding conductor pattern 15B is connected to the second member 20 via the conductor pattern 25B on the second member 20 side. The first-component-upper conductor projection 100 is connected to the protruding portion protruding the conductor pattern 15B.

Next, the excellent effects of the thirty-seventh embodiment will be described.

In the thirty-seventh embodiment, as in the third embodiment, the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed without reducing the heat conduction characteristics from the power stage transistor 31 to the first member 10.

In the thirty-seventh embodiment, in addition to the heat conduction path (arrow of broken line) of the semiconductor device according to the thirty-sixth embodiment (fig. 46), a heat conduction path (arrow of solid line) from the second member 20 to the conductor protrusion 100 on the first member through the conductor pattern 25B on the second member 20 side and the conductor pattern 15B on the first member 10 side is formed. Therefore, compared to the thirty-sixth embodiment, the thermal resistance of the heat conduction path from the power stage transistor 31 to the conductor protrusion 100 on the first member is reduced. This can improve the heat dissipation from the power stage transistor 31.

(thirty-eighth embodiment)

Next, a semiconductor device according to a thirty-eighth embodiment is described with reference to fig. 49. Hereinafter, a description of a structure common to the semiconductor device (fig. 9) according to the fourth embodiment will be omitted.

Fig. 49 is a schematic top view of a semiconductor device according to a thirty-eighth embodiment. In the thirty-eighth embodiment, the conductor pattern 15B on the first member 10 side overlapped with the conductor pattern 25B on the second member 20 side of the fourth embodiment (fig. 9) protrudes from the second member 20 toward the four directions in a plan view. The two first-component-upper conductor protrusions 100 are connected to the protruding portions of the conductor pattern 15B.

Next, the excellent effects of the thirty-eighth embodiment will be described.

In the thirty-eighth embodiment, as in the fourth embodiment (fig. 9), the joining strength of the second member 20 and the first member 10 can be improved. In addition, as in the thirty-seventh embodiment (fig. 47 and 48), the heat dissipation from the power stage transistor 31 can be improved.

Next, a semiconductor device according to a modification of the thirty-eighth embodiment will be described with reference to fig. 50 to 54. Fig. 50 to 54 are schematic plan views of a semiconductor device according to a modification of the thirty-eighth embodiment. In the thirty-eighth embodiment (fig. 49), the conductor pattern 25B on the second member 20 side and the conductor pattern 15B on the first member 10 side are arranged without gaps along the edge of the second member 20 in a plan view.

In the modification shown in fig. 50, similarly to the semiconductor device (fig. 10) according to the fifth embodiment, the conductor pattern 25B and the slit of the conductor pattern 15B are provided at the position intersecting the inter-member connection wiring 85 connected to the input terminal 41. That is, the conductor patterns 15B and 25B do not overlap with the inter-component connection wiring 85. The two first-component-upper conductor protrusions 100 are connected to the protruding portions of the conductor pattern 15B.

In the modification shown in fig. 51, similarly to the semiconductor device (fig. 11) according to the sixth embodiment, the conductor pattern 25B and the slit of the conductor pattern 15B are provided at the position intersecting the inter-member connection wiring 85 connected to the input terminal 41 and the position intersecting the two inter-member connection wirings 86 connected to the two bias terminals 42, respectively. That is, the conductor patterns 15B and 25B do not overlap with the inter-component connection wirings 85 and 86.

In the modification shown in fig. 52, as in the semiconductor device (fig. 12) according to the seventh embodiment, the conductor pattern 25A is separated into two conductor patterns 25A1, 25A2, and the conductor pattern 15A is also separated into two conductor patterns 15A1, 15A2. Further, similarly to the modification example shown in fig. 51, slits are provided at two positions of the conductor patterns 15B and 25B. The conductor patterns 15A1 and 25A1 are arranged for one of the two blocks of the plurality of power stage transistors 31, and the conductor patterns 15A2 and 25A2 are arranged for the other block. The two first-component-upper conductor protrusions 100 are connected to the protruding portions of the conductor pattern 15B.

In the modification shown in fig. 53, as in the semiconductor device according to the eighth embodiment (fig. 13), the plurality of power stage transistors 31 are not separated into blocks, all the power stage transistors 31 are arranged at equal intervals, one bias terminal 42 is provided, and one inter-component connection wiring 86 connected to the bias terminal 42 is provided. As in the modification shown in fig. 50, a slit is provided at one position of the conductor patterns 15B and 25B. All power stage transistors 31 are included in the conductor patterns 15A, 25A in a top view. The two first-component-upper conductor protrusions 100 are connected to the protruding portions of the conductor pattern 15B.

In the modification shown in fig. 54, a plurality of power stage transistors 31 are arranged in a staggered pattern like the semiconductor device according to the ninth embodiment (fig. 14), and a slit is provided at one of the conductor patterns 15B and 25B like the modification shown in fig. 50. The two first-component-upper conductor protrusions 100 are connected to the protruding portions of the conductor pattern 15B.

In the modification shown in the drawings of fig. 50 to 54, as in the semiconductor device according to the thirty-eighth embodiment, the heat dissipation from the power stage transistor 31 can be improved.

Thirty-ninth embodiment

Next, a semiconductor device according to a thirty-ninth embodiment is described with reference to fig. 55. Hereinafter, a description of a structure common to the semiconductor device (fig. 15) according to the tenth embodiment will be omitted.

Fig. 55 is a schematic top view of a semiconductor device according to a thirty-ninth embodiment. In the tenth embodiment (fig. 15), the conductor pattern 15A on the first member 10 side and the conductor pattern 25A on the second member 20 side are extended from the region where the plurality of power stage transistors 31 are arranged in a direction other than the direction toward the region where the input side circuit unit 40 is arranged, to the edge of the second member 20. In contrast, in the thirty-ninth embodiment, the conductor pattern 15A on the first member 10 side protrudes from the inner side to the outer side of the second member 20 in a plan view. The two first-component-upper conductor protrusions 100 are arranged at the protruding portion and connected to the conductor pattern 15A. That is, the protruding conductor pattern 15A includes a plurality of power stage transistors 31 in a plan view.

Next, the excellent effects of the thirty-ninth embodiment will be described.

In the thirty-ninth embodiment, as in the tenth embodiment (fig. 15), oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed. In the thirty-ninth embodiment, the area of the conductor patterns 15A and 25A including the plurality of power stage transistors 31 in plan view is larger than that of the thirty-seventh embodiment (fig. 47). Therefore, the heat dissipation by the thermal path from the plurality of power stage transistors 31 to the first component 10 via the conductor patterns 15A, 25A is improved.

In the thirty-ninth embodiment, the conductor pattern 15A is connected to the first-component-upper conductor bump 100, so that a thermal path is formed from the power stage transistor 31 to the module substrate through the second-component-20-side conductor pattern 25A, the first-component-10-side conductor pattern 15A, and the first-component-upper conductor bump 100. Therefore, the heat dissipation from the power stage transistor 31 can be further improved.

Next, a semiconductor device according to a modification of the thirty-ninth embodiment will be described with reference to fig. 56. Fig. 56 is a schematic plan view of a semiconductor device according to a modification of the thirty-ninth embodiment.

In the modification shown in fig. 56, as in the semiconductor device (fig. 16) according to the eleventh embodiment, a plurality of conductor patterns 25C are dispersed in the region surrounded by the conductor patterns 15A, 25A and the conductor patterns 15B, 25B. The conductor pattern 15C on the first member 10 side is arranged to substantially overlap with the plurality of conductor patterns 25C on the second member 20 side. The two first-component-upper conductor protrusions 100 are disposed on the protruding portion of the conductor pattern 15A and connected to the conductor pattern 15A.

In the modification of the thirty-ninth embodiment shown in fig. 56, the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed. Further, the joining strength between the second member 20 and the first member 10 can be improved.

Fortieth embodiment

Next, a semiconductor device according to a fortieth embodiment is described with reference to fig. 57. Hereinafter, a description of a structure common to the semiconductor device (fig. 17) according to the twelfth embodiment will be omitted.

Fig. 57 is a schematic top view of a semiconductor device according to a fortieth embodiment. In the twelfth embodiment (fig. 17), the conductor patterns 15A, 25A and the conductor patterns 15B, 25B are included in the second member 20 in a plan view. In contrast, in the fortieth embodiment, the conductor patterns 15A and 15B protrude outside the second member 20 in a plan view. The two first-component-upper conductor protrusions 100 are disposed on the protruding portion of the conductor pattern 15A and connected to the conductor pattern 15A.

Next, the excellent effects of the fortieth embodiment will be described.

In the fortieth embodiment, as in the twelfth embodiment, oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed. In the fortieth embodiment, heat dissipation from the power stage transistor 31 can be improved as in the thirty-ninth embodiment.

Forty-first embodiment

Next, a semiconductor device according to a forty-first embodiment will be described with reference to fig. 58. Hereinafter, a description of a structure common to the semiconductor device according to the thirteenth embodiment (fig. 18 and 19) will be omitted.

Fig. 58 is a schematic top view of a semiconductor device according to a forty-first embodiment. In fig. 18 showing the semiconductor device of the thirteenth embodiment, only the second member 20 is shown, the first member 10 is not shown, and the conductor protrusion on the first member is not explicitly shown. In the fortieth embodiment, the conductor-bump base pattern 101 is arranged outside the second member 20 in a plan view in the same manner as in the thirty-sixth embodiment (fig. 45 and 46), and the conductor bumps 100 on the first member are arranged to be included in the conductor-bump base pattern 101.

As in the thirteenth embodiment (fig. 18), the conductor pattern 15A on the first member 10 side and the conductor pattern 25A on the second member 20 side including the power stage transistor 31 in plan view are arranged. Further, a conductor pattern 15D including the driver stage transistor 51 on the first member 10 side and a conductor pattern 25D including the second member 20 side are arranged.

Next, the excellent effects of the forty-first embodiment will be described.

In the forty-first embodiment, as in the thirteenth embodiment (fig. 18 and 19), the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed without reducing the heat conduction characteristics from the power stage transistor 31 provided in the second member 20 to the first member 10. In the forty-first embodiment, the heat radiation from the second member 20 can be improved in the same manner as in the thirty-sixth embodiment (fig. 45 and 46).

Next, a preferred position of disposing the conductor protrusion 100 on the first member will be described. The preferred positional relationship of the conductor protrusion 100 on the first member and the second member 20 is the same as in the case of the thirty-sixth embodiment (fig. 45). The amount of heat generated from the power stage transistor 31 provided in the second component 20 is larger than the amount of heat generated from the driving stage transistor 51. Therefore, it is preferable to dispose the first-component-upper-conductor protrusion 100 at a position where the shortest distance from the first-component-upper-conductor protrusion 100 to the power stage transistor 31 is shorter than the shortest distance to the driving stage transistor 51.

Forty-second embodiment

Next, a semiconductor device according to a forty-second embodiment will be described with reference to fig. 59. Hereinafter, a description of a structure common to the semiconductor device according to the sixteenth embodiment (fig. 22) will be omitted.

Fig. 59 is a schematic top view of a semiconductor device according to a forty-second embodiment. In the sixteenth embodiment (fig. 22), four conductor patterns 25E on the first member 10 side are arranged at four corners of the second member 20, respectively, and conductor patterns (not explicitly shown in fig. 22) on the first member 10 side are arranged at positions overlapping the conductor patterns 25E. The conductor patterns (not explicitly shown in fig. 22) on the first member 10 side are arranged to overlap with the conductor patterns 25A and 25D on the second member 20 side, respectively.

In the forty-second embodiment, each of the conductor patterns 15E arranged at the four corners of the second member 20 protrudes from the inside to the outside of the second member 20 in a plan view. The conductor protrusions 100 on the first member are arranged on the protruding portions of the two conductor patterns 15E, and are connected to the conductor patterns 15E. For example, the conductor pattern 15E having the shortest distance to the power stage transistor 31 among the four conductor patterns 15E, and the protruding portion of the second short conductor pattern 15E are provided with the first-component-upper conductor protrusion 100. The first component-side conductor bumps 100 may be connected to the protruding portions of one conductor pattern 15E or three or more conductor patterns 15E.

The conductor patterns 15A and 15D on the first member 10 side are arranged to overlap with the conductor patterns 25A and 25D on the second member 20 side, respectively.

Next, the excellent effects of the forty-second embodiment will be described.

In the forty-second embodiment, as in the sixteenth embodiment (fig. 22), the heat conduction characteristics from the power stage transistor 31 provided in the second component 20 to the first component 10 are not reduced, and the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed. In the forty-second embodiment, the heat radiation from the second member 20 can be improved in the same manner as in the thirty-sixth embodiment (fig. 45 and 46).

Forty-third embodiment

Next, a semiconductor device according to a forty-third embodiment will be described with reference to fig. 60. Hereinafter, a description of a structure common to the semiconductor device according to the seventeenth embodiment (fig. 23) will be omitted.

Fig. 60 is a schematic top view of a semiconductor device according to a forty-third embodiment. In the seventeenth embodiment (fig. 23), the conductor pattern 25B on the second member 20 side and the conductor pattern on the first member 10 side that substantially overlaps the conductor pattern 25B are included in the second member 20 in a plan view. In contrast, in the forty-third embodiment, the conductor pattern 15B on the first member 10 side arranged along the edge of the second member 20 protrudes from the inside to the outside of the second member 20 in a plan view. The two first-component-upper conductor protrusions 100 are disposed on the protruding portion of the conductor pattern 15A and connected to the conductor pattern 15A.

Next, the excellent effects of the forty-third embodiment will be described.

In the forty-third embodiment, as in the seventeenth embodiment (fig. 23), the heat conduction characteristics from the power stage transistor 31 provided in the second component 20 to the first component 10 are not reduced, and the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed. In the forty-third embodiment, the heat radiation from the second member 20 can be improved as in the thirty-sixth embodiment (fig. 45 and 46).

Next, a semiconductor device according to a modification of the forty-third embodiment will be described with reference to the drawings of fig. 61 to 67. Fig. 61 to 67 are schematic plan views of a semiconductor device according to a modification of the forty-third embodiment.

In the forty-third embodiment (fig. 60), the protruding amount of the conductor pattern 15B from the edge is constant from one end to the other end of each of the four edges of the second member 20. In contrast, in the modification shown in fig. 61, the protruding conductor pattern 15B along both edges (the right edge and the left edge in fig. 61) of the second member 20 includes a relatively large protruding amount portion and a relatively small protruding amount portion. Therefore, the outer peripheral line of the protruding conductor pattern 15B changes stepwise at the boundary between the relatively large protruding amount portion and the relatively small portion. The conductor projection 100 on the first member is connected to a portion of the protruding conductor pattern 15B, which protrudes relatively much.

In the modification shown in fig. 62, as in the eighteenth embodiment (fig. 24), the conductor pattern along the edge of the second member 20 is separated into conductor patterns 15B1, 25B1 on the signal output side and conductor patterns 15B2, 25B2 on the signal input side. The conductor patterns 15B1, 15B2 extend from the inside to the outside of the second member 20 in a plan view. The two first-component-upper conductor projections 100 are connected to the protruding portions of the conductor pattern 15B1 on the signal output side.

In the modification shown in fig. 63, the two first-member upper-conductor protrusions 100 are connected to the protruding portions of the signal-input-side conductor patterns 15B 2. In the modification shown in fig. 64, two first-component-side conductor bumps 100 are connected to the protruding portion of the signal-output-side conductor pattern 15B1, and the other two first-component-side conductor bumps 100 are connected to the protruding portion of the signal-input-side conductor pattern 15B 2.

In the modification shown in fig. 65, the conductor bumps 100 on the first member are connected to the protruding portions of the conductor patterns 15B1 on the signal output side, as in the modification shown in fig. 62. In the modification shown in fig. 65, as in the nineteenth embodiment (fig. 25), the conductor pattern including the plurality of power stage transistors 31 is separated into two conductor patterns 25A1 and 25A2 corresponding to two blocks of the power stage transistors 31. Likewise, the conductor pattern on the first member 10 side is also separated into two conductor patterns 15A1 and 15A2.

In the modification shown in fig. 66, two first-member-upper conductor protrusions 100 are connected to the protruding portion of the protruding conductor pattern 15B1, as in the modification shown in fig. 62. In the modification shown in fig. 66, a battery voltage terminal 66, a driving stage bias control terminal 67, and two power stage bias control terminals 68 are arranged in the second member 20, as in the twentieth embodiment (fig. 26 and 27).

An inter-component connection wiring 76 is connected to the battery voltage terminal 66, an inter-component connection wiring 77 is connected to the driving stage bias control terminal 67, and two inter-component connection wirings 78 are connected to the two power stage bias control terminals 68, respectively. The inter-member connection wirings 76, 77, 78 intersect the conductor patterns 15B2, 25B2 in a plan view, extend to the outside of the second member 20, and overlap the conductor patterns 15B2, 25B2 at the intersection position. These inter-component connection wirings 76, 77, 78 are connected to a control circuit formed in the first component 10.

In the modification shown in fig. 67, the input terminal 65 is further arranged in the second member 20, and the inter-member connection wiring 75 is connected to the input terminal 65, as compared with the modification shown in fig. 66. The inter-component connection wiring 75 extends to the outside of the second component 20 in a plan view. A high-frequency signal is input from a circuit provided in the first component 10 to the input terminal 65 via the inter-component connection wiring 75.

The conductor pattern on the second member 20 side arranged along the edge of the second member 20 is separated into two conductor patterns 25B21, 25B22 at the position crossing the inter-member connection wiring 75, and the conductor pattern on the first member 10 side is also separated into two conductor patterns 15B21, 15B22 at the position crossing the inter-member connection wiring 75. That is, the inter-component connection wiring 75 and the conductor pattern do not overlap each other in a plan view. Two first-component-upper conductor protrusions 100 are connected to the protruding portion of the protruding conductor pattern 15B 1.

In the modification shown in the drawings of fig. 61 to 67, as in the forty-third embodiment (fig. 60), the heat transfer characteristic from the power stage transistor 31 to the first member 10 is not reduced, the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed, and the heat dissipation from the second member 20 can be improved.

Fourth embodiment

Next, a semiconductor device according to a forty-fourth embodiment will be described with reference to fig. 68. Hereinafter, a description of a structure common to the semiconductor device according to the twenty-second embodiment (fig. 30) will be omitted.

Fig. 68 is a schematic top view of a semiconductor device according to a forty-fourth embodiment. The semiconductor device according to the forty-fourth embodiment includes a plurality of conductor patterns 25F arranged at intervals along the edge of the second member 20, as in the twenty-second embodiment (fig. 30). The conductor pattern 15F on the first member 10 side is arranged to overlap each of the plurality of conductor patterns 25F. Each of the plurality of conductor patterns 15F protrudes from the inner side to the outer side of the second member 20 in a plan view. The two first-component-upper conductor protrusions 100 are connected to the protruding portions of the two protruding conductor patterns 15F, respectively. The number of the conductor protrusions 100 on the first member may be one or three or more.

Next, the excellent effects of the forty-fourth embodiment will be described.

In the forty-fourth embodiment, as in the twenty-second embodiment (fig. 30), the heat conduction characteristics from the power stage transistor 31 provided in the second component 20 to the first component 10 are not reduced, and the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed. In the forty-fourth embodiment, the heat radiation from the second member 20 can be improved in the same manner as in the thirty-sixth embodiment (fig. 45 and 46).

Forty-fifth embodiment

Next, a semiconductor device according to a forty-fifth embodiment is described with reference to fig. 69. Hereinafter, a description of a structure common to the semiconductor device according to the twenty-third embodiment (fig. 31) will be omitted.

Fig. 69 is a schematic top view of a semiconductor device according to a forty-fifth embodiment. The semiconductor device according to the forty-fifth embodiment, like the semiconductor device according to the twenty-third embodiment (fig. 31), the conductor patterns 25BO, 25BI arranged along the edge of the second member 20 double-surround the region inside the second member 20 in a plan view. The conductor patterns 15BO, 15BI on the first member 10 side are arranged to overlap each of the conductor patterns 25BO, 25 BI. The outer conductor pattern 15BO extends from the inner side to the outer side of the second member 20 in plan view.

The two first-member upper conductor protrusions 100 are connected to the protruding portions protruding the conductor patterns 15 BO. The number of the conductor protrusions 100 on the first member may be one or three or more.

Next, the excellent effects of the forty-fifth embodiment will be described.

In the forty-fifth embodiment, as in the twenty-third embodiment (fig. 31), the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed without reducing the heat conduction characteristics from the power stage transistor 31 provided in the second component 20 to the first component 10. In the forty-fifth embodiment, the heat radiation from the second member 20 can be improved as in the thirty-sixth embodiment (fig. 45 and 46).

Next, a semiconductor device according to a modification of the forty-fifth embodiment will be described with reference to fig. 70 and 71. Fig. 70 and 71 are schematic plan views of a semiconductor device according to a modification of the forty-fifth embodiment.

In the modification shown in fig. 70, the conductor pattern on the inner peripheral side arranged along the edge of the second member 20 is separated into the conductor pattern 25BI1 on the signal output side and the conductor pattern 25BI2 on the signal input side, as in the twenty-fourth embodiment (fig. 32). The conductor pattern 15BI on the first member 10 side is also separated into a conductor pattern 15BI1 on the signal output side and a conductor pattern 15BI2 on the signal input side. The two first-member upper conductor protrusions 100 are connected to the protruding portions protruding the conductor patterns 15 BO.

In the modification shown in fig. 71, not only the conductor pattern on the inner periphery side but also the conductor pattern on the outer periphery side are separated into the conductor pattern 25BO1 on the signal output side and the conductor pattern 25BO2 on the signal input side in the same manner as in the twenty-fifth embodiment (fig. 33). The conductor pattern on the first member 10 side is also separated into a conductor pattern 15BO1 on the signal output side and a conductor pattern 15BO2 on the signal input side. The two first-member upper conductor protrusions 100 are connected to the protruding portions of the protruding conductor patterns 15BO 1. The protruding amount of the position where the conductor bump 100 on the first member is connected is larger than the protruding amount of the conductor pattern 15BO2 on the signal input side.

In the modification shown in fig. 70 and 71, as in the forty-fifth embodiment, the heat conduction characteristics from the power stage transistor 31 provided in the second member 20 to the first member 10 are not reduced, and the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed. Further, heat dissipation from the second member 20 can be improved.

Fourth and sixth embodiments

Next, a semiconductor device according to a forty-sixth embodiment will be described with reference to fig. 72. Hereinafter, a description of a structure common to the semiconductor device (fig. 34) according to the twenty-sixth embodiment will be omitted.

Fig. 72 is a schematic top view of a semiconductor device according to a forty-sixth embodiment. Like the twenty-sixth embodiment (fig. 34), the conductor patterns 25A, 25B, 25D on the second member 20 side are arranged, and the conductor patterns 15A, 15B, 15D on the first member 10 side are arranged so as to overlap with the conductor patterns 25A, 25B, 25D on the second member 20 side. In the twenty-sixth embodiment (fig. 34), the conductor patterns 15A, 15B are included in the second member 20 in a plan view. In contrast, in the forty-sixth embodiment, the conductor patterns 15A, 15B protrude from the inside to the outside of the second member 20 in a plan view. The two first-component-upper conductor protrusions 100 are connected to the protruding portions protruding the conductor patterns 15A.

Next, the excellent effects of the forty-sixth embodiment will be described.

In the forty-sixth embodiment, as in the twenty-sixth embodiment (fig. 34), the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed without reducing the heat conduction characteristics from the power stage transistor 31 provided in the second component 20 to the first component 10. Further, as in the thirty-sixth embodiment (fig. 45 and 46), the heat radiation from the second member 20 can be improved.

Next, a semiconductor device according to a modification of the forty-sixth embodiment will be described with reference to fig. 73 and 74. Fig. 73 and 74 are schematic plan views of a semiconductor device according to a modification of the forty-sixth embodiment.

In the modification shown in fig. 73, a plurality of conductor patterns 25G are distributed in the region where the input side circuit unit 40 is arranged, as in the twenty-seventh embodiment (fig. 35). The conductor pattern 15G on the first member 10 side is arranged to overlap each of the plurality of conductor patterns 25G. However, the plurality of conductor patterns 15G and 25G do not overlap the inductor 72L of the input side circuit unit 40 in a plan view. The two first-component-upper conductor protrusions 100 are connected to the protruding portions protruding the conductor patterns 15A.

In the modification of the forty-sixth embodiment shown in fig. 74, conductor patterns 15GL, 25GL overlapping the inductor 72L are arranged in addition to conductor patterns 15G, 25G scattered so as not to overlap the inductor 72L. The two first-component-upper conductor protrusions 100 are connected to the protruding portions protruding the conductor patterns 15A.

In the modification shown in fig. 73 and 74, as in the forty-sixth embodiment, the heat radiation from the second member 20 can be improved while suppressing the oscillation caused by positive feedback from the output-side circuit to the input-side circuit unit 40.

Forty-seventh embodiment

Next, a semiconductor device according to a forty-seventh embodiment will be described with reference to fig. 75. Hereinafter, a description of a structure common to the semiconductor device (fig. 37) according to the twenty-ninth embodiment will be omitted.

Fig. 75 is a schematic top view of a semiconductor device according to a forty-seventh embodiment. In the twenty-ninth embodiment (fig. 37), the conductor pattern 25B arranged along the edge of the second member 20 is included in the second member 20 in a plan view, and the conductor pattern 15B on the first member 10 side is also included in the second member 20 in a plan view. In contrast, in the forty-seventh embodiment, the conductor pattern 15B on the first member 10 side protrudes from the inside to the outside of the second member 20 in a plan view. The two first-component-upper conductor protrusions 100 are connected to the protruding portions protruding the conductor patterns 15B.

Further, the conductor patterns 15A1, 25A1 are configured to contain one block of the plurality of power stage transistors 31, and the conductor patterns 15A2, 25A2 are configured to contain the other block.

Next, the excellent effects of the forty-seventh embodiment will be described.

In the forty-seventh embodiment, as in the twenty-ninth embodiment (fig. 37), the oscillation caused by positive feedback from the circuit on the output side to the circuit unit 40 on the input side can be suppressed without reducing the heat conduction characteristics from the power stage transistor 31 provided in the second component 20 to the first component 10. In the forty-seventh embodiment, the heat radiation from the second member 20 can be improved as in the thirty-sixth embodiment (fig. 45 and 46).

Next, a preferred positional relationship between the power stage transistor 31 and the conductor bump 100 on the first member will be described. In the thirty-sixth embodiment (fig. 45), the plurality of power stage transistors 31 are arranged in one column, but in the forty-seventh embodiment, the plurality of power stage transistors 31 arranged in two columns substantially in parallel constitute one block, and two of the blocks are arranged.

In the thirty-sixth embodiment (fig. 45), one geometric center C is defined for the region where the plurality of power stage transistors 31 are arranged. In the forty-seventh embodiment, the geometric center C of the region where the plurality of power stage transistors 31 are arranged is defined for each block of the power stage transistors 31. Further, for each geometric center C, a circle 110 passing through the nearest corner of the second member 20 is defined with the geometric center C as the center.

For one block, the conductor protrusion 100 on the first component is preferably arranged to at least partially overlap with the area inside the circle 110 centered on the geometric center C of the block. For another block, it is also preferable that the conductor protrusion 100 on the first member is arranged to overlap at least partially with an area inside the circle 110 centered on the geometric center C of the block.

Next, a semiconductor device according to a modification of the forty-seventh embodiment will be described with reference to fig. 76 and 77. Fig. 76 and 77 are schematic plan views of a semiconductor device according to a modification of the forty-seventh embodiment.

In the modification shown in fig. 76, as in the thirty-first embodiment (fig. 38), conductor patterns 15A and 25A including one block of a plurality of power stage transistors 31 and conductor patterns 15B and 25B including another block are connected to each other. The two first-component-upper conductor protrusions 100 are connected to the protruding portions protruding the conductor patterns 15B.

In the modification shown in fig. 77, similarly to the thirty-first embodiment (fig. 39 and 40), the emitter electrode 32E surrounds the circular base electrode 32B of the power stage transistor 31 in a plan view, and the collector electrode 32C surrounds the emitter electrode 32E. The two first-component-upper conductor protrusions 100 are connected to the protruding portions protruding the conductor patterns 15B.

In the modification shown in fig. 76 and 77, as in the forty-seventh embodiment, the oscillation caused by positive feedback from the output-side circuit to the input-side circuit unit 40 can be suppressed, and the heat dissipation from the second member 20 can be improved.

Forty-eighth embodiment

Next, a semiconductor device according to a forty-eighth embodiment is described with reference to fig. 78. Hereinafter, a description of a structure common to the semiconductor device (fig. 41) according to the thirty-second embodiment will be omitted.

Fig. 78 is a schematic top view of a semiconductor device according to a forty-eighth embodiment. In the thirty-second embodiment (fig. 41), the conductor patterns 25B1, 25B2, 25B3, 25B4, and the conductor pattern on the first member 10 side overlapping with these conductor patterns are included in the second member 20 in a plan view. In contrast, in the forty-eighth embodiment, the conductor patterns 15B1, 15B2, 15B3, 15B4 on the first member 10 side, which overlap with the conductor patterns 25B1, 25B2, 25B3, 25B4, respectively, protrude from the inside to the outside of the second member 20 in a plan view.

The two first-component-upper conductor protrusions 100 are connected to the protruding portions protruding the conductor pattern 15B 1. The number of the conductor protrusions 100 on the first member may be one or three or more. The first-member conductor protrusions 100 may be connected to the protruding portions of the conductor patterns 15B2, 15B3, 15B4, and the like.

Next, the excellent effects of the forty-eighth embodiment will be described.

In the forty-eighth embodiment as well, as in the thirty-second embodiment (fig. 41), the coupling of the plurality of power stage transistors 31 and the input side circuit unit 40 constituting the differential doherty power amplifier can be reduced. In the forty-eighth embodiment, the heat radiation from the second member 20 can be improved in the same manner as in the thirty-sixth embodiment (fig. 45 and 46).

Next, a semiconductor device according to a modification of the forty-eighth embodiment will be described with reference to fig. 79. Fig. 79 is a schematic plan view of a semiconductor device according to a modification of the forty-eighth embodiment. In the forty-eighth embodiment (fig. 78), as in the thirty-second embodiment (fig. 41), conductor patterns 15A1 and 25A1 are arranged corresponding to two blocks of a plurality of power stage transistors 31 operating as carrier amplifiers of a differential doherty power amplifier, and conductor patterns 15A2 and 25A2 are arranged corresponding to two blocks of a plurality of power stage transistors 31 operating as peak amplifiers. In contrast, in the modification of the forty-eighth embodiment shown in fig. 79, similar to the thirty-third embodiment (fig. 42), conductor patterns 15a11, 25a11, conductor patterns 15a12, 25a12, conductor patterns 15a21, 25a21, and conductor patterns 15a22, 25a22 are arranged corresponding to each of the four blocks of the plurality of power stage transistors 31. The two first-component-upper conductor protrusions 100 are connected to the protruding portions protruding the conductor pattern 15B 1.

In the modification of the forty-eighth embodiment as well, as in the forty-eighth embodiment, the coupling of the plurality of power stage transistors 31 and the input side circuit unit 40 can be reduced, and the heat dissipation from the second member 20 can be improved.

Based on the above embodiments described in the present specification, the following invention is disclosed.

A semiconductor device is provided with:

a first component having a first face;

the high-frequency amplifying circuit includes:

at least one power stage transistor;

The semiconductor device according to < 2 > and < 1 >, wherein,

the bonding member includes a second conductor pattern separate from the first conductor pattern, in addition to the first conductor pattern, and the power stage transistor is arranged outside the second conductor pattern in a plan view.

The semiconductor device according to < 3 > and < 2 >, wherein,

the second conductor pattern includes a conductor pattern disposed along an edge of the second member in a plan view.

The semiconductor device according to < 4 > and < 3 >, wherein,

the input side circuit unit is arranged on a single side of a straight line passing through the power stage transistors in parallel with the direction in which the power stage transistors are arranged in a planar view,

the conductor pattern of the second conductor pattern disposed along the edge of the second member includes: a conductor pattern having a U-shape that opens from the power stage transistor toward the input side circuit unit in a plan view.

The semiconductor device according to < 5 > and < 3 >, wherein,

the second conductor pattern is arranged along an edge of the second member in a ring shape surrounding the high-frequency amplifying circuit in a plan view.

The semiconductor device according to < 6 > and < 5 >, wherein,

the second conductor pattern is arranged along an edge of the second member in a ring shape in a plan view, surrounds the high-frequency amplifying circuit, and includes two conductor patterns separated in a direction separating the power stage transistor and the input side circuit unit.

The semiconductor device according to < 7 > and < 5 >, wherein,

the second conductor pattern is a conductor pattern that annularly surrounds the high-frequency amplifying circuit in a plan view, and includes: at least a conductor pattern on the inner peripheral side and a conductor pattern on the outer peripheral side of the high-frequency amplification circuit are doubly surrounded.

The semiconductor device according to < 8 > to < 7 >, wherein,

The conductor pattern on the inner peripheral side of the second conductor pattern includes: two conductor patterns separated in a direction separating the power stage transistor and the input side circuit unit.

The semiconductor device according to < 9 > and < 2 >, wherein,

the second member has a square or rectangular shape in plan view,

the second conductor pattern includes: four conductor patterns disposed at four corners of the second member, respectively.

The semiconductor device according to any one of < 10 > and < 2 > - < 9 >,

the second conductor pattern includes: a plurality of conductor patterns which are scattered so as to at least partially overlap with the input side circuit unit.

The semiconductor device according to < 11 > and < 2 >, wherein,

the first conductor pattern reaches a part of the edge of the second member in a plan view,

the second conductor pattern partially overlaps the input-side circuit unit and reaches another portion of the edge of the second member in a plan view.

The semiconductor device according to any one of < 12 > to < 11 >, wherein,

the input side circuit unit includes a driving stage transistor electrically connected to the power stage transistor,

The second conductor pattern includes: the semiconductor device includes a conductor pattern of the driving transistor in a plan view.

The semiconductor device according to any one of < 1 > < 12 >,

the power stage transistor includes: a transistor constituting a carrier amplifier of the doherty power amplifier and a transistor of the peak amplifier,

the first conductor pattern includes, in a plan view: a conductor pattern including a transistor of the carrier amplifier and a conductor pattern including a transistor of the peak amplifier, which are separated from each other.

The semiconductor device according to any one of < 1 > < 13 >,

the second member is smaller than the first member in plan view,

the semiconductor device further includes inter-component connection wiring disposed on a surface of the second member opposite to the second surface and the first surface, the inter-component connection wiring crossing from an inner side of the second member and an edge of the second surface to the first surface on an outer side of the second member in a plan view,

the inter-component connection wiring is connected to the input-side circuit unit and is arranged outside the first conductor pattern in a plan view.

The semiconductor device according to < 15 > and < 14 >, wherein,

the inter-member connection wiring is disposed at a position not overlapping the bonding member in a plan view.

The semiconductor device according to any one of < 1 > < 13 >,

the input side circuit unit includes a terminal conductor protrusion protruding from a surface of the second member opposite to the second surface as an external connection terminal,

the terminal conductor protrusion is disposed at a position not overlapping the joint member in a plan view.

The semiconductor device according to any one of < 1 > < 16 >,

the first surface extends outside the second member in a plan view, and a first member upper conductor protrusion protruding from the first surface of the first member is further provided outside the second member.

The semiconductor device according to < 18 > and < 17 >, wherein,

the shortest distance from the conductor projection on the first member to the second member in a plan view is 2 times or less the minimum distance between two parallel lines when the conductor projection on the first member is sandwiched between two parallel lines which are tangential from both sides in a plan view.

The semiconductor device according to < 17 > or < 18 > wherein,

The second member has a convex polygon shape in a plan view,

at least a part of the conductor protrusion on the first member overlaps with a region inside a circle having a geometric center including a smallest square of the power stage transistor as a center in plan view and passing through a corner of the second member nearest to the geometric center.

The semiconductor device according to any one of < 17 > < 19 >,

the above-mentioned joint component includes: a protruding conductor pattern protruding from the inner side to the outer side of the second member in a plan view,

the conductor projection on the first member is connected to the protruding portion protruding the conductor pattern.

The semiconductor device according to < 21 > and < 20 >, wherein,

the portion of the protruding portion protruding from the conductor pattern along one edge of the second member includes: a relatively large protruding portion and a relatively small protruding portion, and the conductor protrusion on the first member is connected to the relatively large protruding portion.

The semiconductor device according to < 22 > and < 21 >, wherein,

the protruding conductor pattern includes the first conductor pattern, and the conductor protrusion on the first member is connected to the protruding portion of the first conductor pattern.

The semiconductor device according to any one of < 23 > to < 19 > - < 22 >, wherein,

the bonding member further includes a second conductor pattern separated from the first conductor pattern,

the input side circuit unit is arranged on one side of a straight line parallel to the first direction and passing through the power stage transistors in a plan view,

the second conductor pattern includes: two conductor patterns separated in a direction separating the power stage transistor and the input side circuit unit,

the first member upper conductor bump is connected to one of the two conductor patterns of the second conductor pattern, on which the power stage transistor is disposed.

The semiconductor device according to any one of < 17 > < 22 >,

the plurality of power stage transistors are arranged in a first direction in a planar view, and the conductor protrusions on the first member are arranged at two positions which are symmetrical with respect to a straight line passing through a geometric center of a minimum including quadrangle having sides parallel to the first direction and including the plurality of power stage transistors and orthogonal to the first direction.

A semiconductor device comprising:

a semiconductor component including a compound semiconductor;

a high-frequency amplifying circuit formed on the semiconductor device; and

a conductor member disposed on one surface of the semiconductor member,

the high-frequency amplifying circuit includes:

at least one power stage transistor;

the conductor part comprises at least one conductor pattern,

The semiconductor device according to < 26 > and < 25 >, wherein,

the input side circuit unit includes: terminals exposed on the surface opposite to the surface on which the conductor members are disposed.

The above embodiments are examples, and it is needless to say that substitution or combination of the portions of the structures shown in the different embodiments can be performed. The same operational effects of the same structure based on the plurality of embodiments are not mentioned in order in each embodiment. Also, the present invention is not limited to the above-described embodiments. It will be apparent to those skilled in the art that various alterations, modifications, combinations, etc. can be made, for example.

Claims

1. A semiconductor device is provided with:

a first component having a first face;

the high-frequency amplifying circuit includes:

at least one power stage transistor;

2. The semiconductor device according to claim 1, wherein,

3. The semiconductor device according to claim 2, wherein,

4. The semiconductor device according to claim 3, wherein,

5. The semiconductor device according to claim 3, wherein,

6. The semiconductor device according to claim 5, wherein,

7. The semiconductor device according to claim 5, wherein,

8. The semiconductor device according to claim 7, wherein,

9. The semiconductor device according to claim 2, wherein,

the second member has a square or rectangular shape in plan view,

10. The semiconductor device according to any one of claims 2 to 9, wherein,

11. The semiconductor device according to claim 2, wherein,

12. The semiconductor device according to any one of claims 2 to 5, wherein,

13. The semiconductor device according to any one of claims 1 to 5, wherein,

14. The semiconductor device according to any one of claims 1 to 5, wherein,

the second member is smaller than the first member in plan view,

15. The semiconductor device of claim 14, wherein,

16. The semiconductor device according to any one of claims 1 to 5, wherein,

17. The semiconductor device according to claim 1, wherein,

18. The semiconductor device of claim 17, wherein,

19. A semiconductor device is provided with:

a semiconductor component including a compound semiconductor;

a high-frequency amplifying circuit formed on the semiconductor device; and

a conductor member disposed on one surface of the semiconductor member,

the high-frequency amplifying circuit includes:

at least one power stage transistor;

The conductor part comprises at least one conductor pattern,

20. The semiconductor device of claim 19, wherein,