CN116581049A - Scanning method for analyzing defect design structure - Google Patents
Scanning method for analyzing defect design structure Download PDFInfo
- Publication number
- CN116581049A CN116581049A CN202310615325.XA CN202310615325A CN116581049A CN 116581049 A CN116581049 A CN 116581049A CN 202310615325 A CN202310615325 A CN 202310615325A CN 116581049 A CN116581049 A CN 116581049A
- Authority
- CN
- China
- Prior art keywords
- scanning
- defect
- design
- analyzing
- machine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007547 defect Effects 0.000 title claims abstract description 102
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004458 analytical method Methods 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 238000010586 diagram Methods 0.000 claims description 5
- 230000007246 mechanism Effects 0.000 abstract description 4
- 238000012916 structural analysis Methods 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
- G06T7/0006—Industrial image inspection using a design-rule based approach
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/60—Analysis of geometric attributes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/10—Image acquisition modality
- G06T2207/10056—Microscopic image
- G06T2207/10061—Microscopic image from scanning electron microscope
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Vision & Pattern Recognition (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Quality & Reliability (AREA)
- Geometry (AREA)
- Analysing Materials By The Use Of Radiation (AREA)
Abstract
The invention provides a scanning method for analyzing a defect design structure, which comprises a scanning machine and a device to be tested, wherein the scanning machine is imported with design file information of the device to be tested, and the design file information comprises various size information; setting corresponding defect structure analysis according to different graphs in the design file information; acquiring a scanning result of the device to be detected by using a scanning machine, and judging whether the defect of the scanning structure is related to at least one piece of size information; if yes, re-analyzing the scanning structure by using the scanning machine, outputting the scanning structure and giving out a defect alarm if the number percentage of defects of the scanning structure is in a design size range corresponding to any size information; if not, the scanning is ended and a scanning result is output. The invention can rapidly analyze the structure of scanning defects and increase the dimension of defect analysis; according to the structural analysis result of the defects, the source of the defects and the generation mechanism of the defects can be traced quickly, and the defect analysis efficiency is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a scanning method for analyzing a defect design structure.
Background
With the continuous development of integrated circuit processes, the critical dimensions of semiconductor devices are also becoming smaller and smaller, and the complexity of patterns is also increasing, which not only increases the requirements of semiconductor processes and machines, but also provides new challenges for efficient response and rapid tracking of detected defects.
Along with the progress of technology, the precision of the scanner is continuously improved, the size of the defects which can be detected is continuously reduced, and the variety is continuously increased. How to quickly locate the source and mechanism of occurrence of defects in a wide variety of defects, we often need to resort to many other analytical tools and analytical techniques. The design structure of the characteristics of the defects is also an important item in the defect analysis process. With the continuous shrinking of semiconductor process dimensions, more and more design dimensions are reaching the limit dimensions of the machine process, so the correlation between defects and design structures becomes stronger. Therefore, it is important to quickly obtain the design structure size analysis of the detected defects.
In order to solve the above-mentioned problems, a new scanning method for analyzing the defect design structure is needed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a scanning method for analyzing a defect design structure, which is used for solving the problem that more and more design sizes in the prior art are about to reach the limit size of the machine process, so that the correlation between the defect and the design structure is strong, and thus the efficient response and rapid tracking of the detected defect are required to be improved.
To achieve the above and other related objects, the present invention provides a scanning method for analyzing a defect design structure, 1, comprising:
step one, providing a scanning machine and a device to be tested, wherein the scanning machine is imported with design file information of the device to be tested, and the design file information comprises various size information;
step two, corresponding defect structure analysis is set according to different patterns in the design file information;
step three, acquiring a scanning result of the device to be detected by using the scanning machine, and judging whether the defect of the scanning structure is related to at least one piece of size information;
if yes, re-analyzing the scanning structure by using the scanning machine, wherein the number percentage of defects of the scanning structure is in a designed size range corresponding to any size information, outputting the scanning structure and giving out a defect alarm;
if not, ending the scanning and outputting the scanning result.
Preferably, the scanning machine in the first step is a scanning electron microscope machine.
Preferably, the design file information in the first step is acquired using a GDS file.
Preferably, the size information in the first step includes main size information and at least one sub size information.
Preferably, the design file information in the first step includes an active area pattern, a gate polysilicon pattern, an epitaxial layer pattern, a contact hole pattern, and critical dimension data of each pattern.
Preferably, the analysis of the defect structure in the second step includes outputting a critical dimension of the defect structure and scanning a structural diagram.
Preferably, the method for analyzing the defect structure corresponding to different graphic settings in the design file information in the second step includes: judging whether the graph needs to be provided with the corresponding defect structure analysis or not; if yes, adding the defect structure analysis program into the scanning machine; if not, adopting the original scanning program of the scanning machine.
Preferably, in the third step, after the scanning result is obtained by the original scanning program of the scanning machine, the method further includes: judging whether the defects of the graph corresponding to the device to be tested are related to the structure according to the scanning structure; if yes, setting the defect structure analysis of the graph.
Preferably, in the third step, the method for re-analyzing the scanning structure by using the scanning machine, where the number percentage of defects in the scanning structure is in a design size range corresponding to any one of the size information, and outputting the scanning structure and sending out a defect alarm includes: judging whether the number of the scanning defects is consistent with a design size corresponding to certain size information, is larger than or smaller than at least 80%; if yes, outputting the scanning structure and sending out the defect alarm.
As described above, the scanning method for analyzing a defect design structure of the present invention has the following advantageous effects:
the invention can rapidly analyze the structure of scanning defects, output parameters such as structure size, structure diagram and the like, and increase the dimension of defect analysis; according to the structural analysis result of the defects, the source of the defects and the generation mechanism of the defects can be traced quickly, and the defect analysis efficiency is improved; the stability of the process tool to the limit design dimensions can be monitored more efficiently.
Drawings
Fig. 1 is a schematic diagram of a scanning method according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides a scanning method for analyzing a defect design structure, which includes:
step one, providing a scanning machine and a device to be tested, wherein the scanning machine is imported with design file information of the device to be tested, and the design file information comprises various size information;
the residual defects of the polysilicon in the high-K metal process such as 28 nanometer technology nodes are closely related to the design sizes of the polysilicon, and different design sizes correspond to weak windows of different processes;
the defect of aluminum in the high-K metal process of the 28 nanometer technology node is closely related to the design size of the polysilicon, and the smaller the design size of the polysilicon is, the weaker the corresponding aluminum filling capability is;
in the tungsten connection process, it is required to determine whether the defect of tungsten is mainly in NMOS or PMOS, and is located in a common contact hole or a common contact hole, and the defect corresponds to different failure models in different structures, and the associated weak process windows are different
In an alternative embodiment, the scanning device in the first step is a scanning electron microscope device.
In an alternative embodiment, the design file information in step one is obtained using a GDS file.
In an alternative embodiment, the size information in step one includes primary size information and at least one secondary size information; when the scanner scans, the scanning result corresponding to the main size information can be selected to be synchronously output.
In an alternative embodiment, the design file information in the first step includes an active area pattern, a gate polysilicon pattern, an epitaxial layer pattern, a contact hole pattern, and critical dimension data of each pattern, and more types of data may exist according to practical situations.
Step two, corresponding defect structure analysis is set according to different patterns in the design file information; namely, the device manufactured by partial station patterns has the defect of special structure, and a special defect structure analysis is needed to be added in a scanning machine;
in an alternative embodiment, the defect structure analysis in step two includes outputting a critical dimension of the defect structure and scanning the structure map.
In an alternative embodiment, the method for analyzing the defect structure corresponding to the different graphic settings in the design file information in the second step includes: judging whether the graph needs to be provided with corresponding defect structure analysis or not; if yes, adding a defect structure analysis program in the scanning machine; if not, the original scanning program of the scanning machine is adopted.
Step three, a scanning machine is used for obtaining a scanning result of the device to be detected, and whether the defect of the scanning structure is related to at least one piece of size information is judged; for example, judging whether the scanning structure needs further analysis, if so, importing the scanning structure into a virtual system of a machine for analysis, and if not, ending the scanning; or judging whether the defect of the scanning result is related to the scanning structure, if so, importing the scanning structure into a virtual system of the machine for analysis, and if not, ending the scanning;
if yes, re-analyzing the scanning structure by using the scanning machine, namely importing the scanning data into a virtual system of the machine for analysis, and outputting the scanning structure and giving out a defect alarm if the number percentage of defects of the scanning structure is in a design size range corresponding to any size information;
if not, the scanning is ended and a scanning result is output.
In an optional embodiment, in step three, after the scanning result is obtained by using the original scanning program of the scanning machine, the method further includes: judging whether defects corresponding to the patterns in the device to be tested are related to the structure or not according to the scanning structure; if yes, the defect structure analysis of the graph is set.
In an optional embodiment, in the third step, the scanning structure is re-analyzed by using the scanning machine, and if the number percentage of defects of the scanning structure is in a design size range corresponding to any size information, the method for outputting the scanning structure and sending out a defect alarm includes: judging whether the number of scanning defects is consistent with the design size corresponding to certain size information, and is more than or less than at least 80%; if yes, outputting the scanning structure and giving out a fault alarm.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the invention can rapidly analyze the structure of the scanning defect, output parameters such as the structure size, the structure diagram and the like, and increase the dimension of defect analysis; according to the structural analysis result of the defects, the source of the defects and the generation mechanism of the defects can be traced quickly, and the defect analysis efficiency is improved; the stability of the process tool to the limit design dimensions can be monitored more efficiently. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. A scanning method for analyzing a defect design structure, comprising at least:
step one, providing a scanning machine and a device to be tested, wherein the scanning machine is imported with design file information of the device to be tested, and the design file information comprises various size information;
step two, corresponding defect structure analysis is set according to different patterns in the design file information;
step three, acquiring a scanning result of the device to be detected by using the scanning machine, and judging whether the defect of the scanning structure is related to at least one piece of size information;
if yes, re-analyzing the scanning structure by using the scanning machine, wherein the number percentage of defects of the scanning structure is in a designed size range corresponding to any size information, outputting the scanning structure and giving out a defect alarm;
if not, ending the scanning and outputting the scanning result.
2. The scanning method for analyzing a defect design structure according to claim 1, wherein: the scanning machine in the first step is a scanning electron microscope machine.
3. The scanning method for analyzing a defect design structure according to claim 1, wherein: and step one, obtaining the design file information by using a GDS file.
4. The scanning method for analyzing a defect design structure according to claim 1, wherein: the size information in the first step includes primary size information and at least one secondary size information.
5. The scanning method for analyzing a defect design structure according to claim 1, wherein: the design file information in the first step comprises an active area pattern, a grid polycrystalline silicon pattern, an epitaxial layer pattern, a contact hole pattern and key dimension data of each pattern.
6. The scanning method for analyzing a defect design structure according to claim 1, wherein: and step two, the analysis of the defect structure comprises outputting the critical dimension of the defect structure and scanning a structural diagram.
7. The scanning method for analyzing a defect design structure according to claim 1, wherein: the method for analyzing the defect structure corresponding to different graphic settings in the design file information comprises the following steps: judging whether the graph needs to be provided with the corresponding defect structure analysis or not; if yes, adding the defect structure analysis program into the scanning machine;
if not, adopting the original scanning program of the scanning machine.
8. The method of claim 7, wherein the scanning for analyzing the defect design structure comprises: in the third step, after the original scanning program using the scanning machine station obtains the scanning result, the method further includes: judging whether the defects of the graph corresponding to the device to be tested are related to the structure according to the scanning structure; if yes, setting the defect structure analysis of the graph.
9. The scanning method for analyzing a defect design structure according to claim 1, wherein: in the third step, the scanning structure is re-analyzed by using the scanning machine, and if the number percentage of defects of the scanning structure is in a design size range corresponding to any one of the size information, the method for outputting the scanning structure and sending out defect alarm comprises: judging whether the number of the scanning defects is consistent with a design size corresponding to certain size information, is larger than or smaller than at least 80%; if yes, outputting the scanning structure and sending out the defect alarm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202310615325.XA CN116581049A (en) | 2023-05-29 | 2023-05-29 | Scanning method for analyzing defect design structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202310615325.XA CN116581049A (en) | 2023-05-29 | 2023-05-29 | Scanning method for analyzing defect design structure |
Publications (1)
Publication Number | Publication Date |
---|---|
CN116581049A true CN116581049A (en) | 2023-08-11 |
Family
ID=87535632
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202310615325.XA Pending CN116581049A (en) | 2023-05-29 | 2023-05-29 | Scanning method for analyzing defect design structure |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN116581049A (en) |
-
2023
- 2023-05-29 CN CN202310615325.XA patent/CN116581049A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5425779B2 (en) | A computer-implemented method for determining whether an actual defect is a potential systematic defect or a potentially random defect | |
Kim et al. | TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling | |
US8139844B2 (en) | Methods and systems for determining a defect criticality index for defects on wafers | |
CN100336063C (en) | System and method for product yield prediction | |
Khare et al. | From contamination to defects, faults and yield loss: simulation and applications | |
US20180218090A1 (en) | Guided Defect Detection of Integrated Circuits | |
Nurani et al. | In-line yield prediction methodologies using patterned wafer inspection information | |
TWI525463B (en) | Design signature analytics for improving lithographic process of manufacturing semiconductor devices | |
JP2003506900A (en) | Method and apparatus for characterizing a semiconductor device | |
US20180277337A1 (en) | Care Areas for Improved Electron Beam Defect Detection | |
WO2020141092A1 (en) | In-die metrology methods and systems for process control | |
CN110582842B (en) | Metrology-guided test sample formation based on optical test results | |
US7356787B2 (en) | Alternative methodology for defect simulation and system | |
CN116581049A (en) | Scanning method for analyzing defect design structure | |
US20070234260A1 (en) | Method for implementing overlay-based modification of vlsi design layout | |
US9064739B2 (en) | Techniques for quantifying fin-thickness variation in FINFET technology | |
CN116796698A (en) | Chip layout correction method and storage medium | |
US9043743B2 (en) | Automated residual material detection | |
WO2019173655A1 (en) | Region of interest and pattern of interest generation for critical dimension measurement | |
US20130252350A1 (en) | System and method for generating care areas for defect inspection | |
JP2005276915A (en) | Process management system and method | |
Blauberg et al. | Understanding process and design systematics: Case study on monitoring strategy and understanding root cause of fin defectivity | |
Kondo et al. | An accurate Coulomb mobility model for MOS inversion layer and its application to NO-oxynitride devices | |
Lee et al. | Hot spot management through design based metrology: measurement and filtering | |
US7634127B1 (en) | Efficient storage of fail data to aid in fault isolation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |