CN116580748A - Configuration method, device, equipment and storage medium of memory chip test fixture - Google Patents

Configuration method, device, equipment and storage medium of memory chip test fixture Download PDF

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Publication number
CN116580748A
CN116580748A CN202310460687.6A CN202310460687A CN116580748A CN 116580748 A CN116580748 A CN 116580748A CN 202310460687 A CN202310460687 A CN 202310460687A CN 116580748 A CN116580748 A CN 116580748A
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memory chip
chip
target
bios
data block
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CN202310460687.6A
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CN116580748B (en
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叶德明
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Shenzhen Jingcun Technology Co ltd
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Shenzhen Jingcun Technology Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0403—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals during or with feedback to manufacture
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56004—Pattern generation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Techniques For Improving Reliability Of Storages (AREA)
  • Stored Programmes (AREA)

Abstract

The embodiment of the application provides a configuration method, a device, equipment and a storage medium of a memory chip test fixture, wherein the method comprises the following steps: acquiring a BIOS file of a memory chip test fixture and initial chip parameters of an initial memory chip, wherein the BIOS file comprises a plurality of configuration data which are arranged in sequence, and the initial memory chip corresponds to the BIOS file; according to the initial chip parameters, carrying out matching processing on the BIOS file, and determining a target data block in the BIOS file, wherein the target data block comprises a plurality of adjacent configuration data, and the target data block is used for representing memory SPD information; receiving target chip parameters of a target memory chip; updating the target data block according to the target chip parameters so as to update the BIOS file; writing the updated BIOS file into the memory chip test fixture to refresh the BIOS version of the memory chip test fixture, wherein the refreshed BIOS version is matched with the target memory chip. The embodiment of the application can improve the testing efficiency and reduce the labor cost.

Description

Configuration method, device, equipment and storage medium of memory chip test fixture
Technical Field
The present application relates to the field of chip testing technologies, but is not limited to, and in particular, to a method, an apparatus, a device, and a storage medium for configuring a memory chip testing fixture.
Background
Before the memory chips are put into use, each memory chip needs to be tested by using a memory chip test jig, and unqualified memory chips are removed according to test results so as to ensure the reliability of the memory chips after being put into use.
At present, a memory chip test fixture is generally used for testing various memory chips, the memory chip test fixture can test the memory chips matched with the current BIOS version, if the memory chips to be tested are not matched with the current BIOS version, the BIOS source codes are required to be modified and recompiled according to the chip parameters of the memory chips to be tested, and then the BIOS version of the memory chip test fixture is refreshed by writing in the compiling file of the BIOS source codes, but a great deal of time is required for compiling the BIOS source codes, so that the test efficiency of the memory chips is low, and a developer is required to build a compiling environment, so that the labor cost is high.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the application provides a configuration method, a device, equipment and a storage medium of a memory chip test fixture, which can improve test efficiency and reduce labor cost.
To achieve the above object, a first aspect of an embodiment of the present application provides a method for configuring a memory chip test fixture, including: acquiring a BIOS file of the memory chip test fixture and initial chip parameters of an initial memory chip, wherein the BIOS file comprises a plurality of configuration data which are arranged in sequence, and the initial memory chip corresponds to the BIOS file; according to the initial chip parameters, matching the BIOS file, and determining a target data block in the BIOS file, wherein the target data block comprises a plurality of adjacent configuration data, and the target data block is used for representing memory SPD information; receiving target chip parameters of a target memory chip; according to the target chip parameters, updating the target data blocks to update the BIOS file; writing the updated BIOS file into the memory chip testing jig to refresh the BIOS version of the memory chip testing jig, wherein the refreshed BIOS version is matched with the target memory chip.
In some embodiments, the number of initial chip parameters is equal to or greater than two; and performing matching processing on the BIOS file according to the initial chip parameters, and determining a target data block in the BIOS file, wherein the matching processing comprises the following steps: determining chip parameters to be matched in a plurality of initial chip parameters based on a preset matching strategy; determining the configuration data corresponding to each chip parameter to be matched according to each chip parameter to be matched and a preset SPD parameter configuration table, wherein the SPD parameter configuration table is used for indicating the configuration data corresponding to each chip parameter and an arrangement sequence number corresponding to the configuration data, and the arrangement sequence number is a natural number; according to the configuration data corresponding to the parameters of each chip to be matched, carrying out matching processing on the BIOS file to determine a matching data block, wherein the matching data block comprises a plurality of adjacent configuration data; taking the configuration data positioned at the head of the matched data block as head configuration data, taking the arrangement sequence number corresponding to the head configuration data as head arrangement sequence number, taking the configuration data positioned at the tail of the matched data block as tail configuration data, and taking the arrangement sequence number corresponding to the tail configuration data as tail arrangement sequence number; determining a tail end arrangement sequence number according to the SPD parameter configuration table, wherein the tail end arrangement sequence number refers to the arrangement sequence number corresponding to the configuration data at the tail end of the target data block; and determining a target data block in the BIOS file according to the matched data block, the head arrangement sequence number, the tail arrangement sequence number and the tail arrangement sequence number.
In some embodiments, the determining the target data block in the BIOS file according to the matching data block, the header permutation number, the tail permutation number, and the end permutation number includes: when the head arrangement sequence number is zero and the tail arrangement sequence number is smaller than the tail arrangement sequence number, taking a plurality of configuration data which are sequentially arranged behind the tail configuration data as first configuration data in the BIOS file, wherein the number of the first configuration data is equal to the difference value between the tail arrangement sequence number and the tail arrangement sequence number; and determining a target data block in the BIOS file according to the matching data block and the first configuration data.
In some embodiments, the determining the target data block in the BIOS file according to the matching data block, the header permutation number, the tail permutation number, and the end permutation number includes: when the head arrangement sequence number is greater than zero and the tail arrangement sequence number is smaller than the tail arrangement sequence number, taking a plurality of configuration data which are sequentially arranged before the head arrangement data as second configuration data and taking a plurality of configuration data which are sequentially arranged after the tail arrangement data as third configuration data in the BIOS file, wherein the number of the second configuration data is equal to the head arrangement sequence number, and the number of the third configuration data is equal to the difference value between the tail arrangement sequence number and the tail arrangement sequence number; and determining a target data block in the BIOS file according to the second configuration data, the matching data block and the third configuration data.
In some embodiments, the updating the target data block according to the target chip parameter includes: determining the configuration data corresponding to the target chip parameters according to the target chip parameters and the SPD parameter configuration table; and updating the target data block according to the configuration data corresponding to the target chip parameters.
In some embodiments, the writing the updated BIOS file to the memory chip test fixture to refresh the BIOS version of the memory chip test fixture includes: and writing the updated BIOS file into a flash memory, wherein the flash memory is used for writing the updated BIOS file into the memory chip test jig so as to refresh the BIOS version of the memory chip test jig.
To achieve the above object, a second aspect of an embodiment of the present application proposes a configuration system, including: memory chip test fixture; the terminal is in communication connection with the memory chip test fixture through the BIOS programmer, and the terminal is used for executing the configuration method of the memory chip test fixture in the first aspect.
To achieve the above object, a third aspect of the embodiments of the present application provides a configuration device of a memory chip test fixture, including: the device comprises an acquisition unit, a test unit and a test unit, wherein the acquisition unit is used for acquiring a BIOS file of the memory chip test fixture and initial chip parameters of an initial memory chip, the BIOS file comprises a plurality of configuration data which are arranged in sequence, and the initial memory chip corresponds to the BIOS file; the matching unit is used for carrying out matching processing on the BIOS file according to the initial chip parameters, and determining a target data block in the BIOS file, wherein the target data block comprises a plurality of adjacent configuration data, and the target data block is used for representing memory SPD information; the receiving unit is used for receiving target chip parameters of the target memory chip; the updating unit is used for updating the target data block according to the target chip parameters so as to update the BIOS file; and the writing unit is used for writing the updated BIOS file into the memory chip testing jig so as to refresh the BIOS version of the memory chip testing jig, wherein the refreshed BIOS version is matched with the target memory chip.
In order to achieve the above object, a fourth aspect of the present application provides an electronic device, where the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the method for configuring the memory chip test fixture according to the first aspect when executing the computer program.
To achieve the above object, a fifth aspect of the embodiments of the present application provides a storage medium, where the storage medium is a computer readable storage medium, and the storage medium stores a computer program, where the computer program when executed by a processor implements the method for configuring the memory chip test fixture according to the first aspect.
The embodiment of the application provides a configuration method, a device, equipment and a storage medium of a memory chip test fixture, comprising the following steps: acquiring a BIOS file of the memory chip test fixture and initial chip parameters of an initial memory chip, wherein the BIOS file comprises a plurality of configuration data which are arranged in sequence, and the initial memory chip corresponds to the BIOS file; according to the initial chip parameters, matching the BIOS file, and determining a target data block in the BIOS file, wherein the target data block comprises a plurality of adjacent configuration data, and the target data block is used for representing memory SPD information; receiving target chip parameters of a target memory chip; according to the target chip parameters, updating the target data blocks to update the BIOS file; writing the updated BIOS file into the memory chip testing jig to refresh the BIOS version of the memory chip testing jig, wherein the refreshed BIOS version is matched with the target memory chip. According to the scheme provided by the embodiment of the application, the target data block is determined by carrying out matching processing on the BIOS file of the memory chip test fixture, and because the initial memory chip corresponds to the BIOS file, the initial memory chip parameter is equivalent to the chip parameter of the initial memory chip matched with the initial BIOS version, therefore, the target data block used for representing the memory SPD information can be effectively matched according to the initial chip parameter, then the target data block is updated according to the target chip parameter of the target memory chip, so that the chip parameter represented by the memory SPD information is consistent with the target chip parameter of the target memory chip to be tested, the updated BIOS file is written into the memory chip test fixture to refresh the BIOS version, the matching of the refreshed BIOS version and the target memory chip is realized, the memory SPD information is modified by updating the target data block in the BIOS file, the BIOS source code is not required to be recompiled, the time consumed for refreshing the BIOS version is less, a large amount of time can be saved, the test efficiency is improved, in addition, the compiling environment is not required to be built by a developer, and the labor cost can be reduced.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and do not limit the application.
FIG. 1 is a flowchart of a method for configuring a memory chip test fixture according to an embodiment of the present application;
FIG. 2 is a flow chart of a method for determining a target data block according to another embodiment of the present application;
FIG. 3 is a flow chart of a specific method for determining a target data block according to another embodiment of the present application;
FIG. 4 is a flow chart of another specific method for determining a target data block according to another embodiment of the present application;
FIG. 5 is a flow chart of a method for updating a target data block according to another embodiment of the present application;
FIG. 6 is a schematic diagram of a configuration system according to another embodiment of the present application;
FIG. 7 is a schematic diagram of a configuration device of a memory chip test fixture according to another embodiment of the present application;
fig. 8 is a schematic hardware structure of an electronic device according to another embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the description of the present application, the meaning of a number is one or more, the meaning of a number is two or more, and greater than, less than, exceeding, etc. are understood to exclude the present number, and the above, below, within, etc. are understood to include the present number.
It should be noted that although functional block division is performed in a device diagram and a logic sequence is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. The terms first, second and the like in the description, in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
At present, a memory chip test fixture is generally used for testing various memory chips, the memory chip test fixture can test the memory chips matched with the current BIOS version, if the memory chips to be tested are not matched with the current BIOS version, the BIOS source codes are required to be modified and recompiled according to the chip parameters of the memory chips to be tested, and then the BIOS version of the memory chip test fixture is refreshed by writing in the compiling file of the BIOS source codes, but a great deal of time is required for compiling the BIOS source codes, so that the test efficiency of the memory chips is low, and a developer is required to build a compiling environment, so that the labor cost is high.
Aiming at the problems of low testing efficiency and high labor cost of a memory chip, the application provides a configuration method, a device, equipment and a storage medium of a memory chip testing jig, wherein the method comprises the following steps: acquiring a BIOS file of a memory chip test fixture and initial chip parameters of an initial memory chip, wherein the BIOS file comprises a plurality of configuration data which are arranged in sequence, and the initial memory chip corresponds to the BIOS file; according to the initial chip parameters, carrying out matching processing on the BIOS file, and determining a target data block in the BIOS file, wherein the target data block comprises a plurality of adjacent configuration data, and the target data block is used for representing memory SPD information; receiving target chip parameters of a target memory chip; updating the target data block according to the target chip parameters so as to update the BIOS file; writing the updated BIOS file into the memory chip test fixture to refresh the BIOS version of the memory chip test fixture, wherein the refreshed BIOS version is matched with the target memory chip. According to the scheme provided by the embodiment of the application, the target data block is determined by carrying out matching processing on the BIOS file of the memory chip test fixture, and because the initial memory chip corresponds to the BIOS file, the initial memory chip parameter is equivalent to the chip parameter of the initial memory chip matched with the initial BIOS version, therefore, the target data block used for representing the memory SPD information can be effectively matched according to the initial chip parameter, then the target data block is updated according to the target chip parameter of the target memory chip, so that the chip parameter represented by the memory SPD information is consistent with the target chip parameter of the target memory chip to be tested, the updated BIOS file is written into the memory chip test fixture to refresh the BIOS version, the matching of the refreshed BIOS version and the target memory chip is realized, the memory SPD information is modified by updating the target data block in the BIOS file, the BIOS source code is not required to be recompiled, the time consumed for refreshing the BIOS version is less, a large amount of time can be saved, the test efficiency is improved, in addition, the compiling environment is not required to be built by a developer, and the labor cost can be reduced.
The configuration method, device, equipment and storage medium of the memory chip test fixture provided by the embodiment of the application are specifically described by the following embodiment, and the configuration method of the memory chip test fixture in the embodiment of the application is described first.
The embodiment of the application provides a configuration method of a memory chip test fixture, and relates to the technical field of data processing. The configuration method of the memory chip test jig provided by the embodiment of the application can be applied to a terminal, a server and software running in the terminal or the server. In some embodiments, the terminal may be a smart phone, tablet, notebook, desktop, etc.; the server side can be configured as an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, and a cloud server for providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDNs, basic cloud computing services such as big data and artificial intelligent platforms and the like; the software may be an application or the like that implements the configuration method of the memory chip test fixture, but is not limited to the above form.
The application is operational with numerous general purpose or special purpose computer system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like. The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
It should be noted that, in each specific embodiment of the present application, when related processing is required according to user information, user behavior data, user history data, user location information, and other data related to user identity or characteristics, permission or consent of the user is obtained first, and the collection, use, processing, and the like of the data comply with related laws and regulations and standards. In addition, when the embodiment of the application needs to acquire the sensitive personal information of the user, the independent permission or independent consent of the user is acquired through popup or jump to a confirmation page and the like, and after the independent permission or independent consent of the user is definitely acquired, the necessary relevant data of the user for enabling the embodiment of the application to normally operate is acquired.
Embodiments of the present application will be further described below with reference to the accompanying drawings.
As shown in fig. 1, fig. 1 is a flowchart of a method for configuring a memory chip test fixture according to an embodiment of the present application, where the method for configuring a memory chip test fixture may be executed by a server, or may be executed by a terminal, or may be executed by a server in cooperation with the terminal, and the method for configuring a memory chip test fixture includes, but is not limited to, the following steps S110 to S150:
step S110, acquiring a BIOS file of a memory chip test fixture and initial chip parameters of an initial memory chip, wherein the BIOS file comprises a plurality of configuration data which are arranged in sequence, and the initial memory chip corresponds to the BIOS file;
step S120, performing matching processing on the BIOS file according to the initial chip parameters, and determining a target data block in the BIOS file, wherein the target data block comprises a plurality of adjacent configuration data, and the target data block is used for representing memory SPD information;
step S130, receiving target chip parameters of a target memory chip;
step S140, according to the target chip parameters, updating the target data blocks to update the BIOS file;
step S150, writing the updated BIOS file into the memory chip testing jig to refresh the BIOS version of the memory chip testing jig, wherein the refreshed BIOS version is matched with the target memory chip.
It can be understood that, in the memory chip test fixture, the memory chip test fixture is provided with a test motherboard, the test motherboard is provided with a BIOS chip, the BIOS chip can be a NOR FLASH chip, the BIOS file is obtained by reading the data of the BIOS chip, and the updated BIOS file is written into the BIOS chip subsequently; the initial chip parameters can be determined by silk-screen information on an initial memory chip, and also can be determined by initial chip information provided by a manufacturer; the BIOS file can be opened through a 16-system text editor, one configuration data can be one byte, namely one configuration data consists of two-bit 16-system numbers, 16-system matching information is determined through initial chip parameters, then matching processing is carried out on the BIOS file according to the matching information, a target data block is determined, the total number of bytes of the target data block used for representing memory SPD information is usually 512, the memory SPD information is used for representing the actual performance of a memory chip, wherein in the target data block, the configuration data corresponding to bytes 0 to 127 are usually used for representing chip parameters, and the configuration data corresponding to bytes 0 to 127 are updated according to the target chip parameters, so that the memory SPD information represented by the target data block is updated; based on the above, the target data block is determined by performing matching processing on the BIOS file of the memory chip test fixture, and since the initial memory chip corresponds to the BIOS file, the initial chip parameter is equivalent to the chip parameter of the initial memory chip matched with the initial BIOS version, therefore, the target data block for representing the memory SPD information can be effectively matched according to the initial chip parameter, then the target data block is updated according to the target chip parameter of the target memory chip, so that the chip parameter represented by the memory SPD information is consistent with the target chip parameter of the target memory chip to be tested, the updated BIOS file is written into the memory chip test fixture to refresh the BIOS version, the matching between the refreshed BIOS version and the target memory chip is realized, the memory SPD information is modified by updating the target data block in the BIOS file, the BIOS source code does not need to be recompiled, the time consumed for refreshing the BIOS version is less, a large amount of time can be saved, thereby improving the test efficiency, in addition, the compiling environment does not need to be set up by a developer, and the labor cost can be reduced.
It should be noted that, the BIOS file is a binary BIN file; the memory chip test fixture is provided with a Socket test seat, and the Socket test seat is used for placing a memory chip.
It should be noted that, the BIOS programmer may be used to read the BIOS chip on the test motherboard, for example, the BIOS chip is GD25B256E, and each port of the BIOS programmer is connected to a pin corresponding to the BIOS chip through a set wire, and specifically, the BIOS programmer is provided with a CS1 port, a MISO/DQ1 port, a WP/DQ2 port, a GND port, a Vcc port, a CLK port, a HOLD/DQ3 port, and a Reset/IO3 port; the BIOS chip is provided with a CS# pin, an SO (IO 1) pin, an IO2 pin, a VSS pin, a VCC pin, an IO3 pin, an SCLK pin and an SI (IO 0) pin; the CS1 port of the BIOS programmer is connected with the CS# pin of the BIOS chip, the MISO/DQ1 port of the BIOS programmer is connected with the SO (IO 1) pin of the BIOS chip, the WP/DQ2 port of the BIOS programmer is connected with the IO2 pin of the BIOS chip, the GND port of the BIOS programmer is connected with the VSS pin of the BIOS chip, the Vcc port of the BIOS programmer is connected with the VCC pin of the BIOS chip, the CLK port of the BIOS programmer is connected with the IO3 pin of the BIOS chip, the HOLD/DQ3 port of the BIOS programmer is connected with the SCLK pin of the BIOS chip, and the Reset/IO3 port of the BIOS programmer is connected with the SI (IO 0) pin of the BIOS chip.
It should be noted that when the initial memory chip is tested by using the memory chip testing jig, the condition that the version of the initial BIOS is matched with the initial memory chip needs to be satisfied, and the test motherboard of the memory chip testing jig can normally operate, so that the initial memory chip corresponds to the BIOS file; similarly, when the memory chip testing jig is used for testing the target memory chip, the condition that the refreshed BIOS version is matched with the target memory chip needs to be met, and the testing main board of the memory chip testing jig can normally operate.
In specific practice, the memory chip test jig for testing the LPDDR4x memory chip is referred to as a tiger lake jig, the memory chip test jig for the LPDDR5 memory chip is referred to as an AlderLake jig, and LPDDR4x and LPDDR5 are referred to as types of memory chips; for the tiger lake jig, the tiger lake jig is provided with a tiger lake motherboard, and when testing the LPDDR4x memory chips with different chip parameters, the BIOS version of the tiger lake motherboard needs to be refreshed, for example, the chip parameters of the LPDDR4x memory chips include but are not limited to: wafer single die capacity, number of die stacks die and number of modules RANK; similarly, for the alderlike jig, the alderlike jig is provided with an alderlike motherboard, and when testing LPDDR5 memory chips with different chip parameters, the BIOS version of the alderlike motherboard needs to be refreshed, for example, the chip parameters of the LPDDR5 memory chips include, but are not limited to: wafer single die capacity, number of die stacks and number of modules RANK.
In addition, referring to fig. 2, in one embodiment, the number of initial chip parameters is equal to or greater than two; step S120 in the embodiment shown in fig. 1 includes, but is not limited to, the following steps:
step S210, determining chip parameters to be matched in a plurality of initial chip parameters based on a preset matching strategy;
step S220, determining configuration data corresponding to each chip parameter to be matched according to each chip parameter to be matched and a preset SPD parameter configuration table, wherein the SPD parameter configuration table is used for indicating the configuration data corresponding to each chip parameter and an arrangement sequence number corresponding to the configuration data, and the arrangement sequence number is a natural number;
step S230, matching the BIOS file according to configuration data corresponding to each chip parameter to be matched, and determining a matched data block, wherein the matched data block comprises a plurality of adjacent configuration data;
step S240, using the configuration data at the head of the matched data block as the head configuration data, using the arrangement sequence number corresponding to the head configuration data as the head arrangement sequence number, using the configuration data at the tail of the matched data block as the tail configuration data, and using the arrangement sequence number corresponding to the tail configuration data as the tail arrangement sequence number;
Step S250, determining a tail end arrangement sequence number according to the SPD parameter configuration table, wherein the tail end arrangement sequence number refers to an arrangement sequence number corresponding to configuration data at the tail end of the target data block;
step S260, determining the target data block in the BIOS file according to the matched data block, the head arrangement sequence number, the tail arrangement sequence number and the tail arrangement sequence number.
It can be understood that the chip parameters to be matched are selected from the initial chip parameters through the matching strategy, then the configuration data corresponding to the chip parameters to be matched are determined by combining with the SPD parameter configuration table, then the matched data block is matched in the BIOS file, specifically, the BIOS file can be opened through a 16-system text editor, the 16-system configuration data is searched in the 16-system text editor, and the matched data block is determined; then, based on the head arrangement sequence number, the tail arrangement sequence number, and the end arrangement sequence number, the relative position of the matching data block in the target data block can be determined, and therefore, the target data block can be determined in the BIOS file by the matching data block, the head arrangement sequence number, the tail arrangement sequence number, and the end arrangement sequence number.
It should be noted that, when the BIOS file is opened by the 16-system text editor, the byte corresponding to the configuration data can determine the arrangement sequence number corresponding to the configuration data, for example, the arrangement sequence number of the configuration data corresponding to the byte 0 is 0, and the arrangement sequence number of the configuration data corresponding to the byte 1 is 1, so the SPD parameter configuration table records the selectable range of the configuration data of each byte and the chip parameter corresponding to each byte, and the exemplary SPD parameter configuration table corresponding to the byte 3 is shown in the following table 1:
TABLE 1
As shown in table 1, table 1 is an SPD parameter configuration table corresponding to byte 3;
illustratively, the SPD parameter configuration table corresponding to byte4 is shown in Table 2 below:
TABLE 2
As shown in table 2, table 2 is an SPD parameter configuration table corresponding to byte 4; combining the contents of table 1 and table 2, it can be seen that configuration data can be determined by the SPD parameter configuration table and specific chip parameters; for example, for an LPDDR4x memory chip with a total chip capacity of 2GB, 2 die stacks, 1 RANK, a rate of 4266Mbps, and a wafer process of Z42M, the module of the LPDDR4x memory chip is only a DRAM, and the basic module type is an on-board DDR type in combination with table 1, where the byte 3=0x0e, i.e., byte 3=00001110; the LPDDR4x memory chip has no Bank Group, 8 banks, and SDRAM total capacity/die=8gb, in conjunction with table 2, by byte 4=0x15, i.e., byte 4=00010101.
It should be noted that, by adjusting the matching policy, different chip parameters to be matched can be selected, the configuration data contained in the matching data blocks will have differences, the number of the configuration data contained in the matching data blocks will also have differences, the number of the configuration data contained in the matching data blocks is usually greater than or equal to four, and the matching data blocks can be adjusted according to the actual experimental results, which is not limited herein; if the number of matched data blocks is larger, the representative matching precision is lower, the matching precision can be improved by increasing the number of configuration data contained in the matched data blocks, and the optimal selection result of the chip parameters to be matched is as follows: on the premise that the number of matched data blocks is one, the number of configuration data contained in the matched data blocks is minimized; for example, in the configuration data corresponding to the bytes 0 to 127, by generating the matching policy, the matching data block includes configuration data corresponding to the bytes 0 to 3, and may also include configuration data corresponding to the bytes 29 to 32, where the chip parameter corresponding to the byte 0 is the SPD byte number, the chip parameter corresponding to the byte 1 is the SPD revision, the chip parameter corresponding to the byte 2 is the DRAM device type, and the chip parameter corresponding to the byte3 is the module type; if the number of matched data blocks is greater than one, for example, 3 matched data blocks are matched, if 2 matched data blocks are determined to be annotation contents, respectively determining 3 target databases, and in the process of updating the target data blocks, all target databases can be directly and synchronously updated; in addition, the matching policy may be adjusted so that the matching data block includes configuration data corresponding to bytes 0 to 6, where the chip parameters corresponding to byte4 are SDRAM density and Bank, the chip parameters corresponding to byte 5 are SDRAM addresses, and the chip parameters corresponding to byte 6 are SDRAM packet types.
In specific practice, for an LPDDR4x memory chip with a total chip capacity of 2GB, 2 die stacks, 1 RANK, a rate of 4266Mbps, a wafer process of Z42M, byte 0=0x23, byte 1=0x11, byte 2=0x11, byte 3=0x0e, byte 4=0x15, byte 5=0x21, byte 6=0xb 4, a matching data block can be matched by (23, 11, 0E), and then a target data block is determined by the matching data block, where the address field of the target data block in the BIOS file belonging to the binary BIN file is: 01EC 2580-01 EC25FF, memory SPD information for target data blocks byte0 through byte 127.
In addition, referring to fig. 3, in an embodiment, step S260 in the embodiment shown in fig. 2 includes, but is not limited to, the following steps:
step S310, when the head arrangement sequence number is zero and the tail arrangement sequence number is smaller than the tail arrangement sequence number, taking a plurality of configuration data which are sequentially arranged after the tail configuration data as first configuration data in the BIOS file, wherein the number of the first configuration data is equal to the difference value between the tail arrangement sequence number and the tail arrangement sequence number;
step S320, determining a target data block in the BIOS file according to the matching data block and the first configuration data.
It will be appreciated that since the head permutation number is zero, the matched data block is located at the head of the target data block, and the number of the first configuration data located after the matched data block can be determined by calculating the difference between the end permutation number and the tail permutation number, for example, the end permutation number is 127, the tail permutation number is 3, 124 configuration data located after the matched data block are used as the first configuration data, and then the whole formed by the matched data block and the 124 first configuration data is used as the target data block; and by adjusting the matching strategy, the matching data block is positioned at the head of the target data block, so that the tester can conveniently determine the target data block.
In addition, referring to fig. 4, in an embodiment, step S260 in the embodiment shown in fig. 2 includes, but is not limited to, the following steps:
step S410, when the head arrangement sequence number is greater than zero and the tail arrangement sequence number is less than the tail arrangement sequence number, taking a plurality of configuration data which are sequentially arranged before the head arrangement data as second configuration data and a plurality of configuration data which are sequentially arranged after the tail arrangement data as third configuration data in the BIOS file, wherein the number of the second configuration data is equal to the head arrangement sequence number, and the number of the third configuration data is equal to the difference value between the tail arrangement sequence number and the tail arrangement sequence number;
step S420, determining a target data block in the BIOS file according to the second configuration data, the matching data block and the third configuration data.
It will be understood that the matching data block is located in the middle of the target data block, the number of the second configuration data located before the matching data block is determined by the header arrangement sequence number, for example, the header arrangement sequence number is 29, the 29 configuration data located after the matching data block is taken as the second configuration data, the number of the third configuration data located after the matching data block is determined by calculating the difference between the end arrangement sequence number and the tail arrangement sequence number, for example, the end arrangement sequence number is 127, the tail arrangement sequence number is 32, the 95 configuration data located after the matching data block is taken as the third configuration data, and then the whole formed by the 29 second configuration data, the matching data block and the 95 third configuration data is taken as the target data block.
In addition, referring to fig. 5, in an embodiment, step S140 in the embodiment shown in fig. 1 includes, but is not limited to, the following steps:
step S510, determining configuration data corresponding to the target chip parameters according to the target chip parameters and the SPD parameter configuration table;
step S520, updating the target data block according to the configuration data corresponding to the target chip parameters.
It can be understood that, through the target chip parameters of the target memory chip, the corresponding configuration data is found in the SPD parameter configuration table, and then the target data block is updated according to the configuration parameters, so that the chip parameters represented by the memory SPD information are consistent with the target chip parameters of the target memory chip to be tested.
In addition, in one embodiment, step S150 in the embodiment shown in fig. 1 includes, but is not limited to, the following steps:
and writing the updated BIOS file into a flash memory, wherein the flash memory is used for writing the updated BIOS file into the memory chip test jig so as to refresh the BIOS version of the memory chip test jig.
It can be understood that after the BIOS file is written into the flash memory, the test motherboard of the memory chip test fixture is connected with the flash memory, and the test motherboard is switched to Shell mode, and then the BIOS file in the flash memory is written into the memory chip test fixture to refresh the BIOS version of the memory chip test fixture.
It should be noted that the flash memory may be a usb disk.
In addition, referring to fig. 6, the present application further provides a configuration system, including:
a memory chip test fixture 610;
the terminal 620 is in communication connection with the memory chip testing jig 610 through the BIOS programmer 630, and the terminal 620 is configured to execute the configuration method of the memory chip testing jig.
It can be understood that the specific implementation manner of the configuration system is substantially the same as the specific embodiment of the configuration method of the memory chip test fixture, and will not be described herein.
Notably, the terminal 620 is provided with a 16-system text editor, and on the terminal 620, the BIOS file read by the BIOS programmer 630 can be opened by the 16-system text editor; the BIOS programmer 630 is provided with a storage unit, and the BIOS files obtained by reading the BIOS chips in the memory chip test tool 610 may be stored in the buffer, where the memory chip test tool needs to test multiple memory chips, and through the above configuration method, the updated BIOS files corresponding to each memory chip are determined, all the updated BIOS files are stored in the storage unit, and when any kind of memory chip is tested, the corresponding BIOS files are written into the memory chip test tool, and by storing the BIOS files corresponding to each memory chip in the storage unit, the BIOS version is conveniently refreshed, thereby improving the test efficiency.
In addition, referring to fig. 7, the present application further provides a configuration apparatus 700 of a memory chip testing fixture, including:
an obtaining unit 710, configured to obtain a BIOS file of the memory chip test fixture and an initial chip parameter of an initial memory chip, where the BIOS file includes a plurality of sequentially arranged configuration data, and the initial memory chip corresponds to the BIOS file;
a matching unit 720, configured to perform matching processing on the BIOS file according to the initial chip parameter, and determine a target data block in the BIOS file, where the target data block includes a plurality of adjacent configuration data, and the target data block is used to characterize the memory SPD information;
a receiving unit 730, configured to receive a target chip parameter of a target memory chip;
the updating unit 740 is configured to update the target data block according to the target chip parameter, so as to update the BIOS file;
the writing unit 750 is configured to write the updated BIOS file into the memory chip test fixture to refresh the BIOS version of the memory chip test fixture, where the refreshed BIOS version is matched with the target memory chip.
It is understood that the specific implementation of the configuration device 700 of the memory chip test fixture is substantially the same as the specific embodiment of the configuration method of the memory chip test fixture, and will not be described herein.
In addition, referring to fig. 8, fig. 8 illustrates a hardware structure of an electronic device of another embodiment, the electronic device including:
the processor 801 may be implemented by a general purpose CPU (Central Processing Unit ), microprocessor, application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing relevant programs to implement the technical scheme provided by the embodiments of the present application;
the Memory 802 may be implemented in the form of a Read Only Memory (ROM), a static storage device, a dynamic storage device, or a random access Memory (Random Access Memory, RAM). The memory 802 may store an operating system and other application programs, and when the technical solution provided in the embodiments of the present disclosure is implemented by software or firmware, relevant program codes are stored in the memory 802, and the processor 801 invokes a configuration method for executing the memory chip test fixture of the embodiments of the present disclosure, for example, executing the method steps S110 to S150 in fig. 1, the method steps S210 to S260 in fig. 2, the method steps S310 to S320 in fig. 3, the method steps S410 to S420 in fig. 4, and the method steps S510 to S520 in fig. 5 described above;
An input/output interface 803 for implementing information input and output;
the communication interface 804 is configured to implement communication interaction between the device and other devices, and may implement communication in a wired manner (e.g., USB, network cable, etc.), or may implement communication in a wireless manner (e.g., mobile network, WIFI, bluetooth, etc.);
a bus 805 that transfers information between the various components of the device (e.g., the processor 801, the memory 802, the input/output interface 803, and the communication interface 804);
wherein the processor 801, the memory 802, the input/output interface 803, and the communication interface 804 implement communication connection between each other inside the device through a bus 805.
The embodiment of the application also provides a storage medium, which is a computer readable storage medium and is used for computer readable storage, the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the configuration method of the memory chip test fixture, for example, the method steps S110 to S150 in fig. 1, the method steps S210 to S260 in fig. 2, the method steps S310 to S320 in fig. 3, the method steps S410 to S420 in fig. 4, and the method steps S510 to S520 in fig. 5, which are described above.
The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory remotely located relative to the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The embodiment of the application provides a configuration method, a device, equipment and a storage medium of a memory chip test fixture, which are implemented by acquiring a BIOS file of the memory chip test fixture and initial chip parameters of an initial memory chip, wherein the BIOS file comprises a plurality of configuration data which are arranged in sequence, and the initial memory chip corresponds to the BIOS file; according to the initial chip parameters, carrying out matching processing on the BIOS file, and determining a target data block in the BIOS file, wherein the target data block comprises a plurality of adjacent configuration data, and the target data block is used for representing memory SPD information; receiving target chip parameters of a target memory chip; updating the target data block according to the target chip parameters so as to update the BIOS file; writing the updated BIOS file into the memory chip test fixture to refresh the BIOS version of the memory chip test fixture, wherein the refreshed BIOS version is matched with the target memory chip. Based on the above, the target data block is determined by performing matching processing on the BIOS file of the memory chip test fixture, and since the initial memory chip corresponds to the BIOS file, the initial chip parameter is equivalent to the chip parameter of the initial memory chip matched with the initial BIOS version, therefore, the target data block for representing the memory SPD information can be effectively matched according to the initial chip parameter, then the target data block is updated according to the target chip parameter of the target memory chip, so that the chip parameter represented by the memory SPD information is consistent with the target chip parameter of the target memory chip to be tested, the updated BIOS file is written into the memory chip test fixture to refresh the BIOS version, the matching between the refreshed BIOS version and the target memory chip is realized, the memory SPD information is modified by updating the target data block in the BIOS file, the BIOS source code does not need to be recompiled, the time consumed for refreshing the BIOS version is less, a large amount of time can be saved, thereby improving the test efficiency, in addition, the compiling environment does not need to be set up by a developer, and the labor cost can be reduced.
The embodiments described in the embodiments of the present application are for more clearly describing the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application, and those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.
It will be appreciated by those skilled in the art that the solutions shown in fig. 1-5 are not limiting on the embodiments of the application and may include more or fewer steps than shown, or certain steps may be combined, or different steps.
The above described apparatus embodiments are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Those of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.
The terms "first," "second," "third," "fourth," and the like in the description of the application and in the above figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the above-described division of units is merely a logical function division, and there may be another division manner in actual implementation, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including multiple instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method of the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing a program.
The preferred embodiments of the present application have been described above with reference to the accompanying drawings, and are not thereby limiting the scope of the claims of the embodiments of the present application. Any modifications, equivalent substitutions and improvements made by those skilled in the art without departing from the scope and spirit of the embodiments of the present application shall fall within the scope of the claims of the embodiments of the present application.

Claims (10)

1. The configuration method of the memory chip test fixture is characterized by comprising the following steps:
acquiring a BIOS file of the memory chip test fixture and initial chip parameters of an initial memory chip, wherein the BIOS file comprises a plurality of configuration data which are arranged in sequence, and the initial memory chip corresponds to the BIOS file;
according to the initial chip parameters, matching the BIOS file, and determining a target data block in the BIOS file, wherein the target data block comprises a plurality of adjacent configuration data, and the target data block is used for representing memory SPD information;
receiving target chip parameters of a target memory chip;
according to the target chip parameters, updating the target data blocks to update the BIOS file;
writing the updated BIOS file into the memory chip testing jig to refresh the BIOS version of the memory chip testing jig, wherein the refreshed BIOS version is matched with the target memory chip.
2. The method of claim 1, wherein the number of initial chip parameters is equal to or greater than two; and performing matching processing on the BIOS file according to the initial chip parameters, and determining a target data block in the BIOS file, wherein the matching processing comprises the following steps:
Determining chip parameters to be matched in a plurality of initial chip parameters based on a preset matching strategy;
determining the configuration data corresponding to each chip parameter to be matched according to each chip parameter to be matched and a preset SPD parameter configuration table, wherein the SPD parameter configuration table is used for indicating the configuration data corresponding to each chip parameter and an arrangement sequence number corresponding to the configuration data, and the arrangement sequence number is a natural number;
according to the configuration data corresponding to the parameters of each chip to be matched, carrying out matching processing on the BIOS file to determine a matching data block, wherein the matching data block comprises a plurality of adjacent configuration data;
taking the configuration data positioned at the head of the matched data block as head configuration data, taking the arrangement sequence number corresponding to the head configuration data as head arrangement sequence number, taking the configuration data positioned at the tail of the matched data block as tail configuration data, and taking the arrangement sequence number corresponding to the tail configuration data as tail arrangement sequence number;
determining a tail end arrangement sequence number according to the SPD parameter configuration table, wherein the tail end arrangement sequence number refers to the arrangement sequence number corresponding to the configuration data at the tail end of the target data block;
And determining a target data block in the BIOS file according to the matched data block, the head arrangement sequence number, the tail arrangement sequence number and the tail arrangement sequence number.
3. The method of claim 2, wherein said determining a target data block in said BIOS file based on said matching data block, said header sequence number, said tail sequence number, and said tail sequence number comprises:
when the head arrangement sequence number is zero and the tail arrangement sequence number is smaller than the tail arrangement sequence number, taking a plurality of configuration data which are sequentially arranged behind the tail configuration data as first configuration data in the BIOS file, wherein the number of the first configuration data is equal to the difference value between the tail arrangement sequence number and the tail arrangement sequence number;
and determining a target data block in the BIOS file according to the matching data block and the first configuration data.
4. The method of claim 2, wherein said determining a target data block in said BIOS file based on said matching data block, said header sequence number, said tail sequence number, and said tail sequence number comprises:
When the head arrangement sequence number is greater than zero and the tail arrangement sequence number is smaller than the tail arrangement sequence number, taking a plurality of configuration data which are sequentially arranged before the head arrangement data as second configuration data and taking a plurality of configuration data which are sequentially arranged after the tail arrangement data as third configuration data in the BIOS file, wherein the number of the second configuration data is equal to the head arrangement sequence number, and the number of the third configuration data is equal to the difference value between the tail arrangement sequence number and the tail arrangement sequence number;
and determining a target data block in the BIOS file according to the second configuration data, the matching data block and the third configuration data.
5. The method of claim 2, wherein updating the target data block according to the target chip parameter comprises:
determining the configuration data corresponding to the target chip parameters according to the target chip parameters and the SPD parameter configuration table;
and updating the target data block according to the configuration data corresponding to the target chip parameters.
6. The method of claim 1, wherein writing the updated BIOS file to the memory chip test fixture to refresh a BIOS version of the memory chip test fixture comprises:
And writing the updated BIOS file into a flash memory, wherein the flash memory is used for writing the updated BIOS file into the memory chip test jig so as to refresh the BIOS version of the memory chip test jig.
7. A configuration system, comprising:
memory chip test fixture;
a terminal in communication with the memory chip test fixture through a BIOS programmer, the terminal being configured to perform the configuration method of the memory chip test fixture according to any one of claims 1 to 6.
8. The configuration device of the memory chip test fixture is characterized by comprising the following components:
the device comprises an acquisition unit, a test unit and a test unit, wherein the acquisition unit is used for acquiring a BIOS file of the memory chip test fixture and initial chip parameters of an initial memory chip, the BIOS file comprises a plurality of configuration data which are arranged in sequence, and the initial memory chip corresponds to the BIOS file;
the matching unit is used for carrying out matching processing on the BIOS file according to the initial chip parameters, and determining a target data block in the BIOS file, wherein the target data block comprises a plurality of adjacent configuration data, and the target data block is used for representing memory SPD information;
The receiving unit is used for receiving target chip parameters of the target memory chip;
the updating unit is used for updating the target data block according to the target chip parameters so as to update the BIOS file;
and the writing unit is used for writing the updated BIOS file into the memory chip testing jig so as to refresh the BIOS version of the memory chip testing jig, wherein the refreshed BIOS version is matched with the target memory chip.
9. An electronic device, characterized in that the electronic device comprises a memory and a processor, the memory storing a computer program, the processor implementing the method for configuring the memory chip test fixture according to any one of claims 1 to 6 when executing the computer program.
10. A storage medium storing a computer program, wherein the computer program when executed by a processor implements the method of configuring a memory chip test jig according to any one of claims 1 to 6.
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