CN116578377A - RISC-V architecture construction method and device based on android simulator - Google Patents
RISC-V architecture construction method and device based on android simulator Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a method and a device for constructing a RISC-V architecture based on an android simulator, and relates to the technical field of computers. The method of the application comprises the following steps: adding a target board in an instruction set corresponding to the android simulator, and determining configuration information required by the target board, wherein the target board is a virtual board which is set based on a RISC-V architecture and is used for simulating the operation of a main board of hardware equipment; the configuration information is used for defining a hardware simulation function contained in the target board; and adding corresponding data parameters into the instruction set based on the configuration information to obtain an application of RISC-V architecture based on the android simulator, wherein the data parameters at least comprise files and memory mapping for realizing hardware simulation functions defined by the configuration information.
Description
Technical Field
The application relates to the technical field of computers, in particular to a method and a device for constructing a RISC-V architecture based on an android simulator.
Background
In order to develop android software or programs, an electronic computer is often required to be used for simulation operation, and in the process, the actual operation conditions of intelligent equipment such as mobile phones and the like are required to be simulated by using an android simulator, so that operations such as updating, modifying and developing of the software are performed.
At present, in the process of simulating operation by using an android simulator, only architectures such as X86 and ARM are generally supported, namely, the operation of an android system is simulated under the X86 architecture or the ARM architecture, which results in that when a user needs to adopt other frameworks to simulate the operation of the android, the conventional mode is difficult to meet the requirements of the user.
Disclosure of Invention
The embodiment of the application provides a method and a device for constructing a RISC-V architecture based on an android simulator, and mainly aims to realize the method for constructing the RISC-V architecture based on the android simulator, thereby meeting the functional requirements of users for simulating android operation by adopting other architectures.
In order to solve the technical problems, the embodiment of the application provides the following technical scheme:
in a first aspect, the present application provides a method for constructing a RISC-V architecture based on an android simulator, the method comprising:
adding a target board in an instruction set corresponding to the android simulator, and determining configuration information required by the target board, wherein the target board is a virtual board which is set based on a RISC-V architecture and is used for simulating the operation of a main board of hardware equipment; the configuration information is used for defining a hardware simulation function contained in the target board;
And adding corresponding data parameters into the instruction set based on the configuration information to obtain an application of RISC-V architecture based on the android simulator, wherein the data parameters at least comprise files and memory mapping for realizing hardware simulation functions defined by the configuration information.
Optionally, adding a target board in an instruction set corresponding to the android simulator, and determining configuration information required by the target board, including:
determining a target file in the instruction set, and setting the target board frame in the target file, wherein the target file is a file of a virtual board required by the simulation determined by the android simulator in operation;
and determining attribute information of the target board according to a user instruction, and determining the configuration information based on the information, wherein the attribute information at least comprises names of RISC-V architectures, types of RISC-V architectures and simulation functions of the RISC-V architectures.
Optionally, the data parameters include dependent files and function parameters;
the step of adding corresponding data parameters in the instruction set based on the configuration information to obtain an application of RISC-V architecture based on an android simulator comprises the following steps:
Determining functions to be simulated based on the configuration information, and defining function parameters corresponding to each function to be simulated in the target board frame based on the functions to be simulated;
compiling a corresponding dependency file based on the function to be simulated, and adding the dependency file into the instruction set to obtain the RISC-V architecture application based on the android simulator; the dependency files at least comprise basic files for realizing simulation functions based on RISC-V architecture and function files corresponding to the functions to be simulated.
Optionally, before compiling the corresponding dependency file based on the function to be simulated and adding the dependency file to the instruction set to obtain the RISC-V architecture based on the android simulator, the method further includes:
and setting a memory mapping relation of each function to be simulated in a memory control file of the instruction set based on the function to be simulated, wherein the memory mapping relation determines that a RISC-V architecture allocates a memory space occupied by the function to be simulated when the function to be simulated is executed.
Optionally, after compiling the corresponding dependency file based on the function to be simulated and adding the dependency file to the instruction set to obtain the RISC-V architecture based on the android simulator, the method further includes:
Acquiring bottom layer system information from equipment carrying the android simulator, and constructing equipment tree information of the target board based on equipment tree specifications corresponding to the bottom layer system information;
compiling a corresponding dependency file based on the function to be simulated, and adding the dependency file to the instruction set to obtain the RISC-V architecture based on the android simulator, wherein the RISC-V architecture comprises:
compiling a corresponding dependent file based on the function to be simulated, and adding the dependent file and the equipment tree information into the instruction set to obtain the RISC-V architecture application based on the android simulator.
Optionally, compiling the corresponding dependency file based on the function to be simulated, and adding the dependency file and the device tree information to the instruction set includes:
when the system architecture of the device carrying the android simulator is different from the RISC-V architecture, creating a target replacement function, and replacing an original acceleration function in the instruction set with the target replacement function, wherein the target replacement function is used for shielding the acceleration function of the android simulator when the device runs.
Optionally, after the adding corresponding data parameters in the instruction set based on the configuration information to obtain an application of RISC-V architecture based on an android simulator, the method further includes:
and adding starting parameters of the RISC-V architecture application in an interface file of the instruction set so as to start the RISC-V architecture application based on the starting parameters when the android simulator starts.
Optionally, the starting parameters include a kernel starting field, a target board starting field and a virtual device starting field;
the adding the starting parameters of the RISC-V architecture application in the interface file of the instruction set includes:
adding a kernel starting field in kernel starting information of the interface file, wherein the kernel starting field is used for controlling the RISC-V architecture application to start when the android simulator starts based on a kernel;
and/or the number of the groups of groups,
adding the target board starting field in target board starting information of the interface file, wherein the target board starting field is used for controlling the RISC-V architecture application to start when the android simulator receives a target board calling instruction;
and/or the number of the groups of groups,
and adding the virtual equipment starting field in virtual equipment starting information of the interface file, wherein the virtual equipment starting field is used for controlling the RISC-V architecture application to start when the case simulator receives a virtual equipment simulation instruction.
In a second aspect, the present application also provides a device for constructing RISC-V architecture based on an android simulator, the device comprising:
the determining unit is used for adding a target board in an instruction set corresponding to the android simulator and determining configuration information required by the target board, wherein the target board is a virtual board which is set based on a RISC-V architecture and is used for simulating the operation of a main board of hardware equipment; the configuration information is used for defining a hardware simulation function contained in the target board;
and the adding unit is used for adding corresponding data parameters in the instruction set based on the configuration information to obtain the RISC-V architecture application based on the android simulator, wherein the data parameters at least comprise files and memory mapping for realizing the hardware simulation function defined by the configuration information.
Optionally, the determining unit is configured to determine a target file in the instruction set, and set the target board frame in the target file, where the target file is a file of a virtual board required by the android simulator in determining simulation in running; and determining attribute information of the target board according to a user instruction, and determining the configuration information based on the information, wherein the attribute information at least comprises names of RISC-V architectures, types of RISC-V architectures and simulation functions of the RISC-V architectures.
Optionally, the data parameters include dependent files and function parameters;
the adding unit is specifically configured to determine a function to be simulated based on the configuration information, and define a function parameter corresponding to each function to be simulated in the target board frame based on the function to be simulated; compiling a corresponding dependency file based on the function to be simulated, and adding the dependency file into the instruction set to obtain the RISC-V architecture application based on the android simulator; the dependency files at least comprise basic files for realizing simulation functions based on RISC-V architecture and function files corresponding to the functions to be simulated.
Optionally, the apparatus further includes:
the setting unit is used for setting a memory mapping relation of each function to be simulated in a memory control file of the instruction set based on the function to be simulated, wherein the memory mapping relation determines that a RISC-V architecture allocates a memory space occupied by the function to be simulated when the function to be simulated is executed.
Optionally, the apparatus further includes:
the acquisition unit is used for acquiring bottom system information from the equipment carrying the android simulator, and constructing equipment tree information of the target board based on equipment tree specifications corresponding to the bottom system information;
The adding unit is specifically configured to compile a corresponding dependency file based on the function to be simulated, and add the dependency file and the device tree information to the instruction set, so as to obtain the RISC-V architecture application based on the android simulator.
Optionally, the adding unit is specifically configured to create an objective replacement function when it is determined that a system architecture of a device on which the android simulator is installed is different from the RISC-V architecture, and replace an original acceleration function in the instruction set with the objective replacement function, where the objective replacement function is used to mask an acceleration function of the android simulator when the device is running.
Optionally, the apparatus further includes:
and the parameter adding unit is used for adding the starting parameters of the RISC-V architecture application in the interface file of the instruction set so as to start the RISC-V architecture application based on the starting parameters when the android simulator is started.
Optionally, the starting parameters include a kernel starting field, a target board starting field and a virtual device starting field;
the parameter adding unit is specifically configured to add a kernel start field in kernel start information of the interface file, where the kernel start field is configured to control the RISC-V architecture application to start when the android simulator starts based on a kernel;
The parameter adding unit is further specifically configured to add the target board start field to target board start information of the interface file, where the target board start field is configured to control the RISC-V architecture application to start when the android simulator receives a target board call instruction;
the parameter adding unit is further specifically configured to add the virtual device start field to virtual device start information of the interface file, where the virtual device start field is configured to control start of the RISC-V architecture application when the case simulator receives a virtual device simulation instruction.
In a third aspect, the present application further provides a storage medium, where the storage medium includes a stored program, and when the program runs, the device where the storage medium is controlled to execute the method for constructing the RISC-V architecture based on the android simulator according to the first aspect.
In a fourth aspect, the present application further provides a device for constructing a RISC-V architecture based on an android simulator, where the device includes a storage medium; and one or more processors coupled to the storage medium, the processors configured to execute the program instructions stored in the storage medium; the program instructions, when run, perform the method of building an android simulator-based RISC-V architecture of any of the first aspects.
By means of the technical scheme, the technical scheme provided by the application has at least the following advantages:
the application provides a method and a device for constructing a RISC-V architecture based on an android simulator, which can firstly add a target board in an instruction set corresponding to the android simulator and determine configuration information required by the target board, wherein the target board is a virtual board which is set based on the RISC-V architecture and is used for simulating the operation of a main board of hardware equipment; the configuration information is used for defining a hardware simulation function contained in the target board; and adding corresponding data parameters into the instruction set based on the configuration information to obtain an application of the RISC-V architecture based on the android simulator, wherein the data parameters at least comprise files and memory mapping for realizing the hardware simulation function defined by the configuration information, thereby realizing the construction function of the RISC-V architecture based on the android simulator. Compared with the prior art, the method and the device can add corresponding data parameters into the instruction set of the android simulator through the configuration information based on the target board, so that modification and compiling are realized based on the android simulator, the effect of an application program conforming to a RISC-V architecture is obtained, the effect of the android simulator supporting the RISC-V architecture is realized, and the requirement of simulating an android system under the condition that a user needs to adopt an X86 or ARM architecture is met.
The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. In the drawings, wherein like or corresponding reference numerals indicate like or corresponding parts, there are shown by way of illustration, and not limitation, several embodiments of the application, in which:
FIG. 1 shows a flowchart of a method for constructing a RISC-V architecture based on an android simulator according to an embodiment of the present application;
FIG. 2 shows a block diagram of a building block of a RISC-V architecture based on an android simulator according to an embodiment of the present application;
FIG. 3 illustrates a block diagram of another apparatus for building a RISC-V architecture based on an android simulator, according to an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.
It is noted that unless otherwise indicated, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs.
The embodiment of the application provides a flow chart of a method for constructing a RISC-V architecture based on an android simulator, which comprises the following steps as shown in figure 1:
101. and adding a target plate in an instruction set corresponding to the android simulator, and determining configuration information required by the target plate.
The target board is a virtual board which is set based on RISC-V architecture and used for simulating the operation of a main board of the hardware equipment; the configuration information is used to define hardware simulation functions contained in the target board.
In the embodiment of the application, the android simulator has a set formed by instructions meeting the function realization of the android simulator in the running process, namely an execution file of the android simulator, wherein the execution file comprises an integral framework for simulating the android running function. Based on this, in this embodiment, the method of this step may start from the android simulator, and add a virtual board for simulating the operation of the main board of the hardware device in the instruction set, where the target board is set based on the RISC-V architecture specification, and may be understood as a virtual main board, i.e. a virtual board, that simulates the operation of the main boards of the mobile phone and the tablet device. Meanwhile, after the target board is determined, configuration information required by the target board is required to be determined, the configuration information can be understood as information that a user needs RISC-V architecture to simulate a hardware function of the android system in operation, and specifically, the configuration information can be controlled and adjusted through instructions set by the user. The configuration information may include, but is not limited to, the following parameters: name identification of the target board, starting state of the target board, whether the target board can be compiled, functional information mainly simulated by the target board and the like.
102. And adding corresponding data parameters into the instruction set based on the configuration information to obtain the RISC-V architecture application based on the android simulator.
Wherein the data parameters at least comprise files and memory maps for implementing the hardware simulation functions defined by the configuration information.
When the configuration information of the target board is determined, a data parameter corresponding to the configuration information is required to be added to the instruction set based on the configuration information, wherein the data parameter is a parameter instruction which can be identified by the android simulator for various parameters of the target board determined by a user in the previous step, for example, when the configuration information contains the name identifier of the target board, the corresponding data parameter is a statement code of the name identifier of a specific template which can be identified by the android simulator. Since in practical applications, an architecture must rely on the file corresponding to the function and the control information of the memory usage required for each function to operate, in this embodiment, the data parameters also include the above information, that is, the file for implementing the hardware simulation function defined by the configuration information, and the memory map for implementing the hardware simulation function defined by the configuration information. In this way, in the subsequent process of starting the application of the RISC-V architecture based on the android simulator, the effect of simulating the running condition of hardware carrying the android system by the RISC-V architecture can be realized based on each function defined in the target board and the file and memory mapping corresponding to each function.
Based on the above, the present embodiment provides a method for constructing RISC-V architecture based on android simulator. Compared with the prior art, the method and the device can add the target board in the instruction set corresponding to the android simulator and determine the configuration information required by the target board, wherein the target board is a virtual board which is set based on a RISC-V architecture and is used for simulating the operation of a main board of hardware equipment; the configuration information is used for defining a hardware simulation function contained in the target board; and adding corresponding data parameters into the instruction set based on the configuration information to obtain an application of the RISC-V architecture based on the android simulator, wherein the data parameters at least comprise files and memory mapping for realizing the hardware simulation function defined by the configuration information, thereby realizing the construction function of the RISC-V architecture based on the android simulator. Compared with the prior art, the method and the device can add corresponding data parameters into the instruction set of the android simulator through the configuration information based on the target board, so that modification and compiling are realized based on the android simulator, the effect of an application program conforming to a RISC-V architecture is obtained, the effect of the android simulator supporting the RISC-V architecture is realized, and the requirement of simulating an android system under the condition that a user needs to adopt an X86 or ARM architecture is met.
In some embodiments, in step 101 of the foregoing embodiment, adding a target board in an instruction set corresponding to an android simulator, and determining configuration information required for the target board includes:
determining a target file in the instruction set, and setting the target board frame in the target file, wherein the target file is a file of a virtual board required by the simulation determined by the android simulator in operation;
and determining attribute information of the target board according to a user instruction, and determining the configuration information based on the information, wherein the attribute information at least comprises names of RISC-V architectures, types of RISC-V architectures and simulation functions of the RISC-V architectures.
In this embodiment, the target file may specifically be a cmakelist file, which may be understood as a file defining a virtual board included in a top module of the android simulator, that is, by setting a target board frame in the target file based on the determination of the target file in this embodiment, it is ensured that the RISC-V architecture included in the target file can be determined when the android simulator is started later. Meanwhile, the attributes of the current RISC-V architecture application based on the android simulator are determined based on the user instruction, wherein the following main attributes are involved: what the current target board is (the name of RISC-V architecture); what kind of current target plate is, for example, 32 bits or 64 bits; and the simulation function of the current target board, namely the simulation function of the RISC-V architecture. And corresponding configuration information is determined based on the attribute information, so that the configuration information is ensured to be consistent with the functions of the RISC-V architecture required by the user, and the requirement of the user is met.
In some embodiments, because the implementation of any one architecture requires a dependency file for its function and a function parameter defining each function, based on this, the data parameters in this embodiment include the dependency file and the function parameter;
based on this, in step 102 in the foregoing embodiment, adding corresponding data parameters in the instruction set based on the configuration information, to obtain a RISC-V architecture application based on an android simulator, includes:
firstly, determining functions to be simulated based on the configuration information, and defining function parameters corresponding to each function to be simulated in the target board framework based on the functions to be simulated;
compiling a corresponding dependency file based on the function to be simulated, and adding the dependency file into the instruction set to obtain the RISC-V architecture application based on the android simulator; the dependency files at least comprise basic files for realizing simulation functions based on RISC-V architecture and function files corresponding to the functions to be simulated.
In this embodiment, through the configuration information, it can be determined which functions of the hardware, that is, the functions to be simulated described in this embodiment, are actually intended to be simulated in the RISC-V architecture application based on the android simulator, and then, based on the functions to be simulated, function parameters corresponding to each function to be simulated are defined in the target board frame, where the function parameters can be understood as statements that can be identified by the android simulator, and can be used to characterize which, and in particular, which of the functions that the target board has. After the functional parameters are determined. The corresponding dependent file can be compiled based on the function to be compiled, namely the file capable of supporting function realization is also compiled, and then the dependent file is added into the instruction set, so that the definition of the function to be simulated of the target board is realized, and each function realizes the addition of the corresponding file, thereby ensuring the simulation function effect required by a user based on the RISC-V architecture. In addition, in this embodiment, the dependency files actually include two types, one type is a function file corresponding to each function to be simulated, the name implies that the file is a file for ensuring implementation of each function, and the other type is a base file, and the base file can be immediately a base configuration file for realizing the simulation function by using a RISC-V architecture, and can be understood as a necessary file for realizing the simulation function, so long as the two files exist, each function to be simulated can be ensured to be correctly simulated.
In some embodiments, in the process of implementing the actual simulation function, the memory required by each function needs to be controlled and managed, based on which, before compiling the corresponding dependency file based on the function to be simulated and adding the dependency file to the instruction set to obtain the RISC-V architecture based on the android simulator, the method further includes a process of setting the memory requirement of each function to be simulated in advance, specifically:
and setting a memory mapping relation of each function to be simulated in a memory control file of the instruction set based on the function to be simulated, wherein the memory mapping relation determines that a RISC-V architecture allocates a memory space occupied by the function to be simulated when the function to be simulated is executed.
Because each function to be simulated is actually equivalent to a program running, the memory required by each function is required to be set in advance in the simulation process, that is, the book is based on the difference of the functions to be simulated, and the adjustment of the memory mapping relation is required to be carried out in the instruction set and the memory control file.
For example: the following instructions are added in the hw/riscv/virt.c file of the instruction set to realize the effect of setting the memory mapping relation of the function to be simulated, specifically:
[VIRT_GOLDFISH_FB]＝{0x10031000,0x100},
Wherein the instruction characterizes that when the function to be simulated is a display function, a memory address of 0x10031000 to 0x100 is set for the display function, so that when the simulation of the display function is required to be executed later, the simulation function can be executed with the memory address of 0x10031000 to 0x 100.
In some embodiments, after compiling the corresponding dependency file based on the function to be simulated and adding the dependency file to the instruction set to obtain the RISC-V architecture based on the android simulator, the method further includes:
acquiring bottom layer system information from equipment carrying the android simulator, and constructing equipment tree information of the target board based on equipment tree specifications corresponding to the bottom layer system information;
based on the above, compiling a corresponding dependency file based on the function to be simulated, and adding the dependency file to the instruction set to obtain the RISC-V architecture application based on the android simulator, including:
compiling a corresponding dependent file based on the function to be simulated, and adding the dependent file and the equipment tree information into the instruction set to obtain the RISC-V architecture application based on the android simulator.
Since in practical application, the android simulator is generally a computer device when running, and the computing device generally uses a Linux system, in this case, any running device needs to be provided with a device tree, that is, information of device management, based on the requirement of the system, in this embodiment, the underlying system information, that is, linux system information, can be obtained from the device on which the android simulator is mounted, and then the device tree information of the target board is constructed according to the Linux system specification, and in the process of adding a dependent file to an instruction set to obtain the RISC-V architecture application based on the android simulator, the device tree information also needs to be synchronously added to the instruction set, so as to ensure that the RISC-V architecture corresponding to the target board can be correctly run by using the Linux system as the device of the underlying system.
In some embodiments, compiling the corresponding dependency file based on the function to be simulated and adding the dependency file and the device tree information to the instruction set includes:
when the system architecture of the device carrying the android simulator is different from the RISC-V architecture, creating a target replacement function, and replacing an original acceleration function in the instruction set with the target replacement function, wherein the target replacement function is used for shielding the acceleration function of the android simulator when the device runs.
In the operating system of the X86 architecture, the computer device accelerates the application by using the KVM function, so as to improve the operation efficiency, but the acceleration mode has a precondition that the computer device is used as a host, and the android simulator is used as a client, so that the two architectures need to ensure that the KVM function can be correctly invoked by the same, in order to ensure that the RISC-V architecture based on the android simulator described in this embodiment is correctly operated, an objective replacement function, such as a KVM stub function, is created based on the method of this embodiment, and the main function of the function is to replace the original KVM acceleration function, so that the original acceleration function (KVM acceleration function) in the instruction set is replaced based on the objective replacement function (KVM stub function), thereby ensuring that the RISC-V architecture is correctly operated when the RISC-V architecture is executed under the heterogeneous operating system between the X86 architecture and the RISC-V architecture, and the problem that the RISC-V architecture cannot be normally operated due to the acceleration function invocation is avoided.
In some embodiments, since the installation simulator needs to call the architecture that it is installed on during running, in order to ensure that the target board added in the foregoing embodiments can be correctly called, the interface file of the original android simulator needs to be modified, based on which, after the corresponding data parameters are added in the instruction set in step 102 of the foregoing embodiments based on the configuration information, to obtain the RISC-V architecture application based on the android simulator, the method further includes:
And adding starting parameters of the RISC-V architecture application in an interface file of the instruction set so as to start the RISC-V architecture application based on the starting parameters when the android simulator starts.
Therefore, when the android simulator is started, the RISC-V architecture application can be started based on the modified starting parameters, the independent setting of a starting path and corresponding starting files is avoided, and the processing process of interface files is simplified.
In some embodiments, the boot parameters include a kernel boot field, a target board boot field, and a virtual device boot field;
the adding the starting parameters of the RISC-V architecture application in the interface file of the instruction set includes:
in one aspect, a kernel start field is added in kernel start information of the interface file, where the kernel start field is used to control the RISC-V architecture application to start when the android simulator starts based on a kernel.
For example, in this embodiment, the kernel initiation information of the interface file may be android-qemu2-glue/qemu-setup. const boost isx86=arch & (str (arch (), "x 86") ||str (arch (), "riscv 64")).
On the other hand, adding the target board starting field in target board starting information of the interface file, wherein the target board starting field is used for controlling the RISC-V architecture application to start when the android simulator receives a target board calling instruction;
for example, in this embodiment, the target board start information of the interface file may be android/emulgator/main-emulgator.cpp, and the adding the target board start field includes:
static bool isCpuArchSupportedByRanchu(const char*avdArch){
{"arm","arm64","mips","mips64","x86","x86_64","riscv64"}}
in yet another aspect, the virtual device start field is added in virtual device start information of the interface file, where the virtual device start field is used to control start of the RISC-V architecture application when the case simulator receives a virtual device simulation instruction.
For example, in the present embodiment, the virtual device of the interface file starts information android/android-emu/android/avd/info.c; and the process of adding the virtual device start field may be: if ((strncmp (i- > targetAbi, "riscv64", 7) = 0) | (strncmp (i- > targetAbi, "lp64d", 5) = 0))
Through adding the kernel starting field, the target board starting field and the virtual equipment starting field in the three different modes, the starting requirements can be met when RISC-V architecture application is started under different conditions, and convenience of use of users is ensured.
Further, as an implementation of the method shown in fig. 1, another embodiment of the present application further provides a device for constructing RISC-V architecture based on an android simulator. The embodiment of the device corresponds to the embodiment of the method, and for convenience of reading, details of the embodiment of the method are not repeated one by one, but it should be clear that the device in the embodiment can correspondingly realize all the details of the embodiment of the method. In order to implement a method for constructing a RISC-V architecture based on an android simulator, as shown in fig. 2, the device includes:
the determining unit 21 may be configured to add a target board to an instruction set corresponding to the android simulator, and determine configuration information required by the target board, where the target board is a virtual board set based on a RISC-V architecture and may be used to simulate operation of a main board of a hardware device; the configuration information may be used to define hardware simulation functions contained by the target board;
the adding unit 22 may be configured to add corresponding data parameters to the instruction set based on the configuration information, to obtain an application of RISC-V architecture based on the android simulator, where the data parameters include at least a file and a memory map for implementing a hardware simulation function defined by the configuration information.
Further, as shown in fig. 3, the determining unit 21 may be configured to determine a target file in the instruction set, and set the target board frame in the target file, where the target file is a file of a virtual board required by the android simulator to determine a simulation at runtime; and determining attribute information of the target board according to a user instruction, and determining the configuration information based on the information, wherein the attribute information at least comprises names of RISC-V architectures, types of RISC-V architectures and simulation functions of the RISC-V architectures.
Further, as shown in fig. 3, the data parameters include dependent files and function parameters;
the adding unit 22 may specifically be configured to determine a function to be simulated based on the configuration information, and define, in the target board frame, a function parameter corresponding to each function to be simulated based on the function to be simulated; compiling a corresponding dependency file based on the function to be simulated, and adding the dependency file into the instruction set to obtain the RISC-V architecture application based on the android simulator; the dependency files at least comprise basic files for realizing simulation functions based on RISC-V architecture and function files corresponding to the functions to be simulated.
Further, as shown in fig. 3, the apparatus further includes:
the setting unit 23 may be configured to set, based on the functions to be simulated, a memory mapping relationship of each function to be simulated in a memory control file of the instruction set, where the memory mapping relationship determines that the RISC-V architecture allocates a memory space occupied by the functions to be simulated when the functions to be simulated are executed.
Further, as shown in fig. 3, the apparatus further includes:
an obtaining unit 24, configured to obtain bottom layer system information from a device on which the android simulator is installed, and construct device tree information of the target board based on a device tree specification corresponding to the bottom layer system information;
the adding unit 22 may specifically be configured to compile a corresponding dependency file based on the function to be simulated, and add the dependency file and the device tree information to the instruction set, so as to obtain the RISC-V architecture application based on the android simulator.
Further, as shown in fig. 3, the adding unit 22 may specifically be configured to, when it is determined that there is a difference between the system architecture of the device on which the android simulator is installed and the RISC-V architecture, create an objective replacement function, and replace the original acceleration function in the instruction set with the objective replacement function, where the objective replacement function may be used to mask the acceleration function of the android simulator when the device is running.
Further, as shown in fig. 3, the apparatus further includes:
a parameter adding unit 25 may be configured to add a start-up parameter of the RISC-V architecture application in an interface file of the instruction set, so as to start up the RISC-V architecture application based on the start-up parameter when the android simulator starts up.
Further, as shown in fig. 3, the start parameters include a kernel start field, a target board start field, and a virtual device start field;
the parameter adding unit 25 may specifically be configured to add a kernel start field to kernel start information of the interface file, where the kernel start field may be used to control the RISC-V architecture application to start when the android simulator starts based on a kernel;
the parameter adding unit may be further specifically configured to add the target board start field to target board start information of the interface file, where the target board start field may be used to control the RISC-V architecture application to start when the android simulator receives a target board call instruction;
the parameter adding unit may be further specifically configured to add the virtual device start field to virtual device start information of the interface file, where the virtual device start field may be used to control start of the RISC-V architecture application when the case simulator receives a virtual device simulation instruction.
In order to achieve the above objective, according to another aspect of the present application, an embodiment of the present application further provides a storage medium, where the storage medium includes a stored program, and when the program runs, the device where the storage medium is controlled to execute the above method for constructing RISC-V architecture based on the android simulator.
To achieve the above object, according to another aspect of the present application, an embodiment of the present application further provides a device for constructing RISC-V architecture based on an android simulator, the device including a storage medium; and one or more processors coupled to the storage medium, the processors configured to execute the program instructions stored in the storage medium; executing the method for constructing the RISC-V architecture based on the android simulator when the program instructions run.
The embodiment of the application provides a method and a device for constructing a RISC-V architecture based on an android simulator, wherein in the embodiment of the application, a target board can be added in an instruction set corresponding to the android simulator and configuration information required by the target board is determined, wherein the target board is a virtual board which is set based on the RISC-V architecture and is used for simulating the operation of a main board of hardware equipment; the configuration information is used for defining a hardware simulation function contained in the target board; and adding corresponding data parameters into the instruction set based on the configuration information to obtain an application of the RISC-V architecture based on the android simulator, wherein the data parameters at least comprise files and memory mapping for realizing the hardware simulation function defined by the configuration information, thereby realizing the construction function of the RISC-V architecture based on the android simulator. Compared with the prior art, the method and the device can add corresponding data parameters into the instruction set of the android simulator through the configuration information based on the target board, so that modification and compiling are realized based on the android simulator, the effect of an application program conforming to a RISC-V architecture is obtained, the effect of the android simulator supporting the RISC-V architecture is realized, and the requirement of simulating an android system under the condition that a user needs to adopt an X86 or ARM architecture is met.
The construction device of the RISC-V architecture based on the android simulator comprises a processor and a memory, wherein the determination unit, the adding unit and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.
The processor includes a kernel, and the kernel fetches the corresponding program unit from the memory. The kernel can be provided with one or more than one, and the method for constructing the RISC-V architecture based on the android simulator is realized by adjusting kernel parameters, so that the functional requirement of a user for simulating the android operation by adopting other architectures is met.
The embodiment of the application provides a construction device of a RISC-V architecture based on an android simulator, which comprises a storage medium; and one or more processors coupled to the storage medium, the processors configured to execute the program instructions stored in the storage medium; the program instructions execute the method for constructing the RISC-V architecture based on the android simulator when running.
The embodiment of the application provides a storage medium, which comprises a stored program, wherein when the program runs, equipment in which the storage medium is controlled to execute the method for constructing the RISC-V architecture based on the android simulator.
The storage medium may include volatile memory, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM), among other forms in computer readable media, the memory including at least one memory chip.
The embodiment of the application provides equipment, which comprises a processor, a memory and a program stored in the memory and capable of running on the processor, wherein the processor realizes the following steps when executing the program: adding a target board in an instruction set corresponding to the android simulator, and determining configuration information required by the target board, wherein the target board is a virtual board which is set based on a RISC-V architecture and is used for simulating the operation of a main board of hardware equipment; the configuration information is used for defining a hardware simulation function contained in the target board; and adding corresponding data parameters into the instruction set based on the configuration information to obtain an application of RISC-V architecture based on the android simulator, wherein the data parameters at least comprise files and memory mapping for realizing hardware simulation functions defined by the configuration information.
Further, adding a target board in an instruction set corresponding to the android simulator, and determining configuration information required by the target board, including:
Determining a target file in the instruction set, and setting the target board frame in the target file, wherein the target file is a file of a virtual board required by the simulation determined by the android simulator in operation;
and determining attribute information of the target board according to a user instruction, and determining the configuration information based on the information, wherein the attribute information at least comprises names of RISC-V architectures, types of RISC-V architectures and simulation functions of the RISC-V architectures.
Further, the data parameters include dependent files and functional parameters;
the step of adding corresponding data parameters in the instruction set based on the configuration information to obtain an application of RISC-V architecture based on an android simulator comprises the following steps:
determining functions to be simulated based on the configuration information, and defining function parameters corresponding to each function to be simulated in the target board frame based on the functions to be simulated;
compiling a corresponding dependency file based on the function to be simulated, and adding the dependency file into the instruction set to obtain the RISC-V architecture application based on the android simulator; the dependency files at least comprise basic files for realizing simulation functions based on RISC-V architecture and function files corresponding to the functions to be simulated.
Further, before compiling the corresponding dependency file based on the function to be simulated and adding the dependency file to the instruction set to obtain the RISC-V architecture based on the android simulator, the method further includes:
and setting a memory mapping relation of each function to be simulated in a memory control file of the instruction set based on the function to be simulated, wherein the memory mapping relation determines that a RISC-V architecture allocates a memory space occupied by the function to be simulated when the function to be simulated is executed.
Further, after compiling the corresponding dependency file based on the function to be simulated and adding the dependency file to the instruction set to obtain the RISC-V architecture based on the android simulator, the method further includes:
acquiring bottom layer system information from equipment carrying the android simulator, and constructing equipment tree information of the target board based on equipment tree specifications corresponding to the bottom layer system information;
compiling a corresponding dependency file based on the function to be simulated, and adding the dependency file to the instruction set to obtain the RISC-V architecture based on the android simulator, wherein the RISC-V architecture comprises:
Compiling a corresponding dependent file based on the function to be simulated, and adding the dependent file and the equipment tree information into the instruction set to obtain the RISC-V architecture application based on the android simulator.
Further, compiling the corresponding dependency file based on the function to be simulated, and adding the dependency file and the equipment tree information to the instruction set includes:
when the system architecture of the device carrying the android simulator is different from the RISC-V architecture, creating a target replacement function, and replacing an original acceleration function in the instruction set with the target replacement function, wherein the target replacement function is used for shielding the acceleration function of the android simulator when the device runs.
Further, after the corresponding data parameters are added in the instruction set based on the configuration information to obtain the RISC-V architecture application based on the android simulator, the method further includes:
and adding starting parameters of the RISC-V architecture application in an interface file of the instruction set so as to start the RISC-V architecture application based on the starting parameters when the android simulator starts.
Further, the starting parameters comprise a kernel starting field, a target board starting field and a virtual device starting field;
the adding the starting parameters of the RISC-V architecture application in the interface file of the instruction set includes:
adding a kernel starting field in kernel starting information of the interface file, wherein the kernel starting field is used for controlling the RISC-V architecture application to start when the android simulator starts based on a kernel;
and/or the number of the groups of groups,
adding the target board starting field in target board starting information of the interface file, wherein the target board starting field is used for controlling the RISC-V architecture application to start when the android simulator receives a target board calling instruction;
and/or the number of the groups of groups,
and adding the virtual equipment starting field in virtual equipment starting information of the interface file, wherein the virtual equipment starting field is used for controlling the RISC-V architecture application to start when the case simulator receives a virtual equipment simulation instruction.
The application also provides a computer program product adapted to perform, when executed on a data processing device, a program code initialized with the method steps of: adding a target board in an instruction set corresponding to the android simulator, and determining configuration information required by the target board, wherein the target board is a virtual board which is set based on a RISC-V architecture and is used for simulating the operation of a main board of hardware equipment; the configuration information is used for defining a hardware simulation function contained in the target board; and adding corresponding data parameters into the instruction set based on the configuration information to obtain an application of RISC-V architecture based on the android simulator, wherein the data parameters at least comprise files and memory mapping for realizing hardware simulation functions defined by the configuration information.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, etc., such as Read Only Memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (11)
1. A method for constructing RISC-V architecture based on an android simulator, the method comprising:
adding a target board in an instruction set corresponding to the android simulator, and determining configuration information required by the target board, wherein the target board is a virtual board which is set based on a RISC-V architecture and is used for simulating the operation of a main board of hardware equipment; the configuration information is used for defining a hardware simulation function contained in the target board;
And adding corresponding data parameters into the instruction set based on the configuration information to obtain an application of RISC-V architecture based on the android simulator, wherein the data parameters at least comprise files and memory mapping for realizing hardware simulation functions defined by the configuration information.
2. The method according to claim 1, wherein adding a target board in the instruction set corresponding to the android simulator and determining configuration information required by the target board comprises:
determining a target file in the instruction set, and setting the target board frame in the target file, wherein the target file is a file of a virtual board required by the simulation determined by the android simulator in operation;
and determining attribute information of the target board according to a user instruction, and determining the configuration information based on the information, wherein the attribute information at least comprises names of RISC-V architectures, types of RISC-V architectures and simulation functions of the RISC-V architectures.
3. The method of claim 2, wherein the data parameters include dependent file and function parameters;
the step of adding corresponding data parameters in the instruction set based on the configuration information to obtain an application of RISC-V architecture based on an android simulator comprises the following steps:
Determining functions to be simulated based on the configuration information, and defining function parameters corresponding to each function to be simulated in the target board frame based on the functions to be simulated;
compiling a corresponding dependency file based on the function to be simulated, and adding the dependency file into the instruction set to obtain the RISC-V architecture application based on the android simulator; the dependency files at least comprise basic files for realizing simulation functions based on RISC-V architecture and function files corresponding to the functions to be simulated.
4. A method according to claim 3, wherein before compiling the corresponding dependency file based on the function to be emulated and adding the dependency file to the instruction set, the method further comprises:
and setting a memory mapping relation of each function to be simulated in a memory control file of the instruction set based on the function to be simulated, wherein the memory mapping relation determines that a RISC-V architecture allocates a memory space occupied by the function to be simulated when the function to be simulated is executed.
5. A method according to claim 3, wherein after compiling the corresponding dependency file based on the function to be emulated and adding the dependency file to the instruction set, the method further comprises:
Acquiring bottom layer system information from equipment carrying the android simulator, and constructing equipment tree information of the target board based on equipment tree specifications corresponding to the bottom layer system information;
compiling a corresponding dependency file based on the function to be simulated, and adding the dependency file to the instruction set to obtain the RISC-V architecture based on the android simulator, wherein the RISC-V architecture comprises:
compiling a corresponding dependent file based on the function to be simulated, and adding the dependent file and the equipment tree information into the instruction set to obtain the RISC-V architecture application based on the android simulator.
6. The method of claim 5, wherein compiling the corresponding dependency file based on the function to be simulated and adding the dependency file and the device tree information to the instruction set comprises:
when the system architecture of the device carrying the android simulator is different from the RISC-V architecture, creating a target replacement function, and replacing an original acceleration function in the instruction set with the target replacement function, wherein the target replacement function is used for shielding the acceleration function of the android simulator when the device runs.
7. The method of claim 1, wherein after adding the corresponding data parameters in the instruction set based on the configuration information to obtain an android simulator-based RISC-V architecture application, the method further comprises:
and adding starting parameters of the RISC-V architecture application in an interface file of the instruction set so as to start the RISC-V architecture application based on the starting parameters when the android simulator starts.
8. The method of claim 7, wherein the boot parameters include a kernel boot field, a target board boot field, and a virtual device boot field;
the adding the starting parameters of the RISC-V architecture application in the interface file of the instruction set includes:
adding a kernel starting field in kernel starting information of the interface file, wherein the kernel starting field is used for controlling the RISC-V architecture application to start when the android simulator starts based on a kernel;
and/or the number of the groups of groups,
adding the target board starting field in target board starting information of the interface file, wherein the target board starting field is used for controlling the RISC-V architecture application to start when the android simulator receives a target board calling instruction;
And/or the number of the groups of groups,
and adding the virtual equipment starting field in virtual equipment starting information of the interface file, wherein the virtual equipment starting field is used for controlling the RISC-V architecture application to start when the case simulator receives a virtual equipment simulation instruction.
9. A device for building RISC-V architecture based on an android simulator, the device comprising:
the determining unit is used for adding a target board in an instruction set corresponding to the android simulator and determining configuration information required by the target board, wherein the target board is a virtual board which is set based on a RISC-V architecture and is used for simulating the operation of a main board of hardware equipment; the configuration information is used for defining a hardware simulation function contained in the target board;
and the adding unit is used for adding corresponding data parameters in the instruction set based on the configuration information to obtain the RISC-V architecture application based on the android simulator, wherein the data parameters at least comprise files and memory mapping for realizing the hardware simulation function defined by the configuration information.
10. A storage medium comprising a stored program, wherein the program, when run, controls a device in which the storage medium is located to perform the method of constructing an RISC-V architecture based on an android simulator as claimed in any one of claims 1-8.
11. A device for constructing a RISC-V architecture based on an android simulator, the device comprising a storage medium; and one or more processors coupled to the storage medium, the processors configured to execute the program instructions stored in the storage medium; the program instructions, when run, perform the method of constructing an android simulator-based RISC-V architecture of any one of claims 1-8.
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