CN116578149A - Band gap reference circuit and electronic equipment - Google Patents

Abstract

The application discloses a band gap reference circuit and electronic equipment. The band-gap reference circuit comprises a reference voltage generating module, an operational amplifier and a current biasing module, wherein the operational amplifier is connected with the reference voltage generating module, the operational amplifier clamps voltages of an inverting input end and a non-inverting input end of the operational amplifier to enable the reference voltage generating module to generate band-gap reference voltage, and the current biasing module is used for generating bias current required by the operation of the operational amplifier according to the first bias voltage and a sleep mode signal, so that the band-gap reference circuit is quickly switched from the sleep mode to the working mode, and the starting time of the band-gap reference circuit is shortened.

Description

Band gap reference circuit and electronic equipment

Technical Field

The present application relates to the field of integrated circuits, and more particularly, to a bandgap reference circuit and an electronic device.

Background

With the continuous development of integrated circuit technology, electronic devices are increasingly pursuing low power consumption and low latency performance. When the electronic equipment is in an idle state, each circuit module in the whole system is in an off state, so that standby power consumption can be effectively reduced; when the signal is enabled, each circuit module in the whole system can be started quickly to enter a normal working state, but in some application scenes, in order to monitor the change of the external state in real time, a band gap reference circuit is still needed to provide reference voltage for certain modules in the chip under the conditions of dormancy, standby and the like.

Furthermore, electronic devices are increasingly demanding for the start-up procedure. The bandgap reference circuit is the most important component of the overall analog circuitry, and its start-up time will greatly affect the start-up speed of the overall system. The existing band gap reference circuit generally comprises a starting module and a reference voltage generating module, wherein a starting current is provided for a reference core in the starting process through the starting module, and then stable band gap reference voltage is finally generated through operational amplifier adjustment in the reference voltage generating module.

Disclosure of Invention

In view of the above problems, an object of the present application is to provide a bandgap reference circuit and an electronic apparatus, which improve the problem of slow start-up speed of the bandgap reference circuit.

According to an aspect of an embodiment of the present application, there is provided a bandgap reference circuit including: a reference voltage generation module having an output node for generating a bandgap reference voltage; the operational amplifier is connected with a first node and a second node in the reference voltage generation module and is used for clamping voltages at the first node and the second node; and the current bias module is used for generating bias current required by the operation of the operational amplifier according to the first bias voltage and a sleep mode signal so as to enable the band gap reference circuit to be rapidly switched from the sleep mode to the working mode.

Optionally, the bandgap reference circuit further includes: the starting module is used for providing starting current for the reference voltage generating module when the power supply end is electrified.

Optionally, the bandgap reference circuit further includes: the first sample hold module is used for transmitting the band gap reference voltage generated by the reference voltage generation module to the voltage output end of the band gap reference circuit when the band gap reference circuit is in a working mode; and maintaining the voltage at the voltage output terminal when the bandgap reference circuit is in a sleep mode.

Optionally, the bandgap reference circuit further includes: and the second sample hold module is connected with the output end of the operational amplifier and is used for holding the voltage of the output end of the operational amplifier when the band gap reference circuit is in the sleep mode.

Optionally, the reference voltage generating module further has a third node, and the third node generates a second bias voltage of at least one cascode structure in the operational amplifier.

Optionally, the reference voltage generating module includes: a first transistor and a first resistor connected in series between a supply terminal and the third node, a common node of the first transistor and the first resistor serving as the output node to generate the bandgap reference voltage; a second resistor, a third resistor and a first triode connected in series between the third node and ground, the common node of the second resistor and the third resistor being connected as the first node to the inverting input of the operational amplifier; and a fourth resistor and a second triode connected in series between the third node and ground, the control ends of the first triode and the second triode being connected with ground, the common node of the fourth resistor and the second triode being connected as the second node with the non-inverting input end of the operational amplifier.

Optionally, the starting module includes: the control end of the second transistor is in short circuit with the first end, and the control end of the third transistor is in short circuit with the second end; and a third transistor connected between the power supply terminal and an output node of the reference voltage generation module, a control terminal of the third transistor being connected to a control terminal of the second transistor.

Optionally, the operational amplifier includes: a control end of the fourth transistor is connected with the second node, a control end of the fifth transistor is connected with the first node, and a second end of the fourth transistor and a second end of the fifth transistor are connected with the current bias module; a sixth transistor and a seventh transistor, the control terminals of the sixth transistor and the seventh transistor being configured to receive the second bias voltage, the second terminal of the sixth transistor being connected to the first terminal of the fourth transistor, the second terminal of the seventh transistor being connected to the first terminal of the fifth transistor; an eighth transistor and a ninth transistor connected in series between a power supply terminal and a first terminal of the sixth transistor, a control terminal of the eighth transistor and the ninth transistor being connected to a second terminal of the ninth transistor; and a tenth transistor and an eleventh transistor connected in series between the power supply terminal and the first terminal of the seventh transistor, a control terminal of the tenth transistor being connected to a control terminal of the eighth transistor, a control terminal of the eleventh transistor being connected to a control terminal of the ninth transistor, a common node of the eleventh transistor and the seventh transistor being an output terminal of the operational amplifier.

Optionally, the current bias module includes: a twelfth transistor, a sixth resistor and a thirteenth transistor connected in series between the output terminal of the bias current and ground, a control terminal of the twelfth transistor being configured to receive the first bias voltage, a control terminal of the thirteenth transistor being configured to receive the sleep mode signal, the sleep mode signal being configured to control the bandgap reference circuit to be in an operating mode or a sleep mode; and a first capacitor connected between the control terminal of the twelfth transistor and ground.

According to another aspect of the embodiments of the present application, there is provided an electronic device including the bandgap reference circuit described above.

The band gap reference circuit provided by the embodiment of the application comprises a reference voltage generation module, an operational amplifier and a current bias module, wherein the operational amplifier is connected with the reference voltage generation module, the operational amplifier clamps the voltages of an inverting input end and a non-inverting input end of the operational amplifier to enable the reference voltage generation module to generate band gap reference voltage, and the current bias module is used for generating bias current required by the operation of the operational amplifier according to the first bias voltage and a sleep mode signal, so that the band gap reference circuit is quickly switched from the sleep mode to the working mode, and the starting time of the band gap reference circuit is shortened.

Furthermore, the band-gap reference circuit of the application also comprises a sample-hold module arranged at the voltage output end and the output of the operational amplifier, and the sample-hold module can keep the output band-gap reference voltage and the output voltage of the operational amplifier in a stable state when the band-gap reference circuit is in a dormant mode. With this arrangement, when the bandgap reference circuit is switched from the sleep mode to the operation mode, the bandgap reference voltage and the output voltage of the operational amplifier need only rise from the steady state, and do not need to rise from zero, so that the start-up time of the bandgap reference circuit can be further shortened.

Furthermore, the reference voltage generating module is also used for generating the bias voltage of at least one cascode structure in the operational amplifier, and an additional voltage bias structure is not required to be arranged in the circuit, so that the area and the cost of the circuit can be reduced, the bias voltage of the operational amplifier and the reference voltage of the reference voltage generating module can be simultaneously established, and the starting time of the band-gap reference circuit is further shortened.

Drawings

The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings, in which:

fig. 1 shows a schematic circuit diagram of a bandgap reference circuit according to the prior art.

Fig. 2 shows a schematic block circuit diagram of a bandgap reference circuit in accordance with an embodiment of the application.

Fig. 3 shows a schematic circuit diagram of a bandgap reference circuit according to an embodiment of the application.

Fig. 4 shows an operational waveform diagram of a bandgap reference circuit in accordance with an embodiment of the application.

Fig. 5 shows a schematic circuit block diagram of an electronic device according to an embodiment of the application.

Detailed Description

Various embodiments of the present application will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.

It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

In the application, a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) transistor comprises a first end, a second end and a control end, and in the on state of the MOS transistor, current flows from the first end to the second end. The first end, the second end and the control end of the PMOS tube are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the NMOS tube are respectively a drain electrode, a source electrode and a grid electrode. A transistor (also known as a bipolar transistor) includes a first terminal, a second terminal, and a control terminal, and in the on state of the transistor, current flows from the first terminal to the second terminal. The first end, the second end and the control end of the PNP tube are respectively an emitter, a collector and a base, and the first end, the second end and the control end of the NPN tube are respectively a collector, an emitter and a base.

The application will be further described with reference to the drawings and examples.

Fig. 1 shows a schematic circuit diagram of a bandgap reference circuit according to the prior art. As shown in fig. 1, the existing bandgap reference circuit 100 includes a reference voltage generation module 110 and a start-up module 120. The reference voltage generation module 110 includes an operational amplifier A1, an NMOS transistor M1, resistors R1 to R4, and two transistors Q1 and Q2. The transistor M1 is an NMOS transistor, and the transistors Q1 and Q2 are PNP transistors. The drain electrode of the NMOS transistor M1 is connected with the power supply voltage VDD, the grid electrode of the NMOS transistor M1 is connected with the output of the operational amplifier A1, the source electrode of the NMOS transistor M1 is connected with the first end of the resistor R1, the first end of the resistor R2 is connected with the second end of the resistor R1 at the node C, the second end of the resistor R2 is connected with the first end of the resistor R3, the second end of the resistor R3 is connected with the emitter electrode of the PNP triode Q1, the collector electrode of the PNP triode Q1 is connected with the ground, the first end of the resistor R4 is connected with the second end of the resistor R1 at the node C, the second end of the resistor R4 is connected with the emitter electrode of the PNP triode Q2, the base electrode of the PNP triode Q2 is connected with the base electrode of the PNP triode Q1, and the collector electrode of the PNP triode Q2 is connected with the ground. The operational amplifier A1 has a non-inverting input terminal and an inverting input terminal, the inverting input terminal thereof is connected to the node a between the resistors R2 and R3, and the non-inverting input terminal thereof is connected to the node B between the resistor R4 and the PNP transistor Q2. One end of the start-up module 120 is connected to the power supply voltage VDD, and the other end of the start-up module 120 is connected to the node C.

In the starting process of the existing bandgap reference circuit 100, a starting current is injected into the reference voltage generating module 110 through the starting module, the transistors Q1 and Q2 are turned on, then the voltage between the nodes a and B is equal through feedback adjustment of the operational amplifier A1, and finally a stable reference voltage Vref is generated at the source end of the transistor M1.

In the conventional bandgap reference circuit 100, since the operational amplifier A1 is added to the reference voltage generating circuit 110, it is necessary to provide the compensation capacitor C1 at the output terminal of the operational amplifier A1 in order to ensure the stability of the loop. In addition, in order to ensure the normal operation of the operational amplifier A1, an additional bias current needs to be provided to the operational amplifier A1, and as shown in fig. 1, an additional bias current Ibias2 is provided to the operational amplifier A1 through a current mirror formed by the bias current Ibias1 and the transistors M2 and M3. Therefore, when the bandgap reference circuit 100 is restarted, the compensation capacitor C1 needs to be recharged, and the bias current of the operational amplifier A1 needs to be reestablished, so that the starting time of the entire bandgap reference circuit is long, which greatly increases the starting time of the chip, and the requirement of quick starting cannot be met.

Fig. 2 and 3 show schematic circuit block diagrams and circuit diagrams, respectively, of a bandgap reference circuit according to an embodiment of the application. As shown in fig. 2 and 3, the bandgap reference circuit 200 of the present embodiment includes a reference voltage generation module 210, an operational amplifier A2, a current bias module 220, a start-up module 230, and sample-and-hold modules 240 and 250.

Wherein the reference voltage generation module 210 is configured to generate a bandgap reference voltage having a zero temperature coefficient. In one embodiment, the reference voltage generation module 210 includes an NMOS transistor M1, PNP transistors Q1 and Q2, and resistors R1, R2, R3, and R4. The drain of the NMOS transistor M1 is connected to the power supply voltage VDD of the power supply terminal, the source of the NMOS transistor M1 is connected to the first terminal of the resistor R1, the second terminal of the resistor R1 is connected to the node C, and the node D between the NMOS transistor M1 and the resistor R1 is used to output a bandgap reference voltage having a zero temperature coefficient. Resistors R2 and R3 are connected in series between node C and the emitter of PNP transistor Q1, resistor R4 is connected between node C and the emitter of PNP transistor Q2, and the collectors and bases of PNP transistors Q1 and Q2 are connected to ground.

The inverting input of the operational amplifier A2 is connected to the node a between the resistors R2 and R3, the non-inverting input of the operational amplifier A2 is connected to the node B between the resistor R4 and the PNP transistor Q2, and the output of the operational amplifier A2 is connected to the gate of the NMOS transistor M1 through the sample-and-hold module 250. The operational amplifier A2 outputs a constant voltage by clamping the voltage Va input to the inverting input terminal and the voltage Vb of the non-inverting input terminal to be equal, so that the control NMOS transistor M1 can supply a stable reference current to the PNP transistors Q1 and Q2, and the reference voltage generation module 210 generates the bandgap reference voltage using the difference of the emitter-base voltages between the PNP transistors Q1 and Q2.

In an example embodiment, as shown in fig. 3, the operational amplifier A2 includes NMOS transistors M4, M5, M6, and M7, and PMOS transistors M8, M9, M10, and M11.

The NMOS transistors M4 and M5 form a differential input pair of the operational amplifier A2, the sources of the NMOS transistors M4 and M5 are connected to the current bias module 220, the gate of the NMOS transistor M4 is connected to the node B as the non-inverting input of the operational amplifier A2, and the gate of the NMOS transistor M5 is connected to the node a as the inverting input of the operational amplifier A2.

The NMOS transistors M6-M7 are respectively connected to form a common-source common-gate structure, and the PMOS transistors M8-M11 are respectively connected to form a common-source common-gate structure. The sources of the PMOS transistors M8 and M10 are connected with the power supply voltage VDD, the sources of the PMOS transistors M9 and M11 are respectively connected with the drains of the PMOS transistors M8 and M10, the gates of the PMOS transistors M8-M11 are connected with the drain of the PMOS transistor M9, the drain of the PMOS transistor M9 is also connected with the drain of the NMOS transistor M6, the drain of the PMOS transistor M11 is connected with the drain of the NMOS transistor M7, and the common node of the two is used as the output end of the operational amplifier A2. The source of the NMOS transistor M6 is connected to the drain of the NMOS transistor M4, the source of the NMOS transistor M7 is connected to the drain of the NMOS transistor M5, and the gates of the NMOS transistors M6 and M7 are connected to each other and receive a bias voltage Vbias2.

For example, the bias voltages Vbias2 of NMOS transistors M6 and M7 may be provided by reference voltage generation module 210. For example, the bias voltages Vbias2 of NMOS transistors M6 and M7 may be provided by node C in reference voltage generating module 210, i.e., the gates of NMOS transistors M6 and M7 are connected to node C in reference voltage generating module 210. By adopting the reference voltage generating module 210 to provide the bias voltage of the cascode structure of the operational amplifier A2, no additional voltage bias structure needs to be provided in the circuit, so that the bias voltage of the operational amplifier A2 can be established simultaneously with the reference voltage of the reference voltage generating module 210, the problem of increasing the start-up time of the bandgap reference circuit due to the addition of the additional voltage bias structure can be avoided, and the start-up time of the bandgap reference circuit 200 can be primarily shortened.

The current bias module 220 is connected to the tail current terminal of the operational amplifier A2, and is configured to generate a bias current required for the operation of the operational amplifier A2 according to the bias voltage Vbias1 and a sleep mode signal EN, so that the bandgap reference circuit 200 can be rapidly switched from the sleep mode to the operation mode.

In an exemplary embodiment, as shown in fig. 3, the current bias module 220 includes NMOS transistors M12, M13, a resistor R6, and a capacitor C3. The NMOS transistor M12, the resistor R6, and the NMOS transistor M13 are connected in series between the bias current output terminal of the current bias module 220 and ground, the drain of the NMOS transistor M12 is connected to the output terminal of the current bias module 220, the gate of the NMOS transistor M12 is configured to receive the bias voltage Vbias1, the source of the NMOS transistor M12 is connected to the first terminal of the resistor R6, the second terminal of the resistor R6 is connected to the drain of the NMOS transistor M13, the gate of the NMOS transistor M13 is connected to the sleep mode signal EN, and the source of the NMOS transistor M13 is connected to ground. The capacitor C3 is connected between the gate of the NMOS transistor M12 and ground. When the sleep mode signal EN is active (e.g., low), the NMOS transistor M13 is turned off, the current bias module 220 is turned off, and no bias current is supplied to the operational amplifier A2, which in turn turns off the operational amplifier A2. Thus, during sleep mode, bandgap reference circuit 200 is turned off, generating no current loss. When the sleep mode signal EN is inactive (e.g., high level), the NMOS transistor M13 is turned on, and the current bias module 220 rapidly establishes a bias current according to the bias voltage Vbias1, so that the operational amplifier A2 can be rapidly turned on, and the bandgap reference circuit 200 can be rapidly switched from the sleep mode to the operation mode. In the present embodiment, the current bias module 220 generates a bias current according to the bias voltage Vbias1, the NMOS transistor M12 and the resistor R6, i.e. bias current ibias= (Vbias 1-vth_m12)/R6, wherein vth_m12 represents the threshold voltage of the NMOS transistor M12. Compared with the bandgap reference circuit in the prior art, the current bias module 220 of the present embodiment does not need to charge the capacitor C3 when the system is switched from the sleep mode to the operation mode, so that the start-up time of the bandgap reference circuit can be further shortened.

The start-up module 230 is connected between a power supply terminal and an output node D of the reference voltage generating module 210, and the start-up module 230 is configured to provide a start-up voltage to the reference voltage generating module 210 when a power supply voltage VDD of the power supply terminal is powered up, and start-up the entire reference voltage generating module 210 through the start-up module 230 when the power supply voltage VDD starts to rise.

Further, the start-up module 230 includes NMOS transistors M2 and M3, a resistor R5, and a PNP transistor Q3. The first end of the resistor R5 is connected to the power supply voltage VDD, the second end of the resistor R5 is connected to the gate and the drain of the NMOS transistor M2, the source of the NMOS transistor M2 is connected to the emitter of the PNP transistor Q3, the base and the collector of the PNP transistor Q3 are connected to the ground, the drain of the NMOS transistor M3 is connected to the power supply voltage VDD, the gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor M2, and the source of the NMOS transistor M3 is connected to the output node D of the reference voltage generating module 210.

The sample-and-hold modules 240 and 250 are respectively used to hold the voltage at the voltage output terminal of the bandgap reference circuit 200 and the voltage at the output terminal of the operational amplifier A2 when the bandgap reference circuit 200 is in the sleep mode.

Illustratively, the sample-and-hold module 240 is connected between the output node D of the reference voltage generating module 240 and the voltage output terminal of the bandgap reference circuit 200, and when the bandgap reference circuit 200 is in the operating mode, the sample-and-hold module 240 transmits the bandgap reference voltage Vref generated at the output node D to the voltage output terminal of the bandgap reference circuit; the sample-and-hold module 240 holds the voltage at the voltage output when the bandgap reference circuit 200 is in sleep mode. Further, the sample-and-hold module 240 includes a switch S1 and a capacitor C1, the switch S1 is connected between the output node D of the reference voltage generating module 210 and the voltage output terminal of the bandgap reference circuit 200, which is turned on and off by the sleep enable signal EN, and the capacitor C1 is connected between the voltage output terminal and ground. When the sleep enable signal EN is inactive (e.g., high level), the bandgap reference circuit 200 is in the operation mode, the switch S1 is turned on, and the bandgap reference voltage Vref generated by the reference voltage generating module 210 is provided to the voltage output terminal; when the sleep enable signal EN is active (e.g., high), the bandgap reference circuit 200 is in sleep mode, the switch S1 is turned off, and the bandgap reference voltage Vref at the voltage output terminal is held by the capacitor C1.

Similarly, the sample-and-hold module 250 includes a switch S2 connected between the output of the operational amplifier A2 and the gate of the NMOS transistor M1, and a capacitor C2 connected between the gate of the NMOS transistor M1 and ground, the switch S2 being turned on and off by the sleep enable signal EN. When the sleep enable signal EN is inactive (e.g., high level), the switch S2 is turned on, the capacitor C2 samples the output voltage of the operational amplifier A2, and when the sleep enable signal EN is active (e.g., low level), the switch S2 is turned off, and the output voltage of the operational amplifier A2 is maintained by the capacitor C2, thereby ensuring that the voltage at the gate of the NMOS transistor M1 does not drop.

As is apparent from the above description, the bandgap reference circuit 200 of the present embodiment is provided with a sample-and-hold module at the voltage output end and the output of the operational amplifier A2, and the capacitor in the sample-and-hold module holds the bandgap reference voltage Vref at the voltage output end and the output voltage of the operational amplifier A2 when the bandgap reference circuit 200 is in the sleep mode, so that the bandgap reference voltage Vref and the output voltage of the operational amplifier A2 climb from a steady state value without climbing from zero when the bandgap reference voltage 200 is switched from the sleep mode to the operation mode, and thus the starting speed of the bandgap reference circuit can be greatly accelerated.

Further, when the bandgap reference circuit 200 is switched from the sleep mode to the operation mode, the start-up current of the reference voltage generating module 210 is provided by the NMOS transistor M1 and the capacitor C1, and if the bandgap reference voltage Vref drops, the NMOS transistor M1 can supplement the capacitor C1 with current, so as to avoid the drop of the bandgap reference voltage Vref.

Fig. 4 shows an operational waveform diagram of a bandgap reference circuit in accordance with an embodiment of the application. Fig. 4 shows waveforms of the power supply voltage VDD, the sleep enable signal EN, and the bandgap reference voltage Vref, respectively, and the operation principle of the bandgap reference circuit of the present embodiment will be described in detail with reference to fig. 4.

As shown in fig. 4, at time t1, the power supply voltage VDD starts to be established, the sleep enable signal EN also turns to a high level, the bandgap reference circuit 200 starts to enter an operation mode, at this time, a start-up circuit 230 provides a start-up current to the reference voltage generating module 210, PNP transistors Q1 and Q2 are turned on, the bandgap reference voltage Vref gradually rises, and at the same time, the voltages of the nodes a and B are equalized through feedback adjustment of the operational amplifier A2, so that the bandgap reference voltage Vref finally tends to be stable. At time t2, sleep enable signal EN toggles low, bandgap reference circuit 200 switches from operating mode to sleep mode, NMOS transistor M13 in current bias block 220 turns off, current bias block 220 no longer provides bias current to operational amplifier A2, and then operational amplifier A2 is turned off, while switches S1 and S2 in sample-and-hold blocks 240 and 250 are turned off, holding bandgap reference voltage Vref and the output voltage of operational amplifier A2 via capacitors C1 and C2, respectively. At time t3, the sleep enable signal EN turns high again, the current bias module 220 turns on again, and provides bias current to the operational amplifier A2, and then turns on the operational amplifier A2, at which time the output voltage of the operational amplifier A2 only needs to rise from a steady state value. Meanwhile, the charge stored in the capacitor C1 provides a starting current to the reference voltage generating module 210, and the PNP transistors Q1 and Q2 in the reference voltage generating module 210 are turned on, so that the bandgap reference voltage Vref output by the reference voltage generating module 210 can be re-established. Meanwhile, due to the power supply of the capacitor C1 to the reference voltage generating module 210, a certain drop occurs in the bandgap reference voltage Vref at the voltage output end, and at this time, the NMOS transistor M1 supplements current to the capacitor C1, so as to avoid the drop of the bandgap reference voltage Vref.

In addition, other embodiments of the present application provide an electronic device 300.

Fig. 5 shows a schematic circuit block diagram of an electronic device according to an embodiment of the application. As shown in fig. 5, the electronic device 300 includes a bandgap reference circuit 200. Wherein the bandgap reference circuit 200 may be any of the bandgap reference circuits shown in connection with the above-described embodiments illustrated in fig. 2-3. According to the teachings of the present embodiment, the electronic device 300 has a plurality of modes including, but not limited to, an operational mode and a sleep mode, the bandgap reference circuit 200 operates when the electronic device 300 is in the operational mode to provide a reference for other circuits or modules in the electronic device 300; when the electronic device 300 is in sleep mode, the bandgap reference circuit 200 is turned off while the bandgap reference voltage is held by the sample and hold module, and still a reference can be provided to certain circuits or modules in the electronic device 300 that need to monitor changes in external conditions in real time. When the electronic device 300 is switched from the sleep mode to the operation mode, the bandgap reference circuit 200 can be started up quickly, so that the starting time of the electronic device 300 is shortened, and the requirement of quick start is met.

The electronic device described herein refers to a device that can be used in a mobile environment and supports multiple communication schemes such as GSM, EDGE, TD _scdma, tdd_lte, fdd_lte, and the like, including a mobile phone, a notebook computer, a tablet computer, a vehicle-mounted computer, and the like.

In summary, the bandgap reference circuit provided by the embodiment of the application includes a reference voltage generating module, an operational amplifier and a current biasing module, wherein the operational amplifier is connected with the reference voltage generating module, the operational amplifier clamps voltages of an inverting input end and a non-inverting input end of the operational amplifier to enable the reference voltage generating module to generate a bandgap reference voltage, and the current biasing module is used for generating a bias current required by the operation of the operational amplifier according to a first bias voltage and a sleep mode signal, so that the bandgap reference circuit is quickly switched from the sleep mode to the working mode, and the starting time of the bandgap reference circuit is shortened.

Furthermore, the band-gap reference circuit of the application also comprises a sample-hold module arranged at the voltage output end and the output of the operational amplifier, and the sample-hold module can keep the output band-gap reference voltage and the output voltage of the operational amplifier in a stable state when the band-gap reference circuit is in a dormant mode. With this arrangement, when the bandgap reference circuit is switched from the sleep mode to the operation mode, the bandgap reference voltage and the output voltage of the operational amplifier need only rise from the steady state, and do not need to rise from zero, so that the start-up time of the bandgap reference circuit can be further shortened.

Furthermore, the reference voltage generating module is also used for generating the bias voltage of at least one cascode structure in the operational amplifier, and an additional voltage bias structure is not required to be arranged in the circuit, so that the area and the cost of the circuit can be reduced, the bias voltage of the operational amplifier and the reference voltage of the reference voltage generating module can be simultaneously established, and the starting time of the band-gap reference circuit is further shortened.

It should be noted that although the device is described herein as an N-channel or P-channel device, or an N-type or P-type doped region, it will be appreciated by those of ordinary skill in the art that complementary devices may be implemented in accordance with the present application. It will be appreciated by those of ordinary skill in the art that conductivity type refers to a mechanism by which electrical conduction occurs, such as by hole or electron conduction, so conductivity type does not relate to doping concentration but rather to doping type, such as P-type or N-type. It will be appreciated by those of ordinary skill in the art that the terms "during", "when" and "when … …" as used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the start of a start-up action, but rather there may be some small but reasonable delay or delays between it and the reaction action (reaction) initiated by the start-up action, such as various transmission delays and the like. The word "about" or "substantially" is used herein to mean that an element value (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation such that the value or position is difficult to strictly assume the stated value. It has been well established in the art that deviations of at least ten percent (10%) (at least twenty percent (20%)) for semiconductor doping concentrations are reasonable deviations from the exact ideal targets described. When used in connection with a signal state, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.

Furthermore, it should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The scope of the application should be determined by the following claims.

Claims (10)

1. A bandgap reference circuit comprising:

a reference voltage generation module having an output node for generating a bandgap reference voltage;

the operational amplifier is connected with a first node and a second node in the reference voltage generation module and is used for clamping voltages at the first node and the second node; and

and the current bias module is used for generating bias current required by the operation of the operational amplifier according to the first bias voltage and a sleep mode signal so as to enable the band gap reference circuit to be rapidly switched from the sleep mode to the working mode.

2. The bandgap reference circuit of claim 1, further comprising:

the starting module is used for providing starting current for the reference voltage generating module when the power supply end is electrified.

3. The bandgap reference circuit of claim 1, further comprising:

the first sample hold module is used for transmitting the band gap reference voltage generated by the reference voltage generation module to the voltage output end of the band gap reference circuit when the band gap reference circuit is in a working mode; and maintaining the voltage at the voltage output terminal when the bandgap reference circuit is in a sleep mode.

4. The bandgap reference circuit of claim 1, further comprising:

and the second sample hold module is connected with the output end of the operational amplifier and is used for holding the voltage of the output end of the operational amplifier when the band gap reference circuit is in the sleep mode.

5. The bandgap reference circuit of claim 1, wherein,

the reference voltage generation module also has a third node that generates a second bias voltage for at least one cascode structure in the operational amplifier.

6. The bandgap reference circuit of claim 5, wherein the reference voltage generation module comprises:

a first transistor and a first resistor connected in series between a supply terminal and the third node, a common node of the first transistor and the first resistor serving as the output node to generate the bandgap reference voltage;

a second resistor, a third resistor and a first triode connected in series between the third node and ground, the common node of the second resistor and the third resistor being connected as the first node to the inverting input of the operational amplifier; and

and a fourth resistor and a second triode which are connected in series between the third node and the ground, wherein the control ends of the first triode and the second triode are connected with the ground, and the common node of the fourth resistor and the second triode is used as the second node to be connected with the non-inverting input end of the operational amplifier.

7. The bandgap reference circuit of claim 2, wherein the start-up module comprises:

the control end of the second transistor is in short circuit with the first end, and the control end of the third transistor is in short circuit with the second end; and

and a third transistor connected between the power supply terminal and an output node of the reference voltage generating module, a control terminal of the third transistor being connected to a control terminal of the second transistor.

8. The bandgap reference circuit of claim 5, wherein the operational amplifier comprises:

a control end of the fourth transistor is connected with the second node, a control end of the fifth transistor is connected with the first node, and a second end of the fourth transistor and a second end of the fifth transistor are connected with the current bias module;

a sixth transistor and a seventh transistor, the control terminals of the sixth transistor and the seventh transistor being configured to receive the second bias voltage, the second terminal of the sixth transistor being connected to the first terminal of the fourth transistor, the second terminal of the seventh transistor being connected to the first terminal of the fifth transistor;

an eighth transistor and a ninth transistor connected in series between a power supply terminal and a first terminal of the sixth transistor, a control terminal of the eighth transistor and the ninth transistor being connected to a second terminal of the ninth transistor; and

a tenth transistor and an eleventh transistor connected in series between the power supply terminal and the first terminal of the seventh transistor, the control terminal of the tenth transistor being connected to the control terminal of the eighth transistor, the control terminal of the eleventh transistor being connected to the control terminal of the ninth transistor, a common node of the eleventh transistor and the seventh transistor being an output terminal of the operational amplifier.

9. The bandgap reference circuit of claim 1, wherein the current bias module comprises:

a twelfth transistor, a sixth resistor and a thirteenth transistor connected in series between the output terminal of the bias current and ground, a control terminal of the twelfth transistor being configured to receive the first bias voltage, a control terminal of the thirteenth transistor being configured to receive the sleep mode signal, the sleep mode signal being configured to control the bandgap reference circuit to be in an operating mode or a sleep mode; and

a first capacitor connected between the control terminal of the twelfth transistor and ground.

10. An electronic device, comprising:

a bandgap reference circuit as claimed in any of claims 1 to 9.