CN116568039A - SONOS memory forming method - Google Patents

SONOS memory forming method Download PDF

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Publication number
CN116568039A
CN116568039A CN202310634411.5A CN202310634411A CN116568039A CN 116568039 A CN116568039 A CN 116568039A CN 202310634411 A CN202310634411 A CN 202310634411A CN 116568039 A CN116568039 A CN 116568039A
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Prior art keywords
polysilicon
forming
layer
region
opening
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CN202310634411.5A
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Chinese (zh)
Inventor
彭景淞
张可钢
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202310634411.5A priority Critical patent/CN116568039A/en
Publication of CN116568039A publication Critical patent/CN116568039A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Semiconductor Memories (AREA)

Abstract

The invention provides a forming method of a SONOS memory, which comprises the following steps: providing a substrate, forming a storage tube region active region in the substrate, and sequentially forming an ONO layer, first polysilicon and a hard mask layer on the storage tube region active region; forming a first opening in the hard mask layer and the first polysilicon, wherein the surface of the ONO layer is exposed in the first opening; sequentially etching the ONO layer and the active area of the storage tube area from the first opening to the active area of the storage tube area to form a groove in the active area of the storage tube area; forming a blocking oxide layer on the inner wall of the groove; implanting ions into the active region of the storage tube region through the blocking oxide layer to form a source electrode of the storage tube in the active region of the storage tube region; removing the blocking oxide layer; forming a selective tube oxide layer on the inner wall of the groove; forming a gate of the selection tube in the groove and the first opening; the first polysilicon is etched to form the gate of the memory tube. The invention can apply voltage to the storage tube and the selection tube separately.

Description

SONOS memory forming method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a SONOS memory.
Background
With the rapid popularization of electronic products, flash memory is rapidly popularized as a main stream storage carrier at present, and the technology of flash memory is rapidly developed. Non-volatile memory (NVM) technology is divided from storage media into floating gate technology and SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) technology.
The forming method of the SONOS memory in the prior art comprises the following steps: referring to fig. 1 and 2, first, a substrate is provided, in which adjacent active region 101 and shallow trench isolation structure 102 are formed, and in cross section, the active region 101 and the shallow trench isolation structure 102 are both stripe-shaped structures, which extend along the Y direction, and an ONO layer 103 is formed on the active region 101, and the ONO layer 103 is subsequently used as a charge storage layer of a memory cell. Next, a layer of first polysilicon 104 and a hard mask layer 105 are sequentially deposited on the surface of the ONO layer 103. The first polysilicon 104 is subsequently etched to form the gate of the memory tube. The hard mask layer 105 is used as a mask in an etching process, and is made of silicon nitride. Next, referring to fig. 3, the hard mask layer 105 is partially etched to form an opening, and the surface of the first polysilicon 104 is exposed in the opening. A first oxide layer 106 is formed within the opening, the first oxide layer 106 covering the sidewalls of the remaining hard mask layer 105. Next, referring to fig. 4, the first polysilicon 104 and the ONO layer 103 are etched to expose the surface of the active region 101 of the memory tube region, so as to form a trench region with a preliminary depth. Next, referring to fig. 5, an isolation dielectric layer 107, such as an isolation oxide layer, is grown, and the isolation dielectric layer 107 covers the sidewall of the ONO layer 103, the sidewall of the first polysilicon 104, and the first oxide layer 106. Then, the exposed memory tube region active region 101 is etched, and the inside of the memory tube region active region 101 is stopped. A second oxide layer 108 is formed to cover the inner wall of the active region 101 of the memory tube region and the isolation dielectric layer 107, the second oxide layer 108 forming a trench. Next, referring to fig. 5, a silicon nitride sacrificial layer 109 is formed to cover the inner wall of the second oxide layer 108. Next, referring to fig. 6, the silicon nitride sacrificial layer 109 is etched, and the sacrificial dielectric layer on the sidewall of the trench is reserved, so as to expose the surface of the second oxide layer 108. Ion implantation is performed from the exposed second oxide layer 108 into the memory tube region active region 101 to form a memory tube source 110, then the second oxide layer 108 on the surface of the memory tube region active region 101 at the bottom of the trench is etched, the surface of the memory tube region active region 101 is exposed, the surface of the memory tube source 110 is exposed, and the remaining second oxide layer 108 serves as a gate oxide layer. Next, referring to fig. 7, the remaining silicon nitride sacrificial layer 109 is removed, and after the silicon nitride sacrificial layer 109 is removed, the second oxide layer 108 on the inner wall of the trench is exposed. Next, the second polysilicon 111 is filled in the trench, and the rising direction of the second polysilicon 111 in the cross section rises along the X direction and spans the shallow trench isolation structure 102, and the X direction and the Y direction are perpendicular to each other, as shown in fig. 8. Finally, the remaining process is completed.
However, in the prior art SONOS memory forming method, the second polysilicon 111 is used as the gate of the selection tube, the second polysilicon 111 is connected to the source 110 of the memory tube, and the second polysilicon 111 shares one polysilicon with the source 110 of the memory tube and the gate of the selection tube, so that the voltage cannot be independently applied to the memory tube and the selection tube. In addition, during the manufacturing process, the second oxide layer 108 on the surface of the active region 101 of the memory tube region needs to be partially etched, and in this case, in order to protect the second oxide layer 108 of the sidewall, the second oxide layer 108 of the sidewall needs to be protected by using the silicon nitride sacrificial layer 109, which is complicated in process. Further, when the silicon nitride sacrificial layer 109 is removed by the wet process, the second oxide layer 108 is damaged, i.e., the gate oxide layer is damaged.
Disclosure of Invention
The invention aims to provide a forming method of a SONOS memory, which can enable a source electrode of a storage tube and a grid electrode of a selection tube to be separated, so that voltage can be independently applied to the storage tube and the selection tube. And the gate oxide layer can be protected without using a silicon nitride sacrificial layer and reducing the process steps.
In order to achieve the above object, the present invention provides a method for forming a SONOS memory device, comprising:
providing a substrate, forming adjacent active regions and shallow trench isolation structures in the substrate, wherein the cross sections of the active regions are cross-shaped, namely, first active regions along the X direction and second active regions along the Y direction, the X direction and the Y direction are mutually perpendicular, the intersecting part of the first active regions and the second active regions is used as a storage tube region active region, and an ONO layer, a first polysilicon layer and a hard mask layer are sequentially formed on the storage tube region active region;
forming a first opening in the hard mask layer and the first polysilicon, wherein the surface of the ONO layer is exposed in the first opening;
sequentially etching the ONO layer and the storage tube region active region from the first opening to the direction of the storage tube region active region to form a groove in the storage tube region active region;
forming a blocking oxide layer on the inner wall of the groove;
implanting ions into the active region of the storage tube region through the blocking oxide layer to form a source electrode of the storage tube in the active region of the storage tube region;
removing the blocking oxide layer;
forming a selective tube oxide layer on the inner wall of the groove;
forming a grid electrode of a selection tube in the groove and the first opening, wherein the grid electrode of the selection tube rises along the X direction in a cross section;
and etching the first polysilicon to form a grid electrode of the storage tube.
Optionally, in the method for forming a SONOS memory, a first sidewall and a second sidewall are further formed in the first opening, the first sidewall covers a sidewall of the hard mask layer, and the second sidewall covers a sidewall of the first sidewall and a sidewall of the first polysilicon.
Optionally, in the method for forming a SONOS memory, the method for forming a first opening in the hard mask layer and the first polysilicon includes:
etching the hard mask layer to expose part of the surface of the first polysilicon and the residual side wall of the hard mask layer;
forming a first oxide layer, wherein the first oxide layer covers the surface of the first polysilicon, the side walls of the residual hard mask layer and the surface of the hard mask layer;
etching the first oxide layer to expose the surface of the hard mask layer and the surface of the first polysilicon, wherein the rest of the first oxide layer is used as a first side wall;
etching the exposed first polysilicon to form a first opening, wherein the first opening exposes the surface of the ONO layer.
Optionally, in the method for forming a SONOS memory, a first opening is formed in the hard mask layer and the first polysilicon, and after the surface of the ONO layer is exposed in the first opening, the method further includes: and forming a Halo structure in the active region of the storage tube region below the first opening, and sequentially etching the ONO layer, the Halo structure and the active region of the storage tube region to form a groove in the active region of the storage tube region.
Optionally, in the method for forming a SONOS memory, a Halo structure is formed in the active region of the storage tube region under the first opening by means of ion implantation.
Optionally, in the forming method of the SONOS memory, the method for forming the gate of the selection tube in the recess and the first opening includes:
filling the groove and the first opening with second polysilicon, and filling the groove and the first opening with the second polysilicon;
and grinding the surface of the second polysilicon to form a grid electrode of the selection tube.
Optionally, in the forming method of the SONOS memory, after forming the gate of the selection tube in the recess and the first opening, the forming method further includes:
and removing the hard mask layer to expose the surface of the first polysilicon.
Optionally, in the method for forming a SONOS memory, the method for etching the first polysilicon to form a gate of a memory tube includes:
and etching and removing the first polysilicon uncovered by the first side wall to expose the surface of the ONO layer, and forming the grid electrode of the storage tube by the residual first polysilicon.
Optionally, in the method for forming a SONOS memory, after etching the first polysilicon to form a gate of the memory tube, the method further includes:
and implanting ions into the active region of the storage tube region through the ONO layer to form a drain end.
Optionally, in the method for forming a SONOS memory, after implanting ions into the active region of the memory tube region through the ONO layer to form a drain terminal, the method further includes:
and removing the ONO layer uncovered by the first polysilicon to expose the drain end and the surface of the storage tube region active region.
In the method for forming the SONOS memory provided by the invention, the source electrode of the formed memory tube and the grid electrode of the selection tube are separated, so that voltage can be independently applied to the memory tube and the selection tube. And the silicon nitride sacrificial layer is not needed, so that the process steps are reduced, and the gate oxide layer is also protected.
Drawings
FIGS. 1-8 are schematic diagrams of the formation of SONOS memory devices in the prior art;
FIG. 9 is a flow chart of a method of forming a SONOS memory in accordance with an embodiment of the present invention;
fig. 10 to 19 are schematic diagrams illustrating formation of a SONOS memory device according to an embodiment of the present invention;
in the figure: the semiconductor device comprises a 101-memory tube region active region, a 102-shallow trench isolation structure, a 103-ONO layer, a 104-first polysilicon layer, a 105-hard mask layer, a 106-first oxide layer, a 107-isolation dielectric layer, a 108-second oxide layer, a 109-silicon nitride sacrificial layer, a 110-memory tube source electrode, a 111-second polysilicon layer, a 201-active region, a 201A-first active region, a 201B-second active region, a 201C-memory tube region active region, a 202-shallow trench isolation structure, a 203-ONO layer, a 204-first polysilicon layer, a 205-hard mask layer, a 206-first side wall, a 207-Halo structure, a 208-second side wall, a 209-blocking oxide layer, a 210-memory tube source electrode, a 211-select tube oxide layer, a 212-select tube gate electrode and a 213-drain end.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the following, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 9, the present invention provides a method for forming a SONOS memory, including:
s1: providing a substrate, forming adjacent active regions and shallow trench isolation structures in the substrate, wherein the cross sections of the active regions are cross-shaped, namely, first active regions along the X direction and second active regions along the Y direction, the X direction and the Y direction are mutually perpendicular, the intersecting part of the first active regions and the second active regions is used as a storage tube region active region, and an ONO layer, a first polysilicon layer and a hard mask layer are sequentially formed on the storage tube region active region;
s2: forming a first opening in the hard mask layer and the first polysilicon, wherein the surface of the ONO layer is exposed in the first opening;
s3: sequentially etching the ONO layer and the storage tube region active region from the first opening to the direction of the storage tube region active region to form a groove in the storage tube region active region;
s4: forming a blocking oxide layer on the inner wall of the groove;
s5: implanting ions into the active region of the storage tube region through the blocking oxide layer to form a source electrode of the storage tube in the active region of the storage tube region;
s6: removing the blocking oxide layer;
s7: forming a selective tube oxide layer on the inner wall of the groove;
s8: forming a grid electrode of a selection tube in the groove and the first opening, wherein the grid electrode of the selection tube rises along the X direction in a cross section;
s9: and etching the first polysilicon to form a grid electrode of the storage tube.
Referring to fig. 10 and 11, a substrate, which may be a wafer, is provided first. Adjacent active regions 201 and shallow trench isolation structures 202 are formed in the substrate, the cross section of each active region 201 is in a cross shape, each active region is a second active region 201B along the X direction, the first active regions 201A along the Y direction are perpendicular to each other, and the intersection of the first active regions 201A and the second active regions 201B is used as a storage tube region active region 201C. A second active region 201B is connected in the X direction, and gates of subsequent select transistors are formed along the second active region 201B. After the storage tube and the selection tube are formed, when the source end and the drain end are led out, the grid electrode of the selection tube and the source electrode of the storage tube which are formed later are not required to be communicated, and the source end and the drain end can be led out. The ONO layer 203 is formed by sequentially depositing a form of silicon oxide-silicon nitride-silicon oxide on the surface of the memory tube region active region 201C. Next, a first polysilicon 204 is formed by depositing polysilicon on the surface of the ONO layer 203, and a hard mask layer 205 is formed by depositing silicon nitride on the surface of the first polysilicon 204. The embodiment of the invention can be used for a P-type SONOS memory and an N-type SONOS memory. For a P-type SONOS memory, both the source and drain are P-type implants. For an N-type SONOS memory, PW implantation is required before forming the ONO layer, and then the source and drain are N-type implants.
Next, referring to fig. 12, a portion of the hard mask layer 205 is etched away from the surface of the hard mask layer 205, exposing the surface of the first polysilicon 204 and the sidewalls of the hard mask layer 205. The hard mask layer 205 is etched by adopting a photoetching mode, the cross section size of an opening formed after the hard mask layer 205 is etched is the size which can be used for forming a storage tube later, and the minimum size which can be defined by photoetching can be the size which is to be reserved at this time, so that the size can be minimized as much as possible, and the area of a device can be saved. Next, a first oxide layer is formed by depositing silicon dioxide, and covers the surface of the first polysilicon 204 and the sidewalls of the remaining hard mask layer 205 and the surface of the hard mask layer 205; etching the first oxide layer to expose the surface of the hard mask layer 205 and the surface of the first polysilicon 204, and taking the remaining first oxide layer as a first sidewall 206; the first sidewall 206 covers the sidewall of the hard mask layer 205.
Next, referring to fig. 13, the exposed first polysilicon 204 is etched with reference to the first sidewall 206 to expose the surface of the ONO layer 203. At the same time, a first opening in the hard mask layer 205 and the first polysilicon 204 is formed, which exposes the surface of the ONO layer 203, and also exposes the first sidewall 206 and the sidewalls of the first polysilicon 204.
Next, referring to fig. 14, an ion implantation, which may be a doped ion implantation, is performed into the active region 201C of the memory tube region through the exposed ONO layer 203, so as to form a Halo structure 207, where the cross-sectional area of the Halo structure 207 is slightly larger than the area of the first opening, that is, a portion of the Halo structure is located at a corner where the memory tube and the select tube interface.
Next, referring to fig. 15, a second oxide layer is formed by depositing silicon dioxide, wherein the second oxide layer covers the inner wall of the first opening and the surface of the hard mask layer 205, i.e. the second oxide layer covers the surface of the ONO layer 203, the sidewall of the first polysilicon 204, the first sidewall 206 and the surface of the hard mask layer 205. The second oxide layer is etched, the second oxide layer on the surface of the hard mask layer 205 and the second oxide layer on the surface of the ONO layer 203 are removed, the remaining second oxide layer serves as a second sidewall 208, and the second sidewall 208 covers the first sidewall 206 and the sidewall of the first polysilicon 204. Next, the ONO layer 203, the Halo structure 207 and the memory tube region active region 201C with a partial depth are etched with reference to the second sidewall 208 to form a trench, the memory tube region active region 201C on the inner wall of the trench is oxidized to form a blocking oxide layer 209, and ions are injected into the memory tube region active region 201C through the blocking oxide layer 209 on the bottom of the trench to form an active region as a source 210 of the memory tube.
Next, referring to fig. 16 and 17, when the source 210 of the memory tube is formed by implanting ions into the active region 201C of the memory tube region, the blocking oxide layer 209 is damaged, and the blocking oxide layer 209 is removed. The inner wall of the recessed memory tube region active region 201C forms a selective tube oxide layer 211. The first opening and the recess are then filled with a second polysilicon and the surface of the second polysilicon is etched back and ground to be planarized to serve as a gate 212 of the select pipe, which gate 212 of the select pipe is elongated upward in cross section along the X direction, as can be seen in fig. 18, and the gate 212 of the select pipe is formed on the second active region 201B. In contrast to the prior art, the gate 212 of the select transistor does not need to be connected across the shallow trench isolation structure, thus creating conditions for the gate 212 of the select transistor and the source 210 of the memory transistor not to be connected.
Next, referring to fig. 19, the hard mask layer 205 is removed, and the first polysilicon 204 uncovered by the first sidewall 206 is etched and removed, and the remaining first polysilicon 204 is used as the gate of the memory tube. Next, the ONO layer 203 uncovered by the gate of the memory tube is etched and removed. Next, ions are implanted into the active region of the memory tube region not covered by the ONO layer 203 to form the drain 213. Each memory cell is composed of a selection tube and a memory tube grating, the memory tube is in the transverse direction (X direction), the selection tube is in the longitudinal direction (Y direction), and two adjacent memory cells share a source electrode. During reading, one of the storage tubes may be turned off, and a voltage is applied from the source end 210 of the storage tube to read the state of the other storage tube. The bottom of the select tube is a self-aligned source of connectivity. In the process manufacturing method: the sum of the integral width of the two storage tubes on the cross section and the width of the source end on the cross section is defined by photoetching, and the self-alignment process is adopted to define the length of a single storage tube on the cross section, so that the area is reduced; the length of the selection tube is also defined by the etching depth, can be used for manufacturing the selection tube with longer length, and is beneficial to reducing the area.
In summary, in the method for forming a SONOS memory according to the embodiments of the present invention, the source electrode of the formed memory tube and the gate electrode of the selection tube are separated, so that a voltage can be applied to the memory tube and the selection tube separately. And the silicon nitride sacrificial layer is not needed, so that the process steps are reduced, and the gate oxide layer is also protected.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.

Claims (10)

1. A method for forming a SONOS memory device, comprising:
providing a substrate, forming adjacent active regions and shallow trench isolation structures in the substrate, wherein the cross sections of the active regions are cross-shaped, namely, first active regions along the X direction and second active regions along the Y direction, the X direction and the Y direction are mutually perpendicular, the intersecting part of the first active regions and the second active regions is used as a storage tube region active region, and an ONO layer, a first polysilicon layer and a hard mask layer are sequentially formed on the storage tube region active region;
forming a first opening in the hard mask layer and the first polysilicon, wherein the surface of the ONO layer is exposed in the first opening;
sequentially etching the ONO layer and the storage tube region active region from the first opening to the direction of the storage tube region active region to form a groove in the storage tube region active region;
forming a blocking oxide layer on the inner wall of the groove;
implanting ions into the active region of the storage tube region through the blocking oxide layer to form a source electrode of the storage tube in the active region of the storage tube region;
removing the blocking oxide layer;
forming a selective tube oxide layer on the inner wall of the groove;
forming a grid electrode of a selection tube in the groove and the first opening, wherein the grid electrode of the selection tube rises along the X direction in a cross section;
and etching the first polysilicon to form a grid electrode of the storage tube.
2. The method of claim 1, wherein a first sidewall and a second sidewall are further formed in the first opening, the first sidewall covers a sidewall of the hard mask layer, and the second sidewall covers a sidewall of the first sidewall and the first polysilicon.
3. The method of forming a SONOS memory device of claim 2, wherein forming a first opening in the hard mask layer, the first polysilicon, comprises:
etching the hard mask layer to expose part of the surface of the first polysilicon and the residual side wall of the hard mask layer;
forming a first oxide layer, wherein the first oxide layer covers the surface of the first polysilicon, the side walls of the residual hard mask layer and the surface of the hard mask layer;
etching the first oxide layer to expose the surface of the hard mask layer and the surface of the first polysilicon, wherein the rest of the first oxide layer is used as a first side wall;
etching the exposed first polysilicon to form a first opening, wherein the first opening exposes the surface of the ONO layer.
4. The method of claim 1, further comprising, after forming a first opening in the hard mask layer and the first polysilicon, exposing a surface of the ONO layer in the first opening: forming a Halo structure in the storage tube region active region below the first opening; and etching the ONO layer, the Halo structure and the storage tube region active region in sequence to form a groove in the storage tube region active region.
5. The method of claim 4, wherein a Halo structure is formed in the active region of the memory tube region under the first opening by ion implantation.
6. The method of forming a SONOS memory device of claim 1, wherein forming a gate of a select transistor within the recess and the first opening comprises:
filling the groove and the first opening with second polysilicon, and filling the groove and the first opening with the second polysilicon;
and grinding the surface of the second polysilicon to form a grid electrode of the selection tube.
7. The method of forming a SONOS memory device of claim 1, further comprising, after forming a gate of a select tube within the recess and the first opening:
and removing the hard mask layer to expose the surface of the first polysilicon.
8. The method of forming a SONOS memory device of claim 2, wherein etching the first polysilicon to form a gate of a memory cell comprises:
and etching and removing the first polysilicon uncovered by the first side wall to expose the surface of the ONO layer, and forming the grid electrode of the storage tube by the residual first polysilicon.
9. The method of claim 1, further comprising, after etching the first polysilicon to form a gate of a memory tube:
and implanting ions into the active region of the storage tube region through the ONO layer to form a drain end.
10. The method of claim 9, wherein implanting ions into the active region of the memory tube region through the ONO layer to form a drain terminal, further comprises:
and removing the ONO layer uncovered by the first polysilicon to expose the drain end and the surface of the storage tube region active region.
CN202310634411.5A 2023-05-31 2023-05-31 SONOS memory forming method Pending CN116568039A (en)

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Application Number Priority Date Filing Date Title
CN202310634411.5A CN116568039A (en) 2023-05-31 2023-05-31 SONOS memory forming method

Publications (1)

Publication Number Publication Date
CN116568039A true CN116568039A (en) 2023-08-08

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