CN116567444A - Analog-to-digital conversion circuit and infrared imager based on time thickness quantization - Google Patents
Analog-to-digital conversion circuit and infrared imager based on time thickness quantization Download PDFInfo
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- H—ELECTRICITY
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H—ELECTRICITY
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
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Abstract
The invention provides an analog-to-digital conversion circuit and an infrared imager based on time thickness quantification, and relates to the field of integrated circuits. The integrating module integrates the light current within fixed integration time to obtain an integrated voltage, and generates a turnover signal based on the integrated voltage; the digital processing module processes the pulse signals to obtain two charge injection signals and transmits the two charge injection signals to the charge resetting module; the charge resetting module is used for injecting charges into the integrating capacitor in the integrating module to reset the integrating capacitor according to the two charge injection signals; and the counting and storing module counts and stores the pulse signals to obtain a quantification result of the corresponding photocurrent. The charge processing capability of the pixel-level circuit is also obviously improved. Voltage deviation caused by transferring voltage signals inside the pixels to the column-level circuit is reduced, and nonlinearity is reduced. Meanwhile, noise and nonlinearity introduced in the signal transmission process of the pixel-level circuit and the column-level circuit are eliminated, and the signal-to-noise ratio and the linearity of the reading circuit are improved.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to an analog-to-digital conversion circuit based on time thickness quantification and an infrared imager.
Background
Infrared imaging is a technique for identifying an object by detecting infrared radiation emitted by the object, and is currently widely used in the fields of military, space technology, medicine, and the like. The infrared focal plane array component is a main body of an infrared imaging system and consists of an infrared detector and an infrared focal plane reading circuit. The read-out circuit converts the electric signal generated by the infrared detector and outputs the electric signal to an off-chip signal processing system. For infrared focal plane arrays, especially long-wave infrared, the charge processing capability can be significantly improved by using pixel-level analog-to-digital converters (ADCs).
At present, a traditional pixel-level analog-digital converter based on PFM is generally composed of a PFM loop and an N-bit counter, signal current is folded and integrated on an integrating capacitor, signal quantization is realized through multiple counting, but the size of the integrating capacitor is limited due to the pixel area, and a trade-off exists between accuracy and linearity.
The two-stage analog-to-digital conversion structure adopts a voltage resetting mode in the folding integration process, and after integration is finished, residual voltage on an integration capacitor is sampled into a column-level circuit for secondary quantization. In order to improve the charge processing capability, conventional circuits generally employ MOS integration capacitors having large capacitance values per unit area. In addition, in order to ensure the accuracy of the residual voltage quantization, the conventional pixel-level circuit requires that the MOS integration capacitor operates in a limited region where the capacitance value per unit area is large and is substantially unchanged.
Because of this, when the MOS integrating capacitor is reset, a KTC thermal noise charge proportional to the capacitance at the time of reset is injected each time. Meanwhile, the voltage difference change at two ends of the MOS integrating capacitor is limited, so that the swing of the integrating voltage is limited. Therefore, the conventional pixel level circuit has problems that the signal-to-noise ratio is difficult to improve and the charge processing capability is weak. In addition, the residual voltage may deviate during the transfer between the pixel level circuit and the column level circuit, resulting in a non-linearity problem.
Disclosure of Invention
The present invention has been made in view of the above problems, and has as its object to provide an analog-to-digital conversion circuit and an infrared imager based on time-thickening quantization which overcome or at least partially solve the above problems.
A first aspect of an embodiment of the present invention provides an analog-to-digital conversion circuit based on time thickness quantization, where the analog-to-digital conversion circuit includes: the device comprises an integrating module, a digital processing module, a charge resetting module and a counting storage module;
the integration module integrates the light current within a fixed integration time to obtain an integrated voltage, generates a turnover signal based on the integrated voltage, obtains a pulse signal after the turnover signal is subjected to OR gate operation, and transmits the pulse signal to the digital processing module and the counting storage module, wherein the other input signal of the OR gate is a control signal from an off-pixel control unit;
the digital processing module processes the pulse signals to obtain two charge injection signals and transmits the two charge injection signals to the charge resetting module;
the charge resetting module is used for injecting charges into an integrating capacitor in the integrating module according to the two charge injection signals, and resetting the integrating capacitor;
the counting and storing module counts and stores the pulse signals to obtain a quantification result corresponding to the photocurrent;
wherein, the count storage module includes: a counter, a high-order memory module and a low-order memory module;
the counter counts by taking the pulse signal as a clock signal in the fixed integration time, transmits a counting result to the high-order storage module for storage, and resets itself;
after the fixed integration time is over, the photocurrent is still integrated on the integration capacitor to finish the last turnover;
when the last overturn starts, the control signal outside the pixel is changed into a clock signal by the control unit outside the pixel, and a new pulse signal is obtained after the OR gate operation and is transmitted to the counter;
the counter counts the new pulse signals until the last overturn is finished, stops counting, obtains a counting result, transmits the counting result to the low-order storage module for storage, and resets the counting result;
and the sum of the high-order counting result stored in the high-order storage module and the low-order counting result stored in the low-order storage module is the quantization result.
Optionally, the high-order memory module and the low-order memory module are arranged within a pixel; or alternatively, the process may be performed,
the high-order memory module and the low-order memory module are arranged in a column level;
the analog-to-digital conversion circuit is a complete pixel integrated circuit under the condition that the high-order memory module and the low-order memory module are uniformly distributed in pixels, and one pixel corresponds to one complete pixel integrated circuit;
and under the condition that the high-order memory modules and the low-order memory modules are distributed in a column stage, the analog-to-digital conversion circuit is an incomplete pixel integrated circuit, one pixel corresponds to one incomplete pixel integrated circuit, and one column of pixels corresponds to one high-order memory module and one low-order memory module.
Optionally, a first control switch is arranged between the high-order storage module and the counter, and the first control switch is controlled by a high-order counting signal from the pixel external control unit;
a second control switch is arranged between the low-level storage module and the counter, and the second control switch is controlled by a low-level counting signal from the pixel external control unit;
when the first control switch is closed, the high-order storage module receives and stores the high-order counting result;
and when the second switch is closed, the low-order storage module receives and stores the low-order counting result.
Optionally, the digital processing module includes: a logic unit;
the logic unit is respectively connected with the OR gate and the charge reset module;
the logic unit receives the pulse signals output by the OR gate, generates two charge injection signals and transmits the charge injection signals to the charge reset module.
Optionally, the logic unit includes: an AND gate, a first NOT gate, a second NOT gate, a first NOT gate, and a second NOT gate;
the two input ends of the AND gate respectively receive a pulse signal and an integral signal;
the output end of the AND gate is respectively connected with the input end of the first NOT gate and the second input end of the second NOT gate;
the output end of the first NOT gate is connected with the first input end of the first NOT gate;
the second input end of the first NOR gate is connected with the output end of the second NOR gate;
the output end of the first NOR gate is respectively connected with the input end of the second NOR gate and the first input end of the second NOR gate;
the output end of the second NOT gate outputs a first charge injection signal of the two charge injection signals;
the output end of the second NOR gate outputs a second charge injection signal of the two charge injection signals.
Optionally, the charge injection unit includes: the first MOS tube, the second MOS tube and the third MOS tube;
the second end of the first MOS tube is controlled by a first fixed voltage;
the first end of the first MOS tube receives the first charge injection signal;
the third end of the first MOS tube is connected with the first end of the second MOS tube;
the second end of the second MOS tube is controlled by the second fixed voltage;
the third end of the second MOS tube is connected with the first end of the third MOS tube;
the second end of the third MOS tube is controlled by the second charge injection signal;
and a third end of the third MOS tube is connected with the integration module.
Optionally, the integrating module includes: the detector, the MOS tube switch, the integrating capacitor, the total reset switch and the comparator;
one end of the detector is grounded, and the other end of the detector is connected with the first end of the MOS tube switch;
the second end of the MOS tube switch is controlled by an external switch signal;
the third end of the MOS tube switch is respectively connected with the third end of the third MOS tube, the second end of the total reset switch, the first end of the integrating capacitor and the first input end of the comparator;
the first end of the total reset switch receives a total reset voltage;
the second end of the integrating capacitor is grounded;
a second input end of the comparator receives a reference voltage;
the output end of the comparator outputs the turnover signal.
Optionally, during the fixed integration time, the integrated signal is high;
after the fixed integration time has ended, the integrated signal is low.
Optionally, the low level duration of the first one of the two charge injection signals is greater than the low level duration of the second one of the two charge injection signals.
A second aspect of an embodiment of the present invention provides an infrared imager, including: an analog-to-digital conversion circuit based on time-scale quantization as claimed in any one of the first aspects.
According to the analog-to-digital conversion circuit based on time thickness quantization, an integrating module integrates light current in fixed integrating time to obtain integrated voltage, and generates a turnover signal based on the integrated voltage, and the turnover signal is subjected to OR gate operation to obtain a pulse signal and is transmitted to a digital processing module and a counting storage module; the digital processing module processes the pulse signals to obtain two charge injection signals and transmits the two charge injection signals to the charge resetting module; the charge resetting module is used for injecting charges into an integrating capacitor in the integrating module according to the two charge injection signals, and resetting the integrating capacitor; the counting and storing module counts and stores the pulse signals to obtain a quantification result of the corresponding photocurrent.
The counter counts by taking the pulse signal as a clock signal in fixed integration time, and transmits the counting result to the high-order storage module for storage, and then the counter is reset. Different from the traditional mode that the photocurrent can not turn over on the integrating capacitor after the fixed integration time is over, the photocurrent is still integrated on the integrating capacitor after the fixed integration time is over, and the last turn over is completed.
When the last overturn starts, the control signal is changed into a clock signal by the pixel external control unit, and a new pulse signal is obtained after OR gate operation and is transmitted to the counter; the counter counts the new pulse signals, stops counting until the last overturn is finished, obtains a counting result, transmits the counting result to the low-order storage module for storage, and resets the counting result. The sum of the high-order counting result stored in the high-order storage module and the low-order counting result stored in the low-order storage module is the final quantization result.
The final quantization result of the photocurrent of the present invention is only equal to the twice quantized digital quantity: the high-order counting result and the low-order counting result are related and are irrelevant to the size of the integrating capacitor, namely the proposed circuit has no requirement on the working range of the integrating capacitor. Therefore, when the MOS capacitor with a larger capacitance value per unit area is used as the integrating capacitor, the voltage difference across the integrating capacitor can be changed from a stable operation region with a larger capacitance value per unit area to an operation region with a smaller capacitance value per unit area. Therefore, the voltage swing on the MOS integrating capacitor in the proposed circuit is far greater than that of the traditional circuit, and meanwhile, the charge processing capacity of the pixel-level circuit is also obviously improved.
In addition, the light current is quantized in the pixel level circuit, so that voltage deviation caused by transferring a voltage signal in the pixel to the column level circuit is reduced, and nonlinearity is reduced. Meanwhile, noise and nonlinearity introduced in the signal transmission process of the pixel-level circuit and the column-level circuit are eliminated, the signal-to-noise ratio and the linearity of the readout circuit are finally improved, and the power consumption of the readout circuit is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional two-stage analog-to-digital conversion architecture with a mix of pixel and column stages;
fig. 2 is a schematic diagram showing a trend of capacitance change of a conventional MOS capacitor having a large capacitance per unit area;
FIG. 3 is a schematic diagram of an embodiment of an analog-to-digital conversion circuit based on time-scale quantization;
fig. 4 is a schematic diagram of a working sequence corresponding to the charge reset module in the embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The inventor finds that the traditional pixel-level analog-digital converter based on PFM is generally composed of a PFM loop and an N-bit counter, signal current is folded and integrated on an integrating capacitor, signal quantization is realized through multiple counting, but the size of the integrating capacitor is limited by the pixel area, so that a trade-off exists between accuracy and linearity. To improve quantization accuracy, a two-stage analog-to-digital conversion structure in which pixel stages and column stages are mixed may be employed, as shown in fig. 1. The specific circuit structure and operation principle of fig. 1 will be known to those skilled in the art by referring to the structure and principle of the pixel-level analog-to-digital converter that is currently known, and will not be specifically described.
The two-stage analog-to-digital conversion structure adopts a voltage resetting mode in the folding integration process, and after integration is finished, residual voltage on an integration capacitor is sampled into a column-level circuit for secondary quantization. In order to improve the charge processing capability, conventional circuits generally employ MOS capacitors having large capacitance values per unit area. For the MOS capacitor, the capacitance value will also change with the change of the voltage difference across the MOS capacitor, and the change trend is shown in fig. 2. In general, in order to ensure accuracy of quantization of residual voltage, the conventional pixel-level circuit requires that the MOS integration capacitor operates in a limited region with a large capacitance value per unit area and is basically unchanged.
The inventor further researches and discovers that, just because the traditional pixel-level circuit requires the MOS integrating capacitor to work in a limited interval with a larger capacitance value in unit area and basically unchanged, when the MOS integrating capacitor is reset, a KTC thermal noise charge which is proportional to the capacitance value in the resetting process is injected each time. Meanwhile, the voltage difference change at two ends of the MOS integrating capacitor is limited, so that the swing of the integrating voltage is limited. Therefore, the conventional pixel level circuit has problems that the signal-to-noise ratio is difficult to improve and the charge processing capability is weak. In addition, the residual voltage may deviate during the transfer between the pixel level circuit and the column level circuit, resulting in a non-linearity problem. The specific circuit structures and operating principles of fig. 1 and 2 are known to those skilled in the art by referring to the structures and principles of the pixel-level analog-to-digital converter that are currently known, and will not be specifically described.
In order to solve the problems, the inventor creatively provides an analog-to-digital conversion circuit and an infrared imager based on time thickness quantification, which improve the charge processing capacity, increase the linearity and the signal-to-noise ratio of a reading circuit and reduce the power consumption of the reading circuit. The technical scheme of the present invention is explained and illustrated in detail below.
The analog-to-digital conversion circuit based on time thickness quantization in the embodiment of the invention comprises: the device comprises an integrating module, a digital processing module, a charge resetting module and a counting storage module; the integration module integrates the light current within a fixed integration time to obtain an integrated voltage, generates a turnover signal based on the integrated voltage, obtains a pulse signal after the turnover signal is subjected to OR gate operation, and transmits the pulse signal to the digital processing module and the counting storage module, wherein the other input signal of the OR gate is a control signal from a pixel external control unit.
The digital processing module processes the pulse signals to obtain two charge injection signals and transmits the two charge injection signals to the charge resetting module; the charge resetting module is used for injecting charges into the integrating capacitor in the integrating module according to the two charge injection signals, and resetting the integrating capacitor.
The counting and storing module counts and stores the pulse signals to obtain a quantification result of the corresponding photocurrent; wherein, the count storage module includes: a counter, a high-order memory module and a low-order memory module; and the counter counts by taking the pulse signal as a clock signal in fixed integration time, transmits a counting result to the high-order storage module for storage, and resets itself.
Different from the traditional mode that the photocurrent can not turn over on the integrating capacitor after the fixed integration time is over, the photocurrent is still integrated on the integrating capacitor after the fixed integration time is over, and the last turn over is completed. After the fixed integration time is over, the photocurrent is still integrated on the integration capacitor, and the last turnover is completed; when the last overturn starts, the control signal is changed into a clock signal by the pixel external control unit, and a new pulse signal is obtained after OR gate operation and is transmitted to the counter; the counter counts the new pulse signals, stops counting until the last overturning is finished, obtains a counting result, transmits the counting result to the low-order storage module for storage, and resets the counting result; the sum of the high-order counting result stored in the high-order storage module and the low-order counting result stored in the low-order storage module is the final quantization result.
Since the amount of charge stored at the pixel level is quantized for a fixed integration time. The amount of charge quantized as a whole mainly includes a large amount of signal that can be quantized by the coarse quantization structure and a signal margin after integration (i.e., fine quantization). Therefore, the proposed circuit satisfies the following formula regardless of the magnitude of the photocurrent IINT:
IINT×(tINT+tF)＝Qu×(D0+1)
according to this formula, the specific quantized current may become:
in the above two equations, tF is the duration from the fixed integration time to the end of the last integration (for example, the fixed integration time is ended at 10 ms, and the end of the last integration is 10.1 ms, then tF is 0.1 ms), D0 is the coarse quantization result, QU is the unit charge packet of the coarse quantization structure, and tINT is the integration time of one frame.
Also, as the amount of charge generated by the detector is typically greater than one-fourth of the charge handling capability of the readout circuit, tF/tINT is much less than 1 in the latter. After taylor expansion is performed on the latter equation, the following equation can be simplified:
it can be appreciated that QU and tINT are both known quantities and that only D0 and tF need be quantized to obtain the final quantization result.
Since the coarse quantization structure includes a coarse quantized counter and a memory, the fine quantization structure of the residual time also includes a memory of the fine quantization result. Therefore, the area occupied by the digital circuit in the pixel level circuit is extremely large. If the read-out circuit chip is designed and prepared by adopting an advanced CMOS integrated circuit processing technology with small feature size, the whole analog-to-digital conversion circuit can be realized in one pixel area, and the realization mode is called complete pixel integration. In this case, the high-order memory module and the low-order memory module are arranged in pixels, and one pixel corresponds to one full pixel integrated circuit.
If the problem of the cost of the current sheet is considered, a CMOS integrated circuit processing technology with relatively large feature size can be used for designing and preparing the readout circuit chip, then the whole analog-digital conversion circuit can not be integrated in one pixel area, in this case, the high-order memory module and the low-order memory module can be arranged in a column level, and the analog-digital conversion circuit is an incomplete pixel integrated circuit, one pixel corresponds to one incomplete pixel integrated circuit, and one column of pixels corresponds to one high-order memory module and one low-order memory module.
A first control switch is arranged between the high-order storage module and the counter, and the first control switch is controlled by a high-order counting signal from the pixel external control unit; a second control switch is arranged between the low-level storage module and the counter, and the second control switch is controlled by a low-level counting signal from the pixel external control unit; when the first control switch is closed, the high-order storage module receives and stores a high-order counting result; when the second switch is closed, the low-order storage module receives and stores the low-order counting result. In this way, the counters are multiplexed without setting two counters.
For a digital processing module, it comprises: a logic unit; the logic unit is respectively connected with the OR gate and the charge reset module; the logic unit receives the pulse signals output by the OR gate, generates two charge injection signals, and transmits the two charge injection signals to the charge reset module so as to control the charge reset module to perform charge injection on the integrating capacitor, and reset operation in the integrating process is completed.
Referring to fig. 3, which is a schematic diagram of a preferred analog-to-digital conversion circuit based on time-scale quantization, in one possible embodiment, preferred logic units include: and gate nand, first nor gate inv1, second nor gate inv2, first nor gate nor1, and second nor gate nor2.
The two input ends of the AND gate nand respectively receive the pulse signal and the integral signal INT; the output end of the AND gate nand is respectively connected with the input end of the first NOT gate inv1 and the second input end of the second NOT gate nor 2; the output of the first nor gate inv1 is connected to a first input of the first nor gate nor 1.
The second input end of the first nor gate nor1 is connected with the output end of the second nor gate nor 2; the output end of the first nor gate nor1 is respectively connected with the input end of the second nor gate inv2 and the first input end of the second nor gate nor 2; the output end of the second NOT gate inv2 outputs a first charge injection signal phi 1 of the two charge injection signals; the output terminal of the second nor gate nor2 outputs a second charge injection signal Φ2 of the two charge injection signals.
For better explanation and illustration of the analog-to-digital conversion circuit of the present invention, the counter is shown in fig. 3 by way of example as a 10-bit counter, the high-order Memory block is shown as a 10-bit Memory (D0), and the low-order Memory block is shown as an 8-bit Memory (D1). The upper dashed box in fig. 3 indicates that the analog-to-digital conversion circuit is a complete pixel integrated circuit, and the upper memory module and the lower memory module are disposed in the pixels, where one pixel corresponds to one complete pixel integrated circuit. And the 10-bit Memory (D0) and the 8-bit Memory (D1) are placed in the lower virtual frame, so that the analog-to-digital conversion circuit is an incomplete pixel integrated circuit, and the high-order Memory module and the low-order Memory module are uniformly arranged in the column level. Col < j > represents the j-th column. The arrows between the upper and lower virtual boxes in fig. 3 indicate that 10-bit Memory (D0) and 8-bit Memory (D1) in a pixel are placed in a column level, and do not indicate that the entire analog-to-digital conversion circuit has 4 memories or that the signal stream is transmitted. The two arrows within the issued dashed box represent the final quantized current IINT. TR1 and TR2 represent a first control switch and a second control switch, respectively.
In one possible embodiment, the preferred charge injection unit comprises: the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3; the second end of the first MOS tube M1 is controlled by a first fixed voltage VB1; the first end of the first MOS transistor M1 receives the first charge injection signal Φ1.
The third end of the first MOS tube M1 is connected with the first end of the second MOS tube M2; the second end of the second MOS tube M2 is controlled by a second fixed voltage VB2; the third end of the second MOS tube M2 is connected with the first end of the third MOS tube M3; the second end of the third MOS transistor M3 is controlled by the second charge injection signal φ 2. And a third end of the third MOS tube M2 is connected with the integration module.
The specific structure of the integration module comprises: the detector D, MOS is provided with a switch M0, an integration capacitor CINT, a total reset switch S and a comparator CMP; one end of the detector D is grounded, and the other end of the detector D is connected with the first end of the MOS tube switch M0; the second end of the MOS transistor switch M0 is controlled by the external switching signal GPOL.
The third end of the MOS tube switch M0 is respectively connected with the third end of the third MOS tube M3, the second end of the total reset switch S, the first end of the integration capacitor CINT and the first input end of the comparator CMP; a first end of the total reset switch S receives a total reset voltage VR; the second end of the integrating capacitor CINT is grounded; a second input end of the comparator CMP receives a reference voltage VREF; the output terminal of the comparator CMP outputs a flip signal. The inverted signal is used as an input signal for the or gate.
In combination with the structure of the analog-to-digital conversion circuit, fig. 3 and the operation sequence of the analog-to-digital conversion circuit, the operation principle is as follows:
during integration, the current of detector D is integrated over integration capacitance CINT. The integration capacitance CINT is a MOS capacitance because the unit area of the MOS capacitance is larger than the inter-metal capacitance and the inter-metal finger capacitance of the metal. As the current is drawn, the voltage across the integrating capacitor CINT drops. As the gate voltage decreases, the integrating capacitance CINT exits the strong inversion region and the capacitance per unit area decreases instantaneously.
Since the integration current is unchanged, the voltage across the integration capacitance CINT drops rapidly after the capacitance of the integration capacitance CINT decreases. When this voltage drops below the reference voltage VREF of the comparator CMP, the comparator CMP toggles. After the comparator CMP is turned over, the output of the comparator CMP generates phi 1 and phi 2 signals through the digital processing module, and the charge resetting module is controlled to perform charge injection on the integration capacitor CINT, so that resetting operation is completed.
Meanwhile, the output of the comparator CMP is used as a clock signal CK of the counter, so that the counter counts to finish high-order analog-to-digital conversion, and meanwhile, the output of the counter is transferred to a high-order storage module inside the pixel. After the counter output transitions, the counter is reset. After the fixed integration time is over, the photocurrent does not end as with a conventional focal plane readout circuit, but is still integrated over the integration capacitor CINT, completing the last flip.
This last flip is the process of fine quantization. The specific quantization principle is as follows:
by modifying the control signal CK2, the CK2 signal is always low level in the process of high-order analog-to-digital conversion; in the low-order analog-to-digital conversion process, the CK2 signal is changed into a clock signal, and at this time, the output of the comparator CMP and the clock signal CK2 perform logic operation and are output to the counter as the clock signal. When the last turn is over, the counter stops counting, and the result of the counter is the digital result of low-order quantization, namely the fine quantization result. After the low-order quantization is finished, the low-order quantization result of the counter is output to a low-order storage module in the pixel, and finally all the quantization of the photocurrent corresponding to the detector D of the frame is finished.
The quantization can be performed by the above method because the above circuit satisfies the formula regardless of the magnitude of the photocurrent IINT:
IINT×(tINT+D1×tU)＝QU×(D0+1)
the quantized current IINT may be expressed as:
here, d1×tu is tF, and thus there are: d1×tU/tINT is much smaller than 1. The above formula can be reduced by taylor expansion to:
the formula of the detected charge amount QINT is as follows:
in the above equation, the constant C is set to the nth power of 2, and the multiplication and division in the equation can be implemented with a simple shift.
The pixel circuit adopts charges to reset the integrating capacitor, and no photocurrent loss caused by reset time exists. Thus, the quantization of the charge is a complete integration phase of the capacitance quantization, and no charge loss exists. In the quantization structure described above, although the specific integration time of each pixel in the array is not necessarily the same, the current signal does not change during integration.
The corresponding operation sequence of the charge reset module is shown in fig. 4. After the output of the comparator CMP is generated, generation of Φ1 and Φ2 is realized, thereby generating a charge shown by two formulas to reset the integration capacitance CINT:
ΔQ rst ＝C p ×(V B1 -V B2 )
in the above two formulas, cp is the parasitic capacitance between two MOS transistors, and is usually mainly the parasitic capacitance of the source terminal. The analog-to-digital conversion circuit should increase the voltage swing on the integrating capacitor CINT as much as possible, i.e. the amount of charge for a single reset as much as possible. The analog to digital conversion circuit should make the second fixed voltage VB2 equal to the zero voltage while increasing the value of the first fixed voltage VB1 as much as possible. Furthermore, as can be seen from fig. 4, the duration of the low level of the first charge injection signal Φ1 in the two charge injection signals is longer than the duration of the low level of the second charge injection signal Φ2 in the two charge injection signals, and the specific value is the sum of the duration of the low level of the second charge injection signal Φ2 and 2×td, which is equal to the duration of the low level of the first charge injection signal Φ1.
From the explanation and explanation, the photocurrent IINT is only related to the digital quantities D0 and D1 quantized twice, and is independent of the magnitude of the integrating capacitor CINT, which means that the proposed analog-to-digital conversion circuit has no requirement on the operating interval of the integrating capacitor CINT. Therefore, when the MOS capacitor with a larger capacitance value per unit area is used as the integrating capacitor, the voltage difference across the integrating capacitor can be changed from a stable operation region with a larger capacitance value per unit area to an operation region with a smaller capacitance value per unit area. Thus, the voltage swing on the MOS integrating capacitor in the proposed analog-to-digital conversion circuit is much larger than the voltage swing on the MOS integrating capacitor in the conventional circuit. Meanwhile, the charge processing capability of the pixel-level circuit is also obviously improved. The whole analog-digital conversion circuit can finally calculate two digital results of D0 and D1 to obtain the quantification result of the photocurrent generated by the detector D.
Based on the analog-to-digital conversion circuit based on time thickness quantization, the embodiment of the invention also provides an infrared imager, which comprises: an analog-to-digital conversion circuit based on time-scale quantization as claimed in any one of the above.
Through the above example, according to the analog-to-digital conversion circuit based on time thickness quantization, the integrating module integrates the light current in a fixed integrating time to obtain an integrated voltage, and generates a turnover signal based on the integrated voltage, and the turnover signal is subjected to OR gate operation to obtain a pulse signal and is transmitted to the digital processing module and the counting storage module; the digital processing module processes the pulse signals to obtain two charge injection signals and transmits the two charge injection signals to the charge resetting module; the charge resetting module is used for injecting charges into an integrating capacitor in the integrating module according to the two charge injection signals, and resetting the integrating capacitor; the counting and storing module counts and stores the pulse signals to obtain a quantification result of the corresponding photocurrent.
The counter counts by taking the pulse signal as a clock signal in fixed integration time, and transmits the counting result to the high-order storage module for storage, and then the counter is reset. Different from the traditional mode that the photocurrent can not turn over on the integrating capacitor after the fixed integration time is over, the photocurrent is still integrated on the integrating capacitor after the fixed integration time is over, and the last turn over is completed.
When the last overturn starts, the control signal is changed into a clock signal by the pixel external control unit, and a new pulse signal is obtained after OR gate operation and is transmitted to the counter; the counter counts the new pulse signals, stops counting until the last overturn is finished, obtains a counting result, transmits the counting result to the low-order storage module for storage, and resets the counting result. The sum of the high-order counting result stored in the high-order storage module and the low-order counting result stored in the low-order storage module is the final quantization result.
The final quantization result of the photocurrent of the present invention is only equal to the twice quantized digital quantity: the high-order counting result and the low-order counting result are related and are irrelevant to the size of the integrating capacitor, namely the proposed circuit has no requirement on the working range of the integrating capacitor. Therefore, when the MOS capacitor with a larger capacitance value per unit area is used as the integrating capacitor, the voltage difference across the integrating capacitor can be changed from a stable operation region with a larger capacitance value per unit area to an operation region with a smaller capacitance value per unit area. Therefore, the voltage swing on the MOS integrating capacitor in the proposed circuit is far greater than that of the traditional circuit, and meanwhile, the charge processing capacity of the pixel-level circuit is also obviously improved.
In addition, the light current is quantized in the pixel level circuit, so that voltage deviation caused by transferring a voltage signal in the pixel to the column level circuit is reduced, and nonlinearity is reduced. Meanwhile, noise and nonlinearity introduced in the signal transmission process of the pixel-level circuit and the column-level circuit are eliminated, the signal-to-noise ratio and the linearity of the readout circuit are finally improved, and the power consumption of the readout circuit is reduced.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (10)
1. An analog-to-digital conversion circuit based on time thickness quantization, the analog-to-digital conversion circuit comprising: the device comprises an integrating module, a digital processing module, a charge resetting module and a counting storage module;
the integration module integrates the light current within a fixed integration time to obtain an integrated voltage, generates a turnover signal based on the integrated voltage, obtains a pulse signal after the turnover signal is subjected to OR gate operation, and transmits the pulse signal to the digital processing module and the counting storage module, wherein the other input signal of the OR gate is a control signal from an off-pixel control unit;
the digital processing module processes the pulse signals to obtain two charge injection signals and transmits the two charge injection signals to the charge resetting module;
the charge resetting module is used for injecting charges into an integrating capacitor in the integrating module according to the two charge injection signals, and resetting the integrating capacitor;
the counting and storing module counts and stores the pulse signals to obtain a quantification result corresponding to the photocurrent;
wherein, the count storage module includes: a counter, a high-order memory module and a low-order memory module;
the counter counts by taking the pulse signal as a clock signal in the fixed integration time, transmits a counting result to the high-order storage module for storage, and resets itself;
after the fixed integration time is over, the photocurrent is still integrated on the integration capacitor to finish the last turnover;
when the last overturn starts, the control signal outside the pixel is changed into a clock signal by the control unit outside the pixel, and a new pulse signal is obtained after the OR gate operation and is transmitted to the counter;
the counter counts the new pulse signals until the last overturn is finished, stops counting, obtains a counting result, transmits the counting result to the low-order storage module for storage, and resets the counting result;
and the sum of the high-order counting result stored in the high-order storage module and the low-order counting result stored in the low-order storage module is the quantization result.
2. The analog-to-digital conversion circuit of claim 1, wherein the high-order memory module and the low-order memory module are arranged within a pixel; or alternatively, the process may be performed,
the high-order memory module and the low-order memory module are arranged in a column level;
the analog-to-digital conversion circuit is a complete pixel integrated circuit under the condition that the high-order memory module and the low-order memory module are uniformly distributed in pixels, and one pixel corresponds to one complete pixel integrated circuit;
and under the condition that the high-order memory modules and the low-order memory modules are distributed in a column stage, the analog-to-digital conversion circuit is an incomplete pixel integrated circuit, one pixel corresponds to one incomplete pixel integrated circuit, and one column of pixels corresponds to one high-order memory module and one low-order memory module.
3. The analog-to-digital conversion circuit of claim 1, wherein a first control switch is provided between the high-level storage module and the counter, the first control switch being controlled by a high-level count signal from the off-pixel control unit;
a second control switch is arranged between the low-level storage module and the counter, and the second control switch is controlled by a low-level counting signal from the pixel external control unit;
when the first control switch is closed, the high-order storage module receives and stores the high-order counting result;
and when the second switch is closed, the low-order storage module receives and stores the low-order counting result.
4. The analog-to-digital conversion circuit of claim 1, wherein the digital processing module comprises: a logic unit;
the logic unit is respectively connected with the OR gate and the charge reset module;
the logic unit receives the pulse signals output by the OR gate, generates two charge injection signals and transmits the charge injection signals to the charge reset module.
5. The analog-to-digital conversion circuit of claim 4, wherein said logic unit comprises: an AND gate, a first NOT gate, a second NOT gate, a first NOT gate, and a second NOT gate;
the two input ends of the AND gate respectively receive a pulse signal and an integral signal;
the output end of the AND gate is respectively connected with the input end of the first NOT gate and the second input end of the second NOT gate;
the output end of the first NOT gate is connected with the first input end of the first NOT gate;
the second input end of the first NOR gate is connected with the output end of the second NOR gate;
the output end of the first NOR gate is respectively connected with the input end of the second NOR gate and the first input end of the second NOR gate;
the output end of the second NOT gate outputs a first charge injection signal of the two charge injection signals;
the output end of the second NOR gate outputs a second charge injection signal of the two charge injection signals.
6. The analog-to-digital conversion circuit of claim 5, wherein said charge injection unit comprises: the first MOS tube, the second MOS tube and the third MOS tube;
the second end of the first MOS tube is controlled by a first fixed voltage;
the first end of the first MOS tube receives the first charge injection signal;
the third end of the first MOS tube is connected with the first end of the second MOS tube;
the second end of the second MOS tube is controlled by the second fixed voltage;
the third end of the second MOS tube is connected with the first end of the third MOS tube;
the second end of the third MOS tube is controlled by the second charge injection signal;
and a third end of the third MOS tube is connected with the integration module.
7. The analog-to-digital conversion circuit of claim 6, wherein said integration module comprises: the detector, the MOS tube switch, the integrating capacitor, the total reset switch and the comparator;
one end of the detector is grounded, and the other end of the detector is connected with the first end of the MOS tube switch;
the second end of the MOS tube switch is controlled by an external switch signal;
the third end of the MOS tube switch is respectively connected with the third end of the third MOS tube, the second end of the total reset switch, the first end of the integrating capacitor and the first input end of the comparator;
the first end of the total reset switch receives a total reset voltage;
the second end of the integrating capacitor is grounded;
a second input end of the comparator receives a reference voltage;
the output end of the comparator outputs the turnover signal.
8. The analog-to-digital conversion circuit of claim 1, wherein the integrated signal is high during the fixed integration time;
after the fixed integration time has ended, the integrated signal is low.
9. The analog-to-digital conversion circuit of claim 1, wherein a low duration of a first one of the two charge injection signals is greater than a low duration of a second one of the two charge injection signals.
10. An infrared imager, the infrared imager comprising: an analog-to-digital conversion circuit based on time-scale quantization as claimed in any of claims 1-9.
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