CN116564800A - Method for forming grooves with different depths on semiconductor surface at one time - Google Patents
Method for forming grooves with different depths on semiconductor surface at one time Download PDFInfo
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- CN116564800A CN116564800A CN202310807918.6A CN202310807918A CN116564800A CN 116564800 A CN116564800 A CN 116564800A CN 202310807918 A CN202310807918 A CN 202310807918A CN 116564800 A CN116564800 A CN 116564800A
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- 238000000034 method Methods 0.000 title claims abstract description 79
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 182
- 238000005530 etching Methods 0.000 claims abstract description 60
- 238000001312 dry etching Methods 0.000 claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 238000001039 wet etching Methods 0.000 claims description 9
- 229920000620 organic polymer Polymers 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 14
- 238000013461 design Methods 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000000873 masking effect Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000009740 moulding (composite fabrication) Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000008204 material by function Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention belongs to the technical field of semiconductor device etching, and particularly relates to a method for forming grooves with different depths on the surface of a semiconductor at one time, which comprises the steps of forming a first mask material and a second mask material with slope structures at designated positions on the surface of a etched material, forming a photoresist layer on the second mask material through a photoetching process, and forming a series of windows according to design; etching the second mask material through the series of windows until the first mask material is exposed; and selecting etching conditions of dry etching to enable the etching conditions to have etching effects on the first mask material and the etched material, then performing next etching until a plurality of series grooves with different depths are formed on the etched material, and finally removing all mask materials. The method can form a plurality of series grooves with different depths by one-time photoetching and dry etching technology, has high efficiency and reduces the labor and time cost.
Description
Technical Field
The invention belongs to the technical field of etching for preparing semiconductor devices, and particularly relates to a method for forming series grooves with different depths on the surface of a semiconductor at one time.
Background
In the process of manufacturing semiconductor devices, it is often necessary to form fine trench structures of different sizes and depths on the surface of the semiconductor material or on the surface of different functional materials thereon, which trench structures have a critical effect on the device performance.
For example, in the design of high power silicon carbide MOSFET devices, it is often necessary to design a series of termination structures to ensure proper operation of the device. One such design is to etch multiple series of trenches around the active area with a gradual change in trench depth to improve device performance.
These fine trench structures are often formed by a photolithography process plus a dry etching process, one of the methods used for the dry etching process is to use plasma to physically and chemically react the semiconductor surface exposed to the plasma beam under the action of a reactive gas to etch the semiconductor surface to form the trench structure. The method is called ion beam etching method, and is mainly characterized by high efficiency and strong directivity. This method also requires the coordination of a photolithographic process to create a pattern in the masking material that exposes the surface to be etched to the plasma beam, while portions not to be etched are protected by the masking material.
The specific process is as follows: a photoresist layer is coated on the surface of a semiconductor, and is characterized in that the portion irradiated with light can be dissolved by a specific chemical solvent while the portion not irradiated with light cannot be dissolved (or vice versa). The light passes through the photoetching plate, patterns which can transmit light and cannot transmit light are designed and formed on the photoetching plate and irradiated on the photoresist layer, so that the designed patterns on the photoetching plate are transferred onto the photoresist layer, then a surface window which needs to be etched and removed is formed on the mask by a wet etching method, and finally a needed groove structure is formed in the semiconductor by a dry etching or wet etching method. As shown in fig. 1, the current method of forming the series of trenches having different depths is: and forming grooves with a first depth by first photoetching and dry etching, forming grooves with a second depth by second photoetching and dry etching, and forming a series of grooves with different depths by multiple photoetching and multiple etching.
However, when the method is applied to the condition that the number of the needed series of grooves is relatively large, repeated photoetching and etching are needed for many times, and the technical problem of extremely low efficiency exists.
Disclosure of Invention
In order to solve the technical problems, the invention provides a method for forming grooves with different depths on the surface of a semiconductor at one time, which can form a plurality of series grooves with different depths by a one-time photoetching and dry etching technology, and has high efficiency and greatly reduced labor and time cost.
The method for forming grooves with different depths on the surface of a semiconductor at one time comprises the following steps of:
s1: forming a first mask material with a slope structure with gradually reduced thickness at a designated position on the surface of the etched material;
s2: forming a second mask material with uniform thickness and same slope on the first mask material;
s3: forming a photoresist layer with uniform thickness and same slope on the second mask material, and forming a series of windows on a specific slope area of the photoresist layer according to the design through a photoetching process according to the requirement, wherein the second mask material is partially exposed;
s4: etching the exposed positions on the second mask material to transfer the series of windows to the second mask material to partially expose the first mask material;
s5: and etching the first mask material and the etched material until the series of grooves with different depths are etched on the etched material, and removing the first mask material and the second mask material.
The first mask material in S1 is formed by an imprint method.
In an optimized scheme, the first mask material is a material suitable for imprinting, the first mask material can be an organic polymer, and when the etched material is etched by a dry etching method, the first mask material can also be etched.
The method of forming the second mask material in S2 is performed by any other method that can form a thin film of uniform thickness.
The second mask material may be silicon dioxide or metal. Since the etching rate of the second mask material is much smaller than that of the first mask material and the etched material, the slope structure is ensured not to be damaged before the whole etching is completed.
In the optimization scheme, the angle of the slope structure is less than or equal to 45 degrees. The slope for the mask material plays a role in adjusting the etching front.
And in S4 and S5, transferring the series of windows to the second mask material and the first mask material by a dry etching method or a wet etching method.
And S5, transferring the series of windows to the etched material by a dry etching method. And continuously transferring the design pattern to the surface of the semiconductor through dry etching, removing the mask material, and forming a plurality of series grooves with different depths on the surface of the semiconductor.
In the step S4, the conditions to be satisfied for selecting the second mask material are: the etching rate of the second mask material is far smaller than that of the first mask material and the etched material; the etching rates of the first mask material, the etched material and the second mask material are compared under the same etching method.
In the step S5, the conditions to be satisfied for selecting the first mask material are: the etching rate of the first mask material in the direction vertical to the surface is equal to that of the etched material, and the etching rate of the first mask material in the direction parallel to the surface is smaller than that of the etched material; the etching rate of the first mask material and the etching rate of the etched material are compared under the same etching method.
According to the invention, the etched material and the first mask material are effectively etched by a dry etching method, and due to the existence of the slope, the window area formed on the slope has a height difference, so that the time difference exists between the etching front edge and the surface of the etched material, and finally the grooves formed on the etched material have different depths.
The invention provides a method for forming grooves with different depths on the surface of a semiconductor at one time, which solves the technical problems that repeated photoetching and etching are needed for many times and the efficiency is very low if the number of the grooves is relatively large.
Drawings
FIG. 1 is a flow chart of a conventional ion beam etching process according to the present invention;
FIG. 2 (a) is a schematic illustration of forming a first mask material according to the present invention;
FIG. 2 (b) is a schematic illustration of forming a first mask material and a second mask material in accordance with the present invention;
FIG. 2 (c) is a schematic diagram of the photoresist layer being etched according to the present invention;
FIG. 3 is a schematic diagram of the second mask material and photoresist layer being etched according to the present invention;
FIG. 4 is a schematic diagram of photoresist removal in accordance with the present invention;
FIG. 5 is a schematic diagram of the first mask material, the second mask material and the etched material according to the present invention;
FIG. 6 is a schematic diagram of removing a first mask material and a second mask material according to the present invention;
the specific identification in the figure is as follows:
1-a first mask material, 2-an etched material, 3-a second mask material, 4-slope structures, 5-series windows, 6-slope angles, 7-series grooves and 8-photoresist layers.
Detailed Description
The invention is further illustrated by the following description of specific embodiments:
example 1
As shown in fig. 2 (a), first, a first mask material 1 having a slope structure 4 is formed at a specified position on the surface of a material 2 to be etched; one of the methods of forming the first mask material 1 is an imprinting method, and the slope angle 6 of the slope structure 4 may be set to 45 degrees or less.
The designated position is the position of the groove to be etched in the device design, is related to the structure of the device at the time, and is determined according to actual requirements.
As shown in fig. 2 (b), a second mask material 3 is then formed on the first mask material 1. The second mask material 3 is formed by other methods, the other methods are conventional methods, the stamping method is a forming method of placing a plate material between an upper die and a lower die, changing the thickness of the material under the action of pressure, filling the extruded material into the convex and concave cavities of the die with the undulating fine lines, and forming undulating bulges and characters or patterns on the surface of a workpiece, and the method is also a conventional method.
The second mask material 3 may be silicon dioxide or metal. Since the etching rate of the second mask material 3 is much smaller than the etching rates of the first mask material 1 and the etched material 2, it can be ensured that the ramp structure 4 is not damaged before the entire etching is completed.
As shown in fig. 2 (c), a photoresist layer 8 is formed on the second mask material 3, and a series of windows 5 are formed on the photoresist layer 8 by a photolithography process according to a design.
In this example, the mask material has two layers, namely a first mask material 1 of a first layer and a second mask material 3 of a second layer, a photoresist layer 8 is formed on the second mask material 3 of the second layer, namely a third layer, and a series of windows 5 are opened on the third layer by using a photolithography method to locally expose the second mask material 3;
as shown in fig. 3, the exposed portions of the second mask material 3 are etched by wet or dry etching, and the series of windows 5 are patterned onto the first mask material 1, exposing portions of the first mask material 1.
The second mask material 3 is selected to satisfy the following conditions: the etching rate of the second mask material 3 is much smaller than the etching rates of the first mask material 1 and the etched material 2; the etching rates of the first mask material 1, the etched material 2 and the second mask material 3 are compared under the same etching method, and the etching method is a dry etching method or a wet etching method.
As shown in fig. 4, the photoresist layer 8 of the third layer is removed.
As shown in fig. 5 and 6, the series of windows 5 are transferred to the first mask material 1 by wet or dry etching, and etched to the etched material 2 by dry etching, and finally the first mask material 1 and the second mask material 3 are removed. The conditions to be satisfied for the selection of the first mask material 1 are: the etching rate of the first mask material 1 in the direction vertical to the surface is equal to the etching rate of the etched material 2, and the etching rate of the first mask material 1 in the direction parallel to the surface is smaller than the etching rate of the etched material 2; the etching rate comparison of the first mask material 1 and the etched material 2 should be performed by the same etching method, and the etching method is a dry etching method or a wet etching method.
A series of windows 5 is designed in the first mask material 1 with the ramp structure 4, and when the groove front at the thickest part of the first mask material 1 reaches the surface of the etched material 2, series of grooves 7 of different depths have been formed inside the etched material 2.
Example 2
Based on the content of embodiment 1, the etching method of the first mask material 1 and the second mask material 3, and the etched material 2 is set to be a dry etching method, so that the etched material 2 can be etched effectively, and the first mask material 1 can be etched effectively.
The first mask material 1 is etched by a dry etching method, and the front edges of the grooves etched at the thinnest part in the dry etching process reach the surface of the etched material 2 because the thicknesses of the first mask material 1 in the vertical direction are different, and the front edges of the grooves at other parts are still in the first mask material 1. When the thickest trench front reaches the surface of the etched material 2, the thinnest trench has entered the interior of the etched material 2 to form a series of trenches 7 of different depths inside the etched material 2.
The ramp angle 6 of the ramp structure 4 may be set to less than 45 degrees. Due to the presence of the ramp structure 4, there is a difference in height in the window region formed thereon, and thus there is a difference in time for the etching front to reach the surface of the material 2 to be etched, as shown in fig. 5; the first masking material 1 and the second masking material 3 are removed and finally a series of trenches 7 are formed in the etched material 2 with different depths. As shown in fig. 6, the etching conditions of the dry etching method may not be set in advance, and may be determined according to the specific material to be etched and the mask material.
In the invention, the etched material 2 can be the existing semiconductor material, the first mask material 1 can be an organic polymer, the second mask material 3 can be silicon dioxide, but the thickness of the silicon dioxide must be ensured not to be completely etched in the whole etching process, and the second mask material 3 can also be some metal materials.
The dry or wet etching is a conventional technique in the present invention, and the method of forming the series of windows 5 is also a conventional photolithography technique.
After a first mask material 1 and a second mask material 3 with a slope structure 4 are formed at a designated position on the surface of a material 2 to be etched, a photoresist layer 8 is formed on the second mask material 3 through a photoetching process, and a series of windows 5 are formed according to design. Etching the second mask material 3 through the series of windows 5 until the first mask material 1 is exposed; the etching conditions of the dry etching method are selected to have etching effects on the first mask material 1 and the etched material 2, then the next etching is carried out until the required series of grooves 7 are formed on the etched material 2, and finally all mask materials are removed. The method can form a plurality of series grooves 7 with different depths by one-time photoetching and dry etching technology, has high efficiency and reduces the labor and time cost.
The above examples/experiments are only examples for clarity of illustration and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (8)
1. A method of forming trenches having different depths at a time in a semiconductor surface, comprising: the method comprises the following steps:
s1: forming a first mask material (1) with a slope structure (4) at a designated position on the surface of the etched material (2);
s2: forming a second mask material (3) with the same slope on the first mask material (1);
s3: forming a photoresist layer (8) with the same slope on the second mask material (3), and forming a series of windows (5) on the slope area of the photoresist layer (8) as required to locally expose the second mask material (3);
s4: transferring the series of windows (5) onto the second mask material (3), locally exposing the first mask material (1);
s5: and etching the first mask material (1) and the etched material (2) until the first mask material (1) and the second mask material (3) are removed after the series of grooves (7) with different depths are etched on the etched material (2).
2. A method of forming trenches having different depths at a time in a semiconductor surface according to claim 1, wherein: the inclination angle of the slope structure (4) is less than or equal to 45 degrees.
3. A method of forming trenches having different depths at a time in a semiconductor surface according to claim 1, wherein: the method for forming the first mask material (1) in the step S1 is an imprinting method.
4. A method of forming trenches having different depths at a time in a semiconductor surface according to claim 3, wherein: the first mask material (1) is an organic polymer.
5. A method of forming trenches having different depths at a time in a semiconductor surface according to claim 1, wherein: and in S4 and S5, transferring the series of windows (5) onto the second mask material (3) and the first mask material (1) by a dry etching method or a wet etching method.
6. A method of forming trenches having different depths at a time in a semiconductor surface as recited in claim 5, wherein: in the steps S4 and S5, the conditions to be satisfied for selecting the second mask material (3) are: the etching rate of the second mask material (3) is far smaller than the etching rates of the first mask material (1) and the etched material (2); wherein, the etching rates of the first mask material (1), the etched material (2) and the second mask material (3) are compared under the same etching method.
7. A method of forming trenches having different depths at a time in a semiconductor surface according to claim 1, wherein: and in the step S5, transferring the series of windows (5) onto the etched material (2) by a dry etching method.
8. A method of forming trenches having different depths in a semiconductor surface at a time as claimed in claim 6 or 7, wherein: in the S4 and S5, the conditions to be satisfied for selecting the first mask material (1) are: the etching rate of the first mask material (1) in the direction vertical to the surface is equal to the etching rate of the etched material (2), and the etching rate of the first mask material (1) in the direction parallel to the surface is smaller than the etching rate of the etched material (2); wherein, the etching rate of the first mask material (1) and the etched material (2) is compared under the same etching method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310807918.6A CN116564800B (en) | 2023-07-04 | 2023-07-04 | Method for forming grooves with different depths on semiconductor surface at one time |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310807918.6A CN116564800B (en) | 2023-07-04 | 2023-07-04 | Method for forming grooves with different depths on semiconductor surface at one time |
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| CN116564800A true CN116564800A (en) | 2023-08-08 |
| CN116564800B CN116564800B (en) | 2023-09-08 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000208612A (en) * | 1999-01-14 | 2000-07-28 | Seiko Epson Corp | Production of semiconductor device having trench element isolating region |
| CN102117763A (en) * | 2010-01-06 | 2011-07-06 | 上海华虹Nec电子有限公司 | Manufacturing process method for obtaining inclined trench structure or changing inclination angle of trench structure |
| EP2824692A1 (en) * | 2012-03-05 | 2015-01-14 | Enraytek Optoelectronics Co., Ltd. | Methods for manufacturing isolated deep trench and high-voltage led chip |
| US20200203131A1 (en) * | 2017-10-20 | 2020-06-25 | Lg Chem, Ltd. | Plasma etching method using faraday cage |
| US10823888B1 (en) * | 2019-11-12 | 2020-11-03 | Applied Materials, Inc. | Methods of producing slanted gratings with variable etch depths |
| CN113168021A (en) * | 2018-12-17 | 2021-07-23 | 应用材料公司 | Method for forming multiple gratings |
-
2023
- 2023-07-04 CN CN202310807918.6A patent/CN116564800B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000208612A (en) * | 1999-01-14 | 2000-07-28 | Seiko Epson Corp | Production of semiconductor device having trench element isolating region |
| CN102117763A (en) * | 2010-01-06 | 2011-07-06 | 上海华虹Nec电子有限公司 | Manufacturing process method for obtaining inclined trench structure or changing inclination angle of trench structure |
| EP2824692A1 (en) * | 2012-03-05 | 2015-01-14 | Enraytek Optoelectronics Co., Ltd. | Methods for manufacturing isolated deep trench and high-voltage led chip |
| US20200203131A1 (en) * | 2017-10-20 | 2020-06-25 | Lg Chem, Ltd. | Plasma etching method using faraday cage |
| CN113168021A (en) * | 2018-12-17 | 2021-07-23 | 应用材料公司 | Method for forming multiple gratings |
| US10823888B1 (en) * | 2019-11-12 | 2020-11-03 | Applied Materials, Inc. | Methods of producing slanted gratings with variable etch depths |
| CN114651198A (en) * | 2019-11-12 | 2022-06-21 | 应用材料股份有限公司 | Method of manufacturing slanted gratings with variable etch depth |
Non-Patent Citations (1)
| Title |
|---|
| 李向红;张斌珍;孟祥娇;范新磊;: "基于SU-8的微流沟道的设计和制作", 传感器与微系统, no. 10, pages 99 - 101 * |
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| CN116564800B (en) | 2023-09-08 |
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