CN116564390A

CN116564390A - Operating voltage trimming circuit and method for flash memory

Info

Publication number: CN116564390A
Application number: CN202310485625.0A
Authority: CN
Inventors: 杨光军
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2023-04-28
Filing date: 2023-04-28
Publication date: 2023-08-08

Abstract

The invention discloses an operating voltage trimming circuit of a flash memory, wherein a storage unit adopts a double-split-gate floating gate device, and two floating gates respectively form a storage bit; when programming the selected memory bit, the corresponding control gate line is connected with the control gate programming voltage, and the bit line close to the memory bit is connected with the source programming voltage. The operating voltage trimming circuit includes: the control end of the first charge pump is connected with a multi-bit first digital signal, and the output end of the first charge pump outputs source programming voltage with the magnitude controlled by the first digital signal. And the control end of the second charge pump is connected with a multi-bit second digital signal, and the output end of the second charge pump outputs the programming voltage of the control gate controlled by the second digital signal. The first and second digital signals when programming two memory bits are obtained by performing a fast programming test on the corresponding memory bits of the plurality of memory cells, respectively, so that the source programming voltage and the control gate programming voltage when programming the two memory bits are independently set. The invention also provides an operating voltage trimming method of the flash memory. The invention can improve programming efficiency.

Description

Operating voltage trimming circuit and method for flash memory

Technical Field

The present invention relates to the field of semiconductor integrated circuits, and more particularly, to an operating voltage trimming circuit for flash memories. The invention also relates to an operating voltage trimming method of the flash memory.

Background

FIG. 1 is a schematic cross-sectional view of a memory cell of a conventional flash memory; the existing flash memory comprises a plurality of memory cells (cells) 101, wherein an array unit 301 is formed by the plurality of memory cells 101, and an array structure of the flash memory is formed by arranging the plurality of array units 301. Each of the memory cells 101 employs a split gate floating gate device.

As shown in fig. 1, the split gate floating gate device includes: a first source drain region 205a and a second source drain region 206 that are symmetrical, a plurality of separate first gate structures with floating gates 104 between the first source drain region 205a and the second source drain region 205b, a second gate structure 103 between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

The split gate floating gate device is a double split gate floating gate device, the number of the first gate structures is two, the two first gate structures are respectively indicated by reference numerals 102a and 102b, floating gates of the two first gate structures are respectively used as a storage bit, and in fig. 1, the two first gate structures are respectively indicated by a storage bit 'a' and a storage bit 'b'.

The split gate floating gate device is an N-type device, and the first source drain region 205a and the second source drain region 205b are both composed of n+ regions.

A P-doped channel region is located between the first source drain region 205a and the second source drain region 205b and is covered by each of the first gate structure and the second gate structure 103. The first source drain region 205a and the second source drain region 205b are both formed on the P-type semiconductor substrate 201 and self-aligned to the outer side surfaces of the corresponding two first gate structures, and the channel region is formed by the P-type semiconductor substrate 201 between the first source drain region 205a and the second source drain region 205b or further formed by doping on the P-type semiconductor substrate 201.

The second source drain region 205b of the memory cell 101 is connected to a second source drain electrode, which is connected to the bit line BL1.

The first source drain region 205a of the memory cell 101 is connected to a first source drain electrode, which is connected to a bit line BL0.

Each of the first gate structures is formed by stacking a tunneling dielectric layer 202, the floating gate 104, a control gate dielectric layer 203, and the control gate 105.

Each of the second gate structures 103 is formed by overlapping a word line gate dielectric layer 204 and a word line gate 106.

The control gates 105 are connected to corresponding control gate lines, and the word line gate 106 is connected to the word line WL. In fig. 1, the memory cell 101 includes two first gate structures, so the control gate lines also include two control gate lines, respectively denoted by CG0 and CG1, the control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

In the prior art, the voltages applied when programming (Program) the memory bits 'a' and 'b' of the memory cell 101 are completely symmetrical, as shown in table one:

list one

	CG0(V)	WL(V)	CG1(V)	BL0(V)	BL1
						Memory bit 'a'	9	1.5	5	4.5(Vsp)	Idp
Memory bit 'b'	5	1.5	9	Idp	4.5(Vsp)

As shown in Table one, the voltages applied during the programming operation of memory bit 'a' include:

the control gate line CG1 is connected to 5V, and is used for opening, that is, conducting, a region section of the channel region controlled by the first gate structure 102 b;

the word line WL is connected to 1.5V, and is used for opening the region segment of the channel region controlled by the second gate structure 103;

bit line BL1 is coupled to programming current Idp.

The control gate line CG0 is connected to a high voltage of 9V and the high voltage is a control gate programming Voltage (VCG), the bit line BL0 is connected to a high voltage of 4.5V and the high voltage is a source programming voltage (Vsp), so that after a programming current reaches the bottom of the first gate structure 102a through the area segments of the channel region controlled by the first gate structure 102b and the second gate structure 103, source hot electron injection programming can be realized because both the control gate line CG0 and the bit line BL1 are high voltages.

The applied signal during the programming operation of memory bit 'b' will then pair the voltages of CG0 and CG1, and the signals of BL0 and BL1 will be.

However, in practice, the widths of the first gate structures 102a and 102b are not identical, and particularly when the first gate structures 102a and 102b are defined by using a photolithography process, the area segments L1 and L2 of the channel region formed by the areas covered by the two regions may deviate from each other due to the photolithography process, and due to the different channel lengths, the programming efficiency may be different when the power-up signals are identical, and in the prior art, since the control gate programming voltages and the source programming voltages used for the memory bits 'a' and 'b' are identical, when the setting of the control gate programming voltages and the source programming voltages satisfy the programming efficiency requirement for the memory bit 'a', the programming efficiency for the memory bit 'b' may be low, and vice versa.

Disclosure of Invention

The invention aims to provide an operating voltage trimming circuit of a flash memory, which can improve programming efficiency. Therefore, the invention also provides an operating voltage trimming method of the flash memory.

Therefore, in the operating voltage trimming circuit of the flash memory, the flash memory comprises a plurality of storage units; each memory cell adopts a double split gate floating gate device.

The dual split gate floating gate device includes: the first source drain region and the second source drain region are symmetrically arranged, two separated first grid structures with floating gates are arranged between the first source drain region and the second source drain region, and the second grid structures are arranged between the first grid structures; the first grid structure is provided with a control grid positioned on the top of the floating gate.

The channel region is located between the first source drain region and the second source drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure respectively controls the covered region sections of the channel region, and the lengths of the region sections of the channel region covered by the two first gate structures have deviation.

The control gate of each first gate structure is connected to a corresponding control gate line, and the first source drain region and the second source drain region are connected to corresponding bit lines; the floating gates of the two first gate structures respectively form a storage bit; when programming the selected storage bit, the control grid line corresponding to the storage bit is connected with a control grid programming voltage, and the bit line close to the storage bit is connected with a source programming voltage.

And enabling the storage bit close to the first source drain region to be a first storage bit and the storage bit close to the second source drain region to be a second storage bit.

The operating voltage trimming circuit includes:

the control end of the first charge pump is connected with a multi-bit first digital signal, the output end of the charge pump outputs the source programming voltage, and the magnitude of the source programming voltage is controlled by the first digital signal.

The control end of the first charge pump is connected with a multi-bit second digital signal, the output end of the charge pump outputs the control gate programming voltage, and the magnitude of the source programming voltage is controlled by the second digital signal.

The first digital signal and the second digital signal during the first memory bit programming are obtained by performing a fast program (fast program) test on the first memory bits of the plurality of memory cells in the flash memory, and the first digital signal and the second digital signal during the second memory bit programming are obtained by performing a fast program test on the second memory bits of the plurality of memory cells in the flash memory, so that the setting of the source program voltage and the control gate program voltage during the first memory bit programming is independent of the setting of the source program voltage and the control gate program voltage during the second memory bit programming, to eliminate the influence of the length deviation of the area sections of the channel region covered by the two first gate structures on the programming efficiency and thereby simultaneously improve the programming efficiency of the first memory bit and the second memory bit.

In a further improvement, the widths of the two first gate structures are defined by lithography, and the lengths of the region sections of the channel regions covered by the two first gate structures have deviation caused by the lithography process.

In a further improvement, the operating voltage trimming circuit further comprises: a first data selector and a second data selector.

The input end of the first data selector is connected with a third digital signal and a fourth digital signal, the control end of the first data selector is connected with a selection signal, the output end of the first data selector outputs the first digital signal, and the first data signal is a signal selected from the third digital signal and the fourth digital signal.

The input end of the second data selector is connected with a fifth digital signal and a sixth digital signal, the control end of the second data selector is connected with the selection signal, the output end of the second data selector outputs the second digital signal, and the second data signal is one signal selected from the fifth digital signal and the sixth digital signal.

A further improvement is that the select signal causes the first data signal to select the third digital signal and the second digital signal to select the fifth digital signal when programming the first memory bit and when performing the fast programming test.

The select signal causes the first data signal to select the fourth digital signal and the second digital signal to select the sixth digital signal when programming the second memory bit and when performing the fast programming test.

In the flash memory, the first memory bit and the second memory bit of each memory cell are distinguished by parity of an address of the control gate line.

In the fast programming test, programming test is carried out on the storage bits corresponding to a plurality of storage units at the same time.

The method is further improved in that when the fast programming test corresponding to the first storage bit is performed, the values of the third digital signal and the fifth digital signal are continuously adjusted in the test process so as to adjust the source programming voltage and the control gate programming voltage until the yield meets the requirements.

And continuously adjusting the values of the fourth digital signal and the sixth digital signal in the test process to adjust the source programming voltage and the control gate programming voltage when the fast programming test corresponding to the second storage bit is performed until the yield meets the requirement.

The double-split-gate floating gate device is an N-type device, the first source drain region and the second source drain region are both composed of an N+ region, and the channel region is doped with P type.

Or the double-split-gate floating gate device is a P-type device, and the first source drain region and the second source drain region are both composed of P+ regions; the channel region is doped with N type.

In order to solve the technical problems, in the method for trimming the operating voltage of the flash memory provided by the invention, the flash memory comprises a plurality of memory cells; each memory cell adopts a double split gate floating gate device.

The operating voltage trimming circuit includes:

The operating voltage trimming method comprises the following steps:

And step one, performing a fast programming test on the first storage bits of a plurality of storage units in the flash memory to obtain the first digital signal and the second digital signal when the first storage bits are programmed.

And step two, performing a fast programming test on the second storage bits of the plurality of storage units in the flash memory to obtain the first digital signal and the second digital signal when the second storage bits are programmed.

Step one and step two make the setting of the source programming voltage and the control gate programming voltage when the first storage bit is programmed independent of the setting of the source programming voltage and the control gate programming voltage when the second storage bit is programmed, so as to eliminate the influence of the length deviation of the area sections of the channel region covered by the two first gate structures on the programming efficiency and thereby improve the programming efficiency of the first storage bit and the second storage bit simultaneously.

In the first step, when the fast programming test corresponding to the first storage bit is performed, the values of the third digital signal and the fifth digital signal are continuously adjusted in the test process to adjust the magnitudes of the source programming voltage and the control gate programming voltage until the yield meets the requirement.

And step two, continuously adjusting the values of the fourth digital signal and the sixth digital signal in the test process to adjust the source programming voltage and the control gate programming voltage when the fast programming test corresponding to the second storage bit is performed until the yield meets the requirement.

For the flash memory of the memory unit adopting the double-split gate floating gate device, the control gate programming voltage and the source programming voltage of two memory bits of the memory unit are respectively and independently set, so that the influence of the deviation of the lengths of the area sections of the channel regions corresponding to the two memory bits of the memory unit on the programming efficiency can be eliminated, the programming efficiency of the two memory bits of the memory unit can be simultaneously optimized, and finally the programming efficiency of the whole flash memory can be improved.

The invention can regulate the control gate programming voltage and the source programming voltage of the storage bit through digital signals, and accurately obtain the gate programming voltage and the source programming voltage which meet the required yield through fast programming test, so that the programming efficiency of each storage bit can be optimized.

The invention utilizes the odd-even difference of the addresses of the control grid lines of the two storage bits of the storage unit to easily distinguish the two storage bits, thereby realizing the fast programming test of the two storage bits and obtaining the corresponding control grid programming voltage and source programming voltage.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

FIG. 1 is a schematic cross-sectional view of a memory cell of a conventional flash memory;

FIG. 2 is a circuit diagram of an operating voltage trimming circuit of a flash memory according to an embodiment of the present invention;

FIG. 3 is a flowchart of a method for trimming an operating voltage of a flash memory according to an embodiment of the present invention.

Detailed Description

FIG. 2 is a circuit diagram of an operating voltage trimming circuit of a flash memory according to an embodiment of the invention; in the operating voltage trimming circuit of the flash memory according to the embodiment of the invention, the flash memory includes a plurality of memory cells 101, and the structure diagram of the memory cells 101 is also shown in fig. 1; each of the memory cells 101 employs a dual split gate floating gate 104 device.

The dual split gate floating gate 104 device includes: a first source drain region 205a and a second source drain region 205b symmetrically disposed, two separate first gate structures having a floating gate 104 located between the first source drain region 205a and the second source drain region 205b, the two first gate structures being denoted by reference numerals 102a and 102b, respectively, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

The channel region is located between the first source drain region 205a and the second source drain region 205b and is covered by each of the first gate structure and the second gate structure 103, and each of the first gate structure and the second gate structure 103 controls a region section of the covered channel region, and lengths of the region sections of the channel regions covered by the two first gate structures have a deviation, as in fig. 1, lengths L1 and L2 of the region sections of the channel regions covered by the two first gate structures are not identical. In some embodiments, the width of the two first gate structures is defined by photolithography, and the lengths of the region segments of the channel region covered by the two first gate structures have deviations caused by the photolithography process.

In the embodiment of the present invention, the dual-split gate floating gate 104 device is an N-type device, the first source drain region 205a and the second source drain region 205b are both composed of an n+ region, and the channel region is doped with P-type material. In other embodiments can also be: the dual split gate floating gate 104 device is a P-type device, and the first source drain region 205a and the second source drain region 205b are both composed of p+ regions; the channel region is doped with N type.

The control gate 105 of each of the first gate structures is connected to a corresponding control gate line, two of which are labeled CG0 and CG1 in fig. 1, respectively. The first source drain region 205a and the second source drain region 205b are connected to corresponding bit lines, and in fig. 1, two bit lines are respectively labeled with BL0 and BL 1; the floating gates 104 of the two first gate structures respectively form a memory bit, and the two memory bits are respectively marked with 'a' and 'b'; when programming the selected storage bit, the control gate line corresponding to the storage bit is connected with a control gate programming voltage, and the bit line close to the storage bit is connected with a source programming voltage Vsp.

Let the storage bit adjacent to the first source drain region 205a be a first storage bit, i.e., storage bit 'a', and the storage bit adjacent to the second source drain region 205b be a second storage bit, i.e., storage bit 'b'.

The operating voltage trimming circuit includes:

the first charge pump 301, the control end of the first charge pump 301 is connected to a multi-bit first digital signal, the output end of the charge pump outputs the source programming voltage Vsp, and the magnitude of the source programming voltage Vsp is controlled by the first digital signal. In fig. 2, the first digital signal is represented by ft_vsp < m:0>, m representing the number of bits of the first digital signal as m+1 bits.

And the control end of the first charge pump 301 is connected with a multi-bit second digital signal, the output end of the charge pump outputs the control gate programming voltage, and the magnitude of the source programming voltage Vsp is controlled by the second digital signal. In fig. 2, the first digital signal is represented by ft_vcg < m:0 >.

The first digital signal and the second digital signal during the first memory bit programming are obtained by performing a fast programming test on the first memory bits of the plurality of memory cells 101 in the flash memory, and the first digital signal and the second digital signal during the second memory bit programming are obtained by performing a fast programming test on the second memory bits of the plurality of memory cells 101 in the flash memory, so that the setting of the source program voltage Vsp and the control gate program voltage during the first memory bit programming is independent of the setting of the source program voltage Vsp and the control gate program voltage during the second memory bit programming, to eliminate the influence of the length deviation of the area sections of the channel region covered by the two first gate structures on the programming efficiency and thereby simultaneously improve the programming efficiency of the first memory bit and the second memory bit.

In an embodiment of the present invention, the operating voltage trimming circuit further includes: a first data selector 303 and a second data selector 304.

The input end of the first data selector 303 is connected to a third digital signal and a fourth digital signal, the control end is connected to a selection signal, the output end outputs the first digital signal, and the first data signal is a signal selected from the third digital signal and the fourth digital signal. In fig. 2, the third digital signal is denoted by ft_vsp0< m:0>, and the fourth digital signal is denoted by ft_vsp1< m:0 >. The select signal is represented by CGSEL.

The input end of the second data selector 304 is connected to a fifth digital signal and a sixth digital signal, the control end is connected to the selection signal, and the output end outputs the second digital signal, where the second data signal is a signal selected from the fifth digital signal and the sixth digital signal. In FIG. 2, the fifth digital signal is represented by FT_VCG0< m:0 >; the sixth digital signal is represented by FT_VCG1< m:0 >.

The select signal causes the first data signal to select the third digital signal and the second digital signal to select the fifth digital signal when programming the first memory bit and when performing the fast programming test.

In the embodiment of the present invention, in the flash memory, the first memory bit and the second memory bit of each of the memory cells 101 are distinguished by parity of an address of the control gate line.

In the fast program test, program tests are simultaneously performed on memory bits corresponding to a plurality of the memory cells 101.

And continuously adjusting the values of the third digital signal and the fifth digital signal in the test process to adjust the source programming voltage Vsp and the control gate programming voltage when the fast programming test corresponding to the first storage bit is performed until the yield meets the requirement.

And continuously adjusting the values of the fourth digital signal and the sixth digital signal in the test process to adjust the source programming voltage Vsp and the control gate programming voltage when the fast programming test corresponding to the second storage bit is performed until the yield meets the requirement.

For the flash memory of the memory cell 101 adopting the dual split gate floating gate 104 device, the control gate programming voltage and the source programming voltage Vsp of the two memory bits of the memory cell 101 are respectively and independently set, so that the influence of the deviation of the lengths of the area segments of the channel regions corresponding to the two memory bits of the memory cell 101 on the programming efficiency can be eliminated, the programming efficiency of the two memory bits of the memory cell 101 can be simultaneously optimized, and finally the programming efficiency of the whole flash memory can be improved.

The embodiment of the invention can regulate the control gate programming voltage and the source programming voltage Vsp of the storage bit through digital signals, accurately obtain the gate programming voltage and the source programming voltage Vsp which meet the required yield through fast programming test, and optimize the programming efficiency of each storage bit.

The embodiment of the invention can easily distinguish the two storage bits by utilizing the odd-even difference of the addresses of the control grid lines of the two storage bits of the storage unit 101, thereby realizing the fast programming test of the two storage bits and obtaining the corresponding control grid programming voltage and source programming voltage Vsp.

FIG. 3 is a flowchart of a method for trimming operating voltage of a flash memory according to an embodiment of the present invention; in the method for trimming the operating voltage of the flash memory according to the embodiment of the invention, the flash memory includes a plurality of memory cells 101, and the structure diagram of the memory cells 101 is also shown in fig. 1; each of the memory cells 101 employs a dual split gate floating gate 104 device.

In the method of the embodiment of the present invention, the dual-split gate floating gate 104 device is an N-type device, the first source drain region 205a and the second source drain region 205b are both composed of an n+ region, and the channel region is doped with P-type material. Other embodiments of the method can also be: the dual split gate floating gate 104 device is a P-type device, and the first source drain region 205a and the second source drain region 205b are both composed of p+ regions; the channel region is doped with N type.

The operating voltage trimming circuit includes:

The operating voltage trimming method comprises the following steps:

step one, performing a fast programming test on the first storage bits of the plurality of storage units 101 in the flash memory to obtain the first digital signal and the second digital signal when the first storage bits are programmed;

step two, performing a fast programming test on the second storage bits of the plurality of storage units 101 in the flash memory to obtain the first digital signal and the second digital signal when the second storage bits are programmed;

step one and step two make the setting of the source programming voltage Vsp and the control gate programming voltage at the time of programming the first memory bit independent of the setting of the source programming voltage Vsp and the control gate programming voltage at the time of programming the second memory bit, so as to eliminate the influence of the length deviation of the area sections of the channel region covered by the two first gate structures on the programming efficiency and thereby improve the programming efficiency of the first memory bit and the second memory bit simultaneously.

In the method of the embodiment of the invention, the operating voltage trimming circuit further comprises: a first data selector 303 and a second data selector 304.

The input end of the first data selector 303 is connected to a third digital signal and a fourth digital signal, the control end is connected to a selection signal, the output end outputs the first digital signal, and the first data signal is a signal selected from the third digital signal and the fourth digital signal. In fig. 2, the third digital signal is denoted by ft_vsp0< m:0>, and the fourth digital signal is denoted by ft_vsp1< m:0>. The select signal is represented by CGSEL.

The input end of the second data selector 304 is connected to a fifth digital signal and a sixth digital signal, the control end is connected to the selection signal, and the output end outputs the second digital signal, where the second data signal is a signal selected from the fifth digital signal and the sixth digital signal. In FIG. 2, the fifth digital signal is represented by FT_VCG0< m:0 >; the sixth digital signal is represented by FT_VCG1< m:0>.

The select signal causes the first data signal to select the third digital signal and the second digital signal to select the fifth digital signal when programming the first memory bit and when performing the fast programming test. As shown in fig. 3, steps S101a and S101b in fig. 3 correspond to step one, in step S101a, the selection signal is Set to 0, i.e., cgsel=0, at which time the first data signal selects the third digital signal, i.e., ft_vsp < m:0>, selects ft_vsp0< m:0>, the second digital signal selects the fifth digital signal, i.e., ft_vcg < m:0>, ft_vcg0< m:0>, the value of Vsp0/VCG0 is Set by ft_vsp0< m:0> and ft_vcg0< m:0>, and then the fast programming test, i.e., set Vsp0/vcg0 do fast program (cgsel=0), is performed. Judging whether the yield reaches the standard, namely, "yield=ok? If the yield does not reach the standard, then the FT_Vsp0< m:0> and FT_VCG0< m:0> need to be adjusted to adjust the value of Vsp0/VCG0, and the fast programming test is repeated. If the yield reaches the standard, i.e., yield=ok, step 101b is performed, and modified values of Vsp0/VCG0 and ft_vsp0< m:0> and ft_vcg0< m:0>, i.e., trim vsp0/vcg0 ft_vsp0< m:0> & ft_vcg0< m:0>, are obtained in step 101 b.

The select signal causes the first data signal to select the fourth digital signal and the second digital signal to select the sixth digital signal when programming the second memory bit and when performing the fast programming test. As shown in fig. 3, steps S102a and S102b in fig. 3 correspond to step S102a, wherein in step S102a, the selection signal is Set to 1, i.e., cgsel=1, at which time the first data signal selects the third digital signal, i.e., ft_vsp < m:0>, selects ft_vsp1< m:0>, the second digital signal selects the fifth digital signal, i.e., ft_vcg < m:0>, ft_vcg1< m:0>, the values of Vsp1/VCG1 are Set by ft_vsp1< m:0> and ft_vcg1< m:0>, and then the fast programming test, i.e., set Vsp1/vcg1 do fast program (cgsel=1), is performed. Judging whether the yield reaches the standard, namely, "yield=ok? If the yield does not reach the standard, then the FT_Vsp1< m:0> and FT_VCG1< m:0> need to be adjusted to adjust the value of Vsp1/VCG1, and the fast programming test is repeated. If the yield reaches the standard, i.e., yield=ok, step 102b is performed, and modified values of Vsp1/VCG1 and ft_vsp1< m:0> and ft_vcg1< m:0>, i.e., trim Vsp1/vcg1 ft_vsp1< m:0> & ft_vcg1< m:0>, are obtained in step 102 b.

In the method according to the embodiment of the present invention, in the flash memory, the first memory bit and the second memory bit of each of the memory cells 101 are distinguished by parity of an address of the control gate line.

The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims

1. The operating voltage trimming circuit of the flash memory is characterized in that the flash memory comprises a plurality of storage units; each storage unit adopts a double-split gate floating gate device;

the dual split gate floating gate device includes: the first source drain region and the second source drain region are symmetrically arranged, two separated first grid structures with floating gates are arranged between the first source drain region and the second source drain region, and the second grid structures are arranged between the first grid structures; the first grid structure is provided with a control grid positioned at the top of the floating gate;

a channel region is positioned between the first source drain region and the second source drain region and is covered by each first grid structure and each second grid structure, each first grid structure and each second grid structure respectively control the covered region section of the channel region, and the lengths of the region sections of the channel regions covered by the two first grid structures have deviation;

The control gate of each first gate structure is connected to a corresponding control gate line, and the first source drain region and the second source drain region are connected to corresponding bit lines; the floating gates of the two first gate structures respectively form a storage bit; when programming the selected storage bit, the control grid line corresponding to the storage bit is connected with a control grid programming voltage, and the bit line close to the storage bit is connected with a source programming voltage;

the storage bit close to the first source drain region is made to be a first storage bit, and the storage bit close to the second source drain region is made to be a second storage bit;

the operating voltage trimming circuit includes:

the control end of the first charge pump is connected with a multi-bit first digital signal, the output end of the charge pump outputs the source programming voltage, and the magnitude of the source programming voltage is controlled by the first digital signal;

the control end of the first charge pump is connected with a multi-bit second digital signal, the output end of the charge pump outputs the control gate programming voltage, and the magnitude of the source programming voltage is controlled by the second digital signal;

the first digital signal and the second digital signal are obtained by performing a fast programming test on the first storage bits of a plurality of storage units in the flash memory, and the first digital signal and the second digital signal are obtained by performing a fast programming test on the second storage bits of a plurality of storage units in the flash memory, so that the setting of the source programming voltage and the control gate programming voltage during the first storage bit programming is independent of the setting of the source programming voltage and the control gate programming voltage during the second storage bit programming, thereby eliminating the influence of the length deviation of the area sections of the channel areas covered by the two first gate structures on the programming efficiency and simultaneously improving the programming efficiency of the first storage bits and the second storage bits.

2. The operating voltage trimming circuit of the flash memory according to claim 1, wherein: the width of the two first gate structures is defined by lithography, and the length of the region section of the channel region covered by the two first gate structures has deviation caused by the lithography process.

3. The operating voltage trimming circuit of the flash memory according to claim 1, wherein: the operating voltage trimming circuit further includes: a first data selector and a second data selector;

the input end of the first data selector is connected with a third digital signal and a fourth digital signal, the control end of the first data selector is connected with a selection signal, the output end of the first data selector outputs the first digital signal, and the first data signal is a signal selected from the third digital signal and the fourth digital signal;

4. The operating voltage trimming circuit of the flash memory according to claim 3, wherein: the select signal causes the first data signal to select the third digital signal and the second digital signal to select the fifth digital signal when programming the first memory bit and when performing the fast programming test;

5. The operating voltage trimming circuit of the flash memory of claim 4, wherein: in the flash memory, the first memory bit and the second memory bit of each of the memory cells are distinguished by parity of an address of the control gate line.

6. The operating voltage trimming circuit of the flash memory of claim 5, wherein: in the fast programming test, programming test is carried out on the storage bits corresponding to the storage units at the same time.

7. The operating voltage trimming circuit of the flash memory of claim 6, wherein: when the fast programming test corresponding to the first storage bit is carried out, continuously adjusting the values of the third digital signal and the fifth digital signal in the test process to adjust the magnitudes of the source programming voltage and the control gate programming voltage until the yield meets the requirement;

8. The operating voltage trimming circuit of the flash memory according to claim 1, wherein: the double-split-gate floating gate device is an N-type device, the first source drain region and the second source drain region are both composed of an N+ region, and the channel region is doped with P type;

9. The operating voltage trimming method of the flash memory is characterized in that the flash memory comprises a plurality of storage units; each storage unit adopts a double-split gate floating gate device;

the operating voltage trimming circuit includes:

the operating voltage trimming method comprises the following steps:

Step one, performing a fast programming test on the first storage bits of a plurality of storage units in the flash memory to obtain the first digital signal and the second digital signal when the first storage bits are programmed;

performing a fast programming test on the second storage bits of the plurality of storage units in the flash memory to obtain the first digital signal and the second digital signal when the second storage bits are programmed;

10. The method for trimming the operating voltage of the flash memory according to claim 9, wherein: the width of the two first gate structures is defined by lithography, and the length of the region section of the channel region covered by the two first gate structures has deviation caused by the lithography process.

11. The method for trimming the operating voltage of the flash memory according to claim 9, wherein: the operating voltage trimming circuit further includes: a first data selector and a second data selector;

12. The method for trimming the operating voltage of the flash memory according to claim 11, wherein: the select signal causes the first data signal to select the third digital signal and the second digital signal to select the fifth digital signal when programming the first memory bit and when performing the fast programming test;

13. The method for trimming the operating voltage of the flash memory according to claim 12, wherein: in the flash memory, the first memory bit and the second memory bit of each of the memory cells are distinguished by parity of an address of the control gate line.

14. The method for trimming the operating voltage of the flash memory according to claim 13, wherein: in the fast programming test, programming test is carried out on the storage bits corresponding to the storage units at the same time.

15. The method for trimming the operating voltage of the flash memory according to claim 14, wherein: in the first step, when the fast programming test corresponding to the first storage bit is performed, continuously adjusting the values of the third digital signal and the fifth digital signal in the test process to adjust the magnitudes of the source programming voltage and the control gate programming voltage until the yield meets the requirement;

16. The method for trimming the operating voltage of the flash memory according to claim 9, wherein: the double-split-gate floating gate device is an N-type device, the first source drain region and the second source drain region are both composed of an N+ region, and the channel region is doped with P type;