CN116563419B - Correction method and device for wafer map configuration data, electronic equipment and storage medium - Google Patents
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Abstract
The application provides a method and a device for correcting wafer map configuration data, electronic equipment and a storage medium, wherein the method comprises the following steps: based on the type of the historical wafer and the test node, carrying out aggregation treatment on the historical chip test data corresponding to the historical wafer, and determining a historical chip test data set corresponding to the historical wafer; determining historical wafer map configuration data of a historical wafer based on a maximum abscissa value, a minimum abscissa value, a maximum ordinate value and a minimum ordinate value of a historical chip in a horizontal axis direction and a vertical axis direction under the historical chip test data set; and determining target wafer map configuration data of the target wafer consistent with the type of the historical wafer and the test node, and correcting the historical wafer map configuration data based on the target wafer map configuration data. And continuously correcting according to the configuration data of the target wafer map and the configuration data of the historical wafer map, so that the accuracy and the integrity of the configuration data of the wafer map are improved, and the wafer map is accurately drawn.
Description
Technical Field
The present application relates to the field of data processing, and in particular, to a method and apparatus for correcting wafer map configuration data, an electronic device, and a storage medium.
Background
In the semiconductor manufacturing process, wafer map is a basic data configuration file for describing the surface of a chip. At present, in the field of chip testing, the scene of drawing a wafer map is quite many, the wafer map is drawn depending on the metadata of the wafer map, the existing method is to manually configure the metadata related to the wafer map on a page before data storage, and the method for manually configuring has the following problems: the configuration information of the wafer map is not contained in the data before the data is stored, and the correct wafer map is not drawn when the page is analyzed; manual operation errors can also cause incorrect drawing of wafer maps; relying on manual labor increases labor cost, and the wafer map configuration data is static and cannot be updated in real time according to actual conditions. Therefore, when new process or design changes occur, the wafer map configuration data needs to be reconfigured, increasing production cost and workload. Therefore, how to improve the accuracy and integrity of the wafer map configuration data becomes a non-trivial technical problem.
Disclosure of Invention
Accordingly, the present application is directed to a method, an apparatus, an electronic device, and a storage medium for correcting wafer map configuration data, which can continuously correct the wafer map configuration data according to the target wafer map configuration data and the history wafer map configuration data of new test data through entering a system continuously with the lapse of time, thereby improving the accuracy and the integrity of the configuration data of the wafer map, and ensuring the accurate drawing of the wafer map.
The embodiment of the application provides a correction method of wafer map configuration data, which comprises the following steps:
based on the type of the historical wafer and the test node, carrying out aggregation treatment on a plurality of historical chip test data corresponding to the historical wafer, and determining a historical chip test data set corresponding to the historical wafer;
determining historical wafer map configuration data of the historical wafer based on a maximum abscissa value, a minimum abscissa value, a maximum ordinate value and a minimum ordinate value of the historical chip in the horizontal axis direction and the vertical axis direction under the historical chip test data set; the historical wafer map configuration data comprises historical wafer center positions and historical wafer radiuses;
And determining target wafer map configuration data of a target wafer consistent with the type of the historical wafer and the test node, and correcting the historical wafer map configuration data based on the target wafer map configuration data.
In one possible implementation manner, for the historical wafer center position, the determining the historical wafer map configuration data of the historical wafer based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value of the historical chip in the horizontal axis direction under the historical chip test data set includes:
determining a historical height scale value and a historical width scale value of the historical chip test data set based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value;
and determining the historical wafer center position in the historical wafer map configuration data based on the historical height scale value, the historical width scale value, the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value.
In one possible implementation manner, the determining the historical height scale value and the historical width scale value of the historical chip test data set based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value includes:
subtracting the minimum abscissa value from the maximum abscissa value to determine a first difference;
subtracting the minimum ordinate value from the maximum ordinate value to determine a second difference;
determining a ratio between the historical width scale value and the historical height scale value based on a ratio of the second difference value to the first difference value; wherein the historical width scale value is 1;
and determining the historical height scale value based on the ratio between the historical width scale value and the historical height scale value and the historical width scale value.
In one possible implementation, the determining the historical wafer center position in the historical wafer map configuration data based on the historical altitude scale value, the historical width scale value, the maximum abscissa value, the minimum abscissa value, the maximum ordinate value, and the minimum ordinate value includes:
Adding the minimum abscissa value and a first target value to determine a first sum value, subtracting the first sum value from the maximum abscissa value, and determining a third difference value;
multiplying the third difference value by the historical width scale value to determine a first product, dividing the first product by a second target value, and determining an abscissa value of the historical wafer center position;
adding the minimum ordinate value and the first target value to determine a second sum value, subtracting the second sum value from the maximum ordinate value, and determining a fourth difference value;
multiplying the fourth difference value by the historical height scale value to determine a second product, dividing the second product by the second target value, and determining an ordinate value of the historical wafer center position; wherein the first target value is 1 and the second target value is 2.
In one possible implementation, for the historical wafer radius, the determining the historical wafer map configuration data of the historical wafer based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value, and the minimum ordinate value of the historical chip in the horizontal axis direction under the historical chip test data set includes:
Determining coordinates of corner points of a plurality of edge historical chips in the historical chip test data set;
determining the relative distance from the coordinates of the corner points of each edge history chip to the center position of the history wafer according to Pythagorean theorem;
and screening out the maximum relative distance from the plurality of relative distances, and determining the maximum relative distance as the historical wafer radius in the historical wafer map configuration data.
In one possible implementation, the historical wafer map configuration data further includes a historical notch direction, the historical notch direction being determined by:
determining the notch direction of each historical chip in the historical chip test data set; wherein the slot direction includes an upper slot direction, a lower slot direction, a left Fang Caokou direction, and a right slot direction;
and determining the notch direction corresponding to the most historical chips as the historical notch direction of the historical wafer.
In one possible implementation, the modifying the historical wafer map configuration data based on the target wafer map configuration data includes:
correcting the historical wafer center position based on the target wafer center position in the target wafer map configuration data;
And correcting the historical wafer radius based on the target wafer radius in the target wafer map configuration data.
The embodiment of the application also provides a device for correcting the wafer map configuration data, which comprises:
the aggregation module is used for carrying out aggregation processing on a plurality of historical chip test data corresponding to the historical wafer based on the type of the historical wafer and the test node, and determining a historical chip test data set corresponding to the historical wafer;
the determining module is used for determining historical wafer map configuration data of the historical wafer based on a maximum abscissa value, a minimum abscissa value, a maximum ordinate value and a minimum ordinate value of the historical chip in the horizontal axis direction and the vertical axis direction under the historical chip test data set; the historical wafer map configuration data comprises historical wafer center positions and historical wafer radiuses;
and the adjustment module is used for determining target wafer map configuration data of the target wafer consistent with the type of the historical wafer and the test node, and correcting the historical wafer map configuration data based on the target wafer map configuration data.
The embodiment of the application also provides electronic equipment, which comprises: the system comprises a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, the processor and the memory are communicated through the bus when the electronic device runs, and the machine-readable instructions are executed by the processor to execute the steps of the wafer map configuration data correction method.
The embodiment of the application also provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to execute the steps of the wafer map configuration data correction method.
The embodiment of the application provides a correction method, a correction device, electronic equipment and a storage medium for wafer map configuration data, wherein the correction method comprises the following steps: based on the type of the historical wafer and the test node, carrying out aggregation treatment on a plurality of historical chip test data corresponding to the historical wafer, and determining a historical chip test data set corresponding to the historical wafer; determining historical wafer map configuration data of the historical wafer based on a maximum abscissa value, a minimum abscissa value, a maximum ordinate value and a minimum ordinate value of the historical chip in the horizontal axis direction and the vertical axis direction under the historical chip test data set; the historical wafer map configuration data comprises historical wafer center positions and historical wafer radiuses; and determining target wafer map configuration data of a target wafer consistent with the type of the historical wafer and the test node, and correcting the historical wafer map configuration data based on the target wafer map configuration data. Through the continuous entering of test data along with the time, the configuration data of the target wafer map and the configuration data of the historical wafer map of the newly obtained test data can be subjected to continuous correction, so that the accuracy and the integrity of the configuration data of the wafer map are improved, and the wafer map is accurately drawn.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for correcting wafer map configuration data according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a device for correcting wafer map configuration data according to an embodiment of the present application;
FIG. 3 is a second schematic diagram of a device for correcting wafer map configuration data according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for the purpose of illustration and description only and are not intended to limit the scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this disclosure, illustrates operations implemented according to some embodiments of the present application. It should be appreciated that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to or removed from the flow diagrams by those skilled in the art under the direction of the present disclosure.
In addition, the described embodiments are only some, but not all, embodiments of the application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art based on embodiments of the application without making any inventive effort, fall within the scope of the application.
In order to enable those skilled in the art to make and use the present disclosure, the following embodiments are provided in connection with a particular application scenario "modify wafer map configuration data", and the general principles defined herein may be applied to other embodiments and application scenarios without departing from the spirit and scope of the present disclosure.
The method, the device, the electronic equipment or the computer readable storage medium can be applied to any scene needing to correct the wafer map configuration data, the embodiment of the application is not limited to specific application scenes, and any scheme using the method, the device, the electronic equipment and the storage medium for correcting the wafer map configuration data provided by the embodiment of the application is within the protection scope of the application.
First, an application scenario to which the present application is applicable will be described. The application can be applied to the technical field of data processing.
It was found that wafer map is a basic data profile used to describe the chip surface during semiconductor fabrication. At present, in the field of chip testing, the scene of drawing a wafer map is quite many, the wafer map is drawn depending on the metadata of the wafer map, the existing method is to manually configure the metadata related to the wafer map on a page before data storage, and the method for manually configuring has the following problems: the configuration information of the wafer map is not contained in the data before the data is stored, and the correct wafer map is not drawn when the page is analyzed; manual operation errors can also cause incorrect drawing of wafer maps; relying on manual labor increases labor cost, and the wafer map configuration data is static and cannot be updated in real time according to actual conditions. Therefore, when new process or design changes occur, the wafer map configuration data needs to be reconfigured, increasing production cost and workload. Therefore, how to improve the accuracy and integrity of the wafer map configuration data becomes a non-trivial technical problem.
Based on the above, the embodiment of the application provides a correction method for wafer map configuration data, which can continuously correct the target wafer map configuration data and the historical wafer map configuration data of new obtained test data through continuously entering a system along with the time, thereby improving the accuracy and the integrity of the configuration data of the wafer map and ensuring that the wafer map is accurately drawn.
Referring to fig. 1, fig. 1 is a flowchart of a method for correcting wafer map configuration data according to an embodiment of the application. As shown in fig. 1, the correction method provided by the embodiment of the application includes:
s101: and based on the type of the historical wafer and the aggregation processing of the plurality of historical chip test data corresponding to the historical wafer by the test node, determining a historical chip test data set corresponding to the historical wafer.
In the step, according to the type of the historical wafer and the test node, aggregation processing is carried out on a plurality of historical chip test data corresponding to the historical wafer, and a historical chip test data set corresponding to the historical wafer is determined.
The method comprises the steps of storing historical chip test data in an stdf file, analyzing the historical chip test data in the stdf file, storing the historical chip test data in hdfs, preprocessing historical chip test original data stored in the hdfs, processing other data including data cleaning, data deduplication, data normalization, flying spot elimination and the like, and carrying out dimension aggregation on the plurality of historical chip test data after data processing by a distributed computing component according to the type of the historical wafer and a test node to obtain a historical chip test data set.
S102: and determining the historical wafer map configuration data of the historical wafer based on the maximum abscissa value, the minimum abscissa value and the maximum ordinate value and the minimum ordinate value of the historical chip in the horizontal axis direction and the vertical axis direction under the historical chip test data set.
In the step, the historical wafer map configuration data of the historical wafer is determined according to the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value of the historical chip in the horizontal axis direction and the maximum ordinate value and the minimum ordinate value in the vertical axis direction under the historical chip test data set.
Here, the maximum abscissa value, the minimum abscissa value, and the maximum ordinate value and the minimum ordinate value of the history chip in the horizontal axis (X axis) direction, and the maximum ordinate value and the minimum ordinate value in the vertical axis (Y axis) direction are determined by testing the history chip.
In one possible implementation manner, for the historical wafer center position, the determining the historical wafer map configuration data of the historical wafer based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value of the historical chip in the horizontal axis direction under the historical chip test data set includes:
A: and determining a historical height scale value and a historical width scale value of the historical chip test data set based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value.
Here, the historical height scale value and the historical width scale value of the historical chip test data set are determined based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value, and the minimum ordinate value.
The historical height scale value and the historical width scale value are not the actual height and width of the historical chip, but the proportional relation of the height and the width of the historical chip.
In one possible implementation manner, the determining the historical height scale value and the historical width scale value of the historical chip test data set based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value includes:
a: subtracting the minimum abscissa value from the maximum abscissa value to determine a first difference; and subtracting the minimum ordinate value from the maximum ordinate value to determine a second difference.
Here, subtracting the minimum abscissa value from the maximum abscissa value to determine a first difference; and subtracting the minimum ordinate value from the maximum ordinate value to determine a second difference.
b: determining a ratio between the historical width scale value and the historical height scale value based on a ratio of the second difference value to the first difference value; wherein the historical width scale value is 1.
Here, a ratio between the historical width scale value and the historical height scale value is determined according to a ratio of the second difference value to the first difference value.
c: and determining the historical height scale value based on the ratio between the historical width scale value and the historical height scale value and the historical width scale value.
Here, the historical height scale value is determined from the ratio between the historical width scale value and the historical height scale value and the historical width scale value.
Wherein, the historical altitude scale value is determined by the following formula:
wherein, the liquid crystal display device comprises a liquid crystal display device,maxYfor the maximum value of the ordinate,minYfor the minimum value of the ordinate,maxXfor the maximum value of the abscissa of the values,minXfor the minimum value of the abscissa value,DieWidthfor the historical width scale value,DieHeightis a historical altitude scale value.
B: and determining the historical wafer center position in the historical wafer map configuration data based on the historical height scale value, the historical width scale value, the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value.
Here, the historical wafer center position in the historical wafer map configuration data is determined based on the historical height scale value, the historical width scale value, the maximum abscissa value, the minimum abscissa value, the maximum ordinate value, and the minimum ordinate value.
In one possible implementation, the determining the historical wafer center position in the historical wafer map configuration data based on the historical height scale value, the historical width scale value, the maximum abscissa value, the minimum abscissa value, the maximum ordinate value, and the minimum ordinate value includes:
(1): and adding the minimum abscissa value and a first target value to determine a first sum value, subtracting the first sum value from the maximum abscissa value, and determining a third difference value.
Here, the minimum abscissa value is added to the first target value, a first sum value is determined, and the maximum abscissa value is subtracted from the first sum value, and a third difference value is determined.
(2): and multiplying the third difference value by the historical width scale value to determine a first product, dividing the first product by a second target value, and determining the abscissa value of the historical wafer center position.
Here, the third difference value is multiplied by the historical width scale value to determine a first product, and the first product is divided by the second target value to determine an abscissa value of the historical wafer center position.
(3): and adding the minimum ordinate value and the first target value to determine a second sum value, subtracting the second sum value from the maximum ordinate value, and determining a fourth difference value.
Here, the minimum ordinate value is added to the first target value, a second sum value is determined, and the maximum ordinate value is subtracted from the second sum value, and a fourth difference value is determined.
Here, the historical wafer center position is determined by the following formula:
wherein, the liquid crystal display device comprises a liquid crystal display device,maxYfor the maximum value of the ordinate,minYfor the minimum value of the ordinate,maxXfor the maximum value of the abscissa of the values,minXfor the minimum value of the abscissa value,DieWidthfor the historical width scale value,DieHeightfor the historical altitude scale value,circleYis the ordinate of the historical wafer center position,circleXis the abscissa of the historical wafer center position.
In one possible implementation, for the historical wafer radius, the determining the historical wafer map configuration data of the historical wafer based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value, and the minimum ordinate value of the historical chip in the horizontal axis direction under the historical chip test data set includes:
I: and determining coordinates of corner points of a plurality of edge historical chips in the historical chip test data set.
Here, coordinates of corner points of a plurality of edge history chips among the history chip test data set are determined by chip test.
The shape of the history chip is rectangular, and the edge history chip is the history chip of the outermost test on the history wafer.
II: and determining the relative distance from the coordinates of the corner points of each edge history chip to the center position of the history wafer according to the Pythagorean theorem.
Here, the relative distance from the coordinates of the corner points of each edge history chip to the center position of the history wafer is determined according to the pythagorean theorem.
Here, there are one corner of the edge history chip, which is left upper, left lower, right upper and right lower, and assuming that the coordinate of one die is x, the coordinate of the left upper is (x-0.5, y+0.5), and the other corner is analogized.
Here, the relative distance from the coordinates of the corner points of the edge history chip to the center position of the history wafer is determined by the following formula:
wherein, the liquid crystal display device comprises a liquid crystal display device,cornerXis the abscissa of the corner points of the edge history chip,cornerYis the ordinate of the corner point of the edge history chip,circleYis the ordinate of the historical wafer center position, circleXIs the abscissa of the historical wafer center position,circleRadiusis the relative distance.
III: and screening out the maximum relative distance from the plurality of relative distances, and determining the maximum relative distance as the historical wafer radius in the historical wafer map configuration data.
Here, a maximum relative distance is selected from among the plurality of relative distances, and the maximum relative distance is determined as a historical wafer radius among the historical wafer map configuration data.
In one possible implementation, the historical wafer map configuration data further includes a historical notch direction, the historical notch direction being determined by:
i: determining the notch direction of each historical chip in the historical chip test data set; wherein the slot direction includes an upper slot direction, a lower slot direction, a left Fang Caokou direction, and a right slot direction.
Here, the notch direction of each historical chip in the historical chip test data set is counted.
ii: and determining the notch direction corresponding to the most historical chips as the historical notch direction of the historical wafer.
Here, the notch direction corresponding to the most history chip is determined as the history notch direction of the history wafer.
Wherein, the historical wafer map configuration data is written into hdfs and mysql, the historical wafer map configuration data stored by hdfs is used as continuous calculation correction, and the program stored by mysql and provided for drawing wafer map is used as configuration data, so that the wafer map can be accurately drawn.
S103: and determining target wafer map configuration data of a target wafer consistent with the type of the historical wafer and the test node, and correcting the historical wafer map configuration data based on the target wafer map configuration data.
In the step, the target wafer map configuration data of the target wafer consistent with the type of the historical wafer and the testing node is determined, and the historical wafer map configuration data is corrected according to the target wafer map configuration data.
Here, the determining process of the target wafer map configuration data is consistent with the determining process of the historical wafer map configuration data, and this part will not be described in detail.
The test data continuously enter the system along with the time, the historical wafer map configuration data stored in the hdfs can be corrected based on the target wafer map configuration data of the new test data, and the purpose of the historical wafer map configuration data in the steps is to use an incremental calculation method to ensure that calculated data is not recalculated, so that the calculation performance is greatly improved.
In one possible implementation, the modifying the historical wafer map configuration data based on the target wafer map configuration data includes:
correcting the historical wafer center position based on the target wafer center position in the target wafer map configuration data; and correcting the historical wafer radius based on the target wafer radius in the target wafer map configuration data.
Here, the historical wafer center position is corrected according to the target wafer center position in the target wafer map configuration data; and correcting the historical wafer radius according to the target wafer radius in the target wafer map configuration data.
The historical notch direction can be corrected according to the target notch direction in the target wafer map configuration data.
In a specific embodiment, the historical chip test data is derived from an stdf file, the data of the stdf file is analyzed and stored on hdfs, and the chip test original data stored on the hdfs is preprocessed, including data cleaning, data deduplication, data normalization, flying spot elimination and the like. And aggregating the plurality of historical chip test data by using the distributed computing assembly and taking the type of the historical wafer and the test node as dimension aggregation, so as to obtain a historical chip test data set. And determining corresponding historical wafer map configuration data according to the historical chip test data set, writing the historical wafer map configuration data calculated in the steps into hdfs and mysql, wherein the historical wafer map configuration data stored in the hdfs is used as continuous calculation correction, and the historical wafer map configuration data stored in the mysql is provided for a program drawing a wafer map as configuration data.
The embodiment of the application provides a correction method of wafer map configuration data, which comprises the following steps: based on the type of the historical wafer and the test node, carrying out aggregation treatment on a plurality of historical chip test data corresponding to the historical wafer, and determining a historical chip test data set corresponding to the historical wafer; determining historical wafer map configuration data of the historical wafer based on a maximum abscissa value, a minimum abscissa value, a maximum ordinate value and a minimum ordinate value of the historical chip in the horizontal axis direction and the vertical axis direction under the historical chip test data set; the historical wafer map configuration data comprises historical wafer center positions and historical wafer radiuses; and determining target wafer map configuration data of a target wafer consistent with the type of the historical wafer and the test node, and correcting the historical wafer map configuration data based on the target wafer map configuration data. Through the continuous entering of test data along with the time, the configuration data of the target wafer map and the configuration data of the historical wafer map of the newly obtained test data can be subjected to continuous correction, so that the accuracy and the integrity of the configuration data of the wafer map are improved, and the wafer map is accurately drawn.
Referring to fig. 2 and 3, fig. 2 is a schematic structural diagram of a device for correcting wafer map configuration data according to an embodiment of the application; fig. 3 is a second schematic structural diagram of a device for correcting wafer map configuration data according to an embodiment of the present application. As shown in fig. 2, the correction device 200 of wafer map configuration data includes:
an aggregation module 210, configured to aggregate a plurality of historical chip test data corresponding to a historical wafer based on a type of the historical wafer and a test node, and determine a historical chip test data set corresponding to the historical wafer;
a determining module 220, configured to determine historical wafer map configuration data of the historical wafer based on a maximum abscissa value, a minimum abscissa value, a maximum ordinate value and a minimum ordinate value of the historical chip in the horizontal axis direction, and the vertical axis direction; the historical wafer map configuration data comprises historical wafer center positions and historical wafer radiuses;
and the adjustment module 230 is configured to determine target wafer map configuration data of a target wafer consistent with the type of the historical wafer and the test node, and correct the historical wafer map configuration data based on the target wafer map configuration data.
Further, when the determining module 220 is configured to determine, for the historical wafer center position of the historical wafer, the historical wafer map configuration data of the historical wafer based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value of the historical chip in the historical chip test data set in the horizontal axis direction, the maximum ordinate value and the minimum ordinate value in the vertical axis direction, the determining module 220 is specifically configured to:
determining a historical height scale value and a historical width scale value of the historical chip test data set based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value;
and determining the historical wafer center position in the historical wafer map configuration data based on the historical height scale value, the historical width scale value, the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value.
Further, when the determining module 220 is configured to determine the historical altitude scale value and the historical width scale value of the historical chip test data set based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value, the determining module 220 is specifically configured to:
Subtracting the minimum abscissa value from the maximum abscissa value to determine a first difference;
subtracting the minimum ordinate value from the maximum ordinate value to determine a second difference;
determining a ratio between the historical width scale value and the historical height scale value based on a ratio of the second difference value to the first difference value; wherein the historical width scale value is 1;
and determining the historical height scale value based on the ratio between the historical width scale value and the historical height scale value and the historical width scale value.
Further, when the determining module 220 is configured to determine the historical wafer center position in the historical wafer map configuration data based on the historical altitude scale value, the historical width scale value, the maximum abscissa value, the minimum abscissa value, the maximum ordinate value, and the minimum ordinate value, the determining module 220 is specifically configured to:
adding the minimum abscissa value and a first target value to determine a first sum value, subtracting the first sum value from the maximum abscissa value, and determining a third difference value;
multiplying the third difference value by the historical width scale value to determine a first product, dividing the first product by a second target value, and determining an abscissa value of the historical wafer center position;
Adding the minimum ordinate value and the first target value to determine a second sum value, subtracting the second sum value from the maximum ordinate value, and determining a fourth difference value;
multiplying the fourth difference value by the historical height scale value to determine a second product, dividing the second product by the second target value, and determining an ordinate value of the historical wafer center position; wherein the first target value is 1 and the second target value is 2.
Further, when the determining module 220 is configured to determine, for the radius of the historical wafer, the historical wafer map configuration data of the historical wafer based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value of the historical chip in the historical chip test data set in the horizontal axis direction, the maximum ordinate value and the minimum ordinate value in the vertical axis direction, the determining module 220 is specifically configured to:
determining coordinates of corner points of a plurality of edge historical chips in the historical chip test data set;
determining the relative distance from the coordinates of the corner points of each edge history chip to the center position of the history wafer according to Pythagorean theorem;
And screening out the maximum relative distance from the plurality of relative distances, and determining the maximum relative distance as the historical wafer radius in the historical wafer map configuration data.
Further, as shown in fig. 3, the correction device 200 further includes a notch direction determining module 240, where the notch direction determining module 240 determines the historical notch direction by:
determining the notch direction of each historical chip in the historical chip test data set; wherein the slot direction includes an upper slot direction, a lower slot direction, a left Fang Caokou direction, and a right slot direction;
and determining the notch direction corresponding to the most historical chips as the historical notch direction of the historical wafer.
Further, when the adjusting module 230 is configured to correct the historical wafer map configuration data based on the target wafer map configuration data, the adjusting module 230 is specifically configured to:
correcting the historical wafer center position based on the target wafer center position in the target wafer map configuration data;
and correcting the historical wafer radius based on the target wafer radius in the target wafer map configuration data.
The embodiment of the application provides a correction device for wafer map configuration data, which comprises: the aggregation module is used for carrying out aggregation processing on a plurality of historical chip test data corresponding to the historical wafer based on the type of the historical wafer and the test node, and determining a historical chip test data set corresponding to the historical wafer; the determining module is used for determining historical wafer map configuration data of the historical wafer based on a maximum abscissa value, a minimum abscissa value, a maximum ordinate value and a minimum ordinate value of the historical chip in the horizontal axis direction and the vertical axis direction under the historical chip test data set; the historical wafer map configuration data comprises historical wafer center positions and historical wafer radiuses; and the adjustment module is used for determining target wafer map configuration data of the target wafer consistent with the type of the historical wafer and the test node, and correcting the historical wafer map configuration data based on the target wafer map configuration data. Through the continuous entering of test data along with the time, the configuration data of the target wafer map and the configuration data of the historical wafer map of the newly obtained test data can be subjected to continuous correction, so that the accuracy and the integrity of the configuration data of the wafer map are improved, and the wafer map is accurately drawn.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the application. As shown in fig. 4, the electronic device 400 includes a processor 410, a memory 420, and a bus 430.
The memory 420 stores machine-readable instructions executable by the processor 410, when the electronic device 400 is running, the processor 410 communicates with the memory 420 through the bus 430, and when the machine-readable instructions are executed by the processor 410, the steps of the method for correcting wafer map configuration data in the method embodiment shown in fig. 1 can be executed, and detailed description of the method embodiment will be omitted.
The embodiment of the present application further provides a computer readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the method for correcting wafer map configuration data in the method embodiment shown in fig. 1 may be executed, and a specific implementation manner may refer to the method embodiment and will not be described herein.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Finally, it should be noted that: the above examples are only specific embodiments of the present application, and are not intended to limit the scope of the present application, but it should be understood by those skilled in the art that the present application is not limited thereto, and that the present application is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A method for correcting wafer map configuration data, the method comprising:
based on the type of the historical wafer and the test node, carrying out aggregation treatment on a plurality of historical chip test data corresponding to the historical wafer, and determining a historical chip test data set corresponding to the historical wafer;
determining historical wafer map configuration data of the historical wafer based on a maximum abscissa value, a minimum abscissa value, a historical height scale value, a historical width scale value, a maximum ordinate value and a minimum ordinate value of the historical chip in the horizontal axis direction under the historical chip test data set; the historical wafer map configuration data comprises historical wafer center positions and historical wafer radiuses; the historical height scale value and the historical width scale value are proportional relations between the height and the width of the historical chip;
and determining target wafer map configuration data of a target wafer consistent with the type of the historical wafer and the test node, and correcting the historical wafer map configuration data based on the target wafer map configuration data.
2. The method of claim 1, wherein determining the historical wafer map configuration data for the historical wafer based on the maximum abscissa value, the minimum abscissa value, the historical height scale value, the historical width scale value, the maximum ordinate value, and the minimum ordinate value of the historical chip in the historical chip test data set in the horizontal axis direction with respect to the historical wafer center position comprises:
Determining a historical height scale value and a historical width scale value of the historical chip test data set based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value;
and determining the historical wafer center position in the historical wafer map configuration data based on the historical height scale value, the historical width scale value, the maximum abscissa value, the minimum abscissa value, the maximum ordinate value and the minimum ordinate value.
3. The correction method as claimed in claim 2, wherein said determining the historical height scale value and the historical width scale value of the historical chip test data set based on the maximum abscissa value, the minimum abscissa value, the maximum ordinate value, and the minimum ordinate value comprises:
subtracting the minimum abscissa value from the maximum abscissa value to determine a first difference;
subtracting the minimum ordinate value from the maximum ordinate value to determine a second difference;
determining a ratio between the historical width scale value and the historical height scale value based on a ratio of the second difference value to the first difference value; wherein the historical width scale value is 1;
And determining the historical height scale value based on the ratio between the historical width scale value and the historical height scale value and the historical width scale value.
4. The method of claim 2, wherein determining the historical wafer center location in the historical wafer map configuration data based on the historical height scale value, the historical width scale value, the maximum abscissa value, the minimum abscissa value, the maximum ordinate value, and the minimum ordinate value comprises:
adding the minimum abscissa value and a first target value to determine a first sum value, subtracting the first sum value from the maximum abscissa value, and determining a third difference value;
multiplying the third difference value by the historical width scale value to determine a first product, dividing the first product by a second target value, and determining an abscissa value of the historical wafer center position;
adding the minimum ordinate value and the first target value to determine a second sum value, subtracting the second sum value from the maximum ordinate value, and determining a fourth difference value;
multiplying the fourth difference value by the historical height scale value to determine a second product, dividing the second product by the second target value, and determining an ordinate value of the historical wafer center position; wherein the first target value is 1 and the second target value is 2.
5. The method of claim 1, wherein determining historical wafer map configuration data for the historical wafer based on a maximum abscissa value, a minimum abscissa value, a historical height scale value, a historical width scale value, a maximum ordinate value, and a minimum ordinate value of the historical chips in the historical chip test data set in a horizontal axis direction with respect to the historical wafer radius comprises:
determining coordinates of corner points of a plurality of edge historical chips in the historical chip test data set;
determining the relative distance from the coordinates of the corner points of each edge history chip to the center position of the history wafer according to Pythagorean theorem;
and screening out the maximum relative distance from the plurality of relative distances, and determining the maximum relative distance as the historical wafer radius in the historical wafer map configuration data.
6. The method of claim 1, wherein the historical wafer map configuration data further includes a historical notch direction, the historical notch direction being determined by:
determining the notch direction of each historical chip in the historical chip test data set; wherein the slot direction includes an upper slot direction, a lower slot direction, a left Fang Caokou direction, and a right slot direction;
And determining the notch direction corresponding to the most historical chips as the historical notch direction of the historical wafer.
7. The correction method as set forth in claim 1, wherein said correcting said historical wafer map configuration data based on said target wafer map configuration data includes:
correcting the historical wafer center position based on the target wafer center position in the target wafer map configuration data;
and correcting the historical wafer radius based on the target wafer radius in the target wafer map configuration data.
8. A correction device for wafer map configuration data, the correction device comprising:
the aggregation module is used for carrying out aggregation processing on a plurality of historical chip test data corresponding to the historical wafer based on the type of the historical wafer and the test node, and determining a historical chip test data set corresponding to the historical wafer;
the determining module is used for determining historical wafer map configuration data of the historical wafer based on a maximum abscissa value, a minimum abscissa value, a historical height scale value, a historical width scale value, a maximum ordinate value and a minimum ordinate value of the historical chip in the horizontal axis direction under the historical chip test data set; the historical wafer map configuration data comprises historical wafer center positions and historical wafer radiuses;
And the adjustment module is used for determining target wafer map configuration data of the target wafer consistent with the type of the historical wafer and the test node, and correcting the historical wafer map configuration data based on the target wafer map configuration data.
9. An electronic device, comprising: a processor, a memory and a bus, said memory storing machine readable instructions executable by said processor, said processor and said memory communicating via said bus when the electronic device is running, said machine readable instructions when executed by said processor performing the steps of the wafer map configuration data modification method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of the method for correcting wafer map configuration data according to any one of claims 1 to 7.
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