CN116562221A - Method, device, equipment and storage medium for marking printed circuit board - Google Patents

Method, device, equipment and storage medium for marking printed circuit board Download PDF

Info

Publication number
CN116562221A
CN116562221A CN202310664176.6A CN202310664176A CN116562221A CN 116562221 A CN116562221 A CN 116562221A CN 202310664176 A CN202310664176 A CN 202310664176A CN 116562221 A CN116562221 A CN 116562221A
Authority
CN
China
Prior art keywords
target
contour
layer
information
marking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310664176.6A
Other languages
Chinese (zh)
Inventor
张定农
张世杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Inspur Intelligent Technology Co Ltd
Original Assignee
Suzhou Inspur Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Inspur Intelligent Technology Co Ltd filed Critical Suzhou Inspur Intelligent Technology Co Ltd
Priority to CN202310664176.6A priority Critical patent/CN116562221A/en
Publication of CN116562221A publication Critical patent/CN116562221A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/31—Design entry, e.g. editors specifically adapted for circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/30—Computing systems specially adapted for manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

The invention relates to the technical field of integrated circuits, and discloses a method, a device, equipment and a storage medium for marking a printed circuit board, wherein the method comprises the following steps: acquiring a contour layer corresponding to a target plate in a printed circuit board; the contour layer comprises at least two layers; determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate, and performing size marking on the target contour based on the coordinate information acquired by the sampling points; displaying the size mark of the target outline on a target interface, and writing the information to be marked into an outline layer; the method can improve the accuracy and efficiency of dimension marking of the target contour and provide guarantee for normal operation, smooth manufacture, cost saving and system stability of the printed circuit board.

Description

Method, device, equipment and storage medium for marking printed circuit board
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a method, an apparatus, a device, and a storage medium for marking a printed circuit board.
Background
Because the layout is continuously changed during the printed circuit board process, if the external frame layer needs to be modified due to key devices or other limitations, engineers are required to correct the boundary design specifications (the part forbidden region and the routing forbidden region) of the shape of the printed circuit board, and the layout of the connection board diagram is also included. At the moment, the engineer is required to manually select the instructions one by one and then use the right button of the mouse to match with the selection instructions to achieve the function of marking the size, and meanwhile, the corresponding marking information is required to be manually input, so that the reworking time of the engineer in the research and development process is increased, and the problem of omission is easy to occur.
Disclosure of Invention
In view of this, the invention provides a method, a device and a storage medium for marking a printed circuit board, which are used for solving the problems that in the process of changing the outline of the existing printed circuit board, an engineer is required to manually select instructions one by one and then use a right button of a mouse to cooperate with the selected instructions to achieve the function of marking the size, and meanwhile, corresponding marking information is required to be manually operated, so that the reworking time of the engineer in the research and development process is increased, and omission is easy to occur.
In a first aspect, the present invention provides a method for marking a printed circuit board, the method comprising: acquiring a contour layer corresponding to a target plate in a printed circuit board; the contour layer comprises at least two layers; determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate, and performing size marking on the target contour based on the coordinate information acquired by the sampling points; and displaying the size mark of the target outline on a target interface, and writing the information to be marked into the outline layer. Through the process, the accuracy and the efficiency of the dimension marking of the single board and the connecting board can be improved, and the guarantee is provided for the normal operation, smooth manufacturing, cost saving and system stability of the printed circuit board.
In an alternative embodiment, determining sampling points for a target contour in a contour layer includes:
taking the inflection point of the target contour as a sampling point;
and/or taking two endpoints of any side of the target contour as sampling points.
In an alternative embodiment, sizing the target contour based on the coordinate information collected by the sampling points includes:
according to the coordinate values of the coordinates in the coordinate information, determining the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate;
calculating the maximum side length and the maximum side width according to the maximum value and the minimum value of the abscissa and the maximum value and the minimum value of the ordinate;
and (5) dimensioning the target contour according to the maximum side length and the maximum side width.
In an alternative embodiment, sizing the target outline on the target interface includes:
acquiring a dimension mark of a target outline;
uploading the dimension label of the target outline to the corresponding position of the target interface for display.
In an alternative embodiment, writing the information to be marked to the contour layer includes:
acquiring the information type of the information to be marked;
And determining the contour layer corresponding to the information to be marked according to the information type, and writing the information to be marked into the contour layer.
In an alternative embodiment, after writing the information to be marked into the contour layer, the method further includes:
acquiring a target position of information to be marked on a target contour;
and marking the information to be marked at the target position.
In an alternative embodiment, the target contours and dimensions of one of the contour layers are marked and imported into another layer or layers that are different from the target contours.
In a second aspect, the present invention provides an apparatus for marking a printed circuit board according to an embodiment of the present invention, the apparatus mainly includes: the device comprises a contour acquisition module, a contour marking module and an information display module; the contour acquisition module is used for acquiring a contour layer corresponding to a target plate in the printed circuit board; the profile layer comprises at least two layers; the contour labeling module is used for determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate and labeling the size of the target contour based on the coordinate information acquired by the sampling points; the information display module is used for displaying the dimension mark of the target outline on the target interface and writing the information to be marked into the outline layer. Through the process, the accuracy and the efficiency of the dimension marking of the single board and the connecting board can be improved, and the guarantee is provided for the normal operation, smooth manufacturing, cost saving and system stability of the printed circuit board.
In a third aspect, the present invention provides a computer device comprising: the processor executes the computer instructions, thereby executing the marking method of the printed circuit board according to the first aspect or any corresponding implementation mode thereof.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to execute the method for marking a printed circuit board according to the first aspect or any one of the embodiments corresponding thereto.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic illustration of an application environment of an embodiment of the present invention;
FIG. 2 is a flow chart of a marking method of a printed circuit board according to an embodiment of the invention;
FIG. 3 is a first schematic diagram of target veneer labeling in a veneer layer according to an embodiment of the present invention;
FIG. 4 is a second schematic diagram of target veneer labeling in a veneer layer according to an embodiment of the present invention;
FIG. 5 is a flowchart of a marking method of another PCB according to an embodiment of the invention;
FIG. 6 is a flowchart of a method for marking a printed circuit board according to another embodiment of the present invention;
FIG. 7 is an effect diagram of a target interface in an embodiment of the invention;
FIG. 8 is a flowchart of a marking method of a printed circuit board according to another embodiment of the present invention;
fig. 9 is a block diagram of a marking device of a printed circuit board according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first and second in the description and claims of the invention and in the above-mentioned figures are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the term "include" and any variations thereof is intended to cover non-exclusive protection. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. The term "plurality" in the present invention may mean at least two, for example, two, three or more, and embodiments of the present invention are not limited.
Referring to fig. 1, fig. 1 is a schematic diagram of an application environment according to an embodiment of the present invention, where the application environment includes a client 10 that may include a display 11, a processor 12, and a memory 13. The client 10 may be communicatively coupled to the server 20 via a network 30, the server 20 being operable to provide services (e.g., application services, etc.) to clients installed on the server, and a database 21 may be provided on the server 20 or independent of the server 20 for providing data storage services to the server 20. In addition, a processing engine 22 may be run in the server 20, which processing engine 22 may be used to perform the steps performed by the server 20.
Alternatively, the client 10 may be, but is not limited to, a terminal capable of calculating data, such as a mobile terminal (e.g., a mobile phone, a tablet computer), a notebook computer, a PC (Personal Computer, a personal computer) or the like, and the network may include, but is not limited to, a wireless network or a wired network. Wherein the wireless network comprises: bluetooth, WIFI (Wireless Fidelity ) and other networks that enable wireless communications. The wired network may include, but is not limited to: wide area network, metropolitan area network, server cluster. The server 20 may include, but is not limited to, any hardware device that can perform calculations.
In addition, in this embodiment, the marking method of the printed circuit board can be applied to, but not limited to, an independent processing device with a relatively high processing capability, without data interaction. For example, the processing device may be, but is not limited to, a relatively powerful terminal device, i.e., the operations of the marking method of the printed circuit board described above may be integrated into a single processing device. The above is merely an example, and is not limited in any way in the present embodiment.
Alternatively, in the present embodiment, the marking method of the printed circuit board may be performed by the server 20, may be performed by the client 10, or may be performed by both the server 20 and the client 10. The method for marking the printed circuit board by the client 10 according to the embodiment of the present invention may be performed by the client installed thereon.
In accordance with an embodiment of the present invention, there is provided an embodiment of a method for labeling a printed circuit board, it being noted that the steps shown in the flowchart of the figures may be performed in a computer system such as a set of computer-executable instructions, and, although a logical sequence is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than what is shown or described herein.
In this embodiment, a method for marking a printed circuit board is provided, which may be used for the client, and fig. 2 is a flowchart of a method for marking a printed circuit board according to an embodiment of the present invention, as shown in fig. 2, where the flowchart includes the following steps:
step S201, obtaining a contour layer corresponding to a target board in a printed circuit board.
In this embodiment, the outline layer corresponding to the target board in the printed circuit board is obtained, so that the target outline in the outline layer is conveniently marked. The contour layer at least comprises two layers, and the contour layer is a layer for representing contour information of the appearance of the printed circuit board in the printed circuit board.
In an alternative embodiment, the target plate may be a single plate, so that the corresponding profile layer may comprise a single plate layer and a link plate layer. Wherein, a single board has only one veneer layer, and the connecting board is a board frame extending outside the single board, and sometimes the extending direction or the extending directions are reversed or a plurality of extending directions, so that the boards are uniformly identified as the connecting board layer.
When the method is implemented, firstly, the veneer name of the veneer is obtained, then the veneer is associated with the corresponding veneer layer and the layer name of the connecting plate layer according to the veneer name, so that the veneer is determined according to the veneer name, and the veneer layer and the connecting plate layer corresponding to the veneer are determined according to the association relation between the veneer name and the layer name. It will be appreciated that the above veneer layer and connecting plate layer are only examples, and may be adjusted according to actual requirements in other embodiments.
Step S202, determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate, and performing size marking on the target contour based on the coordinate information acquired by the sampling points.
In this embodiment, the sampling points of the target contour in the contour layer are determined based on the origin coordinates of the target plate, so that the size of the target contour is marked according to the coordinate information collected by each sampling point. It can be understood that the relative position of the target plate is conveniently identified through the setting of the origin coordinates, and then the determination and the labeling of the target contour position in the contour layer are carried out according to the relative position of the target plate.
In an alternative embodiment, the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate may be determined according to the coordinate value of each coordinate in the coordinate information; then calculating the maximum side length and the maximum side width according to the maximum value and the minimum value of the abscissa and the maximum value and the minimum value of the ordinate; and finally, marking the size of the target outline according to the maximum side length and the maximum side width. Each coordinate in the coordinate information collected by each sampling point is determined based on the original point coordinate of the target plate, and each coordinate forms the outer contour of the target contour in the contour layer, so that a necessary condition is provided for the dimension marking of the target contour. Optionally, when calculating the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate, the coordinates may be sorted according to the sizes of the X-axis coordinate and the Y-axis coordinate, and then calculated.
In an alternative embodiment, the sampling point may be determined based on the origin coordinate of the target plate and the inflection point of the target contour in the contour layer, then the maximum side length and the maximum side width of the target contour in the contour layer are calculated according to the maximum value and the minimum value of the ordinate of each coordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate in the coordinate information collected by the sampling point, and finally the dimension marking is performed according to the maximum side length and the maximum side width of the target contour. Compared with the method that sampling points of the target contour are determined according to the preset step length, the method has the advantages that the information acquisition and calculation efficiency is higher and more accurate.
In an alternative embodiment, as shown in fig. 3 to fig. 4, the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate may be calculated based on the origin coordinates of the single boards, the coordinates of the single boards on the left and right sides of the maximum X-axis and the coordinates of the single boards on the upper and lower sides of the maximum Y-axis, and finally the coordinates of the single boards on the left and right sides of the maximum X-axis and the coordinates of the upper and lower sides of the maximum Y-axis, so as to obtain the maximum side length and the maximum side width of the single boards in the single boards, and finally the dimension marking is performed according to the maximum side length and the maximum side width of the single boards.
In an alternative implementation manner, the maximum side length and the maximum side width of the target contour in the contour layer can be calculated based on the original point coordinates of the target plate and two end points of any side of the target contour in the contour layer as sampling points, and then the maximum value and the minimum value of the ordinate of each coordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate in the coordinate information acquired by the sampling points, and finally the dimension marking is performed according to the maximum side length and the maximum side width of the target contour. Compared with the method that sampling points of the target contour are determined according to the preset step length, the method has the advantages that the information acquisition and calculation efficiency is higher and more accurate.
It can be understood that by automatically marking the target contour in the contour layer, the defect that the instruction is tedious to point one by one when the target contour is marked in the related technology is overcome, and meanwhile, the method can be used for each post personnel to perform engineering confirmation stage of wiring design, and can automatically complete the quick marking of the maximum sizes of the single board and the connecting board.
In an alternative embodiment, the target contour and the size label of one of the contour layers are introduced into another layer or other layers different from the target contour so as to intuitively obtain the size relation between the target contour and the other contours.
For example, when at least one veneer is arranged in the connecting plate to be marked, or the veneer outline and the size mark are required to be led into the connecting plate, after the connecting plate of the connecting plate layer is marked, the veneer outline and the size mark of the veneer on the veneer layer can be directly obtained, and the veneer outline and the size mark are covered on the connecting plate in the connecting plate layer, so that the size relation between the target veneer and the connecting plate is intuitively obtained, and further, the problems that the size of the target veneer is oversized, the size of the connecting plate is undersized, or the layout of the target veneer on the connecting plate is unreasonable, and the waste plate edge is smaller and the cutting or the processing of the rear plate cannot be performed are avoided.
Step S203, the dimension marking of the target outline is displayed on the target interface, and the information to be marked is written into the outline layer.
In this embodiment, the dimension marking of the target outline is displayed on the target interface, so that the related post personnel can quickly read and confirm the dimensions of the target single board and the connecting board in the engineering confirmation stage or the manufacturing stage, thereby meeting the actual application requirements. And writing the information to be marked into the profile layer so as to remind a wiring engineer of confirming the target profile information and marking the use.
Specifically, the size label of the target outline can be obtained first, and then the size label of the target outline is uploaded to the corresponding position of the target interface for display. Meanwhile, the information type of the information to be marked is obtained, the contour layer corresponding to the information to be marked is determined according to the information type, and the information to be marked is written into the contour layer.
In an alternative implementation manner, the single board size (marked by the single board size) and the connecting board size (marked by the connecting board size) can be uploaded to the target interface for display, so that the related post personnel can quickly read and confirm the target single board and the connecting board size in the engineering confirmation stage or the manufacturing stage, and the practical application requirement is met. Meanwhile, the information to be marked is led into the single board layer and the connecting board layer at the target interface, so that a wiring engineer can be reminded of confirmation and use of target single board and connecting board information.
In an alternative implementation manner, the information extraction program or the related grabbing tool can grab the single board size marked on the single board in the single board layer, and upload the single board size to the corresponding position of the target interface for display. The same information extraction program or a related grabbing tool can be adopted to grab the link size of the link plate layer for marking the link plate, and the link plate size information is uploaded to the corresponding position of the target interface for displaying. And meanwhile, the information to be marked is imported into the single board layer and the connecting board layer at the target interface so as to remind a wiring engineer of confirmation and use of target single board and connecting board information.
The marking method of the printed circuit board provided by the embodiment comprises the steps of firstly obtaining a contour layer corresponding to a target board in the printed circuit board so as to mark a target contour in the contour layer; then determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate so as to size label the target contour according to the coordinate information acquired by each sampling point; the size of the target outline is marked and displayed on the target interface, so that the related post personnel can quickly read and confirm the size of the target outline in the engineering confirmation stage or the manufacturing stage, the actual application requirement is met, and meanwhile, the information to be marked is written into the outline layer on the target interface, so that the wiring engineer can be reminded of confirming and using the target outline information. Therefore, the method and the device can improve the accuracy and efficiency of marking the target outline size, and provide guarantee for normal operation, smooth manufacturing, cost saving and system stability of the printed circuit board.
In this embodiment, a method for marking a printed circuit board is provided, which may be used for the client, and fig. 5 is a flowchart of a method for marking a printed circuit board according to an embodiment of the present invention, as shown in fig. 5, where the flowchart includes the following steps:
step S501, obtaining a contour layer corresponding to a target board in a printed circuit board.
In this embodiment, the outline layer corresponding to the target board in the printed circuit board is obtained, so that the target outline in the outline layer is conveniently marked. Wherein the contour layer comprises at least two layers.
In an alternative embodiment, the target plate may be a single plate and the contour layer may include a single plate layer and a link plate layer. When the method is implemented, firstly, the veneer name of the veneer is obtained, then the veneer is associated with the corresponding veneer layer and the layer name of the connecting plate layer according to the veneer name, so that the veneer is determined according to the veneer name, and the veneer layer and the connecting plate layer corresponding to the veneer are determined according to the association relation between the veneer name and the layer name. It will be appreciated that the above veneer layer and connecting plate layer are only examples, and may be adjusted according to actual requirements in other embodiments.
Step S502, determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate, and performing size marking on the target contour based on the coordinate information acquired by the sampling points.
In this embodiment, the sampling points of the target contour in the contour layer are determined based on the origin coordinates of the target plate, so that the size of the target contour is marked according to the coordinate information collected by each sampling point. It can be understood that the relative position of the target plate is conveniently identified through the setting of the origin coordinates, and then the determination and the labeling of the target contour position in the contour layer are carried out according to the relative position of the target plate.
Specifically, in the step S502 of dimensioning the target contour based on the coordinate information collected by the sampling points, the step includes:
step S5021, determining the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate according to the coordinate values of the coordinates in the coordinate information.
In this embodiment, the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate are determined according to the coordinate values of the coordinates in the coordinate information, so as to further calculate the maximum side length and the maximum side width of the target contour (such as a single board or a connecting board), and further size-label the target contour according to the maximum side length and the maximum side width.
In step S5022, the maximum side length and the maximum side width are calculated according to the maximum and minimum values of the abscissa and the maximum and minimum values of the ordinate.
In this embodiment, the maximum side length and the maximum side width of the target contour in the contour layer are calculated according to the maximum value and the minimum value of the abscissa and the maximum value and the minimum value of the ordinate, so as to provide a necessary condition for the dimension marking of the target contour.
And step S5023, marking the size of the target outline according to the maximum side length and the maximum side width.
By marking the single board according to the maximum side length and the maximum side width of the target outline, the defect that the instruction is tedious to select one by one when marking the target outline, such as the single board and the connecting board, in the related technology is solved, and meanwhile, the method can be used for each post personnel to automatically finish the rapid marking of the maximum sizes of the single board and the connecting board in the engineering confirmation stage of wiring design.
The coordinate values of the coordinates in the coordinate information are determined based on the original point coordinates of the target plate, and the coordinates in the coordinate information form the outer contour of the target contour, so that a necessary condition is provided for the dimension marking of the target contour. Optionally, when calculating the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate in the coordinate information, the coordinates may be sorted according to the sizes of the X-axis coordinate and the Y-axis coordinate, and then calculated.
For example, when a command for obtaining a target contour in a veneer layer, such as a dimension marking command of the veneer contour, for example, marking the target contour in a Skill language, determining a coordinate dimension of two ends of an X axis based on an origin coordinate of the target board, for example, a is equal to an X coordinate of a maximum left edge of the veneer layer, b is equal to an X coordinate of a maximum right edge of the veneer layer, and calculating a difference between absolute values by using the method of: the value of X is obtained from the values of a-b, the value is displayed in the Skill icon X field, and then the dimension marking of the veneer outline is carried out according to the value of X.
It can be understood that the relative position of the target contour is conveniently identified by setting the origin coordinates, so that the dimension marking of the target contour in the contour layer, such as the dimension marking of the connecting plate contour in the connecting plate layer and the dimension marking of the single plate contour in the single plate layer, is performed according to the relative position of the target plate.
In step S503, the size label of the target contour is displayed on the target interface, and the information to be labeled is written into the contour layer.
In this embodiment, the dimensions of the target outline, such as the dimensions of the veneer outline and the dimensions of the connecting board outline, are uploaded to the target interface for display, so that the relevant post personnel can quickly read and confirm the dimensions of the target veneer and the connecting board in the engineering confirmation stage or the manufacturing stage, thereby meeting the actual application requirements. Meanwhile, the information to be marked is led into the outline layer, such as the single board layer and the connecting board layer, at the target interface, so that a wiring engineer can be reminded of confirming and using the target single board and the connecting board information.
Please refer to step S203 in the embodiment shown in fig. 2 in detail, which is not described herein.
The marking method of the printed circuit board provided by the embodiment comprises the steps of firstly obtaining a contour layer corresponding to a target board in the printed circuit board so as to mark a target contour in the contour layer; then determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate so as to size label the target contour according to the coordinate information acquired by each sampling point; the size of the target outline is marked and displayed on the target interface, so that the related post personnel can quickly read and confirm the size of the target outline in the engineering confirmation stage or the manufacturing stage, the actual application requirement is met, and meanwhile, the information to be marked is written into the outline layer on the target interface, so that the wiring engineer can be reminded of confirming and using the target outline information. Therefore, the method and the device can improve the accuracy and efficiency of marking the target outline size, and provide guarantee for normal operation, smooth manufacturing, cost saving and system stability of the printed circuit board.
In this embodiment, a method for marking a printed circuit board is provided, which may be used for the client, and fig. 6 is a flowchart of a method for marking a printed circuit board according to an embodiment of the present invention, as shown in fig. 6, where the flowchart includes the following steps:
Step S601, obtaining a contour layer corresponding to a target board in the printed circuit board.
In this embodiment, the outline layer corresponding to the target board in the printed circuit board is obtained, so that the target outline in the outline layer is conveniently marked. Wherein the contour layer comprises at least two layers.
In an alternative embodiment, the target plate may be a single plate and the contour layer may include a single plate layer and a link plate layer. When the method is implemented, firstly, the veneer name of the veneer is obtained, then the veneer is associated with the corresponding veneer layer and the layer name of the connecting plate layer according to the veneer name, so that the veneer is determined according to the veneer name, and the veneer layer and the connecting plate layer corresponding to the veneer are determined according to the association relation between the veneer name and the layer name. It will be appreciated that the above veneer layer and connecting plate layer are only examples, and may be adjusted according to actual requirements in other embodiments.
Step S602, determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate, and performing size marking on the target contour based on the coordinate information acquired by the sampling points.
In this embodiment, the sampling points of the target contour in the contour layer are determined based on the origin coordinates of the target plate, so that the size of the target contour is marked according to the coordinate information collected by each sampling point. It can be understood that the relative position of the target plate is conveniently identified through the setting of the origin coordinates, and then the determination and the labeling of the target contour position in the contour layer are carried out according to the relative position of the target plate.
In an alternative embodiment, the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate may be determined according to the coordinate value of each coordinate in the coordinate information; then calculating the maximum side length and the maximum side width according to the maximum value and the minimum value of the abscissa and the maximum value and the minimum value of the ordinate; and finally, marking the size of the target outline according to the maximum side length and the maximum side width. Each coordinate in the coordinate information collected by each sampling point is determined based on the original point coordinate of the target plate, and each coordinate forms the outer contour of the target contour in the contour layer, so that a necessary condition is provided for the dimension marking of the target contour. Optionally, when calculating the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate, the coordinates may be sorted according to the sizes of the X-axis coordinate and the Y-axis coordinate, and then calculated.
In an alternative embodiment, the sampling point may be determined based on the origin coordinate of the target plate and the inflection point of the target contour in the contour layer, then the maximum side length and the maximum side width of the target contour in the contour layer are calculated according to the maximum value and the minimum value of the ordinate of each coordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate in the coordinate information collected by the sampling point, and finally the dimension marking is performed according to the maximum side length and the maximum side width of the target contour.
Please refer to step S502 in the embodiment shown in fig. 5 in detail, which is not described herein.
Step S603, the dimension marking of the target outline is displayed on the target interface, and the information to be marked is written into the outline layer.
In this embodiment, the dimension marking of the target outline is displayed on the target interface, so that the related post personnel can quickly read and confirm the dimensions of the target single board and the connecting board in the engineering confirmation stage or the manufacturing stage, thereby meeting the actual application requirements. And writing the information to be marked into the profile layer so as to remind a wiring engineer of confirming the target profile information and marking the use.
Specifically, the size label of the target outline can be obtained first, and then the size label of the target outline is uploaded to the corresponding position of the target interface for display. Meanwhile, the information type of the information to be marked is obtained, the contour layer corresponding to the information to be marked is determined according to the information type, and the information to be marked is written into the contour layer.
In an alternative implementation manner, the single board size (marked by the single board size) and the connecting board size (marked by the connecting board size) can be uploaded to the target interface for display, so that the related post personnel can quickly read and confirm the target single board and the connecting board size in the engineering confirmation stage or the manufacturing stage, and the practical application requirement is met. Meanwhile, the information to be marked is led into the single board layer and the connecting board layer at the target interface, so that a wiring engineer can be reminded of confirmation and use of target single board and connecting board information.
In an alternative implementation manner, the information extraction program or the related grabbing tool can grab the single board size marked on the single board in the single board layer, and upload the single board size to the corresponding position of the target interface for display. The same information extraction program or a related grabbing tool can be adopted to grab the link size of the link plate layer for marking the link plate, and the link plate size information is uploaded to the corresponding position of the target interface for displaying. And meanwhile, the information to be marked is imported into the single board layer and the connecting board layer at the target interface so as to remind a wiring engineer of confirmation and use of target single board and connecting board information.
Specifically, the writing of the information to be marked into the contour layer in step S603 includes:
in step S6031, the information type of the information to be marked is obtained.
In this embodiment, the information type of the information to be marked is obtained, so that the contour layer to which the information to be marked belongs is determined according to the information type of the information to be marked.
In an alternative embodiment, as shown in fig. 7, taking the profile layer as a veneer layer and the link layer as an example, the information to be marked may include F: FAB is a shorthand for manufacturing, typically indicated in a connection board; FABNOTE: the method comprises the steps that a user adds writing notes by himself/herself in PCB manufacturing notes or PCB production notes; a Plated hole: gold plated holes, typically marked next to the hole, such as a hole in a target veneer; degree 0: the angle is 0 degree, and when the connecting plates are marked, the forward or reverse placement of the connecting plates can be conveniently identified; degree 180: the angle is 180 degrees: DATE: date of manufacture. It will be appreciated that a piece of label information is equivalent to a concept of a part.
Step S6032, determining the contour layer corresponding to the information to be marked according to the information type, and writing the information to be marked into the contour layer.
In this embodiment, the profile layer to which the information to be marked belongs is determined according to the information type of the information to be marked, so that the information to be marked can be conveniently imported into the corresponding profile layer, such as a single board layer and a connecting board layer. It will be appreciated that the same type of text may be imported into the same or different profile layers. The information to be marked is correspondingly imported into the single board layer and the connecting board layer according to the outline layer to which the information to be marked belongs, so that a wiring engineer is reminded of confirming and using the target single board and the connecting board information. The CIS engineer may also build the part for which information is to be indicated and update it in the part database.
For example, when the information to be marked is a platform, the labeling characters are imported onto the single board of the single board layer so as to mark the corresponding part information or remind the CIS engineering to create or import the corresponding part. When the information to be marked is Degre 0, the labeling characters are imported onto the connecting plate of the connecting plate layer.
The marking method of the printed circuit board provided by the embodiment comprises the steps of firstly obtaining a contour layer corresponding to a target board in the printed circuit board so as to mark a target contour in the contour layer; then determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate so as to size label the target contour according to the coordinate information acquired by each sampling point; the size of the target outline is marked and displayed on the target interface, so that the related post personnel can quickly read and confirm the size of the target outline in the engineering confirmation stage or the manufacturing stage, the actual application requirement is met, and meanwhile, the information to be marked is written into the outline layer on the target interface, so that the wiring engineer can be reminded of confirming and using the target outline information. Therefore, the method and the device can improve the accuracy and efficiency of marking the target outline size, and provide guarantee for normal operation, smooth manufacturing, cost saving and system stability of the printed circuit board.
In this embodiment, a method for marking a printed circuit board is provided, which may be used for the client, and fig. 8 is a flowchart of a method for marking a printed circuit board according to an embodiment of the present invention, as shown in fig. 8, where the flowchart includes the following steps:
step S801, a contour layer corresponding to a target board in a printed circuit board is obtained.
In this embodiment, the outline layer corresponding to the target board in the printed circuit board is obtained, so that the target outline in the outline layer is conveniently marked. Wherein the contour layer comprises at least two layers.
In an alternative embodiment, the target plate may be a single plate and the contour layer may include a single plate layer and a link plate layer. When the method is implemented, firstly, the veneer name of the veneer is obtained, then the veneer is associated with the corresponding veneer layer and the layer name of the connecting plate layer according to the veneer name, so that the veneer is determined according to the veneer name, and the veneer layer and the connecting plate layer corresponding to the veneer are determined according to the association relation between the veneer name and the layer name. It will be appreciated that the above veneer layer and connecting plate layer are only examples, and may be adjusted according to actual requirements in other embodiments.
Please refer to step S201 in the embodiment shown in fig. 2 in detail, which is not described herein.
Step S802, determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate, and performing size marking on the target contour based on the coordinate information acquired by the sampling points.
In this embodiment, the sampling points of the target contour in the contour layer are determined based on the origin coordinates of the target plate, so that the size of the target contour is marked according to the coordinate information collected by each sampling point. It can be understood that the relative position of the target plate is conveniently identified through the setting of the origin coordinates, and then the determination and the labeling of the target contour position in the contour layer are carried out according to the relative position of the target plate.
Please refer to step S502 in the embodiment shown in fig. 5 in detail, which is not described herein.
Step S803, the dimension marking of the target outline is displayed on the target interface, and the information to be marked is written into the outline layer.
In this embodiment, the dimension marking of the target outline is displayed on the target interface, so that the related post personnel can quickly read and confirm the dimensions of the target single board and the connecting board in the engineering confirmation stage or the manufacturing stage, thereby meeting the actual application requirements. And writing the information to be marked into the profile layer so as to remind a wiring engineer of confirming the target profile information and marking the use.
Please refer to step S603 in the embodiment shown in fig. 6, which is not described herein.
In step S804, the target contour and the size of one of the contour layers are marked, and the target contour and the size of one of the contour layers are imported into another layer or another layer different from the target contour.
In this embodiment, the target profile and the size of one of the profile layers are marked, and the target profile and the size of one of the profile layers are led into another layer or another layer different from the target profile, so that the reading and the confirmation of a plurality of profile information in the subsequent manufacturing engineering are facilitated.
For example, when at least one veneer is arranged in the connecting plate to be marked, or the veneer outline and the size mark are required to be led into the connecting plate, after the connecting plate of the connecting plate layer is marked, the veneer outline and the size mark of the veneer on the veneer layer can be directly obtained, and the veneer outline and the size mark are covered on the connecting plate in the connecting plate layer, so that the size relation between the target veneer and the connecting plate is intuitively obtained, and further, the problems that the size of the target veneer is oversized, the size of the connecting plate is undersized, or the layout of the target veneer on the connecting plate is unreasonable, and the waste plate edge is smaller and the cutting or the processing of the rear plate cannot be performed are avoided.
The marking method of the printed circuit board provided by the embodiment comprises the steps of firstly obtaining a contour layer corresponding to a target board in the printed circuit board so as to mark a target contour in the contour layer; then determining sampling points of the target contour in the contour layer based on the origin coordinates of the target plate so as to size label the target contour according to the coordinate information acquired by each sampling point; the size of the target outline is marked and displayed on the target interface, so that the related post personnel can quickly read and confirm the size of the target outline in the engineering confirmation stage or the manufacturing stage, the actual application requirement is met, and meanwhile, the information to be marked is written into the outline layer on the target interface, so that the wiring engineer can be reminded of confirming and using the target outline information; and marking the target contour and the size of one of the contour layers, and guiding the target contour and the size into another layer or other layers different from the target contour, so that the reading and the confirmation of a plurality of target contour information in the subsequent manufacturing engineering are facilitated. Therefore, the invention can improve the accuracy and efficiency of marking the target outline and the size, and provides guarantee for the normal operation, smooth manufacture, cost saving and system stability of the printed circuit board.
The embodiment also provides a marking device for a printed circuit board, which is used for realizing the above embodiment and the preferred implementation, and the description is omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a marking device for a printed circuit board, as shown in fig. 9, including:
the profile acquisition module 901 is configured to acquire a profile layer corresponding to a target board in a printed circuit board.
Wherein the contour layer comprises at least two layers.
The contour labeling module 902 is configured to determine a sampling point for a target contour in the contour layer based on an origin coordinate of the target plate, and size label the target contour based on coordinate information acquired by the sampling point.
In some alternative embodiments, the contouring module 902 includes:
the sampling point determining unit is used for taking the inflection point of the target contour as a sampling point;
and/or taking two endpoints of any side of the target contour as sampling points.
And the coordinate value determining unit is used for determining the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate according to the coordinate values of the coordinates in the coordinate information.
And the side length calculating unit is used for calculating the maximum side length and the maximum side width according to the maximum value and the minimum value of the abscissa and the maximum value and the minimum value of the ordinate.
And the contour marking unit is used for marking the size of the target contour according to the maximum side length and the maximum side width.
And the size acquisition unit is used for acquiring the size marking of the target outline.
And the marking display unit is used for uploading the size marking of the target outline to the corresponding position of the target interface for display.
The information acquisition unit is used for acquiring the information type of the information to be marked.
The information writing unit is used for determining the contour layer corresponding to the information to be marked according to the information type and writing the information to be marked into the contour layer.
At least one single board is arranged in the connection board, and the connection board marking module 903 is further configured to mark a target contour and a size of one of the contour layers, and introduce the target contour and the size into another layer or another layer different from the target contour.
And the position acquisition unit is used for acquiring the target position of the information to be marked on the target outline.
The information marking unit is used for marking the information to be marked at the target position.
In some alternative embodiments, the apparatus further comprises:
and the information importing module is used for annotating the target contour and the size of one layer in the contour layers and importing the target contour and the size into another layer or other layers different from the target contour.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The marking means of the printed circuit board in this embodiment are presented in the form of functional units, here referred to as ASIC (application specific integrated circuit) circuits, processors and memories executing one or more software or fixed programs, and/or other devices that can provide the above described functions.
The embodiment of the invention also provides computer equipment, which is provided with the marking device of the printed circuit board shown in the figure 9.
Referring to fig. 10, fig. 10 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 10, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 10.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created from the use of the computer device of the presentation of a sort of applet landing page, and the like. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, server clusters, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims (10)

1. A method of marking a printed circuit board, the method comprising:
acquiring a contour layer corresponding to a target plate in a printed circuit board; the profile layer comprises at least two layers;
determining sampling points of a target contour in the contour layer based on origin coordinates of the target plate, and performing size marking on the target contour based on coordinate information acquired by the sampling points;
and displaying the dimension marking of the target outline on a target interface, and writing information to be marked into the outline layer.
2. The method of claim 1, wherein determining sampling points for a target contour in the contour layer comprises:
taking the inflection point of the target contour as a sampling point;
and/or taking two endpoints of any side of the target contour as sampling points.
3. The method of claim 2, wherein sizing the target contour based on the coordinate information collected by the sampling points comprises:
According to the coordinate values of the coordinates in the coordinate information, determining the maximum value and the minimum value of the ordinate under the same abscissa and the maximum value and the minimum value of the abscissa under the same ordinate;
calculating the maximum side length and the maximum side width according to the maximum value and the minimum value of the abscissa and the maximum value and the minimum value of the ordinate;
and marking the size of the target outline according to the maximum side length and the maximum side width.
4. The method of claim 1, wherein displaying the sizing of the target outline on a target interface comprises:
acquiring the dimension marking of the target outline;
and uploading the dimension label of the target outline to a corresponding position of the target interface for display.
5. The method according to claim 1, wherein writing the information to be marked to the profile layer comprises:
acquiring the information type of the information to be marked;
and determining a contour layer corresponding to the information to be marked according to the information type, and writing the information to be marked into the contour layer.
6. The method of claim 5, further comprising, after writing the information to be marked to the profile layer:
Acquiring a target position of the information to be marked on the target contour;
and marking the information to be marked at the target position.
7. The method according to any one of claims 1 to 6, further comprising:
and marking the target contour and the size of one layer in the contour layers, and leading the target contour and the size into another layer or other layers different from the target contour.
8. A marking device for a printed circuit board, the device comprising:
the contour acquisition module is used for acquiring a contour layer corresponding to a target plate in the printed circuit board; the profile layer comprises at least two layers;
the contour labeling module is used for determining sampling points of the target contour in the contour layer based on the original point coordinates of the target plate and labeling the size of the target contour based on the coordinate information acquired by the sampling points;
and the information display module is used for displaying the dimension mark of the target outline on a target interface and writing the information to be marked into the outline layer.
9. A computer device, comprising:
a memory and a processor in communication with each other, the memory having stored therein computer instructions which, upon execution, cause the processor to perform the method of any of claims 1 to 7.
10. A computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any one of claims 1 to 7.
CN202310664176.6A 2023-06-06 2023-06-06 Method, device, equipment and storage medium for marking printed circuit board Pending CN116562221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310664176.6A CN116562221A (en) 2023-06-06 2023-06-06 Method, device, equipment and storage medium for marking printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310664176.6A CN116562221A (en) 2023-06-06 2023-06-06 Method, device, equipment and storage medium for marking printed circuit board

Publications (1)

Publication Number Publication Date
CN116562221A true CN116562221A (en) 2023-08-08

Family

ID=87494686

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310664176.6A Pending CN116562221A (en) 2023-06-06 2023-06-06 Method, device, equipment and storage medium for marking printed circuit board

Country Status (1)

Country Link
CN (1) CN116562221A (en)

Similar Documents

Publication Publication Date Title
EP3451206B1 (en) Method, apparatus, and device for generating a visual model layout of a space
US11568118B2 (en) Electronic device, method for generating package drawing and computer readable storage medium
US20220414066A1 (en) Data management system, management method, and storage medium
CN110096270A (en) A kind of design drawing method for splitting and system based on .NET plug-in unit
US20190102489A1 (en) Generating a template-driven schematic from a netlist of electronic circuits
CN109766139B (en) Configuration method and device of configuration file
CN111429097A (en) BIM-based automatic matching method and system for field progress and model
US10296693B2 (en) Three-dimensional composite solid component modeling
CN112235949A (en) Method, device and equipment for digging differential via hole in printed circuit board design
CN113608805B (en) Mask prediction method, image processing method, display method and device
CN114329669A (en) Online collaborative editing method and device, electronic equipment and storage medium
CN116562221A (en) Method, device, equipment and storage medium for marking printed circuit board
US20070038668A1 (en) Object matching management system enabling instantaneous reflection of change in object information in operation terminals
CN114092641A (en) Method, device and equipment for generating wiring board drawing and readable storage medium
CN110852035A (en) PCB design platform capable of independently learning
CN116795383B (en) Process data issuing method, issuing device, electronic equipment and storage medium
US11900033B2 (en) Methods and systems for printed circuit board component placement and approval
JP5264305B2 (en) Circuit editing support method, program thereof, recording medium thereof, and circuit editing support device
KR100886657B1 (en) System and Method for making Basic Document of Dimensional Accuracy Check Sheet for Block in Ship Production
CN114139866A (en) Online modular process file system and method
CN113687813A (en) AI image recognition-based product prototype processing method and device and related equipment
CN114925129A (en) Data stereo analysis method and device, electronic equipment and storage medium
CN117172187A (en) Method and system for automatically marking PNL board V-CUT data, PCB manufacturing software and processing equipment
CN114237603A (en) Portal interface layout method and device
CN112417813A (en) Method and apparatus for generating printed matter, storage medium, and electronic apparatus

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination