CN116561028A - Memory control method and memory storage system - Google Patents
Memory control method and memory storage system Download PDFInfo
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- CN116561028A CN116561028A CN202210109108.9A CN202210109108A CN116561028A CN 116561028 A CN116561028 A CN 116561028A CN 202210109108 A CN202210109108 A CN 202210109108A CN 116561028 A CN116561028 A CN 116561028A
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- 230000005055 memory storage Effects 0.000 title claims abstract description 156
- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000001816 cooling Methods 0.000 claims abstract description 19
- 230000004044 response Effects 0.000 claims abstract description 18
- 238000013507 mapping Methods 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 3
- 230000000977 initiatory effect Effects 0.000 claims description 3
- 230000008569 process Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30083—Power or thermal control instructions
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides a memory control method and a memory storage system. The method comprises the following steps: in the memory shutdown program, the host system sends a first control instruction to a memory storage device, wherein the memory storage device is provided with a volatile memory module and a rewritable nonvolatile memory module; the memory storage device turns off the volatile memory module in response to the first control instruction; and in the state that the volatile memory module is closed, the memory storage device maintains the normal operation of the rewritable nonvolatile memory module. Therefore, the cooling efficiency of the memory storage device can be improved.
Description
Technical Field
The present invention relates to a memory control technology, and more particularly, to a memory control method and a memory storage system.
Background
Generally, memory devices or other types of electronic devices have temperature control mechanisms built into them. When the temperature inside the device is too high, the temperature control mechanism can be started to cool down. However, most memory devices do not take into account the heat generated by the volatile memory in the device when performing the cooling operation, resulting in poor cooling efficiency of the device.
Disclosure of Invention
In view of the above, the present invention provides a memory control method and a memory storage system, which can improve the cooling efficiency of the memory storage device by closing the volatile memory in the memory storage device.
Embodiments of the present invention provide a memory control method for a memory storage system. The memory storage system includes a host system and a memory storage device. The memory control method includes: in a memory shutdown procedure, the host system sends a first control instruction to the memory storage device, wherein the memory storage device is provided with a volatile memory module and a rewritable nonvolatile memory module; the memory storage device closing the volatile memory module in response to the first control instruction; and in a state that the volatile memory module is closed, the memory storage device maintains the normal operation of the rewritable nonvolatile memory module.
The embodiment of the invention also provides a memory storage system, which comprises a host system and a memory storage device. The memory storage device is connected to the host system. The memory storage device has a volatile memory module and a rewritable non-volatile memory module. In a memory shutdown procedure, the host system is configured to send a first control instruction to the memory storage device. The memory storage device is to shut down the volatile memory module in response to the first control instruction. The memory storage device is also used for maintaining the normal operation of the rewritable nonvolatile memory module in a state that the volatile memory module is closed.
Based on the above, in the memory shutdown procedure, the host system may send a first control instruction to the memory storage device that includes both the volatile memory module and the rewritable nonvolatile memory module, so as to instruct the memory storage device to shutdown the internal volatile memory module. Meanwhile, in the state that the volatile memory module is closed, the memory storage device can still maintain the normal operation of the rewritable nonvolatile memory module. Therefore, in the normal operation state of the rewritable nonvolatile memory module, the cooling efficiency of the memory storage device can be improved.
Drawings
FIG. 1 is a schematic diagram of a memory storage system according to an embodiment of the invention;
fig. 2 to 5 are flowcharts of a memory control method according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
FIG. 1 is a schematic diagram of a memory storage system according to an embodiment of the invention. Referring to fig. 1, a memory storage system 10 includes a host system 11 and a memory storage device 12. Host system 11 may store data to memory storage device 12 or read data from memory storage device 12. Host system 11 is any system that can cooperate with memory storage device 12 to store data, such as a computer system. Host system 11 may be implemented in a variety of electronic devices such as smart phones, tablet computers, notebook computers, desktop computers, industrial computers, gaming machines, or video cameras. The memory storage device 12 may be a usb disk, a memory card, a solid state disk (Solid State Drive, SSD), a Secure Digital (SD) card, a Compact Flash (CF) card, or other nonvolatile memory storage devices.
Host system 11 may include a connection interface 111 and a processor 112. The connection interface 111 is used to connect the host system 11 to the memory storage device 12. Host system 11 may communicate with memory storage device 12 through connection interface 111. For example, connection interface 111 may transmit data to memory storage 12 or receive data from memory storage 12.
The processor 112 is connected to the connection interface 111. Processor 112 may be responsible for the operation of host system 11 in whole or in part. For example, the processor 112 may include a central processing unit (Central Processing Unit, CPU) or other programmable general purpose or special purpose microprocessor, digital signal processor (Digital Signal Processor, DSP), programmable controller, application specific integrated circuit (Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices.
In an embodiment, host system 11 may also include any practically required hardware devices, such as memory, battery cells, network interface cards, keyboards (or touch pads), screens and/or speakers, etc. Further, in the following embodiments, the description of the processor 112 may be equivalent to the description of the host system 11.
The memory storage device 12 includes a connection interface 121, a memory controller 122, a volatile memory module 123, and a rewritable nonvolatile memory module 124. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, memory storage 12 may communicate with host system 11 through connection interface 112. For example, the connection interfaces 111 and 121 may conform to various connection interface standards such as serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA), high speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express), or universal serial bus (Universal Serial Bus, USB). In one embodiment, the connection interfaces 111 and 121 conform to the NVM Express (NVMe) specification.
The memory controller 122 is connected to the connection interface 121, the volatile memory module 123, and the rewritable nonvolatile memory module 124. The memory controller 122 is used to control the operation of the memory storage device 12 in whole or in part. In addition, the memory controller 122 can perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 124 according to the instructions of the host system 11. In an embodiment, the memory controller 122 may comprise a flash memory controller.
The volatile memory module 123 is used for temporarily storing data. For example, the volatile memory module 123 may include dynamic random access memory (Dynamic Random Access Memory, DRAM). The volatile memory module 123 may lose the stored data in the power-off state.
The rewritable nonvolatile memory module 124 is used for storing data written by the host system 11. For example, the rewritable nonvolatile memory module 124 may include various flash memory modules. The memory cells in the rewritable nonvolatile memory module 124 store data with a change in the threshold voltage. In addition, the rewritable nonvolatile memory module 124 can store data in a power-off state.
In one embodiment, the data access speed of the volatile memory module 123 is faster than the data access speed of the rewritable nonvolatile memory module 124. Further, in the following embodiments, the description of the memory controller 122 may be equivalent to the description of the memory storage device 12.
In one embodiment, the processor 112 may initiate a memory shutdown procedure. In a memory shutdown program, the processor 112 may instruct the memory storage device 12 to shutdown the volatile memory module 123. It should be noted that after the volatile memory module 123 is turned off, the memory storage device 12 and the rewritable nonvolatile memory module 124 can still maintain normal operation. Thus, the processor 112 may assist in cooling the memory storage device 12 by executing a memory shutdown procedure.
Fig. 2 is a flowchart of a memory control method according to an embodiment of the present invention. Referring to fig. 1 and 2, in step S201, in a memory shutdown procedure, the host system 11 may send a control command (also referred to as a first control command) to the memory storage device 12. For example, the processor 112 may send the first control instruction to the memory storage device 12 through the connection interface 111. For example, the first control instruction may include a developer instruction. The first control instruction may instruct the memory storage device 12 to shut down the volatile memory module 123.
In step S202, the memory storage device 12 turns off the volatile memory module 123 in response to the first control instruction. For example, the memory controller 122 may receive a first control instruction through the connection interface 121. In response to the first control instruction, the memory controller 122 may shut off the power supplied from the memory storage device 12 to the volatile memory module 123 to shut down the volatile memory module 123.
In step S203, the memory storage device 12 can maintain the normal operation of the rewritable nonvolatile memory module 124 in the state that the volatile memory module 123 is turned off. For example, after power is stopped to the volatile memory module 123, the memory controller 122 may still continuously access the rewritable nonvolatile memory module 124 to perform data reading, writing, and/or erasing to the rewritable nonvolatile memory module 124.
It should be noted that in the state where the volatile memory module 123 is turned off, the amount of heat generation per unit time of the memory storage device 12 can be reduced. Thus, by shutting down the volatile memory module 123, it may be helpful to assist the memory storage device 12 in cooling down and/or to increase the cooling efficiency of the memory storage device 12.
In one embodiment, after receiving the first control instruction and before shutting down the volatile memory module 123, the memory controller 122 may copy a portion of the data (also referred to as first data) in the volatile memory module 123 into the rewritable nonvolatile memory module 124 for saving. At the same time, the memory controller 122 may copy another portion of the data (also referred to as second data) in the volatile memory module 123 into the memory controller 122 for saving. Thus, even if the volatile memory module 123 is turned off (e.g., powered down), the data originally stored in the volatile memory module 123 can be continuously saved (i.e., backed up).
In one embodiment, the first data may include logical-to-physical mapping information describing a mapping relationship between logical units and physical units. The logical units may be used to map to physical units. The physical units may include physical sectors, physical pages, physical blocks, or the like of the rewritable nonvolatile memory module 124, including various physical management units of a plurality of memory cells. For example, one logical unit may correspond to one logical block location (Logical Block Address, LBA) and one physical unit may correspond to one physical block location (Physical Block Address, PBA). The memory controller 122 can access physical units in the rewritable nonvolatile memory module 124 according to this logical-to-physical mapping information. Thus, after the first data is backed up to the rewritable nonvolatile memory module 124, the memory controller 122 can still perform the data access operation according to the first data in the rewritable nonvolatile memory module 124.
In one embodiment, the second data may include firmware code (firmware code) to control the memory storage device 12. For example, the second data may be copied to a static random access memory (Static Random Access Memory, SRAM) in the memory controller 122. Thus, after the second data is backed up to the memory controller 122, the memory controller 122 may still continuously run the second data to control the memory storage device 12, such as to access the rewritable nonvolatile memory module 124.
In one embodiment, by backing up the data (e.g., the first data and the second data) in the volatile memory module 123 in advance, the memory storage device 12 (including the memory controller 112 and the rewritable nonvolatile memory module 124) can still function normally after the volatile memory module 123 is powered off. In addition, after the power supply to the volatile memory module 123 is restored, the backed-up data (e.g., the first data and the second data) can be restored to the volatile memory module 123 to restore the operation efficiency of the memory storage device 12.
In one embodiment, the processor 112 may determine whether to initiate the memory shutdown procedure based on whether the temperature of the memory storage device 12 is above a threshold and/or whether the memory storage device 12 initiates a cool down procedure. For example, the processor 112 may initiate the memory shutdown procedure in a state where the temperature of the memory storage device 12 is above a threshold and/or the memory storage device 12 initiates a cool down procedure. Alternatively, the processor 112 may not initiate the memory shutdown procedure in a state where the temperature of the memory storage device 12 is not above a threshold and the memory storage device 12 is not initiating a cool down procedure. It should be noted that the processor 112 may also initiate the memory shutdown procedure according to other conditions, depending on the actual requirements.
Fig. 3 is a flowchart of a memory control method according to an embodiment of the present invention. Referring to fig. 1 and 3, in step S301, the host system 11 (i.e. the processor 112) can determine whether the temperature of the memory storage device 12 is higher than a predetermined value. If the temperature of the memory storage device 12 is higher than the preset value, the processor 112 may initiate the memory shutdown procedure in step S303. If the temperature of the memory storage device 12 is not higher than the preset value, in step S302, the processor 112 may determine whether the memory storage device 12 starts the cooling process. If the memory storage device 12 has initiated the cool-down procedure, the processor 112 may initiate the memory shutdown procedure in step S303. In addition, if the temperature of the memory storage device 12 is not higher than the threshold value and the memory storage device 12 does not start the cooling process, the process returns to step S301.
In one embodiment, the processor 112 may send a query to the memory storage device 12 to query whether it supports the memory shutdown procedure before executing the memory shutdown procedure. If the memory storage device 12 supports the memory shutdown procedure, the processor 112 may then initiate and execute the memory shutdown procedure. If the memory storage device 12 does not support the memory shutdown procedure, the processor 112 may not execute the memory shutdown procedure.
Fig. 4 is a flowchart of a memory control method according to an embodiment of the present invention. Referring to fig. 1 and 4, in step S401, before executing the memory shutdown procedure, the host system 11 (i.e. the processor 112) may send a query command to the memory storage device 12. In step S402, the memory storage device 12 responds to the inquiry command to determine whether the host system 11 supports the memory shutdown procedure. For example, the memory controller 122 may query a settings table according to the query. The memory controller 122 may transmit a response to the host system 11 based on the information in the configuration table. The processor 112 can learn from this response whether the memory storage device 12 supports the memory shutdown procedure.
In one embodiment, after shutting down the volatile memory module 123, the processor 112 may detect a temperature and/or a busy state of the memory storage device 12 to determine whether to restart the volatile memory module 123. For example, the processor 112 may determine whether to restart the volatile memory module 123 based on whether the temperature of the memory storage device 12 is below a threshold and/or whether the memory storage device 12 is out of a busy state. Alternatively, in one embodiment, after the volatile memory module 123 is turned off, the processor 112 may determine whether to restart the volatile memory module 123 according to whether the memory storage device 12 ends the cooling process.
Fig. 5 is a flowchart of a memory control method according to an embodiment of the present invention. Referring to fig. 1 and 5, in step S501, after the volatile memory module 123 is turned off, the host system 11 (i.e. the processor 112) may detect the temperature and/or the busy state of the memory storage device 12. In step S502, the processor 112 may send another control instruction (also referred to as a second control instruction) to the memory storage device 12 according to the detection result. In step S503, the memory storage device 12 may restart the volatile memory module 123 in response to the second control instruction, for example, resume the power supply to the volatile memory module 123.
In one embodiment, in response to the temperature of the memory storage device 12 being below a threshold and/or the memory storage device 12 coming out of a busy state, the processor 121 may send the second control instruction to instruct the memory storage device 12 to restart the volatile memory module 123. Alternatively, in an embodiment, in response to the memory storage device 12 ending a previously executed cool down procedure, the processor 121 may send the second control instruction to instruct the memory storage device 12 to restart the volatile memory module 123.
In one embodiment, the memory controller 122 may synchronously execute a cool down procedure while the volatile memory module 123 is turned off in an attempt to lower the temperature of the memory storage device 12. For example, the cooling process may include various cooling-assisted operations to reduce the clock frequency, transmission bandwidth, and/or supply voltage of the memory storage device 12. In particular, in the state of executing the cooling process, the data access performance of the memory storage device 12 is often reduced. Therefore, even if the volatile memory module 123 is turned off, the user may not significantly feel the system performance degradation caused by the turning off of the volatile memory module 123.
In one embodiment, after the volatile memory module 123 is turned off, the processor 112 may provide memory storage space inside the host system 11 for the memory storage device 12 to improve the operating efficiency of the memory storage device 12. For example, the processor 121 may set a portion of the memory storage space within the host system 11 as a host memory buffer (Host Memory Buffer, HMB) area in place of the volatile memory module 123 in the memory storage device 12 that is turned off. In a state where the volatile memory module 123 is turned off, the memory controller 122 can access the host memory buffer, for example, can temporarily store data in the host memory buffer and can read data from the host memory buffer.
However, the steps in fig. 2 to 5 are described in detail above, and will not be described here again. It should be noted that each step in fig. 2 to 5 may be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the methods of fig. 2 to 5 may be used with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.
In summary, the embodiments of the invention provide a method for controlling a memory storage device to close a volatile memory module in the memory storage device by a host system to assist in cooling the memory storage device. Therefore, the cooling efficiency of the memory storage device can be effectively improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (16)
1. A memory control method for a memory storage system, the memory storage system comprising a host system and a memory storage device, the memory control method comprising:
in a memory shutdown procedure, the host system sends a first control instruction to the memory storage device, wherein the memory storage device is provided with a volatile memory module and a rewritable nonvolatile memory module;
the memory storage device closing the volatile memory module in response to the first control instruction; and
in the closed state of the volatile memory module, the memory storage device maintains the normal operation of the rewritable nonvolatile memory module.
2. The memory control method of claim 1, wherein the step of shutting down the volatile memory module comprises:
the memory storage device is powered off from the volatile memory module.
3. The memory control method of claim 2, wherein the step of shutting down the volatile memory module further comprises:
first data in the volatile memory module is copied into the rewritable non-volatile memory module and second data in the volatile memory module is copied into a memory controller of the memory storage device before the power supply to the volatile memory module is cut off by the memory storage device.
4. The memory control method of claim 3, wherein the first data includes logic-to-entity mapping information describing a mapping relationship between logic units and entity units, and the second data includes firmware code to control the memory storage device.
5. The memory control method according to claim 1, further comprising:
in response to the temperature of the memory storage device being above a preset value or the memory storage device initiating a cool down procedure, the host system initiates the memory shutdown procedure to assist in cooling the memory storage device.
6. The memory control method according to claim 1, further comprising:
before executing the memory shutdown program, the host system sends a query instruction to the memory storage device; and
the memory storage device responds to the query instruction in response to whether the host system the memory storage device supports the memory shutdown procedure.
7. The memory control method according to claim 1, further comprising:
after shutting down the volatile memory module, the host system detects at least one of a temperature and a busy state of the memory storage device;
the host system sends a second control instruction to the memory storage device according to the detection result; and
the memory storage device restarts the volatile memory module in response to the second control instruction.
8. The memory control method according to claim 1, further comprising:
after shutting down the volatile memory module, the host system provides memory storage space internal to the host system for use by the memory storage device.
9. A memory storage system, comprising:
a host system; and
a memory storage device connected to the host system,
wherein the memory storage device has a volatile memory module and a rewritable non-volatile memory module,
in a memory shutdown procedure, the host system is configured to send a first control instruction to the memory storage device,
the memory storage device is configured to shut down the volatile memory module in response to the first control instruction, and
the memory storage device is also used for maintaining the normal operation of the rewritable nonvolatile memory module in a state that the volatile memory module is closed.
10. The memory storage system of claim 9, wherein the operation of shutting down the volatile memory module comprises:
the memory storage device is powered off from the volatile memory module.
11. The memory storage system of claim 10, wherein the operation of shutting down the volatile memory module further comprises:
first data in the volatile memory module is copied into the rewritable non-volatile memory module and second data in the volatile memory module is copied into a memory controller of the memory storage device before the power supply to the volatile memory module is cut off by the memory storage device.
12. The memory storage system of claim 11, wherein the first data includes logic-to-entity mapping information to describe a mapping relationship between logical units and entity units, and the second data includes firmware code to control the memory storage device.
13. The memory storage system of claim 9, wherein the host system is further to initiate the memory shutdown procedure to facilitate cooling the memory storage device in response to a temperature of the memory storage device being above a preset value or the memory storage device initiating a cooling procedure.
14. The memory storage system of claim 9, wherein prior to executing the memory shutdown program, the host system is further to send a query instruction to the memory storage device, and
the memory storage device is also configured to respond to the query instruction in response to whether the host system supports the memory shutdown procedure.
15. The memory storage system of claim 9, wherein after shutting down the volatile memory module, the host system is further configured to detect at least one of a temperature and a busy state of the memory storage device,
the host system is also used for sending a second control instruction to the memory storage device according to the detection result, and
the memory storage device is also to restart the volatile memory module in response to the second control instruction.
16. The memory storage system of claim 9, wherein after shutting down the volatile memory module, the host system is further to provide memory storage space internal to the host system for use by the memory storage device.
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| CN202210109108.9A CN116561028A (en) | 2022-01-28 | 2022-01-28 | Memory control method and memory storage system |
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