CN116560568A - Data processing method, memory controller, memory and storage medium - Google Patents

Data processing method, memory controller, memory and storage medium Download PDF

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Publication number
CN116560568A
CN116560568A CN202310403204.9A CN202310403204A CN116560568A CN 116560568 A CN116560568 A CN 116560568A CN 202310403204 A CN202310403204 A CN 202310403204A CN 116560568 A CN116560568 A CN 116560568A
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China
Prior art keywords
data
memory
state
flash memory
flash
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Chinese (zh)
Inventor
刘瑞平
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China Southern Power Grid Big Data Service Co ltd
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China Southern Power Grid Big Data Service Co ltd
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Priority to CN202310403204.9A priority Critical patent/CN116560568A/en
Publication of CN116560568A publication Critical patent/CN116560568A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0647—Migration mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The embodiment of the application relates to the field of storage equipment application, and discloses a data processing method, a memory controller, a memory and a storage medium, wherein the data processing method comprises the following steps: acquiring the state of a memory, wherein the state of the memory comprises a power-on state, a power-off state and an operation state; and writing filling data into the flash memory blocks of the memory according to the state of the memory until the filling data are written into the safe data pages of the flash memory blocks. The method and the device can improve the stability of the data in the word line, thereby ensuring that the data in the flash memory block is in a stable state, reducing the data error correction times and avoiding data loss; thereby providing a more stable and reliable data storage solution for data centers, supercomputers, clouds, edges, and the like.

Description

Data processing method, memory controller, memory and storage medium
Technical Field
The present disclosure relates to the field of storage device applications, and in particular, to a data processing method, a memory controller, a memory, and a storage medium.
Background
With the advent of new technologies such as big data, artificial intelligence, 5G, and internet of things, storage demands of various data centers, supercomputer centers, clouds, edges, and the like are continuously rising, global data volume (such as energy, finance, agriculture, industry, transportation, public utilities, video, and the like) is exponentially increasing, and new demands are put on storage capacity, performance, and reliability by data service demands with large capacity and low time delay. Therefore, the NAND memory with low power consumption and ultra-high density is widely used in various data centers, super computing centers, clouds, edges and the like.
NAND memories such as solid state disks (Solid State Drives, SSD), which are hard disks made using arrays of solid state electronic memory chips, include a control unit and a memory unit (FLASH memory chip or DRAM memory chip). Flash memory (NAND Flash) is the primary storage medium for solid state disks. For a flash block, one word line (word) in the flash block consists of one or several pages (pages).
The stability of the data inside the word line is affected by the page itself constituting the word line and the subsequent pages of the word line, and thus the data inside the word line is easily in an unstable state. The prior art generally adopts data error correction to solve the problems, but the method can seriously reduce the bandwidth, and the data can be lost when the data error correction fails, so that the reliability and the stability of storage such as a data center, a super computing center, cloud, edges and the like can be greatly influenced.
Disclosure of Invention
The embodiment of the application provides a data processing method, a memory controller, a memory and a storage medium, which can improve the stability of data in a word line, thereby ensuring that the data in a flash memory block is in a stable state, reducing the data error correction times and avoiding data loss.
The embodiment of the application provides the following technical scheme:
in a first aspect, an embodiment of the present application provides a data processing method, including:
acquiring the state of a memory, wherein the state of the memory comprises a power-on state, a power-off state and an operation state;
and writing filling data into the flash memory blocks of the memory according to the state of the memory until the filling data are written into the safe data pages of the flash memory blocks.
In some embodiments, the flash memory block includes at least one word line, each word line corresponding to one secure page of data;
writing the filling data to the flash memory block of the memory until the filling data is written to the secure data page of the flash memory block according to the state of the memory, comprising:
and when the memory is in a power-on state or a power-off state, starting to write filling data from the next page of the word line corresponding to the current writing position until the filling data is written to the safety data page corresponding to the word line.
In some embodiments, the method further comprises:
after the valid data in the flash block is reclaimed, new padding data is issued.
In some embodiments, writing the padding data to the flash block of the memory until the padding data is written to the secure data page of the flash block, according to the state of the memory, further comprises:
when the memory is in an operation state, writing filling data into the flash memory block at intervals of preset time;
in some embodiments, the method further comprises:
after each time of writing a filling data, the flash memory block is controlled to wait asynchronously until a preset time interval is reserved, and new filling data is written into the flash memory block again.
In some embodiments, when the memory is in a power-up state, the method further comprises, after writing the pad data from a next page of the word line corresponding to the current writing position until the secure data page corresponding to the word line is written:
and if the free space of the memory is sufficient, moving the effective data on the flash memory block to the free flash memory block.
In some embodiments, moving valid data on a flash block to a free flash block includes:
and after the memory is powered up, controlling the flash memory block to asynchronously execute the moving task.
In some embodiments, prior to moving valid data on the flash block to the free flash block, the method further comprises:
judging whether the free space of the memory is sufficient;
if the number of the free flash memory blocks of the memory is greater than or equal to the preset number, determining that the free space of the memory is sufficient;
if the number of free flash memory blocks of the memory is smaller than the preset number, determining that the free space of the memory is insufficient.
In a second aspect, embodiments of the present application provide a memory controller, including:
the system comprises an acquisition module, a storage module and a control module, wherein the acquisition module is used for acquiring the state of the storage, and the state of the storage comprises a power-on state, a power-off state and an operation state;
and the filling module is used for writing filling data into the flash memory blocks of the memory according to the state of the memory until the filling data are written into the safe data pages of the flash memory blocks.
In some embodiments, the filling module is specifically for:
and when the memory is in a power-on state or a power-off state, starting writing filling data from the next page of the word line corresponding to the current writing position until the filling data is written into the safety data page corresponding to the word line, wherein the flash memory block comprises at least one word line, and each word line corresponds to one safety data page.
In a third aspect, embodiments of the present application provide a memory, including:
at least one processing unit; the method comprises the steps of,
a memory unit in communication with the at least one processing unit; wherein,,
the memory stores instructions executable by the at least one processing unit to cause the at least one processing unit to perform the data processing method of the first aspect.
In a fourth aspect, embodiments of the present application also provide a non-volatile computer-readable storage medium storing computer-executable instructions that, when executed by a memory, cause the memory to perform a data processing method as in the first aspect.
The beneficial effects of the embodiment of the application are that: in a situation different from the prior art, the data processing method provided in the embodiment of the present application includes: acquiring the state of a memory, wherein the state of the memory comprises a power-on state, a power-off state and an operation state; and writing filling data into the flash memory blocks of the memory according to the state of the memory until the filling data are written into the safe data pages of the flash memory blocks. According to the power-on state, the power-off state and the running state of the memory, filling data are written into the flash memory blocks of the memory until the filling data are written into the safe data pages of the flash memory blocks, so that the stability of the data in the word lines can be improved, the data in the flash memory blocks are ensured to be in a stable state, the data error correction times are reduced, and the data loss is avoided; thereby providing a more stable and reliable data storage solution for data centers, supercomputers, clouds, edges, and the like.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
FIG. 1 is a schematic diagram of a memory according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a word line provided in an embodiment of the present application;
FIG. 3 is a schematic diagram of a word line with unstable internal data provided by an embodiment of the present application;
FIG. 4 is a schematic flow chart of a data processing method according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a word line with internal data stabilization according to an embodiment of the present application;
fig. 6 is a schematic diagram of the refinement flow of step S402;
FIG. 7 is a schematic diagram of a write speed of filling data of a memory in different states according to an embodiment of the present disclosure;
FIG. 8 is a schematic flow chart of data migration according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a memory controller according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of another memory according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that, if not conflicting, the various features in the embodiments of the present application may be combined with each other, which is within the protection scope of the present application. In addition, while functional block division is performed in a device diagram and logical order is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. Moreover, the words "first," "second," "third," and the like as used herein do not limit the data and order of execution, but merely distinguish between identical or similar items that have substantially the same function and effect.
The following specifically describes the technical scheme of the present application with reference to the drawings of the specification:
referring to fig. 1, fig. 1 is a schematic structural diagram of a memory according to an embodiment of the present application;
in the embodiment of the application, the memory includes a NAND memory, such as a solid state disk.
As shown in fig. 1, the memory 100 includes a flash memory medium 110 and a memory controller 120 connected to the flash memory medium 110. The memory 100 is in communication connection with the host 200 through a wired or wireless manner, so as to implement data interaction.
The Flash memory medium 110, which is a storage medium of the memory 100, is also called a Flash memory, a NAND Flash, a Flash memory or Flash particles, belongs to one type of memory device, is a nonvolatile memory, and can store data for a long time even without current supply, and has storage characteristics equivalent to a hard disk, so that the Flash memory medium 110 becomes a base of storage media of various portable digital devices.
The memory controller 120 includes a data converter 121, a processor 122, a buffer 123, a flash memory controller 124, and an interface 125.
The data converter 121 is connected to the processor 122 and the flash memory controller 124, respectively, and the data converter 121 is used for converting binary data into hexadecimal data and vice versa. Specifically, when the flash controller 124 writes data to the flash medium 110, binary data to be written is converted into hexadecimal data by the data converter 121, and then written to the flash medium 110. When the flash controller 124 reads data from the flash memory medium 110, hexadecimal data stored in the flash memory medium 110 is converted into binary data by the data converter 121, and then the converted data is read from the binary data page register. The data converter 121 may include a binary data register and a hexadecimal data register, among others. Binary data registers may be used to hold data converted from hexadecimal to binary, and hexadecimal data registers may be used to hold data converted from binary to hexadecimal.
The processor 122 is connected to the data converter 121, the buffer 123, the flash memory controller 124 and the interface 125, where the processor 122 is connected to the data converter 121, the buffer 123, the flash memory controller 124 and the interface 125 through buses or other manners, and is configured to execute nonvolatile software programs, instructions and modules stored in the buffer 123, so as to implement any method embodiment of the present application. On this basis, through firmware development, it is also used for the core processing of the flash translation layer (Flash translation layer, FTL).
The buffer 123 is mainly used for buffering the read/write command sent by the host 200 and the read data or write data obtained from the flash memory medium 110 according to the read/write command sent by the host 200.
The flash controller 124 is connected to the flash medium 110, the data converter 121, the processor 122 and the buffer 123, and is used for accessing the flash medium 110 at the back end and managing various parameters and data I/O of the flash medium 110.
The interface 125 is connected to the host 200 and the data converter 121, the processor 122 and the buffer 123, and is configured to receive data sent by the host 200, or receive data sent by the processor 122, so as to implement data transmission between the host 200 and the processor 122, where the interface 125 may be an NVME/SATA protocol such as SATA-2 interface, SATA-3 interface, SAS interface, MSATA interface, PCI-E interface, ngaf interface, CFast interface, SFF-8639 interface, U.2 interface, AIC interface, and m.2 interface.
Currently, flash memories can be classified into three types according to the difference in storage density: a flash memory (Single Level Cell, SLC) in which one memory cell stores 1bit data, a flash memory (Multiple Level Cell, MLC) in which one memory cell stores 2bit data, and a flash memory (Triple Level Cell, TLC) in which one memory cell stores 3bit data.
For a flash block, a word line (word line) consists of one or several pages (pages), for example TLC, one word line corresponding to three pages: a quick Page (LP), a slow Page (UP), and a super Page (XP).
Referring to fig. 2, fig. 2 is a schematic diagram of a word line according to an embodiment of the present application;
in the embodiment of the present application, a word line of a flash memory block in micro B17A is taken as an example for illustration.
As shown in fig. 2, pages 36, 60 and 61 in the flash memory block form a word line, wherein page 36 is a fast page, page 60 is a super page, and page 61 is a slow page.
It will be appreciated that when the flash memory is not of the One-pass program type, one word line program (WL program) needs to be divided into a plurality of times to stabilize the data. Taking fig. 2 as an example, the word line in fig. 2 needs to be programmed twice to stabilize the data. The first programming requires programming of the fast page (page 36) and the second programming requires programming of the super page (page 60) and slow page (page 61). If the second programming is not completed, the data of the first programming is unstable, i.e., the data of the fast page (page 36) is unstable.
The stability of data within a word line is affected not only by the pages themselves that make up the word line, but also by the pages that follow the word line.
Referring to fig. 3, fig. 3 is a schematic diagram of a word line with unstable internal data according to an embodiment of the present application;
as shown in fig. 3, one word line is composed of a 36 th Page (fast Page), a 60 th Page (super Page) and a 61 th Page (slow Page) in the flash memory block, and the flash memory block further includes a Safe data Page (Safe Page) to which the word line corresponds, and a sufficient amount of data is not written between the slow Page and the Safe data Page of the word line, and the internal data of the word line is in an unstable state.
It will be appreciated that after data is written entirely to a word line (i.e., the fast, super and slow pages that make up the word line all complete data writing), the internal data of that word line remains in an unstable state, requiring that a sufficient amount of data be written to the subsequent pages of that word line, i.e., after a certain number of pages have been programmed down, the internal data of that word line can only be in a stable state.
The prior art generally adopts data error correction to solve the problems, but the method can seriously reduce the bandwidth, and the data can be lost when the data error correction fails, so that the reliability and the stability of storage such as a data center, a super computing center, cloud, edges and the like can be greatly influenced.
Based on this, the embodiment of the application provides a data processing method, so as to improve the stability of the data in the word line, thereby ensuring that the data in the flash memory block is in a stable state, reducing the data error correction times and avoiding the data loss; thereby providing a more stable and reliable data storage solution for data centers, supercomputers, clouds, edges, and the like.
Referring to fig. 4, fig. 4 is a flow chart of a data processing method according to an embodiment of the present application;
the data processing method is applied to a memory, wherein the memory comprises a NAND memory, such as a solid state disk, and the memory comprises a flash memory block.
As shown in fig. 4, the data processing method includes:
step S401: acquiring the state of a memory;
specifically, the states of the memory include a power-on state, a power-off state, and an operating state, and the states of the memory are acquired by the memory controller.
Step S402: and writing filling data into the flash memory blocks of the memory according to the state of the memory until the filling data are written into the safe data pages of the flash memory blocks.
Specifically, the padding data includes invalid data such as: the dummy data, the flash memory block includes at least one word line, each word line corresponding to a secure page of data. And when the memory is in a power-on state, a power-off state or an operating state, writing filling data from the next page of the word line corresponding to the current writing position until the filling data is written to the safety data page corresponding to the word line, so that the internal data of the word line is in a stable state.
Referring to fig. 5, fig. 5 is a schematic diagram of a word line with stable internal data according to an embodiment of the present application; in the embodiment of the present application, the type of the memory to which the data processing method is applied is not limited, and the application to TLC will be described below as an example.
As shown in fig. 5, one word line is composed of a 36 th page (fast page), a 60 th page (super page) and a 61 th page (slow page) in a flash memory block, and fill data is written in each page between the slow page of the word line and a secure data page corresponding to the word line, and the internal data of the word line is in a stable state.
Referring to fig. 6, fig. 6 is a schematic diagram of a refinement flow of step S402;
as shown in fig. 6, step S402: writing the filling data to the flash memory block of the memory until the filling data is written to the secure data page of the flash memory block according to the state of the memory, comprising:
step S421: determining a state of the memory;
specifically, the states of the memory include a power-on state, a power-off state, and an operating state, and the filling speed of the memory in the operating state is lower than the filling speed of the memory in the power-on state or the power-off state.
Step S422: when the memory is in a power-on state or a power-off state, starting writing filling data from the next page of the word line corresponding to the current writing position until the filling data is written into the safety data page corresponding to the word line;
specifically, when the memory is in a power-on state or a power-off state, the dummy data is written from the next page of the word line corresponding to the current writing position until the dummy data is written to the secure data page corresponding to the word line. For example, in fig. 5, dummy data is written from the next page of the slow page of the word line, and dummy data is written in each page between the slow page of the word line and the secure data page corresponding to the word line, so that the internal data of the word line is in a stable state.
In an embodiment of the present application, when the memory is in a power-up state or a power-down state, the method further includes: after the valid data in the flash block is reclaimed, new padding data is issued.
It can be appreciated that when the memory is in a powered-up state or a powered-down state, the memory occupies all resources, accelerating the completion of the fill task. After the valid data in the flash memory block is recovered, new dummy data is immediately issued for writing.
Step S423: and writing filling data into the flash memory block at intervals of preset time when the memory is in an operation state.
Specifically, when the memory is in an operation state, one dummy data is written from the next page of the word line corresponding to the current writing position at preset intervals until the dummy data is written to the safe data page corresponding to the word line. Wherein the preset time is preset in the memory controller, and optionally, the preset time is 600ms.
In an embodiment of the present application, when the memory is in an operating state, the method further includes: after each time of writing a filling data, the flash memory block is controlled to wait asynchronously until a preset time interval is reserved, and new filling data is written into the flash memory block again. Specifically, when the padding data is completed in advance (less than 600 ms), the padding data is not sent out until the rest time is consumed.
It will be appreciated that while the memory is in an operational state, the memory may perform other tasks such as: the host reads the service, so writing dummy data cannot cause bandwidth jitter, and the writing speed of the filling data needs to be reduced. Since one dummy data is written to the flash block every 600ms, there is only one dummy data in the flash block. After writing of one dummy data is completed, if the effective data in the flash memory block is recovered, the flash memory block is controlled to wait asynchronously until a time interval of 600ms from the last dummy data is set, and a new dummy data is continuously issued for writing.
Referring to fig. 7, fig. 7 is a schematic diagram showing a writing speed of filling data of a memory in different states according to an embodiment of the present disclosure;
as shown in fig. 7, the write speed of the filler data when the memory is in the running state is lower than the write speed of the filler data when it is in the power-on state or the power-off state. When the memory is in a power-on state or a power-off state, the memory controller continuously transmits filling data to write, and when the data is recovered, the memory controller does not need to wait and can immediately transmit new filling data; when the memory is in an operating state, the memory controller issues a filling data at preset intervals to write, and when the data is recovered, the flash memory block is controlled to wait asynchronously until the memory controller and the issuing time of the last filling data are at preset intervals, and then a new filling data is issued continuously to write.
In the embodiment of the application, for the flash memory blocks which are not fully written with data, the stored data has risks, and valid data on the flash memory blocks need to be moved to other flash memory blocks. Thus, when the memory is in a powered-on state, the method further comprises: and carrying out data movement on the flash memory block.
Referring to fig. 8, fig. 8 is a schematic flow chart of data movement according to an embodiment of the present application;
as shown in fig. 8, the data moving process includes:
step S801: filling data;
specifically, when the memory is in a power-on state, the dummy data is written from the next page of the word line corresponding to the current writing position until the dummy data is written to the secure data page corresponding to the word line.
Step S802: judging whether the free space of the memory is sufficient;
specifically, if the number of free flash memory blocks of the memory is greater than or equal to the preset number, it is determined that the free space of the memory is sufficient, and step S803 is entered: moving effective data on the flash memory block to an idle flash memory block; if the number of the free flash memory blocks of the memory is smaller than the preset number, determining that the free space of the memory is insufficient, and ending the flow. The preset number is preset in the memory controller, and can be set by a person skilled in the art according to practical situations, which is not limited in this embodiment.
Step S803: and moving the effective data on the flash memory blocks to the idle flash memory blocks.
Specifically, if the free space of the memory is sufficient, the valid data on the flash memory block is moved to the free flash memory block. In an embodiment of the present application, moving valid data on a flash memory block to a free flash memory block includes: and after the memory is powered up, controlling the flash memory block to asynchronously execute the moving task. It will be appreciated that after the valid data on a flash block is moved successfully, the flash block is erased to free space for the flash block to write new data.
In the embodiment of the application, the effective data on the flash memory block is moved to the idle flash memory block, so that the data instability risk of the flash memory block which is not fully written with the data can be reduced.
In an embodiment of the present application, a data processing method is provided, including: acquiring the state of a memory, wherein the state of the memory comprises a power-on state, a power-off state and an operation state; and filling data into the flash memory blocks of the memory according to the state of the memory, and writing the data into the safe data pages of the flash memory blocks. According to the power-on state, the power-off state and the running state of the memory, filling data are written into the flash memory block of the memory until the filling data are written into the safe data page of the flash memory block, so that the stability of the data in the word line can be improved, the data in the flash memory block is ensured to be in a stable state, the data error correction times are reduced, and the data loss is avoided; thereby providing a more stable and reliable data storage solution for data centers, supercomputers, clouds, edges, and the like.
Referring to fig. 9 again, fig. 9 is a schematic structural diagram of a memory controller according to an embodiment of the present disclosure;
as shown in fig. 9, the memory controller 900 includes a fetch module 901 and a fill module 902. The memory controller 900 is applied to a memory, where the memory includes a NAND memory, such as a solid state disk, and the memory further includes a flash block, and the memory controller 900 includes:
the acquiring module 901 is configured to acquire a state of a memory, where the state of the memory includes a power-on state, a power-off state, and an operating state;
a filling module 902, configured to write filling data to the flash memory block of the memory according to the state of the memory until the filling data is written to the secure data page of the flash memory block.
In some embodiments of the present application, the filling module 902 is specifically configured to, when the memory is in a power-up state or a power-down state, start writing filling data from a next page of a word line corresponding to a current writing position until writing to a secure data page corresponding to the word line, where the flash memory block includes at least one word line, and each word line corresponds to one secure data page; or when the memory is in an operation state, writing a filling data into the flash memory block at intervals of preset time.
In some embodiments of the present application, the filling module 902 is further configured to, when the memory is in a power-on state, start writing filling data from a next page of the word line corresponding to a current writing position until after writing to a secure data page corresponding to the word line, if the free space of the memory is sufficient, move valid data on the flash memory block to the free flash memory block.
Referring to fig. 10 again, fig. 10 is a schematic structural diagram of another memory according to the embodiment of the present application;
as shown in fig. 10, the memory 101 includes one or more processing units 1011 and a storage unit 1012. In fig. 10, for example, the processing unit 1011 includes a NAND memory, such as a solid state disk.
The processing unit 1011 and the storage unit 1012 may be connected by a bus or otherwise, for example in fig. 10.
The processing unit 1011 is configured to provide computing and control capabilities for controlling the memory 101 to perform corresponding tasks, for example, for controlling the memory 101 to perform a data processing method according to any of the above method embodiments, including: acquiring the state of a memory, wherein the state of the memory comprises a power-on state, a power-off state and an operation state; and writing filling data into the flash memory blocks of the memory according to the state of the memory until the filling data are written into the safe data pages of the flash memory blocks.
According to the power-on state, the power-off state and the running state of the memory, filling data are written into the flash memory block of the memory until the filling data are written into the safe data page of the flash memory block, so that the stability of the data in the word line can be improved, the data in the flash memory block is ensured to be in a stable state, the data error correction times are reduced, and the data loss is avoided; thereby providing a more stable and reliable data storage solution for data centers, supercomputers, clouds, edges, and the like.
The processing unit 1011 may be a general-purpose processor including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), a hardware chip, or any combination thereof; it may also be a digital signal processor (Digital Signal Processing, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof.
The storage unit 1012, as a non-transitory computer readable storage medium, may be used to store a non-transitory software program, a non-transitory computer executable program, and modules, such as program instructions/modules corresponding to the data processing method in the embodiments of the present application. The processing unit 1011 may implement the data processing method in any of the method embodiments described above by running non-transitory software programs, instructions, and modules stored in the storage unit 1012. In particular, the storage unit 1012 may include a Volatile Memory (VM), such as a random access memory (random access memory, RAM); the storage unit 1012 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory (flash memory), a hard disk (HDD) or a memory (SSD) or other non-transitory solid state memory device; the storage unit 1012 may also include a combination of the types of memories described above.
The storage unit 1012 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, storage unit 1012 optionally includes memory located remotely from processing unit 1011, which may be connected to processing unit 1011 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more modules are stored in the storage unit 1012 that, when executed by the one or more processing units 1011, perform the data processing methods in any of the method embodiments described above, for example, performing the various steps shown in fig. 4 described above.
The embodiments also provide a non-volatile computer storage medium storing computer executable instructions that are executed by one or more memories, for example, the one or more memories may perform the data processing method in any of the method embodiments described above, for example, performing the steps described above, where the memories include NAND memories, for example, solid state disks.
The apparatus or device embodiments described above are merely illustrative, in which the unit modules illustrated as separate components may or may not be physically separate, and the components shown as unit modules may or may not be physical units, may be located in one place, or may be distributed over multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., and include several instructions for up to a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method of each embodiment or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; the technical features of the above embodiments or in the different embodiments may also be combined under the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as above, which are not provided in details for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. A method of data processing, comprising:
acquiring the state of a memory, wherein the state of the memory comprises a power-on state, a power-off state and an operation state;
and writing filling data into a flash memory block of the memory according to the state of the memory until the filling data is written into a safe data page of the flash memory block.
2. The method of claim 1, wherein the flash memory block includes at least one word line, each of the word lines corresponding to one of the secure pages of data;
writing the filling data into the flash memory block of the memory according to the state of the memory until the filling data is written into the safe data page of the flash memory block, wherein the method comprises the following steps:
when the memory is in a power-on state or a power-off state, starting writing the filling data from the next page of the word line corresponding to the current writing position until writing the filling data into the safety data page corresponding to the word line;
the method further comprises the steps of:
and after the effective data in the flash memory block is recovered, issuing new filling data.
3. The method of claim 1, wherein writing filler data to a flash block of the memory until filler data is written to a secure data page of the flash block, according to a state of the memory, further comprises:
writing one filling data into the flash memory block at intervals of preset time when the memory is in an operation state;
the method further comprises the steps of:
and after each time of writing one filling data, controlling the flash memory block to wait asynchronously until a preset time interval is reserved, and writing a new filling data into the flash memory block again.
4. The method of claim 2, wherein while the memory is in a power-up state, writing the filler data from a next page of a word line corresponding to a current writing location until after writing to a secure data page corresponding to the word line, the method further comprising:
and if the free space of the memory is sufficient, moving the effective data on the flash memory block to the free flash memory block.
5. The method of claim 4, wherein moving valid data on the flash block to a free flash block comprises:
and after the memory is powered on, controlling the flash memory block to asynchronously execute the moving task.
6. The method of claim 4, wherein prior to moving valid data on the flash block to a free flash block, the method further comprises:
judging whether the free space of the memory is sufficient;
if the number of the free flash memory blocks of the memory is greater than or equal to the preset number, determining that the free space of the memory is sufficient;
if the number of the free flash memory blocks of the memory is smaller than the preset number, determining that the free space of the memory is insufficient.
7. A memory controller, comprising:
the system comprises an acquisition module, a storage module and a control module, wherein the acquisition module is used for acquiring the state of a storage, and the state of the storage comprises a power-on state, a power-off state and an operation state;
and the filling module is used for writing filling data into the flash memory block of the memory according to the state of the memory until the filling data is written into the safe data page of the flash memory block.
8. The memory controller of claim 7, wherein the population module is specifically configured to:
and when the memory is in a power-on state or a power-off state, starting writing the filling data from the next page of the word line corresponding to the current writing position until the filling data is written to the safety data page corresponding to the word line, wherein the flash memory block comprises at least one word line, and each word line corresponds to one safety data page.
9. A memory, comprising:
at least one processing unit; the method comprises the steps of,
a memory unit in communication with the at least one processing unit; wherein,,
the memory stores instructions executable by the at least one processing unit to cause the at least one processing unit to perform the data processing method of any of claims 1-6.
10. A non-transitory computer readable storage medium storing computer executable instructions which, when executed by a memory, cause the memory to perform the data processing method of any of claims 1-6.
CN202310403204.9A 2023-04-14 2023-04-14 Data processing method, memory controller, memory and storage medium Pending CN116560568A (en)

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