CN116560564A

CN116560564A - Data processing method, flash memory and storage device

Info

Publication number: CN116560564A
Application number: CN202310309686.1A
Authority: CN
Inventors: 黄涛; 严雪过; 梁永贵
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2023-03-27
Filing date: 2023-03-27
Publication date: 2023-08-08

Abstract

The application provides a data processing method, a flash memory and storage equipment, and relates to the technical field of data storage. In the method, a target plane of the flash memory includes a first page register, a second page register, a first memory space, and a second memory space. Based on the first page register, the flash memory can execute the second instruction based on the second page register at the same time in the process of executing the first instruction, thereby realizing parallel execution of the first instruction and the second instruction. Because the flash memory can execute the first instruction and the second instruction in parallel based on different page registers, the second instruction does not need to wait for the execution of the first instruction to be completed and then executed, and does not need to occupy the first page register used for executing the first instruction, thus effectively avoiding the waiting time delay of the second instruction under the condition of ensuring that the first instruction can be normally executed, and improving the performance of the flash memory.

Description

Data processing method, flash memory and storage device

Technical Field

The present disclosure relates to the field of data storage technologies, and in particular, to a data processing method, a flash memory, and a storage device.

Background

Currently, flash memory is generally composed of a plurality of Logical Units (LUNs), and one logical unit is generally composed of planes (planes). In the related art, a sequential execution policy is adopted for a plurality of operations of a plane by a flash memory, in this case, an operation to be executed needs to wait for the execution of the operation currently being executed to finish, and then the execution can be started, which results in an extended execution duration of the operation to be executed, and thus, poor performance of the flash memory is caused.

Therefore, how to improve the performance of the flash memory is a technical problem to be solved.

Disclosure of Invention

The embodiment of the application provides a data processing method, a flash memory and a storage device, wherein in the process of executing one operation, the other operation can be executed in parallel, which is beneficial to improving the performance of the flash memory.

In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

in a first aspect, a data processing method is provided, for a flash memory of a storage device, where the flash memory includes a target plane, and the target plane includes a first page register, a second page register, a first storage space, and a second storage space; the method comprises the following steps: in response to a first instruction, performing a first operation on a first memory space based on a first page register; the first instruction is used for indicating to execute a first operation on the first storage space, and the first instruction comprises a read instruction, a write instruction or an erase instruction; in the process of executing the first instruction, responding to a second instruction, and executing a second operation on a second storage space based on a second page register; the second instructions are used for indicating to execute a second operation on the second storage space; the second instruction includes a read instruction, a write instruction or an erase instruction

In this embodiment, the target plane of the flash memory includes a first page register, a second page register, a first memory space, and a second memory space. Based on this, in the process of executing the first instruction (such as a write instruction, a read instruction or an erase instruction) in the flash memory based on the first page register, that is, based on the first page register, the flash memory may execute the second instruction based on the second page register at the same time, that is, based on the second page register, the flash memory may execute the second operation on the second memory space, thereby implementing the parallel execution of the first instruction and the second instruction.

On the one hand, the flash memory executes the first instruction and the second instruction in parallel based on different page registers, so that the second instruction does not need to wait for the first instruction to be executed and then executed, that is, the first page register is not needed to be idle, and then the second instruction is executed based on the first page register, and the first page register needed by executing the first instruction is not needed to be occupied, therefore, under the condition that the first instruction can be normally executed, the waiting time delay of the second instruction is effectively avoided, and the performance of the flash memory is improved. On the other hand, since the second instruction is executed in parallel during the execution of the first instruction, the number of second instructions executed per unit time of the flash memory can also be increased.

In one possible implementation, the first memory space is a first page and the second memory space is a second page, wherein the first page and the second page are different pages.

In the implementation manner, the first storage space is the first page, the second storage space is the second page, and the first page and the second page are different pages, so that the flash memory can execute different instructions on different pages in parallel, and compared with executing different instructions on the same page in parallel, the data accuracy of the second instruction can be prevented from being influenced by the executed first instruction.

In another possible implementation, the first storage space is a first block, the second storage space is a page in a second block, and the first block and the second block are different blocks.

In the implementation manner, the first storage space is a first block, the second storage space is a page in a second block, and the first block and the second block are different blocks, so that the flash memory can execute different instructions in parallel for different blocks, and compared with executing different instructions in parallel for the same block, the method can avoid the executed first instruction from influencing the data accuracy of the second instruction.

In another possible implementation manner, the first instruction is a write instruction, where the write instruction includes data to be written and an address to be written, the address to be written is an address corresponding to the first storage space, and the write instruction is used for indicating writing the data to be written into the first storage space; based on the first page register, performing a first operation on the first memory space, comprising: writing data to be written into a first page register; and writing the data to be written in the first page register into the first storage space.

In this implementation, a specific implementation of the write instruction is provided. In the execution mode, the flash memory writes the data to be written into the first page register, and writes the data to be written in the first page register into the first storage space, so that the data to be written is written into the first storage space based on the first page register. Because the second page register is not needed for executing the write instruction, the second page register is ensured to be used for executing the second instruction, and further, the problem that the second instruction cannot be executed due to the fact that no free page register exists in the process of executing the write instruction by the flash memory is avoided.

In another possible implementation manner, the first instruction is an erase instruction, where the erase instruction includes an address to be erased, the address to be erased is an address corresponding to the first storage space, and the erase instruction is used to instruct to perform erasing on the first storage space; based on the first page register, performing a first operation on the first memory space, comprising: writing a preset value into a first page register; writing a preset value in a first page register into a first storage space; the preset value is used for indicating that the first storage space is in an erased state.

In this implementation, a specific implementation of the erase instruction is provided. Because the data in the erased storage space on the flash memory is the preset value (such as FFH), in this implementation manner, the flash memory erases the first storage space based on the first page register by writing the preset value into the first page register and writing the preset value in the first page register into the first storage space. The second page register is not needed for executing the erasing instruction, so that the second page register is ensured to be used for executing the second instruction, and further, the problem that the second instruction cannot be executed due to the fact that no free page register exists in the process of executing the erasing instruction in the flash memory is avoided.

In another possible implementation manner, the second instruction is a read instruction, where the read instruction includes an address to be read, where the address to be read is an address corresponding to the second storage space, and the read instruction is used to instruct to perform a read operation on the second storage space; performing a second operation on a second memory space based on the second page register, comprising: reading data in the second storage space to a second page register; and returns the data in the second page register to the device that sent the read instruction.

In this implementation, a specific implementation of the read instruction is provided. In the execution mode, the flash memory reads the data in the second storage space to the second page register, and returns the data in the second page register to the device for sending the read instruction, so that the data to be read is returned to the device for sending the read instruction based on the second page register. Because the first page register is not needed for executing the read instruction, the first page register can be used for executing the first instruction, the first page register is prevented from being used by the first instruction in the process of executing the read instruction by the flash memory, and the influence of the read instruction executed later on the execution performance of the first instruction executed earlier is further avoided.

In another possible implementation manner, the method further includes: responding to the target read instruction, and returning the data in the second page register to the device sending the target read instruction; the target read instruction is used for indicating to read the data in the second storage space.

In this implementation, since the write command/erase command and the read command are executed based on different page registers, respectively, after the flash memory executes the read command, the second page register stores the data in the second storage space. Based on the above, after the target read instruction is received by the flash memory, the data in the second page register can be directly returned, so that the hit rate of the second page register is improved, and the operation of reading the data in the second storage space to the second page register is not required to be repeatedly executed, so that the execution duration of the target read instruction is shortened, and the execution efficiency of the target read instruction is improved.

In another possible implementation manner, the read instruction is a sequential read instruction, the address to be read is a start address of the sequential read instruction, and the sequential read instruction further includes a target value, where the target value is used to indicate the amount of data to be read; performing a second operation on a second memory space based on the second page register, comprising: and based on the second page register, starting from a starting space corresponding to the starting address, sequentially executing reading operation on a plurality of subspaces of the second storage space, wherein the addresses of the subspaces are arranged in sequence, the starting space is a subspace with the address arranged at the first position in the subspaces, and the number of times of executing the reading operation corresponds to the target value.

In the implementation manner, the read instructions are set as sequential read instructions, so that the quantity of the read data in the flash memory is the target value in the process of executing the first instruction, and in this way, in the process of executing the first instruction in the flash memory, the quantity of the read data in the flash memory is improved, and the variety of the types of the read instructions executed in the flash memory is improved.

In another possible implementation manner, the second instruction is a write instruction, where the write instruction includes data to be written and an address to be written, where the address to be written is an address corresponding to the second storage space, and the write instruction is used to instruct writing the data to be written into the second storage space; performing a second operation on a second memory space based on the second page register, comprising: writing data to be written into a second page register; and writing the data to be written in the second page register into the first storage space.

In this implementation, a specific implementation of the write instruction is provided. In the implementation manner, the flash memory writes the data to be written into the second page register, and writes the data to be written in the second page register into the second storage space, so that the data to be written is written into the second storage space based on the second page register. Because the first page register is not needed for executing the write instruction, the first page register can be used for executing the first instruction, the first page register is prevented from being used in the process of executing the write instruction by the flash memory, and the performance of the first instruction (such as the write instruction or the erase instruction) executed first by the write instruction executed later is prevented from being influenced by the write instruction executed later.

In another possible implementation manner, the write instruction is a sequential write instruction, the address to be written is a start address of the sequential write instruction, and the sequential write instruction further includes a target value, where the target value is used to indicate the amount of data to be written; performing a second operation on a second memory space based on the second page register, comprising: and based on the second page register, starting from a starting space corresponding to the starting address, sequentially executing write operation on a plurality of subspaces of the second storage space, wherein the addresses of the subspaces are arranged in sequence, the starting space is a subspace with the address arranged at the first position in the subspaces, and the number of times of executing write operation corresponds to the target value.

In the implementation manner, the write instruction is set as the sequential write instruction, so that the quantity of the written data in the flash memory is the target value in the process of executing the first instruction, and in this way, in the process of executing the first instruction in the flash memory, the quantity of the written data in the flash memory is improved, and the variety of the types of the executed write instruction is improved.

In another possible implementation manner, the target plane further includes at least one third storage space, and in a case where the execution duration of the first instruction is longer than the execution duration of the second instruction, the method further includes: in the process of executing the first instruction, and after the second instruction is executed, responding to at least one third instruction, and executing at least one third operation on at least one third storage space based on the second page register; wherein the third instruction includes a read instruction, a write instruction, or an erase instruction.

In this implementation manner, in the case that the execution duration of the first instruction is longer than that of the second instruction, for example, the first instruction is a write instruction/an erase instruction, the second operation is a read instruction, and the flash memory responds to the at least one third instruction and executes the at least one third operation on the at least one third storage space, so that during the process of executing the write instruction/the erase instruction, the flash memory can execute as many other instructions, for example, the read instruction, in parallel, which is helpful to improve the bandwidth of the other instructions of the flash memory.

In another possible implementation manner, the method further includes: receiving a query instruction; the query instruction is used for indicating the execution result of the first instruction; responding to the inquiry instruction, and returning an execution result of the first instruction to the equipment sending the inquiry instruction; the execution result of the first instruction includes execution success or execution failure.

In the implementation manner, when the first instruction is a write instruction/erase instruction and the second instruction is a read instruction, the flash memory returns an execution result of the first instruction by responding to the query instruction, so that the first instruction and the second instruction are changed into asynchronous operation.

In another possible implementation manner, the target plane further includes a third page register and a fourth storage space, where the third page register is used for caching data to be written into the target plane or used for caching data read out from the target plane, and the method further includes: in the process of executing the first instruction and/or the second instruction, responding to a fourth instruction, and executing a fourth operation on a fourth storage space based on a third page register; the fourth instruction is used for indicating to execute a fourth operation on the fourth storage space; the fourth instruction includes a read instruction, a write instruction, or an erase instruction, and the fourth operation includes a read operation, a write operation, or an erase operation.

In this implementation manner, by setting the target plane to further include the third page register and the fourth storage space, the flash memory can execute three instructions, such as the first instruction, the second instruction, the fourth instruction, etc., in parallel, which is helpful for further improving the performance of the flash memory.

In a second aspect, a data processing method is provided, for a flash memory of a storage device, where the flash memory includes a target plane, and the target plane includes a first page register, a second page register, a first storage space, and a second storage space; the method comprises the following steps: responding to a writing instruction, writing data to be written into a first page register, and writing the data to be written in the first page register into a first storage space; the writing instruction comprises data to be written and an address to be written, wherein the address to be written is an address corresponding to the first storage space; in the process of executing the write instruction, responding to the read instruction, reading the data in the second storage space to a second page register, and returning the data in the second page register to the device for sending the read instruction; the read instruction comprises an address to be read, and the address to be read is an address corresponding to the second storage space.

In this scheme, the target plane of the flash memory includes a first page register, a second page register, a first memory space, and a second memory space. Based on the above, in the process of executing the write instruction by the flash memory based on the first page register, that is, writing the data to be written into the first page register and writing the data to be written in the first page register into the first storage space, the flash memory can execute the read instruction simultaneously based on the second page register, that is, reading the data in the second storage space into the second page register and returning the data in the second page register to the device sending the read instruction, thereby realizing parallel execution of the write instruction and the read instruction. On the one hand, the flash memory performs the write instruction and the read instruction in parallel based on different page registers, so that the read instruction does not need to wait for the write instruction to be performed and then performed, that is, the first page register is not needed to be idle, and then the read instruction is performed based on the first page register, and the first page register used for performing the write instruction is not needed to be occupied, therefore, under the condition that the write instruction can be normally performed, the waiting time delay of the read instruction is effectively avoided, and the performance of the flash memory is improved. On the other hand, since the read instruction is executed in parallel during the execution of the write instruction, the bandwidth of the read instruction can also be increased.

In another possible implementation manner, the read instruction is a sequential read instruction, the address to be read is a start address of the sequential read instruction, and the sequential read instruction further includes a target value, where the target value is used to indicate the amount of data to be read; in response to a read instruction, reading data in the second memory space to the second page register and returning the data in the second page register to the device sending the read instruction, comprising: responding to a sequential reading instruction, sequentially reading data of a plurality of subspaces of a second storage space to a second page register from a start space corresponding to a start address, and sequentially returning the data in the second page register to equipment for sending the sequential reading instruction; the addresses of the subspaces are arranged in sequence, the initial space is a subspace with the addresses arranged in the first subspace, and the number of the subspaces corresponds to the target value.

In another possible implementation, the target plane further includes at least one third storage space; the method further comprises the steps of: in the process of executing the write instruction, and after the read instruction is executed, at least one read operation is executed on at least one third storage space based on the second page register in response to at least one third read instruction.

In another possible implementation manner, the method further includes: receiving a query instruction; the query instruction is used for indicating the execution result of the query writing instruction; responding to the inquiry instruction, and returning an execution result of the write instruction to the equipment sending the inquiry instruction; the execution result of the write instruction includes execution success or execution failure.

In another possible implementation, the target plane further includes a third page register and a third memory space, and the method further includes: in the process of executing the writing instruction and/or the reading instruction, responding to the erasing instruction, and writing a preset value into a third page register; writing a preset value in a third page register into a third storage space; the preset value is used for indicating that the third storage space is in an erased state.

In the second aspect, any possible implementation manner of the technical effects may be referred to the first aspect, and will not be described herein.

In a third aspect, a data processing method is provided, for a flash memory of a storage device, where the flash memory includes a target plane, and the target plane includes a first page register, a second page register, a first storage space, and a second storage space; the method comprises the following steps: writing a preset value into a first page register in response to an erasing instruction, and writing the preset value in the first page register into a first storage space; the erasing instruction comprises an erasing address, wherein the erasing address is an address corresponding to the first storage space; in the process of executing the erasing instruction, responding to the reading instruction, reading the data in the second storage space to a second page register, and returning the data in the second page register to the device for sending the reading instruction; the read instruction comprises an address to be read, and the address to be read is an address corresponding to the second storage space.

In this scheme, the target plane of the flash memory includes a first page register, a second page register, a first memory space, and a second memory space. Based on the above, in the process that the flash memory performs the erasing instruction based on the first page register, that is, the preset value is written into the first page register, and the preset value in the first page register is written into the first storage space, the flash memory can simultaneously perform the reading instruction based on the second page register, that is, the data in the second storage space is read into the second page register, and the data in the second page register is returned to the device sending the reading instruction, thereby realizing the parallel execution of the erasing instruction and the reading instruction.

On the one hand, the flash memory performs the erasing instruction and the reading instruction in parallel based on different page registers, so that the reading instruction does not need to wait for the erasing instruction to be performed and then performed, that is, the first page register is not needed to be idle, and then the reading instruction is performed based on the first page register, and the first page register used for performing the erasing instruction is not needed to be occupied, therefore, under the condition that the erasing instruction can be normally performed, the waiting time delay of the reading instruction is effectively avoided, and the performance of the flash memory is improved. On the other hand, since the read instruction is executed in parallel in the process of executing the erase instruction, the bandwidth of the read instruction can also be increased.

In one possible implementation, the first memory space is a first block, the second memory space is a page of a second block, and the first block and the second block are different blocks.

In another possible implementation manner, the method further includes: receiving a query instruction; the inquiry instruction is used for indicating the execution result of the inquiry erasing instruction; responding to the inquiry command, and returning an execution result of the erasing command to the device sending the inquiry command; the execution result of the erase instruction includes execution success or execution failure.

In another possible implementation, the target plane further includes a third page register and a third block, and the method further includes: in the process of executing the erasing instruction and/or the reading instruction, responding to the writing instruction, and writing the data to be written into the third page register; and writing the data to be written in the third page register into a third storage space.

In the third aspect, reference may be made to the first aspect for any possible technical effect of implementation manner, and details are not repeated here.

In a fourth aspect, a data processing method is provided, for a controller of a storage device, where the storage device further includes a flash memory, the flash memory including a target plane, the target plane including a first page register, a second page register, a first storage space, and a second storage space; the method comprises the following steps: sending a first instruction to a flash memory; the first instruction is used for indicating the flash memory to execute a first operation on the first storage space, and the first instruction comprises a read instruction, a write instruction or an erase instruction; sending a second instruction to the flash memory; the second instruction is used for indicating the flash memory to execute a second operation on the second storage space in the process of executing the first instruction; wherein the second instruction includes a read instruction, a write instruction, or an erase instruction.

In this embodiment, the target plane of the flash memory includes a first page register, a second page register, a first memory space, and a second memory space. Based on the above, after sending the first instruction to the flash memory, the controller continues to send the second instruction to the flash memory, where the second instruction is used to instruct the flash memory to execute the second instruction based on the second page register at the same time in the process of executing the first instruction, so that the flash memory can simultaneously respond to the second instruction in the process of executing the first instruction (such as a read instruction, a write instruction or an erase instruction) based on the first page register, and execute the second instruction (such as a read instruction, a write instruction or an erase instruction) to the second storage space based on the second page register, thereby implementing parallel execution of the first instruction and the second instruction.

On the one hand, the flash memory executes the first instruction and the second instruction in parallel based on different page registers, so that the second instruction does not need to wait for the first instruction to be executed and then executed, that is, the first page register is not needed to be idle, and then the second instruction is executed based on the first page register, and the first page register needed by executing the first instruction is not needed to be occupied, therefore, under the condition that the first instruction can be normally executed, the waiting time delay of the second instruction is effectively avoided, and the performance of the flash memory is improved. On the other hand, since the second instruction is executed in parallel during the execution of the first instruction, the bandwidth of the second instruction can also be increased.

In one possible implementation, the first storage space is a first page and the second storage space is a second page, wherein the first page and the second page are different pages; or the first storage space is a first block, the second storage space is a page in a second block, and the first block and the second block are different blocks.

In another possible implementation manner, the first instruction is a write instruction, where the write instruction includes data to be written and an address to be written, and the address to be written is an address corresponding to the first storage space; the first instruction is used for indicating to write the data to be written into the first storage space; or the first instruction is an erasing instruction, the erasing instruction comprises an address to be erased, the address to be erased is an address corresponding to the first storage space, and the first instruction is used for writing a preset value into the first storage space.

In the implementation manner, since the execution time of the write instruction is 12 times of the execution time of the read instruction, and the execution time of the erase instruction is 180 times of the read instruction, the first instruction is set to indicate that the data to be written is written into the first storage space or the first instruction is used to write the preset value into the first storage space, so that the first instruction with longer execution time is avoided, and the performance of the flash memory when executing the second instruction is influenced.

In another possible implementation manner, the second instruction is a read instruction, where the read instruction includes an address to be read, and the address to be read is an address of the second storage space; the second instruction is used for indicating to read the data of the second storage space.

In the implementation manner, the second instruction is used for indicating to read the data in the second storage space, so that the performance of the flash memory when the flash memory executes the instruction with longer execution time such as the write instruction or the erase instruction can be prevented from being influenced when the flash memory executes the read instruction.

In another possible implementation, the second page register stores data in the second storage space; the method further comprises the steps of: sending a target reading instruction to the flash memory, wherein the target reading instruction is used for indicating to read the data stored in the second storage space; and receiving data in a second page register returned by the flash memory, wherein the data in the second page register is returned by the flash memory in response to the target read instruction.

In this implementation, since the write command/erase command and the read command are executed based on different page registers, respectively, after the flash memory executes the read command, the second page register stores the data in the second storage space. Based on the above, the controller sends the target read instruction to the flash memory to indicate to read the data stored in the second storage space, the flash memory can directly return the data in the second page register, so that the hit rate of the second page register is improved, and the operation of reading the data in the second storage space to the second page register does not need to be repeatedly executed, so that the execution time of the target read instruction is shortened, and the execution efficiency of the target read instruction is improved.

In another possible implementation manner, the read instruction is a sequential read instruction, the address to be read is a start address of the sequential read instruction, and the sequential read instruction further includes a target value, where the target value is used to indicate the amount of data to be read; the sequential reading instruction is used for indicating the flash memory to sequentially execute reading operations on a plurality of subspaces of the second storage space from a starting space corresponding to a starting address in the process of executing the first instruction, wherein the addresses of the subspaces are arranged in sequence, the starting space is a subspace with the address arranged in the first subspace in the subspaces, and the number of times of executing the reading operations corresponds to a target value.

In this implementation manner, when the read instruction is specifically a sequential read instruction, and is used to instruct the flash memory to execute the sequential read operation in the process of executing the first instruction, in this way, in the process of executing the first instruction by the flash memory, the number of data read by the flash memory is improved, and the variety of types of the executed read instruction is also improved.

In another possible implementation manner, the second instruction is a write instruction, where the second instruction includes data to be written and an address to be written, and the address to be written is an address of the second storage space; the second instruction is used for indicating that the data to be written is written into the second storage space.

In another possible implementation manner, the write instruction is a sequential write instruction, the address to be written is a start address of the sequential write instruction, and the write instruction further includes a target value, where the target value is used to indicate the amount of data to be written; the sequential write instruction is used for indicating the flash memory to sequentially execute write operations on a plurality of subspaces of the second storage space from a start space corresponding to the start address in the process of executing the first instruction, wherein the addresses of the subspaces are arranged in sequence, the start space is a subspace with the address arranged in the first subspace in the subspaces, and the number of times of executing the write operations corresponds to the target value.

In this implementation manner, the read instruction is specifically a sequential write instruction, and is used to instruct the flash memory to execute a sequential write operation in the process of executing the first instruction, so that in the process of executing the write instruction/erase instruction in the flash memory, the number of data written in the flash memory is improved, and the variety of types of executed write instructions is also improved.

In another possible implementation, the target plane further includes at least one third storage space; in the case that the execution duration of the first instruction is longer than the execution duration of the second instruction, the method further includes: transmitting at least one third instruction to the flash memory, wherein the at least one third instruction is used for indicating that at least one third operation is performed on at least one third storage space in the process of performing the first operation on the target plane; wherein the third instruction includes a read instruction, a write instruction, or an erase instruction.

In this implementation manner, if the execution duration of the first instruction is longer than the execution duration of the second instruction, and if the first instruction is a write instruction/erase operation instruction and the second operation is a read instruction, the controller sends at least one third instruction to the flash memory to instruct the flash memory to execute at least one third operation on at least one third storage space in the process of executing the first instruction, so that in the process of executing the write instruction/erase instruction in the flash memory, as many other instructions as possible, such as the read instruction, can be executed, which is helpful for improving the bandwidth of other instructions in the flash memory.

In another possible implementation manner, the method further includes: sending a query instruction to the flash memory, wherein the query instruction is used for indicating an execution result of querying the first instruction; and receiving an execution result of the first instruction returned by the flash memory, wherein the execution result of the first instruction comprises execution success or execution failure.

In the implementation manner, when the first instruction is a write instruction/erase instruction and the second instruction is a read instruction, the controller sends a query instruction to the flash memory, so that the flash memory can return an execution result of the first instruction, thereby realizing that the first instruction and the second instruction are changed into asynchronous operation, and further avoiding the first instruction from blocking data return in the execution process of the second instruction.

In another possible implementation, sending a query instruction to the flash memory includes: sending a query instruction to the flash memory within a preset time period after the first instruction is sent; the preset time length is the execution time length of the first instruction.

In the implementation manner, the query instruction is sent to the flash memory by being set in the preset time length sent by the first instruction, so that the flash memory is helped to receive the query instruction after the first instruction is executed, and the accuracy of an execution result is helped to be ensured.

In another possible implementation manner, in a case that the second instruction is a read instruction, sending a query instruction to the flash memory includes: and after receiving the data of the preset value returned by the flash memory, sending a query instruction to the flash memory.

In the implementation manner, after the controller is set to receive the data of the preset value returned by the flash memory, the query instruction is sent to the flash memory, so that the flash memory is facilitated to execute as many read instructions (i.e. the preset values) as possible in the process of executing the write instruction/erase instruction, and further the bandwidth of the read instructions is facilitated to be improved.

In a fifth aspect, there is provided a data processing apparatus comprising: the functional units for executing any of the methods provided in the first aspect, and actions executed by the respective functional units are implemented by hardware or implemented by hardware executing corresponding software. For example, the data processing apparatus may include: a processing unit; a processing unit configured to execute a first operation on the first memory space based on the first page register in response to a first instruction; the first instruction is used for indicating to execute a first operation on the first storage space, and the first instruction comprises a read instruction, a write instruction or an erase instruction; the processing unit is further used for responding to a second instruction and executing a second operation on a second storage space based on a second page register in the process of executing the first instruction; the second instructions are used for indicating to execute a second operation on the second storage space; wherein the second instruction includes a read instruction, a write instruction, or an erase instruction.

In a sixth aspect, there is provided a data processing apparatus comprising: functional units for performing any of the methods provided in the second aspect, the actions performed by the respective functional units are implemented by hardware or by hardware executing corresponding software. For example, the data processing apparatus may comprise a processing unit; the processing unit is used for responding to a writing instruction, writing the data to be written into the first page register and writing the data to be written in the first page register into the first storage space; the writing instruction comprises data to be written and an address to be written, wherein the address to be written is an address corresponding to the first storage space; the processing unit is also used for responding to the read instruction in the process of executing the write instruction, reading the data in the second storage space to the second page register, and returning the data in the second page register to the equipment for sending the read instruction; the read instruction comprises an address to be read, and the address to be read is an address corresponding to the second storage space.

In a seventh aspect, there is provided a data processing apparatus comprising: functional units for performing any of the methods provided in the third aspect, the actions performed by the respective functional units are implemented by hardware or by hardware executing corresponding software. For example, the data processing apparatus may comprise a processing unit; the processing unit is used for responding to the erasing instruction, writing a preset value into the first page register and writing the preset value in the first page register into the first storage space; the erasing instruction comprises an erasing address, wherein the erasing address is an address corresponding to the first storage space; the processing unit is also used for responding to the read instruction in the process of executing the erase instruction, reading the data in the second storage space to the second page register and returning the data in the second page register to the device for sending the read instruction; the read instruction comprises an address to be read, and the address to be read is an address corresponding to the second storage space.

An eighth aspect provides a data processing apparatus, the apparatus comprising: functional units for performing any of the methods provided in the second aspect, the actions performed by the respective functional units are implemented by hardware or by hardware executing corresponding software. For example, the data processing apparatus may include: a transmitting unit; the sending unit is used for sending a first instruction to the flash memory; the first instruction is used for indicating the flash memory to execute a first operation on the first storage space, and the first instruction comprises a read instruction, a write instruction or an erase instruction; the sending unit is also used for sending a second instruction to the flash memory; the second instruction is used for indicating the flash memory to execute a second operation on the second storage space in the process of executing the first instruction; wherein the second instruction includes a read instruction, a write instruction, or an erase instruction.

In a ninth aspect, there is provided a flash memory comprising: the target plane comprises a microprocessor, a first page register, a second page register, a first storage space and a second storage space, wherein the microprocessor is connected with the first page register and the second page register, the first page register is connected with the first storage space, and the second page register is connected with the second storage space.

In the ninth aspect, the flash memory may be configured to perform any one of the methods provided in the first aspect, or any one of the methods provided in the second aspect, or any one of the methods provided in the third aspect.

In a tenth aspect, there is provided a storage device comprising: the controller is in communication connection with the flash memory; the controller is used for sending a read instruction, a write instruction or an erase instruction to the flash memory; the flash memory comprises a target plane, wherein the target plane comprises a microprocessor, a first page register, a second page register, a first storage space and a second storage space, the microprocessor is connected with the first page register and the second page register, the first page register is connected with the first storage space, and the second page register is connected with the second storage space.

Optionally, the storage device includes a solid state disk SSD, an external flash TF card, a secure data SD memory card, or an embedded multimedia card EMMC.

In the tenth aspect, the flash memory may be used to perform any one of the methods provided in the first aspect, or any one of the methods provided in the second aspect, or any one of the methods provided in the third aspect. The controller may be adapted to perform any of the methods provided in the fourth aspect above.

In an eleventh aspect, there is provided a computer device comprising: the storage device is connected with the main board; the storage device comprises a controller and a flash memory, and the controller is in communication connection with the flash memory; the flash memory comprises a target plane, wherein the target plane comprises a microprocessor, a first page register, a second page register, a first storage space and a second storage space, the microprocessor is connected with the first page register and the second page register, the first page register is connected with the first storage space, and the second page register is connected with the second storage space.

In the seventh aspect, the flash memory may be used to perform any one of the methods provided in the first aspect, or any one of the methods provided in the second aspect, or any one of the methods provided in the third aspect. The controller may be adapted to perform any of the methods provided in the fourth aspect above.

In a twelfth aspect, there is provided a computer device comprising: comprising the following steps: the device comprises a processor and a memory, wherein the processor is connected with the memory. The memory is configured to store computer-executable instructions and the processor executes the computer-executable instructions stored in the memory to implement any one of the methods provided in the first, second, third or fourth aspects.

In a thirteenth aspect, there is provided a chip comprising: a processor and interface circuit; the interface circuit is used for receiving the code instruction and transmitting the code instruction to the processor; a processor operable to execute code instructions to perform any of the methods provided in the first, second, third or fourth aspects above.

In a fourteenth aspect, there is provided a computer-readable storage medium storing computer-executable instructions that, when executed on a computer, cause the computer to perform any one of the methods provided in the first, second, third or fourth aspects above.

In a fifteenth aspect, there is provided a computer program product comprising computer-executable instructions which, when run on a computer, cause the computer to perform any one of the methods provided in the first, second, third or fourth aspects above.

The technical effects caused by any implementation manner of the fifth aspect to the fifteenth aspect may refer to the technical effects caused by different implementation manners of the first aspect, and are not repeated here.

Drawings

Fig. 1 is a schematic diagram of a computer device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a memory device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of another computer device according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a flash memory according to an embodiment of the present disclosure;

FIG. 5 is a flowchart of a data processing method according to an embodiment of the present application;

FIG. 6 is a flowchart of another data processing method according to an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating interaction between a controller and a flash memory according to an embodiment of the present application;

FIG. 8 is a schematic diagram illustrating interaction between another controller and a flash memory according to an embodiment of the present disclosure;

FIG. 9 is a flowchart of another data processing method according to an embodiment of the present application;

FIG. 10 is a flowchart of yet another data processing method according to an embodiment of the present application;

FIG. 11 is a schematic diagram of yet another data processing apparatus according to an embodiment of the present application;

FIG. 12 is a schematic diagram of another data processing apparatus according to an embodiment of the present application;

FIG. 13 is a schematic diagram of another data processing apparatus according to an embodiment of the present application;

fig. 14 is a schematic diagram of another data processing apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Wherein, in the description of the present application, "/" means that the related objects are in a "or" relationship, unless otherwise specified, for example, a/B may mean a or B; the term "and/or" in this application is merely an association relation describing an association object, and means that three kinds of relations may exist, for example, a and/or B may mean: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural.

Also, in the description of the present application, unless otherwise indicated, "a plurality" means two or more than two. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.

In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", and the like are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ. Meanwhile, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion that may be readily understood.

First, an application scenario of the embodiment of the present application is described in an exemplary manner.

Flash memory (Flash memory) is a nonvolatile memory (NVRAM), in other words, data in the Flash memory does not disappear after power is turned off.

Currently, flash memory is generally composed of a plurality of logic units, and one logic unit is generally composed of a plurality of planes (planes). Flash memory employs sequential execution policies for multiple instructions of one Plane (Plane) based on the access protocol (ONFI/tggle), in other words, flash memory can execute one instruction on one Plane after executing another instruction on the one Plane.

Illustratively, the plurality of planes includes a first plane including a plurality of memory spaces and a page register (page register), and after the flash memory receives a first instruction (e.g., a write instruction or an erase instruction) for the plurality of memory spaces, the first instruction is executed based on the page register. The flash memory receives a second instruction for the plurality of memory spaces after the first instruction is executed, and receives a third instruction for the plurality of memory spaces after the second instruction is executed based on the page register.

In this case, when the flash memory is used in a scenario with high performance requirements such as artificial intelligence (artificial intelligence, AI) and virtual reality technology (VR), the performance of the flash memory is generally not satisfactory.

In view of this, an embodiment of the present application provides a data processing method, where a target plane of a flash memory includes a first page register, a second page register, a first storage space, and a second storage space. Based on this, in the process that the flash memory responds to the first instruction and performs the first operation (such as a write instruction, a read instruction or an erase instruction) on the first storage space based on the first page register, the second instruction (such as a write instruction, a read instruction or an erase instruction) can be simultaneously performed on the second storage space based on the second page register in response to the second instruction, so that parallel execution of the first instruction and the second instruction is realized. On the one hand, the flash memory executes the first instruction and the second instruction in parallel based on different page registers, so that the second instruction does not need to wait for the first instruction to be executed and then executed, that is, does not need to wait for the first page register to be idle, executes the second instruction based on the first page register, and does not need to occupy the first page register required for executing the first instruction. Therefore, under the condition of ensuring that the first instruction can be normally executed, the waiting time delay of the second instruction is effectively avoided, and the performance of the flash memory is improved. On the other hand, since the second instruction is executed in parallel during the execution of the first instruction, the number of second instructions executed per unit time of the flash memory can also be increased.

Next, an exemplary description is given of a system architecture of an embodiment of the present application.

Fig. 1 is a schematic diagram of a computer device according to an embodiment of the present application.

Referring to fig. 1, a computer device may include a motherboard, a processor, and a storage device. The processor is arranged on the main board and is connected with the storage device through the main board. The number of storage devices may be one or more, and fig. 1 illustrates one storage device.

In this embodiment of the present application, the processor is mainly configured to send a read request, a write request, and the like to the storage device, so as to read data stored in the storage device, write data to be written to the storage device, and the like.

Optionally, the computer device includes a terminal device and a network device.

The terminal devices may include cell phones, augmented reality (augmented reality, AR) devices, virtual Reality (VR) devices, personal digital assistants (personal digital assistant, PDAs), ultra-mobile personal computers (UMPC), tablet computers, notebook computers, netbooks, desktop computers, all-in-one machines, and the like.

The network device may include a server or the like. The server may be one physical or logical server, or may be two or more physical or logical servers sharing different responsibilities, and cooperate to implement various functions of the server.

Alternatively, the processor may comprise a central processing unit (central processing unit, CPU) or a management controller.

Wherein the management controller is completely independent of the CPU of the computer device and can communicate with the CPU through an out-of-band management interface of the computer device. In addition, the management controller may remotely maintain and manage data of the computer device through a dedicated data channel.

By way of example, the management controller may include a monitoring management unit external to the computer device, a management system in a management chip external to the processor, a baseboard management controller (baseboard management controller, BMC), a system management module (system management mode, SMM), and the like. It should be noted that the embodiments of the present application are not limited to the form of the management controller, and the above is merely exemplary. In the following embodiments, only a management controller will be described as an example of a BMC.

It should be noted that different computer devices may be referred to as BMCs differently, for example, some computer devices may be referred to as BMCs, some computer devices may be referred to as iLO, and another computer device may be referred to as iDRAC. Either called BMC or iLO or iracc may be understood as BMC in embodiments of the present invention.

As shown in fig. 2, a schematic diagram of the structure of the memory device shown in fig. 1 is shown.

Referring to fig. 2, the storage device may include a Controller (Controller) and a Flash memory (Flash). Wherein the controller is communicatively coupled to the flash memory via an interface that conforms to the ONFI/TOGGLE protocol.

In this embodiment of the present application, the controller is configured to receive a read request, a write request, and the like sent by the processor, and send a read instruction, a write instruction, and the like to the flash memory in response to the read request, the write request, and the like, so as to read data stored in the flash memory, write data to be written to the flash memory, and the like.

In addition, the controller may be further configured to send an erase instruction to the flash memory to instruct the flash memory to erase the data in the specified memory block.

In this embodiment, the storage device may further include a Volatile Memory (VM), where the volatile memory is located inside the storage device, in other words, the volatile memory is part of the storage device. The volatile memory is communicatively coupled to the controller. The volatile memory is used for storing firmware programs. The controller performs the above actions by running a firmware program in volatile memory.

Alternatively, the storage device may not include a volatile memory, the computer device includes a volatile memory, the volatile memory is disposed on the motherboard and located outside the storage device, and the controller may communicate with the volatile memory on the motherboard, and execute firmware programs in the volatile memory to perform the above actions.

It should be noted that, the setting position of the volatile memory is not limited in the embodiments of the present application. The following description is given by way of example only, and the following description will be given by taking the example in which the volatile memory is located inside the storage device.

In this embodiment, the volatile memory may be a static random-access memory (SRAM) or a dynamic random-access memory (dynamic random access memory, DRAM), etc.

Alternatively, the storage device may be a solid state disk (solid state drive, SSD), an embedded multimedia card (embeded multimedia card, EMMC), an external flash card (TF card), a secure data storage card (secure digital memory card, SD memory card), or the like.

It should be noted that, one storage device may include one or more flash memories, and the number of flash memories configured by different types of storage devices may be the same or different, which is not limited in this embodiment of the present application.

Based on the foregoing, in the first case, the embodiment of the present application may be implemented by the first computer device shown in (a) in fig. 3. In the first computer device, the storage device is an SSD and the processor is a CPU.

In a second case, the embodiments of the present application may be implemented by a second computer device shown in (b) of fig. 3. In the second computer device, the storage device is EMMC and the processor is a management controller.

In a third case, the embodiment of the present application may be implemented by a third computer device shown in (c) of fig. 3. In the third computer device, the storage device is a TF card, and the processor is a CPU.

In a fourth case, the embodiment of the present application may be implemented by a fourth computer device shown in (d) of fig. 3. In the third computer device, the storage device is an SD memory card, and the processor is a CPU.

It should be noted that the embodiments of the present application are not limited to the specific form of the computer device implementing the data processing method in the following embodiments, and the above is merely exemplary. In the following embodiments, only the first computer device will be described as an example.

Alternatively, the Flash memory (Flash) may be a nand Flash memory (NandFlash).

It should be noted that, the embodiments of the present application do not limit the specific form of the flash memory, and the above is only exemplary.

Fig. 4 is a schematic diagram of the structure of the flash memory shown in fig. 2.

In the embodiment of the present application, the flash memory may be sequentially divided into Logical Units (LUNs), planes, blocks (blocks), pages (pages), and cells (cells) from an upper level to a lower level.

Referring to fig. 4, the flash memory may include a plurality of logic units, for example, logic units 1, … …, and logic unit N, respectively, where N is a positive integer greater than 1.

In this embodiment, the flash memory further includes a microprocessor. The microprocessor is in communication connection with the controller and is used for receiving the read instruction, the write instruction, the erase instruction and the like sent by the controller and executing the read instruction, the write instruction, the erase instruction and the like.

By way of example, the microprocessor may be a micro control unit (microcontroller unit, MCU) or the like.

It should be noted that the embodiments of the present application do not limit the specific form of the microprocessor, and the foregoing is merely exemplary.

The read operation is performed for about 50 microseconds, the write operation is performed for about 630 microseconds, and the erase operation is performed for about 9000 microseconds, that is, the read operation is performed for about 12 times the read operation, and the erase operation is performed for about 180 times the read operation.

In the following, taking logic unit 1 as an example, the structure of a plurality of logic units is exemplarily described,

logic cell 1 may include multiple planes, for example, including plane 0 and plane 1.

Optionally, plane 0 includes a plurality of blocks, e.g., block 0, block 2, … …, block B, respectively, where B is an even number greater than 2.

Each of the plurality of blocks may include a plurality of pages, e.g., page 0, page 1, … …, page K, respectively. Wherein K is a positive integer greater than 1.

In this embodiment, plane 0 may also include a first page register (page register 1) and a second page register (page register 2).

Wherein the first page register and the second page register are respectively connected with each page in the plane 0 in a communication way.

In this embodiment, the first page register is used to buffer data to be written in plane 0, and the second page register is used to buffer data read out from plane 0. Based on this, the flash memory executes a write instruction or an erase instruction based on the first page register, and executes a read instruction based on the second page register.

For example, after receiving a write command sent by the controller, the flash memory writes the data to be written carried by the write command into the first page register, and then writes the data to be written in the first page register into page 0 (i.e. the page indicated by the address to be written carried by the write command). After receiving a read instruction sent by the controller, the flash memory firstly reads data in a page 1 (namely, a page indicated by a to-be-read address carried by the read instruction) to a second page register, and then returns the data in the second page register to the controller.

Alternatively, in the embodiment of the present application, the first page register and the second page register may be used to buffer data to be written in the plane 0, and may also be used to buffer data read out from the plane 0. Based on this, the flash memory may execute a read instruction, a write instruction, or an erase instruction based on any one of the free registers.

For example, when a first page register is not idle, that is, the first page register is processing a write instruction, a read instruction, or an erase instruction, an idle second page register may process another write instruction, a read instruction, or an erase instruction.

It is understood that the free page register refers to a page register in which a read instruction, a write instruction, and an erase instruction are not executed.

For example, after receiving a write command sent by the controller, the flash memory writes the data to be written carried by the write command into the free page register (e.g., the first page register), and then writes the data to be written in the first page register into page 0 (i.e., the page indicated by the address to be written carried by the write command). After receiving a read instruction sent by the controller, the flash memory firstly reads data in a page 1 (namely, a page indicated by a to-be-read address carried by the read instruction) to an idle page register (namely, a second page register), and then returns the data in the second page register to the controller.

It should be noted that, the write instruction, the read instruction, or the erase instruction executed by the flash memory may be executed by the microprocessor on the flash memory, or may be executed by other hardware or software programs on the flash memory, which is not limited in this embodiment of the present application.

For the description of plane 1, reference may be made to the above description of plane 0, which is not repeated here.

It should be noted that the embodiments of the present application do not limit the number of logic units in the flash memory, the number of planes in the logic units, the number of blocks in the planes, and the number of pages in the blocks, which are only exemplary.

It should be noted that, the system architecture and the application scenario described in the embodiments of the present application are for more clearly describing the technical solution of the embodiments of the present application, and do not constitute a limitation on the technical solution provided in the embodiments of the present application, and those skilled in the art can know that, with the evolution of the system architecture and the appearance of the new application scenario, the technical solution provided in the embodiments of the present application is also applicable to similar technical problems.

For ease of understanding, the data processing method provided in the present application is described below by way of example with reference to the accompanying drawings. The data processing method is suitable for the computer equipment, the storage equipment and the flash memory shown in the above figures 1 to 4.

In the following, a data processing method according to an embodiment of the present application will be described by taking a storage device as an SSD.

The following embodiments of the present application will exemplarily describe a scheme of a data processing method in four parts.

The first section, in conjunction with FIG. 5, describes the process of the memory device executing a first instruction and a second instruction simultaneously in parallel.

The second part, in conjunction with fig. 6 to 8, describes the procedure of the memory device executing the write instruction and the read instruction in parallel when the first operation is the write instruction and the second operation is the read instruction.

In the third part, in connection with fig. 9, a process of executing the erase command and the read command in parallel by the memory device is described when the first operation is the erase command and the second operation is the read command.

A fourth section, in conjunction with fig. 10, describes the procedure in which the first operation is an erase command, the second operation is a write command, the device is stored, and the erase command and the write command are executed.

Hereinafter, the first part of the embodiment of the present application will be described with reference to fig. 5.

FIG. 5 is a flowchart illustrating a method of data processing according to an exemplary embodiment. Illustratively, the method includes S501-S504.

In this embodiment, the flash memory includes at least one plane, and the at least one plane includes a target plane. Wherein the target plane may be any one of the at least one plane.

In this embodiment, a data processing method is exemplified by a target plane.

The target plane comprises a first page register, a second page register, a first storage space and a second storage space.

S501: the controller sends a first instruction to the flash memory, the first instruction being for instructing to perform a first operation on the first memory space.

Optionally, the first instruction includes a write instruction, an erase instruction, or a read instruction.

The write instruction is used for indicating to execute the write operation on the first storage space, the erase instruction is used for indicating to execute the erase operation on the first storage space, and the read instruction is used for indicating to execute the read operation on the first storage space.

Based on the foregoing, it can be appreciated that the first operation includes a write operation, an erase operation, or a read operation.

In this embodiment, after receiving a first request sent by the CPU, the controller sends a first instruction to the flash memory in response to the first request. When the first request is a write request, the first instruction is a write instruction or an erase instruction. When the first request is a read request, the first instruction is a read instruction.

In one example, the write request is for requesting writing of data to be written to the first storage space, and the first storage space is in an empty or erased state, then the first instruction is a write instruction, in other words, the controller directly instructs the flash memory to write the data to be written to the first storage space.

In another example, the write request is used to request writing of data to be written to the first storage space, and the first storage space stores old data, then the first instruction is an erase instruction, in other words, the controller instructs the flash memory to erase the old data in the first storage space, so that the first storage space is in an erased state. And then, the controller instructs the flash memory to write the data to be written into the first storage space.

S502: the flash memory is responsive to a first instruction to perform a first operation on a first memory space based on a first page register.

In this embodiment, after the flash memory receives the first instruction, the first operation is performed on the first memory space based on the first page register in response to the first instruction. In other words, the flash memory executes the first instruction based on the first page register.

The microprocessor, which may be a flash memory, receives a first instruction and, in response to the first instruction, executes the first instruction based on a first page register.

In this embodiment, the first instruction executed by the flash memory may be executed by the microprocessor of the flash memory, which will not be described later.

Alternatively, S502 includes a plurality of implementation methods, and hereinafter, exemplary description is made by way of modes 1 to 3.

Mode 1: the first instruction is a write instruction, the first instruction comprises an address to be written and data to be written, and the address to be written is an address corresponding to the first storage space.

Based on this, S502 includes: the flash memory is used for responding to a writing instruction, writing data to be written into a first page register, and writing data in the first page register into a first storage space.

In this embodiment, after receiving the write command, the flash memory writes the data to be written into the first page register, and then writes the data to be written in the first page register into the first storage space.

In mode 1, the flash memory writes the data to be written into the first storage space based on the first page register by writing the data to be written into the first page register and writing the data to be written into the first storage space in the first page register. Because the flash memory does not need to use the second page register when executing the write instruction, the second page register can be in an idle state, and further, the first instruction and the second instruction are ensured to have no resource (namely page register) conflict, so that the second page register can be used for executing the second instruction, and the problem that the second instruction cannot be executed due to the fact that the idle page register is not available in the process of executing the write instruction in the flash memory is avoided.

Mode 2: the first instruction is an erasing instruction, the first instruction comprises an address to be erased, and the address to be erased is an address corresponding to the first storage space.

Based on this, S502 includes: the flash memory is used for responding to the erasing instruction, writing a preset value into the first page register, and writing the preset value in the first page register into the first storage space.

The preset value is used for indicating that the first storage space is in an erased state.

It should be noted that the preset value is a value stored in a storage space in an erased state in the related art. Illustratively, the preset value is FFH, where H is used to represent that FF is a hexadecimal value.

For example, after receiving an erase command, the flash memory writes a preset value (such as FFH) into the first page register, and then writes the preset value in the first page register into the first storage space.

It will be appreciated that, since the flash memory in the related art only writes data to the empty or erased memory space, writing the preset value to the first memory space corresponds to marking the first memory space as erased, and thus the flash memory can write data to the first memory space.

It should be noted that, in the embodiment of the present application, the data in the first storage space may be set to a preset value in other manners, for example, the first storage space is subjected to the discharge processing based on the first page register. In addition, the embodiment of the present application may also erase the first storage space by using the erase operation in the related art, in other words, the embodiment of the present application is not limited to how to erase the first storage space.

In mode 2, based on the data in the erased state storage space on the flash memory being a preset value, the flash memory is configured to erase old data in the first storage space based on the first page register by writing the preset value into the first page register and writing the preset value in the first page register into the first storage space. Because the flash memory does not need to use the second page register when executing the erasing instruction, the second page register can be in an idle state, and further, the first instruction and the second instruction are ensured to have no resource (i.e. register) conflict, so that the second page register can be used for executing the second instruction, and the problem that the second instruction cannot be executed due to the fact that the idle page register is not available in the process of executing the erasing instruction in the flash memory is avoided.

Mode 3: the first instruction is a read instruction, and the first instruction comprises an address to be read, wherein the address to be read is an address corresponding to the first storage space.

Based on this, S502 includes: the flash memory reads data in the first memory space to the first page register in response to the read instruction, and returns the data in the first page register to the controller.

In this embodiment, after receiving the read command, the flash memory reads the data in the first storage space to the first page register, and then returns the data in the first page register to the controller.

For other descriptions of mode 3, refer to modes 1 to 2, and are not repeated here.

S503: the controller sends a second instruction to the flash memory.

And the second instruction is used for indicating the flash memory to execute a second operation on the second storage space in the process of executing the first instruction by the flash memory.

In this embodiment, if the first instruction is a write instruction, the process of executing the first instruction includes: and writing the data to be written into the first page register and writing the data to be written in the first page register into the first storage space. If the first instruction is an erase instruction, executing the first instruction includes: writing a preset value into the first page register and writing the preset value in the first page register into the first storage space. If the first instruction is a read instruction, executing the first instruction includes: the data in the first memory space is read to the first page register and returned to the device (i.e., controller) that sent the first instruction.

In this embodiment, after receiving the second request sent by the CPU, the controller does not have to wait for the flash memory to execute the first instruction, and sends the second instruction to the flash memory in response to the second request. Therefore, compared with the related art, after the flash memory executes the first instruction, the controller sends the second instruction to the flash memory, which is helpful to improve the bandwidth of the flash memory, so that more instructions can be received in unit time of the flash memory, and further different instructions can be executed in parallel by the flash memory, thereby improving the performance of the flash memory.

It should be noted that after the controller sends the first instruction to the flash memory, the controller may send the second instruction to the flash memory without confirming whether the flash memory is executing the first instruction, in other words, whether the flash memory starts executing the first instruction or not, the controller may send the second instruction to the flash memory.

For the description of the second request, the second instruction, and the second operation, reference may be made to the description of the first request, the first instruction, and the first operation in S501, which are not repeated herein.

S504: the flash memory performs a second operation on the second memory space based on the second page register in response to the second instruction during execution of the first instruction.

In this embodiment, the flash memory receives the second instruction during the process of executing the first instruction, and because executing the first instruction occupies only the first page register and the second page register is in the idle state, the flash memory can immediately respond to the second instruction and execute the second operation on the second memory space based on the second page register in the idle state. In other words, during execution of a first instruction by the flash memory based on the first page register, the flash memory may execute a second instruction based on the second page register being in an idle state.

Compared with the related art, the second instruction does not need to wait for the execution of the first instruction to be executed, so that the execution duration of the second instruction does not include the duration of waiting for the execution of the first operation to be completed, that is, the waiting duration of the second instruction is avoided, obviously, the execution duration of the second instruction can be obviously reduced, and the performance of the flash memory for executing the second operation is improved.

In this embodiment, the second instruction executed by the flash memory may be executed by the microprocessor of the flash memory, which will not be described later.

Based on this, S504 includes various implementations, and hereinafter, exemplary description is made by way of a to C.

Mode a: the second instruction is a read instruction, and the second instruction comprises an address to be read, wherein the address to be read is an address corresponding to the second storage space.

Based on this, S504 includes: the flash memory reads data in the second memory space to the second page register in response to the read instruction, and returns the data in the second page register to the controller.

In this embodiment, during the process of executing the first instruction based on the first page register, the second page register is in an idle state, and based on this, after the flash memory receives the read instruction, the data in the second storage space is read to the second page register, and then the data in the second page register is returned to the controller.

In the mode a, the flash memory reads the data in the second storage space to the second page register, and returns the data in the second page register to the controller, so that the data to be read is returned to the controller based on the second page register. Because the first page register is not needed for executing the read instruction, the first page register can be used for executing the first instruction, the first page register is prevented from being used in the process of executing the read instruction by the flash memory, and the first instruction executed first is prevented from being influenced by the read instruction executed later.

In this embodiment, the second storage space and the second storage space are different storage spaces.

In this embodiment, the first storage space and the second storage space are set to be different storage spaces, so that data in the first storage space is not used in the process of executing the first instruction on the first storage space by the flash memory, and thus, error data used by the flash memory can be avoided, thereby being beneficial to improving the data accuracy of the second instruction executed later.

In one example, the first memory space is a first block, the second memory space is a page in a second block, and the first block and the second block are different blocks. For example, the first instruction is an erase instruction, and the second instruction is a read instruction or a write instruction.

In this embodiment, by setting the first block and the second block to be different blocks, the data in the first block will not be read in the process of executing the erase command (i.e. the first command) on the first block by the flash memory, so that the flash memory can be prevented from reading error data, for example, a preset value in the first block, thereby helping to improve the data accuracy of the read command (i.e. the second command) executed later.

In another example, the first memory space is a first page and the second memory space is a second page. The first page and the second page may be different pages in different blocks, or the first page and the second page may be different pages in the same block. For example, the first instruction is a write instruction and the second instruction is a read instruction.

In this embodiment, by setting the first page and the second page to be different pages, the data in the first page will not be read in the process of executing the write instruction (i.e. the first instruction) on the first page by the flash memory, so that the flash memory can be prevented from reading error data, thereby helping to improve the data accuracy of the read instruction (i.e. the second instruction) executed later.

The second instruction is originally intended to read new data in the first memory space (i.e. the data to be written in the first instruction), but if the first instruction is not executed, in other words, the data to be written in the first instruction is not written in the first memory space, the second page register reads the data in the first memory space, which results in the second instruction reading erroneous data.

Mode B: the second instruction is a write instruction, and the second instruction comprises an address to be written and data to be written, wherein the address to be written is an address corresponding to the second storage space.

Based on this, S504 includes: the flash memory responds to the writing instruction, writes the data to be written into the second page register, and writes the data to be written in the second page register into the second storage space.

For other descriptions of the mode B, refer to the mode a, and are not repeated here.

Mode C: the second instruction is an erasing instruction, the second instruction comprises an address to be erased, and the address to be erased is an address corresponding to the second block.

Based on this, S504 includes: the flash memory is responsive to an erase instruction to write a preset value into the second page register and to write the preset value in the second page register into the second block.

The preset value is used for indicating that the second block is in an erased state.

For other descriptions of the mode C, refer to the above mode a, and are not repeated here.

In this embodiment, the first instruction and the second instruction may be the same type of instruction, in other words, the first operation and the second operation are the same type of operation. The first operation and the second operation are each a write operation, or are each a read operation, or are each an erase operation, for example.

Alternatively, the first instruction and the second instruction may be different types of instructions, in other words, the first operation and the second operation are different types of operations. Illustratively, the first operation is a write operation or an erase operation, the second operation is a write operation, or the first operation is an erase operation, the second operation is a write operation.

In the above embodiment, after the controller sends the first instruction to the flash memory, the controller continues to send the second instruction to the flash memory, so that the flash memory may receive the second instruction in the process of executing the first instruction on the first storage space. Because the target plane of the flash memory comprises the first page register, the second page register, the first storage space and the second storage space, the flash memory can execute the second instruction based on the second page register at the same time in the process of executing the first instruction based on the first page register, thereby realizing the parallel execution of the first instruction and the second instruction. On the one hand, the flash memory executes the first instruction and the second instruction in parallel based on different page registers, so that the second instruction does not need to wait for the first instruction to be executed and then executed, that is, the first page register is not needed to be idle, and then the second instruction is executed based on the first page register, and the first page register needed by executing the first instruction is not needed to be occupied, therefore, under the condition that the first instruction can be normally executed, the waiting time delay of the second instruction is effectively avoided, and the performance of the flash memory is improved. On the other hand, since the second instructions are executed in parallel during the execution of the first instructions, the number of second instructions executed per unit time of the flash memory can also be increased.

Hereinafter, the second part of the embodiment of the present application will be described with reference to fig. 6 to 8.

FIG. 6 is a flowchart illustrating a method of data processing according to an exemplary embodiment. Illustratively, the method includes S601-S610.

For the description of the flash memory in this embodiment, reference may be made to the first portion, and the description is omitted here.

S601: the controller sends a write command to the flash memory.

The description of S601 refers to the description of the write command in S501, and is not repeated here.

S602: the flash memory performs a write operation to the first memory space based on the first page register in response to the write instruction.

The description of S602 refers to the description of S502 related to the write command, and is not repeated here.

S603: the controller sends a first read command to the flash memory.

The first reading instruction is used for instructing the flash memory to execute a first reading operation on the second storage space.

The first read command includes an address to be read, where the address to be read is an address corresponding to the second storage space, in other words, the first read command is used to instruct to read the data in the second storage space of the target plane.

In this embodiment, the first read instruction may be a sequential read instruction, where the sequential read instruction includes an address to be read and a target value, where the address to be read is a start address of the sequential read instruction, and the target value is used to indicate the amount of data to be read.

In the process of executing the write instruction by the flash memory, the sequential read instruction is used for indicating the flash memory to execute the sequential read operation, in other words, the sequential read instruction is used for indicating the flash memory to sequentially execute the read operation on a plurality of subspaces of the second storage space from a start space corresponding to the start address, wherein the addresses of the subspaces are sequentially arranged, the start space is a subspace with the address arranged at the first in the subspaces, and the number of times of executing the read operation corresponds to the target value.

For example, the number of times the read operation is performed corresponds to the target value, and the number of times the read operation is performed may be the same as the target value. For example, if the target value is 5, 5 read operations are performed. In addition, it is understood that sequential read operations read the same amount of data as the number of times the read operation was performed.

Based on the foregoing, it can be appreciated that when the first instruction is a sequential read instruction, the first read operation is a sequential read operation.

In this embodiment, the storage space read by the sequential read operation is different from the storage space in which the data to be written is written by the write operation.

Illustratively, the write instruction directs writing data to be written to page 0 of the target plane, and the sequential read operation reads data in pages 1 through N of the target plane, N being a positive integer greater than 2. Wherein pages 1 through N are multiple subspaces in the second storage space, and the second storage space may be a block, where each page included in the block is a subspace, and page 0 is different from pages 1, … … and page N.

In this embodiment, the first read command is set as the sequential read command, so that the amount of the read data in the flash memory is the target value in the process of executing the write command, which is helpful for improving the amount of the read data in the flash memory and improving the variety of the types of the read command executed in the process of executing the write command in the flash memory.

Optionally, the target plane further comprises at least one third storage space. The data processing method further comprises the following steps: the controller sends at least one second read instruction to the flash memory. Wherein the at least one second read instruction is for instructing to perform at least one second read operation on the at least one third memory space.

In this embodiment of the present application, after receiving the data requested to be read by the second read instruction returned by the flash memory, the controller sends at least one second read instruction to the flash memory.

It should be noted that the third storage space and the second storage space may be the same storage space, or may be different storage spaces, which is not limited in this embodiment of the present application.

In this embodiment, the total execution duration of the at least one second read instruction is less than or equal to the execution duration of the write instruction.

For example, the duration of the write instruction is about 12 times of the execution duration of the read instruction, and the at least one second read instruction may be 11 read instructions, so that the flash memory may execute 12 read instructions (i.e., 1 first read instruction and 11 second read instructions) during the process of executing the write instruction, which is helpful for fully utilizing the execution time period of the write instruction and maximally improving the bandwidth of the read instruction.

Illustratively, the at least one second read instruction includes read instructions 1, … …, read instruction N, N being a positive integer greater than 1.

Wherein, read instruction 1 is used to indicate data 1, … … in page 1 of the read target plane, and read instruction N is used to indicate data N in page N of the read target plane.

For example, after receiving the data 1 in the page 1 returned by the flash memory, the controller sends the read command 2, … … to the flash memory, and based on the same principle, after receiving the data N-1 in the page N-1 returned by the flash memory, the controller sends the read command N to the flash memory. So far, the controller has sent N read instructions to the flash memory storage.

Because the execution time of the write instruction is about 12 times of the execution time of the read instruction, based on the execution time of the write instruction, the controller sends at least one second read instruction to the flash memory in the process of executing the write instruction by the flash memory, so that at least one read instruction can be executed in the process of executing the write instruction by the flash memory, and the number of the read instructions executed in the unit time of the flash memory can be improved.

It should be noted that "the controller sends at least one second read instruction to the flash memory" may be considered as a specific implementation manner of "sending at least one third instruction to the flash memory in a case where the execution duration of the first instruction is longer than the execution duration of the second instruction".

The description of S603 refers to the description of S503 related to the read instruction, and is not repeated here.

S604: in the process of executing the write instruction, the flash memory responds to the first read instruction and executes the first read operation on the second storage space based on the second page register.

In this embodiment, performing the first read operation on the second memory space based on the second page register includes: and reading the data read by the first read instruction to the second page register, and returning the data in the second page register to the controller.

For example, if the first read command indicates to read the data in the second storage space of the target plane, the flash memory reads the data in the second storage space to the second page register in response to the received first read command and returns the data in the second page register to the controller during execution of the write command.

Optionally, S604 includes: the flash memory performs a sequential read operation based on the second page register in response to the sequential read instruction during execution of the write instruction.

In this embodiment, during the process of executing the write instruction by the flash memory, in response to the sequential read instruction, based on the second page register, a read operation is sequentially executed on a plurality of subspaces of the second storage space from the start space corresponding to the start address.

The second page register is divided into a plurality of subspaces according to addresses in sequence, wherein the subspaces are respectively page 1, … … and page K, and the first subspace of the addresses is page 1.

If the address to be read indicates page 1, the initial space corresponding to the initial address is page 1. If the target value carried by the sequential reading instruction is K, the flash memory sequentially executes the sequential reading operation on pages 1, … … and K from page 1 after receiving the sequential reading instruction. It is understood that the flash memory performs the read operation K times. In other words, the sequential read operation corresponds to K read operations.

FIG. 7 is a schematic diagram showing the interaction between the controller and the flash memory.

Referring to fig. 7, after receiving the sequential reading instruction, the flash memory reads the data 1 in the page 1 to the second page register, and then returns the data 1 in the second page register to the controller. Then, the flash memory sequentially reads data 2, … … in page 2 and data K in page K to the second page register, and sequentially returns data 2, … … and data K in the second page register to the controller.

In this embodiment, by sending the sequential read instruction to the flash memory, so that the flash memory may sequentially perform sequential read operations on multiple pages, not only is the amount of data read in the process of executing the write instruction by the flash memory facilitated, but also the diversity of read instruction types executed in parallel by the flash memory is facilitated.

Optionally, the data processing method further comprises: the flash memory performs at least one second read operation on the at least one third memory space based on the second page register in response to the received at least one second read instruction during execution of the write instruction.

Wherein, at least one second reading instruction corresponds to at least one second reading operation one by one.

FIG. 8 is a schematic diagram showing another interaction between the controller and the flash memory.

Referring to fig. 8, after receiving the read command 1, the flash memory reads the data 1 in the page 1 to the second page register, and then returns the data 1 in the second page register to the controller. Based on the same principle, the flash memory sequentially receives the read instructions 2, … … and the read instruction N, and sequentially returns the data 2, … … and the data N to the controller based on the second page register.

In this embodiment, since the execution duration of the write instruction is about 12 times of the execution duration of the read instruction, the bandwidth of the read instruction executed by the flash memory is improved by executing at least one second read operation on the at least one third memory space based on the second page register in response to the received at least one second read instruction during the execution of the write instruction by the flash memory.

The description of S604 refers to the description of S504 related to the read instruction, and is not repeated here.

S605: the controller receives data returned by the flash memory, wherein the data is read by the first reading instruction.

The first read instruction is for indicating to read data in the second storage space of the target plane, and the data is the data in the second storage space.

In the above embodiment, after sending the write instruction to the flash memory, the controller continues to send the read instruction to the flash memory, so that the flash memory may receive the read instruction in the process of executing the write instruction to the first storage space, where the read instruction is used to instruct to execute the read instruction simultaneously in the process of executing the write instruction. Because the target plane of the flash memory comprises the first page register, the second page register, the first storage space and the second storage space, the flash memory can execute the read instruction based on the second page register at the same time in the process of executing the write instruction based on the first page register, thereby realizing the parallel execution of the write instruction and the read instruction.

On the one hand, the flash memory performs the write instruction and the read instruction in parallel based on different page registers, so that the read instruction does not need to wait for the write instruction to be performed and then performed, that is, the first page register is not needed to be idle, and then the read instruction is performed based on the first page register, and the first page register used for performing the write instruction is not needed to be occupied, therefore, under the condition that the write instruction can be normally performed, the waiting time delay of the read instruction is effectively avoided, and the performance of the flash memory is improved. On the other hand, since the read instructions are executed in parallel during the execution of the write instructions, the number of read instructions executed per unit time of the flash memory can also be increased.

Optionally, S606: the controller sends a target read command to the flash memory.

The target read instruction is used for indicating to read the data in the second storage space.

In this embodiment, after receiving the data in the second page register returned by the flash memory, the controller sends a target read instruction to the flash memory to instruct to read the data in the second storage space.

Optionally, S607: the flash memory returns data in the second page register to the controller in response to the target read instruction.

In some embodiments, since the second page register has data stored in the second memory space, the flash memory does not need to perform an operation of reading the data in the second memory space into the second page register after receiving the target read instruction, but directly performs an operation of returning the data in the second page register to the controller.

In the above embodiment, since the write instruction and the read instruction are executed based on different page registers, respectively, after the flash memory executes the read instruction, the data in the second memory space is stored in the second page register. Based on the above, after the target read instruction is received by the flash memory, the data in the second page register can be directly returned to the controller, so that the hit rate of the second page register is improved, and the operation of reading the data in the second storage space to the second page register does not need to be repeatedly executed, so that the execution time of the target read instruction is shortened, and the execution efficiency of the target read instruction is improved.

Optionally, S608: the controller sends a query instruction to the flash memory to request the execution result of the query write instruction.

In this embodiment, after the first read instruction is executed, for example, after the controller receives the data returned from the flash memory, a query instruction is sent to the flash memory to query the execution result of the write instruction.

In one example, the first read command is a sequential read command, and after receiving the data K returned by the flash memory, the controller sends a query command to the flash memory.

In another example, the controller also sends at least one second read instruction to the flash memory, and after receiving the data N returned by the flash memory, the controller sends a query instruction to the flash memory.

S608 includes various implementations, and is exemplified below by way a through b.

Mode a, S608 includes: and the controller sends a query instruction to the flash memory for a preset time after the write instruction is sent.

In this embodiment, the preset time period may be an execution time period of the write instruction. For example, if the execution duration of the write command is 630 μs, the controller sends a query command to the flash memory after the 630 μs of the write command.

In this embodiment, after the preset time period for sending the write command is set, the query command is sent to the flash memory, which is not only helpful to ensure that the flash memory receives the query command after the write command is executed, but also helps to ensure accuracy of the execution result, for example, it can be avoided that the flash memory returns an execution failure to the controller when the write command is not executed, so that the controller considers that the write command fails to execute successfully. In addition, it is also helpful to end execution of the write instruction as early as possible so that the next operation instruction can be sent to the flash memory.

Mode b, S608 includes: and under the condition that the second instruction is a read instruction, after receiving data of the preset times returned by the flash memory, the controller sends a query instruction to the flash memory.

It should be noted that, the specific value of the preset times is not limited in the embodiment of the present application.

For example, the preset number of times may be determined according to the read command sent by the controller, and as shown above, if the first read command is a sequential read command, the preset number of times may be K. If the controller also sends at least one second read command to the flash memory, the preset number of times may be n+1.

For example, the user may set the preset number of times according to the execution time period of the write instruction and the execution time period of the read instruction, for example, the product of the preset number of times and the execution time period of the read instruction may be set to be greater than or equal to the execution time period of the write instruction.

For example, the execution duration of the write command is 12 times of the execution duration of the read command, in other words, 12 read commands can be executed in parallel in the process of executing one write command by the flash memory, and then the controller can send 12 read commands to the flash memory in the process of executing the write command by the flash memory, so that after receiving 12 data returned by the flash memory, the controller sends a query command to the flash memory.

In this way, after receiving the data of the preset times returned by the flash memory, the query instruction is sent to the flash memory, so that the time period of executing the write instruction by the flash memory is fully utilized, and as many read instructions (i.e. the preset times) as possible can be executed in the process of executing the write instruction, thereby improving the bandwidth of the read instruction.

Optionally, S609: the flash memory responds to the inquiry instruction and returns the execution result of the writing instruction to the controller.

Wherein, the execution result comprises execution success or execution failure.

The success of execution is used for representing that the data to be written is written into the first storage space. The execution failure is used for indicating that the data to be written is not written into the first storage space. The first storage space is not written, which may be a write failure, or the data to be written is not written in the first storage space entirely.

As can be appreciated, in the related art, the principle of asynchronous operation is: each task has one or more callback functions (callbacks), and after the previous task is finished, the callback function is executed instead of executing the next task, and the next task is executed without waiting for the previous task to finish.

Based on the above principle, the controller sends the query instruction to the flash memory, so that the flash memory returns the execution result of the write instruction to the controller, after the flash memory executes the write instruction, the flash memory does not execute the subsequent instruction (i.e. the read instruction), but executes the execution result of the write instruction returned to the controller, i.e. executes the callback function, and the read instruction can start to be executed without waiting for the write instruction to be executed, so that the flash memory can be operated asynchronously when executing the write instruction and executing the read instruction.

Optionally, S610: and the controller receives an execution result of the write instruction returned by the flash memory.

Based on the above, the controller sends the query instruction to the flash memory, on one hand, the flash memory is enabled to respond to the query instruction and return the execution result of the write operation to the controller, so that the write operation and the read operation are changed into asynchronous operation. On the other hand, the controller can determine whether the write instruction is executed based on the execution result returned by the flash memory, so as to determine whether the flash memory has a free page register, and further, if the flash memory has the free page register, continue to send other instructions to the flash memory, so as to further improve the performance of the flash memory.

Hereinafter, a third part of the embodiment of the present application will be described with reference to fig. 9.

FIG. 9 is a flowchart illustrating another data processing method according to an exemplary embodiment. Illustratively, the method includes S901-S910.

S901: the controller sends an erase command to the flash memory.

The description of S901 refers to the description of the erase command in S501, and is not repeated here.

S902: the flash memory performs an erase operation on the first memory space based on the first page register in response to the erase instruction.

The description of S902 refers to the description of the erase command in S502, and is not repeated here.

S903: the controller sends a first read command to the flash memory.

The description of S903 may refer to the description of S603, which is not repeated here.

S904: in the process of executing the erasing instruction, the flash memory responds to the first reading instruction and executes the first reading operation on the second storage space based on the second page register.

The description of S904 may refer to the description of S604, which is not repeated here.

S905: the controller receives data returned by the flash memory, wherein the data is read by the first reading instruction.

The description of S905 may refer to the description of S605, which is not repeated here.

It should be noted that, regarding the technical effect of the third portion, reference may be made to the above second portion, which is not described herein.

S906-S907: see S606-S607 above.

S908: the controller sends a query instruction to the flash memory to query the execution result of the erase instruction.

S909: the flash memory responds to the inquiry instruction and returns the execution result of the erasing instruction to the controller.

The execution result of the erase instruction includes execution success or execution failure.

The success of execution is used to characterize that the first memory space has been successfully erased. The execution failure is used to characterize an unsuccessful erasure of the first memory space.

S910: and the controller receives an execution result of the erasing instruction returned by the flash memory.

For the description of S908-S910, reference may be made to S608-S610, which are not described herein.

Hereinafter, a fourth part of the embodiment of the present application will be described with reference to fig. 10.

Fig. 10 is a flowchart illustrating yet another data processing method according to an exemplary embodiment. Illustratively, the method includes S1001-S1010.

S1001: the controller sends an erase command to the flash memory.

The description of S1001 refers to the description of the erase command in S501, and is not repeated here.

S1002: the flash memory is responsive to an erase instruction to execute the erase instruction on the first memory space based on the first page register.

The description of S1002 refers to the description of the erase command in S502, and is not repeated here.

S1003: the controller sends a first write command to the flash memory.

The first write command is used for indicating to execute a first write operation on the second storage space in the process of executing the erase command in the flash memory.

The description of S1003 may refer to the description of S603, which is not repeated here.

S1004: in the process of executing the erasing instruction, the flash memory responds to the first writing instruction and executes the first writing operation on the second storage space based on the second page register.

The description of S1004 may refer to the description of S604, which is not repeated here.

For the technical effects of the fourth part, reference may be made to the second part, which is not described herein.

S1005: the controller sends a first query instruction to the flash memory, wherein the first query instruction is used for writing an execution result of the instruction.

S1006: the flash memory responds to the first query instruction and returns the execution result of the write instruction to the controller.

S1007: and the controller receives an execution result of the write instruction returned by the flash memory.

For the description of S1005-S1007, reference may be made to S608-S610, which are not described here.

S1008-S1010: see S908-S910 above.

The foregoing description of the solution provided in the embodiments of the present application has been mainly presented in terms of a method. In order to achieve the above functions, the data processing device includes hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The embodiment of the present application may perform the division of the functional modules according to the above method in the exemplary data processing apparatus, for example, the data processing apparatus may include each functional module corresponding to each functional division, or two or more functions may be integrated into one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.

By way of example, fig. 11 shows a schematic diagram of a possible structure of the data processing apparatus (denoted as data processing apparatus 1100) according to the above-described embodiment, where the actions performed by the data processing apparatus 1100 are implemented by a flash memory of a storage device or by the flash memory executing corresponding software. The flash memory comprises a target plane, wherein the target plane comprises a first page register, a second page register, a first storage space and a second storage space. The data processing apparatus comprises a processing unit 1101. A processing unit 1101 for performing a first operation on a first memory space based on a first page register in response to a first instruction; the first instruction is used for indicating to execute a first operation on the first storage space, and the first instruction comprises a read instruction, a write instruction or an erase instruction. For example, S502 shown in fig. 5, S602 shown in fig. 6, S902 shown in fig. 9, S1002 shown in fig. 10. The processing unit 1101 is further configured to perform, in response to a second instruction, a second operation on a second memory space based on a second page register during execution of the first instruction; the second instruction is used for indicating to execute a second operation on the second storage space, and the second instruction comprises a read instruction, a write instruction or an erase instruction. For example, S504 shown in fig. 5, S604 shown in fig. 6, S904 shown in fig. 9, and S1004 shown in fig. 10.

Optionally, the first storage space is a first page, and the second storage space is a second page, wherein the first page and the second page are different pages; or the first storage space is a first block, the second storage space is a page in a second block, and the first block and the second block are different blocks.

Optionally, the first instruction is a write instruction, where the write instruction includes data to be written and an address to be written, the address to be written is an address corresponding to the first storage space, and the write instruction is used for indicating writing the data to be written into the first storage space; the processing unit 1101 specifically is configured to: writing data to be written into a first page register; and writing the data to be written in the first page register into the first storage space.

In another possible implementation manner, the first instruction is an erase instruction, where the erase instruction includes an address to be erased, the address to be erased is an address corresponding to the first storage space, and the erase instruction is used to instruct to perform erasing on the first storage space; the processing unit 1101 specifically is configured to: writing a preset value into a first page register; writing a preset value in a first page register into a first storage space; the preset value is used for indicating that the first storage space is in an erased state.

In another possible implementation manner, the second instruction is a read instruction, where the read instruction includes an address to be read, where the address to be read is an address corresponding to the second storage space, and the read instruction is used to instruct to perform a read operation on the second storage space; the processing unit 1101 specifically is configured to: reading data in the second storage space to a second page register; and returns the data in the second page register to the device that sent the read instruction.

In another possible implementation, the processing unit 1101 is further configured to: responding to the target read instruction, and returning the data in the second page register to the device sending the target read instruction; the target read instruction is used for indicating to read the data in the second storage space.

In another possible implementation manner, the read instruction is a sequential read instruction, the address to be read is a start address of the sequential read instruction, and the sequential read instruction further includes a target value, where the target value is used to indicate the amount of data to be read; the processing unit 1101 specifically is configured to: and based on the second page register, starting from a starting space corresponding to the starting address, sequentially executing reading operation on a plurality of subspaces of the second storage space, wherein the addresses of the subspaces are arranged in sequence, the starting space is a subspace with the address arranged at the first position in the subspaces, and the number of times of executing the reading operation corresponds to the target value.

In another possible implementation manner, the second instruction is a write instruction, where the write instruction includes data to be written and an address to be written, where the address to be written is an address corresponding to the second storage space, and the write instruction is used to instruct writing the data to be written into the second storage space; the processing unit 1101 specifically is configured to: writing data to be written into a second page register; and writing the data to be written in the second page register into the first storage space.

In another possible implementation manner, the write instruction is a sequential write instruction, the address to be written is a start address of the sequential write instruction, and the sequential write instruction further includes a target value, where the target value is used to indicate the amount of data to be written; the processing unit 1101 specifically is configured to: : and based on the second page register, starting from a starting space corresponding to the starting address, sequentially executing write operation on a plurality of subspaces of the second storage space, wherein the addresses of the subspaces are arranged in sequence, the starting space is a subspace with the address arranged at the first position in the subspaces, and the number of times of executing write operation corresponds to the target value.

In another possible implementation manner, the target plane further includes at least one third storage space, and in a case where the execution duration of the first instruction is longer than the execution duration of the second instruction, the processing unit 1101 is further configured to: in the process of executing the first instruction, and after the second instruction is executed, responding to at least one third instruction, and executing at least one third operation on at least one third storage space based on the second page register; wherein the third instruction includes a read instruction, a write instruction, or an erase instruction.

In another possible implementation, the processing unit 1101 is further configured to: receiving a query instruction; the query instruction is used for indicating the execution result of the first instruction; responding to the inquiry instruction, and returning an execution result of the first instruction to the equipment sending the inquiry instruction; the execution result of the first instruction includes execution success or execution failure.

In another possible implementation, the target plane further includes a third page register and a fourth memory space, the third page register being used for caching data to be written into the target plane or for caching data read out from the target plane, and the processing unit 1101 is further configured to: in the process of executing the first instruction and/or the second instruction, responding to a fourth instruction, and executing a fourth operation on a fourth storage space based on a third page register; the fourth instruction is used for indicating to execute a fourth operation on the fourth storage space; the fourth instruction includes a read instruction, a write instruction, or an erase instruction, and the fourth operation includes a read operation, a write operation, or an erase operation.

For a specific description of the above alternative modes, reference may be made to the foregoing method embodiments, and details are not repeated here. In addition, any explanation and description of the beneficial effects of the data processing apparatus 1100 provided above may refer to the corresponding method embodiments described above, and will not be repeated.

By way of example, fig. 12 shows a schematic diagram of one possible configuration of the data processing apparatus (denoted as data processing apparatus 1200) involved in the above-described embodiment, and the actions performed by the data processing apparatus 1200 are implemented by the flash memory of the storage device or by the flash memory executing corresponding software. The flash memory comprises a target plane, wherein the target plane comprises a first page register, a second page register, a first storage space and a second storage space. The data processing apparatus comprises a processing unit 1201. A processing unit 1201, configured to write data to be written into a first page register in response to a write instruction, and write the data to be written in the first page register into a first storage space; the write instruction comprises data to be written and an address to be written, wherein the address to be written is an address corresponding to the first storage space. The processing unit 1201 is further configured to, in response to a read instruction, read data in the second storage space to the second page register and return the data in the second page register to the device that sends the read instruction during the process of executing the write instruction; the read instruction comprises an address to be read, and the address to be read is an address corresponding to the second storage space.

Optionally, the first storage space is a first page, and the second storage space is a second page, wherein the first page and the second page are different pages.

Optionally, the read instruction is a sequential read instruction, the address to be read is a start address of the sequential read instruction, and the sequential read instruction further includes a target value, where the target value is used to indicate the amount of data to be read; the processing unit 1201 is specifically configured to: responding to a sequential reading instruction, sequentially reading data of a plurality of subspaces of a second storage space to a second page register from a start space corresponding to a start address, and sequentially returning the data in the second page register to equipment for sending the sequential reading instruction; the addresses of the subspaces are arranged in sequence, the initial space is a subspace with the addresses arranged in the first subspace, and the number of the subspaces corresponds to the target value.

Optionally, the target plane further comprises at least one third storage space; the processing unit 1201 is also configured to: in the process of executing the write instruction, and after the read instruction is executed, at least one read operation is executed on at least one third storage space based on the second page register in response to at least one third read instruction.

In another possible implementation, the processing unit 1201 is further configured to: receiving a query instruction; the query instruction is used for indicating the execution result of the query writing instruction; responding to the inquiry instruction, and returning an execution result of the write instruction to the equipment sending the inquiry instruction; the execution result of the write instruction includes execution success or execution failure.

In another possible implementation, the target plane further includes a third page register and a third storage space, and the processing unit 1201 is further configured to: in the process of executing the writing instruction and/or the reading instruction, responding to the erasing instruction, and writing a preset value into a third page register; writing a preset value in a third page register into a third storage space; the preset value is used for indicating that the third storage space is in an erased state.

For a specific description of the above alternative modes, reference may be made to the foregoing method embodiments, and details are not repeated here. In addition, any explanation and description of the beneficial effects of the data processing apparatus 1200 provided above may refer to the corresponding method embodiments described above, and will not be repeated.

By way of example, fig. 13 shows a schematic diagram of a possible structure of the data processing apparatus (denoted as data processing apparatus 1300) according to the above embodiment, where the actions performed by the data processing apparatus 1300 are implemented by a flash memory of a storage device or by the flash memory executing corresponding software. The flash memory comprises a target plane, wherein the target plane comprises a first page register, a second page register, a first storage space and a second storage space. The data processing apparatus includes a processing unit 1301. A processing unit 1301 configured to write a preset value into a first page register in response to an erase instruction, and write the preset value in the first page register into a first storage space; the erasing command comprises an erasing address, and the erasing address is an address corresponding to the first storage space. The processing unit 1301 is further configured to, in a process of executing the erase instruction, read data in the second storage space to the second page register in response to the read instruction, and return the data in the second page register to the device that sends the read instruction; the read instruction comprises an address to be read, and the address to be read is an address corresponding to the second storage space.

Optionally, the first storage space is a first block, the second storage space is a page of a second block, and the first block and the second block are different blocks.

Optionally, the read instruction is a sequential read instruction, the address to be read is a start address of the sequential read instruction, and the sequential read instruction further includes a target value, where the target value is used to indicate the amount of data to be read; in response to a read instruction, reading data in the second memory space to the second page register and returning the data in the second page register to the device sending the read instruction, comprising: responding to a sequential reading instruction, sequentially reading data of a plurality of subspaces of a second storage space to a second page register from a start space corresponding to a start address, and sequentially returning the data in the second page register to equipment for sending the sequential reading instruction; the addresses of the subspaces are arranged in sequence, the initial space is a subspace with the addresses arranged in the first subspace, and the number of the subspaces corresponds to the target value.

In another possible implementation, the target plane further includes at least one third storage space; processing unit 1301 is also configured to: in the process of executing the write instruction, and after the read instruction is executed, at least one read operation is executed on at least one third storage space based on the second page register in response to at least one third read instruction.

In another possible implementation, the processing unit 1301 is further configured to: receiving a query instruction; the inquiry instruction is used for indicating the execution result of the inquiry erasing instruction; responding to the inquiry command, and returning an execution result of the erasing command to the device sending the inquiry command; the execution result of the erase instruction includes execution success or execution failure.

In another possible implementation, the target plane further includes a third page register and a third block, and the processing unit 1301 is further configured to: in the process of executing the erasing instruction and/or the reading instruction, responding to the writing instruction, and writing the data to be written into the third page register; and writing the data to be written in the third page register into a third storage space.

For a specific description of the above alternative modes, reference may be made to the foregoing method embodiments, and details are not repeated here. In addition, any explanation and description of the beneficial effects of the data processing apparatus 1300 provided above may refer to the corresponding method embodiments described above, and will not be repeated.

By way of example, fig. 14 shows a schematic diagram of a possible structure of the data processing apparatus (denoted as data processing apparatus 1400) related to the above embodiment, and the actions performed by the data processing apparatus 1400 are implemented by a controller of a storage device or performed by the controller executing corresponding software. The memory device further comprises a flash memory, wherein the flash memory comprises a target plane, and the target plane comprises a first page register, a second page register, a first memory space and a second memory space. The data processing apparatus includes a transmission unit 1401. A transmitting unit 1401 configured to transmit a first instruction to the flash memory; the first instruction is used for indicating the flash memory to execute a first operation on the first storage space, and the first instruction comprises a read instruction, a write instruction or an erase instruction. For example, S501 shown in fig. 5, S601 shown in fig. 6, S901 shown in fig. 9, and S1001 shown in fig. 10. A sending unit 1401, configured to send a second instruction to the flash memory; the second instruction is used for indicating the flash memory to execute a second operation on the second storage space in the process of executing the first instruction; wherein the second instruction includes a read instruction, a write instruction, or an erase instruction. For example, S503 shown in fig. 5, S603 shown in fig. 6, S903 shown in fig. 9, and S1003 shown in fig. 10.

Optionally, the first instruction is a write instruction, where the write instruction includes data to be written and an address to be written, and the address to be written is an address corresponding to the first storage space; the first instruction is used for indicating to write the data to be written into the first storage space; or the first instruction is an erasing instruction, the erasing instruction comprises an address to be erased, the address to be erased is an address corresponding to the first storage space, and the first instruction is used for writing a preset value into the first storage space.

Optionally, the second instruction is a read instruction, where the read instruction includes an address to be read, and the address to be read is an address of the second storage space; the second instruction is used for indicating to read the data of the second storage space.

Optionally, the second page register stores data in a second storage space; the transmitting unit 1401 is further configured to: sending a target reading instruction to the flash memory, wherein the target reading instruction is used for indicating to read the data stored in the second storage space; and receiving data in a second page register returned by the flash memory, wherein the data in the second page register is returned by the flash memory in response to the target read instruction.

Optionally, the read instruction is a sequential read instruction, the address to be read is a start address of the sequential read instruction, and the sequential read instruction further includes a target value, where the target value is used to indicate the amount of data to be read; the sequential reading instruction is used for indicating the flash memory to sequentially execute reading operations on a plurality of subspaces of the second storage space from a starting space corresponding to a starting address in the process of executing the first instruction, wherein the addresses of the subspaces are arranged in sequence, the starting space is a subspace with the address arranged in the first subspace in the subspaces, and the number of times of executing the reading operations corresponds to a target value.

Optionally, the second instruction is a write instruction, where the second instruction includes data to be written and an address to be written, and the address to be written is an address of the second storage space; the second instruction is used for indicating that the data to be written is written into the second storage space.

Optionally, the write instruction is a sequential write instruction, the address to be written is a start address of the sequential write instruction, and the write instruction further includes a target value, where the target value is used to indicate the amount of data to be written; the sequential write instruction is used for indicating the flash memory to sequentially execute write operations on a plurality of subspaces of the second storage space from a start space corresponding to the start address in the process of executing the first instruction, wherein the addresses of the subspaces are arranged in sequence, the start space is a subspace with the address arranged in the first subspace in the subspaces, and the number of times of executing the write operations corresponds to the target value.

Optionally, the target plane further comprises at least one third storage space; in the case where the execution duration of the first instruction is longer than the execution duration of the second instruction, the transmission unit 1401 is further configured to: transmitting at least one third instruction to the flash memory, wherein the at least one third instruction is used for indicating that at least one third operation is performed on at least one third storage space in the process of performing the first operation on the target plane; wherein the third instruction includes a read instruction, a write instruction, or an erase instruction.

Optionally, the transmitting unit 1401 is further configured to: sending a query instruction to the flash memory, wherein the query instruction is used for indicating an execution result of querying the first instruction; and receiving an execution result of the first instruction returned by the flash memory, wherein the execution result of the first instruction comprises execution success or execution failure.

Alternatively, the transmitting unit 1401 specifically functions to: sending a query instruction to the flash memory within a preset time period after the first instruction is sent; the preset time length is the execution time length of the first instruction.

Alternatively, in the case where the second instruction is a read instruction, the transmission unit 1401 is specifically configured to: and after receiving the data of the preset value returned by the flash memory, sending a query instruction to the flash memory.

For a specific description of the above alternative modes, reference may be made to the foregoing method embodiments, and details are not repeated here. In addition, any explanation and description of the beneficial effects of the data processing apparatus 1400 provided above may refer to the corresponding method embodiments described above, and will not be repeated.

The embodiment of the application also provides a computer device, which comprises a processor and a memory, wherein the processor is connected with the memory, the memory stores computer execution instructions, and the processor realizes the data processing method in the embodiment when executing the computer execution instructions. The embodiments of the present application do not set any limit to the specific form of the computer device. For example, the computer device may be a terminal device or a network device. Wherein the terminal device may be referred to as: a terminal, user Equipment (UE), a terminal device, an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent, a user equipment, or the like. The terminal device may be a mobile phone, an augmented reality (augmented reality, AR) device, a Virtual Reality (VR) device, a tablet, a notebook, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (personal digital assistant, PDA), or the like. The network device may be a server or the like in particular. The server may be one physical or logical server, or may be two or more physical or logical servers sharing different responsibilities, and cooperate to implement various functions of the server.

Embodiments of the present application also provide a computer-readable storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform a method performed by any one of the computer devices provided above.

For the explanation of the relevant content and the description of the beneficial effects in any of the above-mentioned computer-readable storage media, reference may be made to the above-mentioned corresponding embodiments, and the description thereof will not be repeated here.

The embodiment of the application also provides a chip. The chip has integrated therein control circuitry and one or more ports for implementing the functions of the computer device described above. Optionally, the functions supported by the chip may be referred to above, and will not be described herein. Those of ordinary skill in the art will appreciate that all or a portion of the steps implementing the above-described embodiments may be implemented by a program to instruct associated hardware. The program may be stored in a computer readable storage medium. The above-mentioned storage medium may be a read-only memory, a random access memory, or the like. The processing unit or processor may be a central processing unit, a general purpose processor, an application specific integrated circuit (application specific integrated circuit, ASIC), a microprocessor (digital signal processor, DSP), a field programmable gate array (field programmable gate array, FPGA) or other programmable logic device, transistor logic device, hardware components, or any combination thereof.

Embodiments of the present application also provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform any of the methods of the above embodiments. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, a website, computer, server, or data center via a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer readable storage media can be any available media that can be accessed by a computer or data storage devices including one or more servers, data centers, etc. that can be integrated with the media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., SSD), etc.

It should be noted that the above-mentioned devices for storing computer instructions or computer programs, such as, but not limited to, the above-mentioned memories, computer-readable storage media, communication chips, and the like, provided in the embodiments of the present application all have non-volatility (non-transparency).

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, a website, computer, server, or data center via a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer readable storage media can be any available media that can be accessed by a computer or data storage devices including one or more servers, data centers, etc. that can be integrated with the media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the present application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present application. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. A data processing method, characterized in that a flash memory for a memory device, the flash memory comprising a target plane, the target plane comprising a first page register, a second page register, a first memory space and a second memory space; the method comprises the following steps:

in response to a first instruction, performing a first operation on the first memory space based on the first page register; the first instruction is used for indicating to execute the first operation on the first storage space, and the first instruction comprises a read instruction, a write instruction or an erase instruction;

in the process of executing the first instruction, responding to a second instruction, and executing a second operation on the second storage space based on the second page register; the second instruction is used for indicating to execute a second operation on the second storage space, and the second instruction comprises a read instruction, a write instruction or an erase instruction.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

the first storage space is a first page, and the second storage space is a second page, wherein the first page and the second page are different pages; or (b)

The first storage space is a first block, the second storage space is a page in a second block, and the first block and the second block are different blocks.

3. A method according to claim 1 or 2, characterized in that,

the first instruction is a write instruction, the write instruction comprises data to be written and an address to be written, the address to be written is an address corresponding to the first storage space, and the write instruction is used for indicating the data to be written into the first storage space; the performing a first operation on the first memory space based on the first page register includes: writing the data to be written into the first page register; writing the data to be written in the first page register into the first storage space; or (b)

The first instruction is an erasing instruction, the erasing instruction comprises an address to be erased, the address to be erased is an address corresponding to the first storage space, and the erasing instruction is used for indicating to erase the first storage space; the performing a first operation on the first memory space based on the first page register includes: writing a preset value into the first page register; writing a preset value in the first page register into the first storage space; the preset value is used for indicating that the first storage space is in an erased state.

4. The method of claim 3, wherein the step of,

the second instruction is a read instruction, the read instruction comprises an address to be read, the address to be read is an address corresponding to the second storage space, and the read instruction is used for indicating to execute a read operation on the second storage space; the performing, based on the second page register, a second operation on the second memory space includes: reading the data in the second storage space to the second page register; and returning the data in the second page register to the device that sent the read instruction.

5. The method of claim 4, wherein the read instruction is a sequential read instruction, the address to be read is a start address of the sequential read instruction, the sequential read instruction further comprising a target value indicating an amount of data to be read; the performing, based on the second page register, a second operation on the second memory space includes:

and based on the second page register, starting from a starting space corresponding to the starting address, sequentially executing reading operation on a plurality of subspaces of the second storage space, wherein the addresses of the subspaces are arranged in sequence, the starting space is a subspace with the address arranged at the first position in the subspaces, and the number of times of executing the reading operation corresponds to the target value.

6. The method of any of claims 1-5, wherein the target plane further comprises at least one third storage space; in the case that the execution duration of the first instruction is longer than the execution duration of the second instruction, the method further includes:

in the process of executing the first instruction, and after the second instruction is executed, responding to at least one third instruction, and executing at least one third operation on the at least one third storage space based on the second page register; wherein the third instruction includes a read instruction, a write instruction, or an erase instruction.

7. A data processing method, characterized in that a flash memory for a memory device, the flash memory comprising a target plane, the target plane comprising a first page register, a second page register, a first memory space and a second memory space; the method comprises the following steps:

responding to a writing instruction, writing data to be written into the first page register, and writing the data to be written in the first page register into the first storage space; the write instruction comprises the data to be written and an address to be written, wherein the address to be written is an address corresponding to the first storage space;

In the process of executing the write instruction, responding to a read instruction, reading the data in the second storage space to the second page register, and returning the data in the second page register to the device sending the read instruction; the read instruction comprises an address to be read, and the address to be read is an address corresponding to the second storage space.

8. The method of claim 7, wherein the first memory space is a first page and the second memory space is a second page, wherein the first page and the second page are different pages.

9. A data processing method, characterized in that a flash memory for a memory device, the flash memory comprising a target plane, the target plane comprising a first page register, a second page register, a first memory space and a second memory space; the method comprises the following steps:

writing a preset value into the first page register in response to an erasing instruction, and writing the preset value in the first page register into the first storage space; the erasing instruction comprises an erasing address, wherein the erasing address is an address corresponding to the first storage space;

In the process of executing the erasing instruction, responding to a reading instruction, reading the data in the second storage space to the second page register, and returning the data in the second page register to the device sending the reading instruction; the read instruction comprises an address to be read, and the address to be read is an address corresponding to the second storage space.

10. The method of claim 9, wherein the first memory space is a first block and the second memory space is a page of a second block, the first block being a different block than the second block.

11. A flash memory, comprising: the target plane comprises a microprocessor, a first page register, a second page register, a first storage space and a second storage space, wherein the microprocessor is connected with the first page register and the second page register, the first page register is connected with the first storage space, and the second page register is connected with the second storage space.

12. The flash memory of claim 11, wherein the memory cells are configured to store the data,

the flash memory is used for responding to a first instruction and executing a first operation on the first storage space based on the first page register; the first instruction is used for indicating to execute the first operation on the first storage space, and the first instruction comprises a read instruction, a write instruction or an erase instruction;

The flash memory is further configured to, in response to a second instruction during execution of the first instruction, perform a second operation on the second storage space based on the second page register; the second instruction is used for indicating to execute a second operation on the second storage space, and the second instruction comprises a read instruction, a write instruction or an erase instruction.

13. A memory device, comprising:

a controller and the flash memory of claim 11 or 12, the controller being communicatively connected to the flash memory; the controller is used for sending a first instruction and a second instruction to the flash memory.

14. A computer device, comprising:

the memory device and motherboard of claim 13, said memory device being connected to said motherboard.