CN116545434B - Frequency trimming circuit applied to frequency-locking ring oscillator - Google Patents

Frequency trimming circuit applied to frequency-locking ring oscillator Download PDF

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CN116545434B
CN116545434B CN202310497166.8A CN202310497166A CN116545434B CN 116545434 B CN116545434 B CN 116545434B CN 202310497166 A CN202310497166 A CN 202310497166A CN 116545434 B CN116545434 B CN 116545434B
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frequency
trimming
resistor
control code
switching transistor
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CN116545434A (en
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Smart Microelectronics Suzhou Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The application discloses a frequency trimming circuit and a trimming method applied to a frequency-locked ring oscillator. The frequency-locked loop oscillator comprises a current-controlled oscillator, an operational amplifier, a frequency-to-voltage converter and a PMOS transistor, wherein the frequency trimming circuit outputs a reference voltage to the operational amplifier, and the frequency trimming circuit comprises: the first trimming unit comprises a first resistor string, a plurality of first switching transistors and a first decoder, wherein one end of each first resistor close to the negative phase input end is connected with the drain electrode of the corresponding first switching transistor, and the source electrode of each first switching transistor is coupled to the ground end; the second trimming unit comprises a second resistor string, a plurality of second switching transistors and a second decoder, wherein one end of each second resistor close to the negative phase input end is connected with the drain electrode of the corresponding second switching transistor, and the source electrode of each second switching transistor is coupled to the negative phase input end. The application has the advantages of linear frequency trimming, uniform frequency trimming precision and small frequency trimming change of the reference voltage.

Description

Frequency trimming circuit applied to frequency-locking ring oscillator
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a frequency trimming circuit and a trimming method for a frequency locked loop oscillator.
Background
Fig. 1 is a basic architecture of a frequency-locked loop oscillator, which is composed of basic modules such as a current-controlled oscillator (Current controlled oscillator, CCO), a frequency-to-voltage converter (F2V converter), an operational amplifier (OTA), resistive voltage-dividing networks R1 and R2, and a PMOS transistor P1. The frequency generated by the oscillation of the CCO is converted into a voltage signal vfb by a frequency-to-voltage converter, the voltage divider network R1 and R2 divide the voltage to obtain a reference voltage vref, and the OTA dynamically adjusts the gate voltage vg of the PMOS transistor P1 by sensing the difference between vfb and vref, thereby dynamically adjusting the current of the CCO to dynamically adjust the frequency value of the CCO. If vfb is below vref, the OTA will cause the vg voltage to decrease, thereby increasing the P1 current, the CCO frequency will increase, and the vfb voltage will also increase. The loop will eventually settle at vfb=vref, at which point the frequency also settles at a certain design value.
The frequency expression of the frequency locked loop oscillator in FIG. 1 isThe resistor R1 and the resistor R2 are two resistors in the resistor divider network, and the resistor Rs and the capacitor Cs come from the frequency-to-voltage converter module, which is not shown in fig. 1. Because of the process deviation, the resistor Rs may have a deviation of about ±15%, and the capacitor Cs may have a deviation of about ±20%, so that the frequency may have a deviation of-27.54% - +47.06%, so that a frequency trimming circuit needs to be added into the circuit. The frequency trimming circuit needs to ensure that the frequency can be trimmed back to the target frequency value under the worst process deviation, so that a certain requirement is put on the trimming range of the frequency. Meanwhile, the trimming precision of the frequency is also required to a certain extent, so that the frequency can be trimmed back to a target frequency value meeting the certain precision requirement.
The trimming control code D <10:0> of 11bits can be used for decoding O <2047:0> through a decoder, and the O <2047:0> can be used for adjusting R1 and R2 through gating one of 2048 switches in a resistor voltage division network, so that trimming of vref voltage is realized, and trimming of frequency is realized. The trimming strategy has the following defects:
1) According to the frequency trimming strategy in the prior art, the frequency is not linear along with the change of the trimming control code, so that the frequency trimming range is asymmetric, for example, the 11bits trimming control code can realize the frequency trimming range of-50% -80%, so that in order to ensure that the negative terminal can have enough frequency trimming range, only the excessive frequency trimming range of the positive terminal can be tolerated, and the excessive design of the frequency trimming range is caused;
2) The frequency is not linear along with the change of the trimming control code, so that the frequency trimming precision is not uniform, for example, the frequency trimming precision is increased along with the increase of the trimming control code, so that the frequency trimming precision is deteriorated; if the frequency trimming precision is to be improved, the number of bits of the trimming control code can only be increased, so that one problem is that the frequency trimming precision can be excessively designed under certain trimming control codes, and the other problem is that the size of a decoder and a switch can be increased, so that the whole area of a circuit is increased;
3) As described in the 1) th, the over design of the frequency trimming range is reflected in that the voltage vref is larger in the variation range of the voltage vref along with trimming control codes, and higher requirements are put forward on the voltage margin of the OTA;
4) The frequency trimming strategy uses a large number of trimming control code bits, and the number of switches is also large, so that the areas of the decoder and the switches are large.
Disclosure of Invention
The application aims to provide a frequency trimming circuit and a trimming method applied to a frequency-locked ring oscillator, which enable frequency trimming linearity, uniform frequency trimming precision, small frequency trimming change of reference voltage, small number of switches and smaller decoder area.
The application discloses a frequency trimming circuit applied to a frequency-locked loop oscillator, the frequency-locked loop oscillator comprises a current control oscillator, an operational amplifier, a frequency-to-voltage converter and a PMOS transistor, the output end of the operational amplifier is coupled to the grid electrode of the PMOS transistor, the drain electrode of the PMOS transistor is coupled to the input of the current control oscillator, the current control oscillator outputs a frequency signal to the frequency-to-voltage converter, the frequency-to-voltage converter converts the frequency signal into a voltage signal and outputs the voltage signal to the positive-phase input end of the operational amplifier, and the frequency trimming circuit outputs a reference voltage to the negative-phase input end of the operational amplifier, wherein the frequency trimming circuit comprises:
The first trimming unit comprises a plurality of first resistor strings connected in series, a plurality of first switching transistors and a first decoder, wherein the first resistor strings are coupled between the negative phase input end and the ground end, one end of each first resistor, which is close to the negative phase input end, is connected with the drain electrode of the corresponding first switching transistor, the source electrode of each first switching transistor is coupled to the ground end, and the first decoder decodes control signals of the first switching transistors according to the coarse adjustment control code; and
The second trimming unit comprises a plurality of second resistor strings connected in series, a plurality of second switching transistors and a second decoder, wherein the second resistor strings are coupled between the negative phase input end and the power supply end, one end of each second resistor, which is close to the negative phase input end, is connected with the drain electrode of the corresponding second switching transistor, the source electrode of each second switching transistor is coupled to the negative phase input end, and the second decoder decodes control signals of each second switching transistor according to the fine tuning control code.
In a preferred embodiment, the first trimming unit includes a six-bit first resistor and a first switching transistor, and the first decoder decodes the six-bit coarse control code into 64 control signals, where the resistances of the first resistors are the same.
In a preferred embodiment, the first switching transistor is an NMOS transistor.
In a preferred embodiment, the second trimming unit includes a six-bit second resistor and a second switching transistor, and the second decoder decodes the six-bit fine tuning control code into 64 control signals, where the resistances of the plurality of second resistors are the same.
In a preferred embodiment, the second switching transistor is an NMOS transistor.
In a preferred embodiment, a first resistor is further coupled between the source of each first switching transistor and ground.
In a preferred embodiment, a second resistor is further coupled between the first resistor string and the negative input.
In a preferred embodiment, a third resistor is further coupled between the second resistor string and the power supply terminal.
The application discloses a frequency trimming method applied to a frequency-locked ring oscillator, which comprises the following steps:
setting the fine control code at a predetermined value;
completely scanning all values of the coarse control code once, and determining the value closest to the target frequency value as the value of the coarse control code; and
And setting the coarse tuning control code at a value closest to a target frequency value, completely scanning all values of the fine tuning control code once, and determining the value closest to the target frequency value as the value of the fine tuning control code.
In a preferred embodiment, the predetermined value is a center value of the fine control code.
Compared with the prior art, the embodiment of the application has the following technical effects:
1) According to the frequency trimming strategy, the coarse tuning frequency is linear along with the change of the trimming control code, the frequency trimming range is symmetrical, the frequency trimming range of +/-55% can be realized by the frequency coarse tuning control code, the frequency deviation caused by the process deviation is covered sufficiently, and the excessive design of the frequency trimming range is avoided;
2) The fine tuning frequency is linear along with the change of the trimming control code, and the frequency trimming control code can realize the frequency trimming precision of 0.1 percent and the frequency trimming precision is uniform;
3) As described in the 1) point, the frequency trimming range of the technical scheme is symmetrical, the excessive design is avoided, the variation range of the reference voltage along with the trimming control code is smaller, and more sufficient voltage margin can be provided for the operational amplifier;
4) The frequency trimming strategy divides trimming control codes into two groups, one group of frequency coarse trimming control codes and one group of frequency fine trimming control codes, so that the number of switches is greatly reduced, and the areas of decoders and switches are also greatly reduced.
The numerous technical features described in the description of the present application are distributed among the various technical solutions, which can make the description too lengthy if all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
Fig. 1 is a schematic diagram of a frequency locked ring oscillator according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a frequency trimming circuit according to an embodiment of the application.
FIG. 3 is a plot of coarse frequency versus decoding of a 6bits coarse control code in accordance with an embodiment of the present application.
Fig. 4 is a plot of fine frequency versus decoding of a 6bits fine control code according to an embodiment of the present application.
Fig. 5 is a flow chart of a frequency trimming method according to an embodiment of the application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be understood by those skilled in the art that the claimed application may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
One embodiment of the application relates to a frequency trimming circuit applied to a frequency-locked loop oscillator. The structure of the frequency-locked loop oscillator as shown in fig. 1, the frequency-locked loop oscillator 100 includes a current-controlled oscillator (CCO) 101, an operational amplifier (OTA) 102, a frequency-to-voltage converter (F2V converter) 103, and a PMOS transistor P1. The output of the operational amplifier 102 is coupled to the gate of the PMOS transistor P1, the drain of the PMOS transistor P1 is coupled to the input of the current controlled oscillator 101, the current controlled oscillator 101 outputs a frequency signal to the frequency-to-voltage converter 103, the frequency-to-voltage converter 103 converts the frequency signal to a voltage signal vfb and outputs to the non-inverting input of the operational amplifier 102, and the frequency trimming circuit 200 outputs a reference voltage vref to the non-inverting input of the operational amplifier 102.
The frequency trimming circuit 200 includes a first trimming unit (trimming resistor R2) and a second trimming unit (trimming resistor R1). The frequency trimming strategy provided by the invention does not adopt a group of trimming control codes to realize a certain frequency trimming range and frequency trimming precision at the same time, but divides the trimming control codes into two groups, namely a group of frequency coarse trimming control codes and a group of frequency fine trimming control codes. Coarse adjustment of frequency is achieved through the size of the trimming resistor R2, and fine adjustment of frequency is achieved through the size of the trimming resistor R1. Compared with the prior art, the frequency trimming strategy has the advantages of being linear in frequency trimming, uniform in frequency trimming precision, small in frequency trimming change of reference voltage, small in switch number, smaller in decoder area and the like.
Referring to fig. 2, the frequency trimming circuit 200 includes a first trimming unit 201 and a second trimming unit 202. The first trimming unit 201 includes a plurality of first resistor strings with first resistors r <63:0> connected in series, a plurality of first switching transistors n <63:0> and a first decoder 203. The first resistor strings are coupled between the negative phase input end and the ground end of the operational amplifier, one end of each first resistor close to the negative phase input end of the operational amplifier is connected with the drain electrode of the corresponding first switching transistor, and the source electrode of each first switching transistor is coupled to the ground end. For example, one end of the first resistor r <0> is connected to the drain electrode of the first switching transistor n <0>, the other end of the first resistor r <0> is connected to one end of the first resistor r <1> and the drain electrode of the first switching transistor n <1>, the gates of the first switching transistors n <63:0> are respectively connected to the control signals freq_coarse <63:0>, and the sources of the first switching transistors n <63:0> are connected to the ground. In one embodiment, a first resistor R1 is further coupled between the source and ground of each first switching transistor n <63:0>. The first decoder 203 decodes CoarseTrim:0 the control signal freq_coarse <63:0> of each first switching transistor according to the coarse control code. In one embodiment, a second resistor R2 is further coupled between the first resistor string and the negative input.
Further, the second trimming unit 202 includes a plurality of second resistor strings connected in series with a plurality of second resistors R <63:0>, a plurality of second switching transistors N <63:0>, and a second decoder 203. The second resistor strings are coupled between the negative phase input end and the power supply end vdd of the operational amplifier, one end of each second resistor, which is close to the negative phase input end of the operational amplifier, is connected with the drain electrode of a corresponding second switching transistor, and the source electrode of each second switching transistor is coupled to the negative phase input end. For example, one end of the second resistor R <0> is connected to the drain electrode of the second switching transistor N <0>, the other end of the second resistor R <0> is connected to one end of the second resistor R <1> and the drain electrode of the second switching transistor N <1>, the grid electrodes of the second switching transistors N <63:0> are respectively connected to the control signals Freq_fine <63:0>, and the source electrodes of the second switching transistors N <63:0> are connected to the negative phase input terminal. The second decoder 203 decodes FineTrim:0 the control signal freq_fine <63:0> of each second switching transistor according to the coarse control code. In one embodiment, a third resistor R3 is further coupled between the second resistor string and the power terminal vdd.
In one embodiment, the first trimming unit includes a six-bit 6-bit first resistor and a first switching transistor, and the first decoder decodes CoarseTrim <5:0> the six-bit 6-bit coarse control code into 64 control signals, wherein the resistances of the first resistors are the same. In one embodiment, the first switching transistor n <63:0> is an NMOS transistor.
In one embodiment, the second trimming unit includes a six-bit 6-bit second resistor and a second switching transistor, and the second decoder decodes FineTrim <5:0> the six-bit 6-bit fine tuning control code into 64 control signals, wherein the resistances of the plurality of second resistors are the same. In one embodiment, the second switching transistor N <63:0> is an NMOS transistor.
In the embodiment of the present application, the first resistor and the second resistor with 6bits are taken as examples, and those skilled in the art should understand that, in other embodiments of the present application, the first resistor string may also use the first resistor with other bits, and the second resistor string may also use the second resistor with other bits, for example, 4bits, 8bits, 16bits, etc., which is not limited by the present application.
Frequency expression by frequency-locked ring oscillatorIt can be known that, since the size of the trimming resistor R2 is proportional to the frequency, the frequency under coarse tuning changes linearly with the trimming control code, and the positive and negative trimming ranges are very symmetrical, which does not cause excessive design of the frequency trimming range, and although the size of the trimming resistor R1 is inversely proportional to the frequency, the frequency under fine tuning also changes linearly with the trimming control code due to the smaller frequency trimming range, and the trimming accuracy is uniform.
The basic steps of frequency trimming are realized by the following steps:
1) Setting a frequency fine tuning control code FineTrim:0 at a center tuning value 0x100000 (32), and then scanning all values CoarseTrim <5:0> from 0 to 63 to find a CoarseTrim <5:0> value closest to a target frequency value;
2) Loading CoarseTrim <5:0> values obtained in step 1), and then scanning FineTrim <5:0> all values from 0 to 63 to find FineTrim <5:0> values closest to the target frequency value;
3) Based on the above two steps, the best CoarseTrim <5:0> value and FineTrim <5:0> value can be found.
Compared with the prior art, the technical scheme of the invention has the advantages of more linear frequency trimming, more uniform frequency trimming precision, smaller frequency trimming change of the reference voltage, greatly reduced number of switches and smaller decoder area.
FIG. 3 is a graph showing the course of a coarse tuning frequency with a 6bits coarse tuning control code decoding. The figure shows that the coarse tuning frequency is linear along with the change of the control code, the frequency trimming range is symmetrical, the 6bits frequency coarse tuning control code can realize the frequency trimming range of +/-55%, the frequency deviation caused by the process deviation is covered sufficiently, and the excessive design of the frequency trimming range is avoided.
FIG. 4 shows the course of the coarse tuning frequency with the decoding of the 6bits fine control code. From the graph, the fine tuning frequency is linear along with the change of the control code, and the 6bits frequency fine tuning control code can realize 0.1% of frequency control precision and has uniform frequency control precision.
Another embodiment of the present application relates to a frequency trimming method applied to a frequency locked loop oscillator, the flowchart of which is shown in fig. 5, and the method includes the following steps:
in step 501, the fine control code is set at a predetermined value. In a preferred embodiment, the predetermined value is a center value of the fine control code.
Step 502, fully scanning all values of the coarse control code through, and determining the value closest to the target frequency value as the value of the coarse control code.
In step 503, the coarse tuning control code is set to the value closest to the target frequency value, all values of the fine tuning control code are scanned completely, and the value closest to the target frequency value is determined as the value of the fine tuning control code.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
The term "coupled to" and its derivatives may be used herein. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between elements that are referred to as being coupled to each other.
This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.
All references mentioned in this specification are to be considered as being included in the disclosure of the application in its entirety so as to be applicable as a basis for modification when necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.

Claims (10)

1. A frequency trimming circuit for a frequency-locked loop oscillator, the frequency-locked loop oscillator comprising a current-controlled oscillator, an operational amplifier, a frequency-to-voltage converter, and a PMOS transistor, an output of the operational amplifier coupled to a gate of the PMOS transistor, a drain of the PMOS transistor coupled to an input of the current-controlled oscillator, the current-controlled oscillator outputting a frequency signal to the frequency-to-voltage converter, the frequency-to-voltage converter converting the frequency signal to a voltage signal and outputting the voltage signal to a positive input of the operational amplifier, the frequency trimming circuit outputting a reference voltage to a negative input of the operational amplifier, wherein the frequency trimming circuit comprises:
The first trimming unit comprises a plurality of first resistor strings connected in series, a plurality of first switching transistors and a first decoder, wherein the first resistor strings are coupled between the negative phase input end and the ground end, one end of each first resistor, which is close to the negative phase input end, is connected with the drain electrode of the corresponding first switching transistor, the source electrode of each first switching transistor is coupled to the ground end, and the first decoder decodes control signals of the first switching transistors according to the coarse adjustment control code; and
The second trimming unit comprises a plurality of second resistor strings connected in series, a plurality of second switching transistors and a second decoder, wherein the second resistor strings are coupled between the negative phase input end and the power supply end, one end of each second resistor, which is close to the negative phase input end, is connected with the drain electrode of the corresponding second switching transistor, the source electrode of each second switching transistor is coupled to the negative phase input end, and the second decoder decodes control signals of each second switching transistor according to the fine tuning control code.
2. The frequency trimming circuit of claim 1, wherein the first trimming unit comprises a six-bit first resistor and a first switching transistor, and the first decoder decodes the six-bit coarse control code into 64 control signals, wherein the resistances of the first resistors are the same.
3. The frequency trimming circuit of claim 2, wherein the first switching transistor is an NMOS transistor.
4. The frequency trimming circuit of claim 1, wherein the second trimming unit comprises a six-bit second resistor and a second switching transistor, and the second decoder decodes the six-bit fine control code into 64 control signals, wherein the resistances of the plurality of second resistors are the same.
5. The frequency trimming circuit of claim 4, wherein the second switching transistor is an NMOS transistor.
6. The frequency trimming circuit of claim 1, wherein a first resistor is further coupled between the source of each first switching transistor and ground.
7. The frequency trimming circuit of claim 1, wherein a second resistor is further coupled between the first resistor string and the negative input.
8. The frequency trimming circuit of claim 1, wherein a third resistor is further coupled between the second resistor string and the power supply terminal.
9. A frequency trimming method applied to a frequency locked loop oscillator, characterized in that a frequency trimming circuit according to any one of claims 1-8 is used, the method comprising the steps of:
setting the fine control code at a predetermined value;
completely scanning all values of the coarse control code once, and determining the value closest to the target frequency value as the value of the coarse control code; and
And setting the coarse tuning control code at a value closest to a target frequency value, completely scanning all values of the fine tuning control code once, and determining the value closest to the target frequency value as the value of the fine tuning control code.
10. The method of frequency trimming according to claim 9, wherein the predetermined value is a center value of the fine control code.
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CN106209083A (en) * 2015-04-29 2016-12-07 中芯国际集成电路制造(上海)有限公司 Annular oscillation circuit and ring oscillator

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