CN116545416A - Quadrature clock generator with duty cycle corrector - Google Patents

Abstract

Quadrature clock generation circuits and techniques are disclosed. An example quadrature clock generator includes: an in-phase (I) clock generation circuit for generating an I clock signal based on a reference clock signal, the I clock signal and the reference clock signal each having a first frequency; a quadrature phase (Q) clock generation circuit for generating a Q clock signal based on the reference clock signal, a rise time control signal, and a fall time control signal, the Q clock signal having the first frequency; and a control circuit for generating the rise time control signal and the fall time control signal based on the I clock signal and the Q clock signal.

Description

Quadrature clock generator with duty cycle corrector

Cross Reference to Related Applications

According to 35USC 119 (e), the present application claims priority and benefit from U.S. provisional patent application No.63/306,408, filed on 3/2 at 2022, which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to circuits and techniques for digital clock generation, and more particularly to generation of quadrature clock signals.

Background

Electronic devices typically employ clock signals for timing and synchronization. For example, a quadrature clock may include an in-phase clock signal and a quadrature phase clock signal, where the quadrature phase clock signal has the same frequency and amplitude as the in-phase clock signal, but is phase shifted by a quarter wavelength, in other words, by 90 ° or pi/2 radians.

The circuitry for generating such quadrature clock signals may be configured to maintain an appropriate duty cycle, amplitude and frequency for each of the in-phase and quadrature-phase clock signals, as well as to maintain a quarter-wavelength phase difference between the in-phase clock signal and the quadrature-phase clock signal.

Disclosure of Invention

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

In some aspects of the present disclosure, circuits and techniques for quadrature clock generation are disclosed. An example quadrature clock generator includes: an in-phase (I) clock generation circuit for generating an I clock signal based on a reference clock signal, the I clock signal and the reference clock signal each having a first frequency; a quadrature phase (Q) clock generation circuit for generating a Q clock signal based on the reference clock signal, a rise time control signal, and a fall time control signal, the Q clock signal having the first frequency; and a control circuit for generating the rise time control signal and the fall time control signal based on the I clock signal and the Q clock signal.

In other aspects of the disclosure, other circuits and techniques for quadrature clock generation are disclosed. An example quadrature clock generator includes: an in-phase (I) clock generation circuit for generating an I clock signal by delaying a reference clock signal, the I clock signal and the reference clock signal each having a first frequency; a quadrature phase (Q) clock generation circuit for generating a Q clock signal by delaying and adjusting a rise time and a fall time of the reference clock signal, the Q clock signal having the first frequency and having a phase offset of 90 ° with respect to the I clock signal; and a control circuit to determine a rise time control signal and a fall time control signal to adjust a rise time and a fall time of the Q clock signal based at least in part on the I clock signal and the Q clock signal.

In further aspects of the present disclosure, circuits and techniques for dual-rail quadrature clock generation are disclosed. An example dual-rail quadrature clock generator includes: an in-phase (I) clock generation circuit for generating a non-inverted I clock signal and an inverted I clock signal based on a non-inverted reference clock signal and an inverted reference clock signal, the non-inverted I clock signal, the non-inverted reference clock signal, and the inverted reference clock signal each having a first frequency; a quadrature phase Q clock generation circuit for generating a non-inverted Q clock signal and an inverted Q clock signal based on the non-inverted reference clock signal, the non-inverted I clock signal, and the inverted Q clock signal, wherein the non-inverted Q clock signal and the inverted Q clock signal have the first frequency; and a control circuit for generating a rise time control signal and a fall time control signal for adjusting a rise time and a fall time of the non-inverted Q clock signal and the inverted Q clock signal, wherein the rise time control signal and the fall time control signal are generated based on the non-inverted I clock signal and the inverted Q clock signal.

Drawings

The present embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

Fig. 1A shows a conventional digital phase splitter circuit that may be used to generate quadrature clock signals.

Fig. 1B shows a timing diagram of the input and output signals of the digital phase splitter circuit of fig. 1A.

Fig. 2 shows a conventional Delay Locked Loop (DLL) circuit for generating a quadrature clock signal.

FIG. 3 illustrates an example quadrature clock generator according to some implementations.

Fig. 4 illustrates an example I-clock delay circuit, which may be one example of the I-clock delay circuit shown in fig. 3.

Fig. 5 shows an example Q clock delay circuit, which may be one example of each of the Q clock delay circuits of fig. 3.

Fig. 6A illustrates an example quadrature clock generator for a dual-rail quadrature clock generation circuit, according to some implementations.

Fig. 6B shows an example control circuit for the quadrature clock generator of fig. 6A.

FIG. 7 illustrates an example IQ phase detection circuit that may be used with the dual rail quadrature clock generation circuit of FIG. 6A, according to some implementations.

Fig. 8 illustrates a timing diagram of input and output signals of the dual rail quadrature clock generation circuit of fig. 6A, according to some implementations.

Detailed Description

In the following description, numerous specific details are set forth, such as examples of specific components, circuits, and processes, in order to provide a thorough understanding of the present disclosure. The term "coupled" as used herein means directly connected or connected through one or more intermediate components or circuits. The terms "electronic system" and "electronic device" may be used interchangeably to refer to any system capable of electronically processing information. Furthermore, in the following description and for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the various aspects of the present disclosure. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the example implementations. In other instances, well-known circuits and devices are shown in block diagram form in order not to obscure the present disclosure. Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory.

These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In this disclosure, a procedure, logic block, process, etc., is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.

Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present disclosure, discussions utilizing terms such as "accessing," "receiving," "transmitting," "using," "selecting," "determining," "normalizing," "multiplying," "averaging," "monitoring," "comparing," "applying," "updating," "measuring," "deriving," or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

In the drawings, a single block may be described as performing one or more functions; however, in actual practice, one or more functions performed by the block may be performed in a single component or across multiple components, and/or may be performed using hardware, using software, or using a combination of hardware and software. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described below generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Further, example input devices may include components other than those shown, including well-known components such as processors, memory, and the like.

The techniques described herein may be implemented in hardware, software, firmware, or any combination thereof, unless specifically described as being implemented in a specific manner. Any features described as modules or components may also be implemented together in an integrated logic device or separately as discrete but interoperable logic devices. If implemented in software, the techniques may be realized at least in part by a non-transitory processor-readable storage medium comprising instructions that, when executed, perform one or more of the methods described above. The non-transitory processor-readable data storage medium may form part of a computer program product, which may include packaging material.

Various implementations generally involve the generation of quadrature clock signals. Some implementations more particularly relate to quadrature clock generators included in integrated circuits. In one implementation, an in-phase (I) clock generation circuit generates an I clock signal based on a reference clock signal, such as by delaying the reference clock signal. Thus, the I clock signal has the same frequency as the reference clock signal. A quadrature phase (Q) clock generation circuit generates a Q clock signal based on a reference clock signal, a rise time control signal, and a fall time control signal. The Q clock signal has the same frequency as the I clock signal (and the reference clock signal), but is phase shifted by 90 degrees with respect to the I clock signal. The control circuit generates a rise time control signal and a fall time control signal based on the I clock signal and the Q clock signal. The rise time control signal and the fall time control signal are used by the Q clock generation circuit to maintain a 90 degree phase offset between the I clock signal and the Q clock signal and to maintain the proper 50% duty cycle of the Q clock signal.

Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. In some implementations, rather than requiring a reference clock signal that is twice the frequency of the desired quadrature clock signal as in some conventional clock generation circuits, the one or more reference clock signals required by the example implementations have the same frequency as the quadrature clock signal generated by the example circuits. This may result in reduced power consumption and heat generation. Furthermore, example implementations may accurately generate quadrature clock signals by determining a phase difference between the I and Q clock signals and correcting for phase mismatch by locking a delay to a 90 degree phase delay between the I and Q clock signals. Further, example implementations may correct any duty cycle mismatch in the Q clock signal in order to ensure accurate clock signal generation for a wide variety of desired clock frequencies.

Fig. 1A shows a conventional digital phase splitter circuit 100A that may be used to generate quadrature clock signals. The digital phase splitter circuit 100A may include a first flip-flop 120, a second flip-flop 130, and an inverter 140. Note that while the first flip-flop 120 and the second flip-flop 130 are shown as D flip-flops, other conventional digital phase splitter circuits may use other types of flip-flops or latches.

The first flip-flop 120 may be clocked by the reference clock signal 110, while the in-phase clock 150 may be generated at the output Q. The output q_bar may be provided at the input D of the first flip-flop 120. The reference clock 110 may be provided to the inverter 140, and the output of the inverter 140 is provided to the input D and the output q_bar of the second flip-flop 130. The quadrature phase clock 160 may be generated at the output q_bar of the second flip-flop 130. Accordingly, the in-phase clock 150 and the quadrature-phase clock 160 may each have a frequency that is half the frequency of the reference clock 110. In other words, for the desired frequencies of clock signals 150 and 160, reference clock 110 having twice the frequency is required.

Fig. 1B shows a timing diagram 100B of input and output signals of the digital phase splitter circuit 100A. Note that reference clock 110 has twice the frequency of in-phase clock 150 and twice the frequency of quadrature-phase clock 160. In other words, the reference clock period 111 is half of the output clock period 151. In addition, note that the phase offset 161 between the quadrature phase clock 160 and the in-phase clock 150 is one-fourth of the output clock period 161.

Fig. 2 illustrates a conventional Delay Locked Loop (DLL) circuit 200 for generating a quadrature clock signal. The DLL circuit 200 includes four delay cells 220 (1) -220 (4) (collectively delay cells 220). Each delay unit is configured to delay the reference clock 210 by a quarter wavelength. For example, each of the delay cells 220 may include an inverter and a capacitor, or another suitable circuit for delaying an input signal. Thus, at the output of the first delay unit 220 (1), the reference clock 210 may be delayed by a quarter wavelength or 90 degrees. The remaining delay stages may have the same structure such that the second delay unit 220 (2) outputs a signal corresponding to the reference clock 210 which has been delayed by half a wavelength or 180 degrees. Similarly, the third delay unit 220 (3) outputs a signal corresponding to the reference clock 210 delayed by three-quarter wavelength or 270 degrees, and the fourth delay unit 220 (4) outputs a signal that should be in phase with the reference clock 210. The DLL circuit 200 outputs an in-phase clock 250 (which may simply be the reference clock 210) and a quadrature phase clock 260 (which may be the output of the first delay unit 220 (1)).

The DLL circuit 200 further includes a delay locked loop 230 that can receive the reference clock 210 and the output of the fourth delay unit 220 (4) and generate a delay control signal for the delay unit 220. Delay locked loop 230 may generate a delay control signal to correct any mismatch between reference clock 210 and the output of delay unit 220 (4), the output of delay unit 220 (4) should be the same and in phase as reference clock 210.

Although the digital phase splitter circuit 100A and the DLL circuit 200 can be used to generate quadrature clock signals, they each have drawbacks. For example, the digital phase splitter circuit 100A requires a reference clock signal having twice the frequency of the desired quadrature clock signal. This may result in undesirably high power consumption or circuit complexity for generating such high frequency reference clock signals. For example, chip-to-chip speeds are increasing due to the bandwidth requirements of high capacity networks and high performance computer systems that may use high resolution video applications such as 4k and 8 k. Further, for backward compatibility and for low power consumption, the interface may also be required to support various data rates, such as 5.4Gbps, 6.75Gbps, 8.1Gbps, 10Gbps, 13.5Gbps, 20Gbps, etc. Furthermore, the digital phase splitter circuit 100A cannot easily adjust for inaccurate duty cycles or phase shifts, which may result in inaccurate clock signals.

The use of the DLL circuit 200 may result in the quadrature clock 260 having a distorted duty cycle because the duty cycle is not controlled and the delay unit 220 of the DLL circuit 200 may distort the duty cycle. In addition, the DLL circuit 200 may experience a harmonic lock problem when the delay provided by the delay locked loop 230 and the delay unit 220 may not lock to one wavelength but may lock to an integer number N of wavelengths. This may lead to functional problems with the DLL circuit 200 or may require additional circuitry to avoid these harmonic lock problems. Furthermore, the delay cells 220 are difficult to match and may not each provide exactly the same amount of delay, which may result in IQ phase delay errors due to such delay cell mismatch.

Thus, it is desirable to generate quadrature clock signals of a wide range of clock frequencies without the need for a dual frequency reference clock, and which can accurately maintain the required phase offset and duty cycle timing between the generated quadrature clock signals.

Example implementations may use fully differential amplifier circuitry to generate quadrature clock signals, and it may use phase detection to detect a phase difference between in-phase (I) and quadrature-phase (Q) clock signals, and adjust the phase offset and duty cycle of the Q clock signals to maintain their desired quarter-wavelength offset and 50% duty cycle.

Fig. 3 illustrates an example quadrature clock generator 300 according to some implementations. The quadrature clock generator 300 receives a reference clock 302, which reference clock 302 may optionally be buffered by a buffer 304. The buffered reference clock 302 may be provided to the I clock delay circuit 306 and one or more Q clock delay circuits 310 (1) -310 (N) (collectively referred to as Q clock delay circuits 310). The I-clock delay circuit may delay the reference clock 302, thereby generating an I-clock 350 that may optionally be buffered by the buffer 308. The I clock 350 has the same frequency as the reference clock 302. Q-clock delay circuits 310 may each delay and adjust the phase offset and duty cycle of reference clock 302 to generate Q-clock 360, which Q-clock 360 may optionally be buffered by buffer 312. Like the I clock 350, the Q clock 360 also has the same frequency as the reference clock 302, but is phase shifted by a quarter wavelength. Each Q-clock delay circuit 310 may also receive a fall time control signal and a rise time control signal, which the Q-clock delay circuit 310 may use to adjust the phase offset and the duty cycle, as discussed in more detail below.

The fall time control signal and the rise time control signal may be generated by a control circuit including a NAND gate 314, a resistor 316, a capacitor 318, a differential amplifier 320, resistors 322, 324, and 326, an amplifier 328, a resistor 330, and a capacitor 332. The NAND gate 314 may receive the I clock 350 at a non-inverting input and the Q clock 360 at an inverting input, outputting an "iqout" signal, which may correspond to the phase difference between the I clock 350 and the Q clock 360. For example, the iqout signal may have a 75% duty cycle when the I and Q clocks 350 and 360 have a desired quarter wavelength or 90 degree phase difference. Note that in some aspects, nand gate 314 may be replaced by a suitable IQ phase detection circuit, as described below.

Resistor 316 and capacitor 318 may generate an "iqout average" signal representing the iqout average. Thus, when the I and Q clocks 350, 360 have an appropriate phase difference of 90 degrees, iqout has on average a value of 75% of the supply voltage of the quadrature clock generator 300, such as 75% of Vdd. The iqout average may be provided at the non-inverting input of the differential amplifier 320. Resistors 322, 324, and 326 may be used to generate another signal having a value of 75% of Vdd, which may be provided at the inverting input of differential amplifier 320. In this way, the fall time control signal provided from the inverted output of the differential amplifier 320 and the rise time control signal provided from the non-inverted output of the differential amplifier 320 may be based on the phase offset between the I clock 350 and the Q clock 360.

Quadrature clock generator 300 may also provide duty cycle correction for Q clock 360. For example, output common mode voltage control for differential amplifier 320 may be provided from the output of amplifier 328. Amplifier 328 has an inverting input coupled to receive a signal having a value of 50% of Vdd that corresponds to the desired 50% duty cycle of Q clock 360. The non-inverting input of amplifier 328 may be coupled to receive a signal corresponding to the average value of Q clock 360. The average value of Q clock 360 may be generated from Q clock 360 using resistor 330 and capacitor 332. The output of amplifier 328 controls the rise time and fall time of Q-clock delay circuit 310 by controlling the output common mode voltage of differential amplifier 320 to adjust the Q-clock 360 duty cycle to 50% because the output of amplifier 328 is based on the difference between the desired 50% duty cycle of Q-clock 360 (represented by the inverting input to amplifier 328) and the actual duty cycle of Q-clock 360 (represented by the non-inverting input to amplifier 328).

Note that while the averaging circuit in fig. 3 is shown as a resistor and a capacitor, such as resistor 316 and capacitor 318, in other aspects other suitable circuits may be used to generate the average signal value.

Fig. 4 illustrates an example I-clock delay circuit 400, which may be one example of the I-clock delay circuit 306 shown in fig. 3. The I-clock delay circuit 400 may include a simple chain of inverters, such as inverters 410 and 430. In other aspects, the I-clock delay circuit may include any number of inverters as long as the output is not inverted relative to the input. The I-clock delay circuit 400 may also include a capacitor 420. Note that for higher frequency clocks, for example for a 10GHz clock, the minimum delay of the Q clock delay circuit may be higher than the desired 90 degree phase difference between the I and Q clocks. An example quadrature clock generator circuit for such a high frequency clock may include a manual delay added to an I clock delay circuit (such as I clock delay circuit 306 or 400) to reduce the I clock and Q clock phase delay difference to the desired 90 degrees.

Fig. 5 shows an example Q clock delay circuit 500, which may be one example of each of the Q clock delay circuits 310 of fig. 3. The Q clock delay circuit 500 may receive a rise time control signal and a fall time control signal, such as from the differential amplifier 320. Q clock delay circuit 500 may also receive an input (such as reference clock 302) or an output from a previous Q clock delay circuit. The input signal may be provided to an inverter 510. The source terminal of inverter 510 may be coupled to the drain terminal of transistor 520 and transistor 520 may be a P-channel metal oxide semiconductor (PMOS) transistor. The source terminal of transistor 520 may be coupled to a supply voltage and the gate terminal of transistor 520 may be coupled to a rise time control signal. The ground terminal of inverter 510 may be coupled to the drain terminal of transistor 530, and transistor 530 may be an N-channel metal oxide semiconductor (NMOS) transistor. The source terminal of transistor 530 may be coupled to ground and the gate terminal of transistor 530 may be coupled to a fall time control signal. The output of inverter 510 may be coupled to capacitor 540 and inverter 550. The output of inverter 550 may be provided as the output of Q clock delay circuit 500.

The Q clock delay unit may be controlled using a rise time control signal and a fall time control signal. For example, when the rise time control signal increases, the rise time delay of the Q clock increases since the transistor 520 becomes weaker. Similarly, as the rise time control signal decreases, the rise time delay of the Q clock decreases as transistor 520 becomes stronger. As the fall time control signal increases, the transistor 530 becomes stronger and the fall time of the Q clock decreases. Similarly, as the fall time control signal decreases, the fall time delay of the Q clock increases.

In some aspects, the quadrature clock generator of the present disclosure may be provided for a dual rail circuit. For example, fig. 6A illustrates an example quadrature clock generator 600A for a dual-rail quadrature clock generation circuit, according to some implementations. The non-inverted reference clock (P reference clock 602) and the inverted reference clock (N reference clock 604) may optionally be provided to the quadrature clock generator 600A after being buffered by respective buffers 606 and 608, rather than a single reference clock as in fig. 3. The P reference clock may be provided to an IP delay circuit 610, and the IP delay circuit 610 may delay the P reference clock 602 and may include a chain of inverters, such as with the I clock delay circuit 400. The output of the IP delay circuit 610 may be provided as a non-inverted I clock signal (IP clock 650) after being optionally buffered by a buffer 612. The N reference clock 604 may be provided to an IN delay circuit 614, the IN delay circuit 614 may delay the N reference clock 604 and may also include a chain of inverters, such as with the I clock delay circuit 400. The output of the IN delay circuit 614 may be provided as an inverted I clock signal (IN clock 655) after being optionally buffered by a buffer 616.

The Q clocks (non-inverted Q clock 660 and inverted Q clock 665) may also be generated similarly to fig. 3. For example, the P reference clock 602 may be provided to one or more QP delay circuits 626 (1) -626 (N) (collectively QP delay circuits 626), each of which may receive a rise time control signal and a fall time control signal. The output of the QP delay circuit 626 can be provided as a QP clock 660 after being optionally buffered by a buffer 628. QP clock 660 may also be coupled to resistor 630 and capacitor 632, and the signal at the node between resistor 630 and capacitor 632 may be referred to as QP load (QP duty). In addition, N reference clocks 604 may be provided to one or more QN delay circuits 634 (1) -634 (N) (collectively QN delay circuits 634), each of which may receive a rise time control signal and a fall time control signal. The output of the QN delay circuit 634 may be provided as a QN clock 665, optionally after buffering by a buffer 636. The QN clock 665 may also be coupled to a resistor 642 and a capacitor 644, and the signal at the node between the resistor 642 and the capacitor 644 may be referred to as a QN load (QN duty).

Note that the QP delay circuit 626 and the QN delay circuit 634 may have the same structure as the Q clock delay circuit 310 or the Q clock delay circuit 500.

The separation of complementary rails, such as the separation of IP clock 650 and IN clock 655, and the separation of QP clock 660 and QN clock 665, may be maintained using any suitable technique, such as using inverter pairs 618/620, 622/624, and 638/640.

The rise time control signal and the fall time control signal may be generated similar to the control circuit of fig. 3. Fig. 6B illustrates an example control circuit 600B for the quadrature clock generator 600A of fig. 6A. The IP clock 650 and the QN clock 665 may be provided to a nand gate 670, the output of which is iqout. Similar to fig. 3, iqout is averaged using resistor 672 and capacitor 674 and provided to differential amplifier 676 at the non-inverting input. The inverting input to the differential amplifier 676 may be a signal having a value corresponding to 75% of the supply voltage of the quadrature clock generator 600A. For example, resistors 678, 680, and 682 coupled between Vdd and ground may be used to generate the signal. Output common mode voltage control for the differential amplifier 676 may be provided from the output of the amplifier 684. The inverting input of the amplifier 684 may be a signal having a value corresponding to 50% of Vdd and the non-inverting input of the amplifier 684 may be the signal QP load (QP duty) shown in fig. 6A. The rise time control signal and the fall time control signal may be respective inverted and non-inverted outputs of the differential amplifier 676.

Although the iqout signal is shown in fig. 3 and 6B as being generated by a nand gate (such as nand gate 314 or nand gate 670), in some other aspects, the iqout may be generated using IQ phase detection circuitry. Fig. 7 illustrates an example IQ phase detection circuit 700 that may be used with the dual-rail quadrature clock generation circuit 600A of fig. 6A, according to some implementations. The first pair of transistors 710 and 720 may each be coupled between a supply voltage (such as Vdd) and iqout. Transistor 710 may have a source terminal coupled to Vdd, a gate terminal coupled to QN clock 665, and a drain terminal coupled to iqout. Transistor 720 may have a drain terminal coupled to Vdd, a gate terminal coupled to QP clock 660, and a source terminal coupled to iqout. The second pair of transistors 730 and 740 may be coupled between Vdd and iqout. Transistor 730 may have a source terminal coupled to Vdd, a gate terminal coupled to IP clock 650, and a drain terminal coupled to iqout. Transistor 740 may have a drain terminal coupled to Vdd, a gate terminal coupled to IN clock 655, and a source terminal coupled to iqout.

The third pair of transistors 750 and 760 and the fourth pair of transistors 770 and 780 may be coupled between iqout and ground. Transistor 750 may have a source terminal coupled to iqout, a gate terminal coupled to IP clock 650, and a drain terminal coupled to a common node between the third pair of transistors 750/760 and the fourth pair of transistors 770/780. The transistor 760 may have a source terminal coupled to a common node between the third pair of transistors 750/760 and the fourth pair of transistors 770/780, a drain terminal coupled to iqout, and a gate terminal coupled to the IN clock 655. Transistor 770 may have a source terminal coupled to a common node, a gate terminal coupled to QN clock 665, and a drain terminal coupled to ground. Transistor 780 may have a drain terminal coupled to a common node, a gate terminal coupled to QP clock 660, and a source terminal coupled to ground.

Using IQ phase detection circuit 700 shown in fig. 7 instead of a nand gate (such as nand gate 314 or nand gate 670) may provide several advantages. For example, then the transistors are the same size, charge injection errors can be reduced. In addition, the loading to all clocks may be the same, which may help match the rise time and fall time of each clock. To reduce the variation between the rise time and the fall time of each clock, the sizes of the pull-up (pull-up) network device and the pull-down (pull-down) network device may be configured to match the rise time and the fall time of the iqout signal.

Fig. 8 shows a timing diagram 800 of input and output signals of the dual rail quadrature clock generation circuit 600A of fig. 6A. As shown with respect to fig. 8, IP clock 650 and IN clock 655 are inverted, but share a common reference clock frequency shown by reference clock period 810. Similarly, QP clock 660 and QN clock 665 share the same clock frequency and reference clock period 810, but are phase shifted by a quarter wavelength or 90 degrees, as shown by phase difference 820. As described above, the iqout signal has a duty cycle of 75%, corresponding to the phase difference between the IN-phase clock signals IP clock 650 and IN clock 655 and the quadrature-phase clock signals QP clock 660 and QN clock 655. The iqout average signal, which represents the average of the iqout signals, has a value corresponding to 75% of Vdd.

Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

In the foregoing description, embodiments have been described with reference to specific examples thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (20)

1. A quadrature clock generator comprising:

an in-phase I clock generation circuit for generating an I clock signal based on a reference clock signal, the I clock signal and the reference clock signal each having a first frequency;

a quadrature phase Q clock generation circuit for generating a Q clock signal based on the reference clock signal, a rise time control signal, and a fall time control signal, the Q clock signal having the first frequency; and

and a control circuit for generating the rise time control signal and the fall time control signal based on the I clock signal and the Q clock signal.

2. The quadrature clock generator of claim 1, wherein the I-clock generation circuit comprises a delay circuit configured to delay the reference clock signal.

3. The quadrature clock generator of claim 1, wherein the Q clock generation circuit comprises a plurality of Q clock delay units, each Q clock delay unit coupled to the rise time control signal and the fall time control signal.

4. A quadrature clock generator according to claim 3, wherein each Q clock delay unit comprises:

a first inverter having an input terminal, a power supply terminal, a ground terminal, and an output terminal;

a first transistor having a gate terminal coupled to the rise time control signal, a source terminal coupled to a supply voltage, and a drain terminal coupled to the supply terminal of the first inverter; and

a second transistor having a gate terminal coupled to the fall time control signal, a source terminal coupled to a ground voltage, and a drain terminal coupled to the ground terminal of the first inverter.

5. The quadrature clock generator of claim 1, wherein the control circuit comprises a differential amplifier comprising:

a non-inverting input terminal for receiving an iqout average signal representing an average of the I and inverted Q clock signals after nand operation;

an inverting input terminal for receiving a signal representing 75% of a supply voltage of the quadrature clock generator;

a terminal for receiving an output common mode voltage signal;

an inverting output for providing the fall time control signal; and

a non-inverting output for providing the rise time control signal.

6. The quadrature clock generator of claim 5, wherein the common-mode signal is generated by an amplifier having an inverting input for receiving a constant voltage signal representing 50% of the supply voltage, a non-inverting input for receiving a signal representing an average value of the Q clock signal, and an output terminal for providing the output common-mode voltage signal.

7. The quadrature clock generator of claim 1, wherein the control circuit is further configured to determine the rise time control signal and the fall time control signal based at least in part on a difference between a duty cycle of the Q clock signal and 50% of a supply voltage of the quadrature clock generator.

8. A quadrature clock generator comprising:

an in-phase I clock generation circuit for generating an I clock signal by delaying a reference clock signal, the I clock signal and the reference clock signal each having a first frequency;

a quadrature-phase Q-clock generation circuit for generating a Q-clock signal by delaying and adjusting a rise time and a fall time of the reference clock signal, the Q-clock signal having the first frequency and having a phase offset of 90 ° with respect to the I-clock signal; and

a control circuit for determining a rise time control signal and a fall time control signal for adjusting the rise time and fall time of the Q clock signal based at least in part on the I clock signal and the Q clock signal.

9. The quadrature clock generator of claim 8, wherein the Q clock generation circuit comprises a plurality of Q clock delay units, each Q clock delay unit coupled to the rise time control signal and the fall time control signal.

10. The quadrature clock generator of claim 8, wherein the rise time delay increases when the rise time control signal increases and the rise time delay decreases when the rise time control signal decreases.

11. The quadrature clock generator of claim 8, wherein the fall time delay decreases when the fall time control signal increases and increases when the fall time control signal decreases.

12. The quadrature clock generator of claim 8, wherein the control circuit is configured to determine the rise time control signal and the fall time control signal based at least in part on the phase offset between the I clock signal and the Q clock signal.

13. The quadrature clock generator of claim 8, wherein the control circuit is configured to determine the phase offset between the I clock signal and the Q clock signal based on a logical nand between the I clock signal and an inverted Q clock signal.

14. The quadrature clock generator of claim 8, wherein the control circuit is further configured to determine the rise time control signal and the fall time control signal based at least in part on a difference between a duty cycle of the Q clock signal and 50% of a supply voltage of the quadrature clock generator.

15. A dual-rail quadrature clock generator, comprising:

an in-phase I clock generation circuit for generating a non-inverted I clock signal and an inverted I clock signal based on a non-inverted reference clock signal and an inverted reference clock signal, the non-inverted I clock signal, the non-inverted reference clock signal, and the inverted reference clock signal each having a first frequency;

a quadrature phase Q clock generation circuit for generating a non-inverted Q clock signal and an inverted Q clock signal based on the non-inverted reference clock signal, the non-inverted I clock signal, and the inverted Q clock signal, wherein the non-inverted Q clock signal and the inverted Q clock signal have the first frequency; and

and a control circuit for generating a rise time control signal and a fall time control signal for adjusting rise time and fall time of the non-inverted Q clock signal and the inverted Q clock signal, wherein the rise time control signal and the fall time control signal are generated based on the non-inverted I clock signal and the inverted Q clock signal.

16. The dual-rail quadrature clock generator of claim 15, wherein the I clock generation circuit comprises a first I delay circuit configured to delay the non-inverted reference clock signal to generate the non-inverted I clock signal and a second I delay circuit configured to delay the inverted reference clock signal to generate the inverted I clock signal.

17. The dual rail quadrature clock generator of claim 15, wherein the Q clock generation circuit comprises:

a plurality of first Q clock delay units, each first Q clock delay unit configured to receive the non-inverted reference clock signal, the rise time control signal, and the fall time control signal; and

a plurality of second Q clock delay units, each configured to receive the inverted reference clock signal, the rise time control signal, and the fall time control signal.

18. The dual-rail quadrature clock generator of claim 17, wherein each first Q clock delay unit and each second Q clock delay unit comprises:

a first inverter having an input terminal, a power supply terminal, a ground terminal, and an output terminal;

a first transistor having a gate terminal coupled to the rise time control signal, a source terminal coupled to a supply voltage, and a drain terminal coupled to the supply terminal of the first inverter; and

a second transistor having a gate terminal coupled to the fall time control signal, a source terminal coupled to a ground voltage, and a drain terminal coupled to the ground terminal of the first inverter.

19. The dual rail quadrature clock generator of claim 15, wherein the control circuit comprises a differential amplifier comprising:

a non-inverting input terminal for receiving an iqout average signal representing an average of the I and inverted Q clock signals after nand operation;

an inverting input terminal for receiving a signal representing 75% of a supply voltage;

a terminal for receiving an output common mode voltage signal;

an inverting output for providing the fall time control signal; and

a non-inverting output for providing the rise time control signal.

20. The dual rail quadrature clock generator of claim 19, wherein the output common-mode voltage signal is generated by an amplifier having an inverting input for receiving a constant voltage signal representing 50% of the supply voltage, a non-inverting input for receiving a signal representing an average value of the Q clock signal, and an output terminal for providing the output common-mode voltage signal.