CN116542194A - Hardware verification method, device, equipment and storage medium - Google Patents

Hardware verification method, device, equipment and storage medium Download PDF

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Publication number
CN116542194A
CN116542194A CN202310544599.4A CN202310544599A CN116542194A CN 116542194 A CN116542194 A CN 116542194A CN 202310544599 A CN202310544599 A CN 202310544599A CN 116542194 A CN116542194 A CN 116542194A
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coverage rate
hardware
random state
random
tested
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李维杰
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Priority to CN202310544599.4A priority Critical patent/CN116542194A/en
Publication of CN116542194A publication Critical patent/CN116542194A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

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  • Computer Hardware Design (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

The application discloses a hardware verification method, a device, equipment and a storage medium, and relates to the field of hardware verification. The method comprises the following steps: verifying the hardware to be tested by using a random test method, and recording the random states of all functional blocks in a hardware design and verification language corresponding to the hardware to be tested in the test process to a first list; acquiring the verified coverage rate, and judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule; if yes, generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by utilizing the new random state until the verified coverage rate reaches the target coverage rate. By controlling the random state of each functional block, the coverage rate is improved rapidly, and the time required by coverage rate convergence is reduced.

Description

Hardware verification method, device, equipment and storage medium
Technical Field
The present invention relates to the field of hardware verification, and in particular, to a method, an apparatus, a device, and a storage medium for hardware verification.
Background
At present, the feature size of hardware design is continuously reduced, taking a chip as an example, the complexity of the chip is gradually increased, and the time and effort required for verifying the complete function of the chip are greatly increased. Functional verification based on RTL (Register Transfer Level, register transfer stage) simulation is a critical but very time consuming step for the design, and the verifier needs to exhaust all possible cases to produce stimulus to the design and cover all possible cases in as short a simulation time as possible, how much of the functionality required by the coverage characterization design is verified.
In the related art, in the chip front-end verification process, a random test is generally used to achieve rapid convergence of coverage rate. The hardware design and verification language uses a random number generator (RNG, random Number Generators) to generate a random number sequence at randomization, the random number generator performing initialization based on a given random seed. Therefore, different random seeds are selected, RNG can generate different random number sequences, and different random seeds are selected for simulation, so that the coverage rate convergence time can be shortened. However, the random number sequence generated by the random seed after switching may partially overlap with the previous random number sequence, which affects the rate of coverage rate convergence.
Disclosure of Invention
In view of the above, the present invention aims to provide a hardware verification method, device, equipment and medium, which can rapidly improve coverage rate and reduce time required for coverage rate convergence. The specific scheme is as follows:
in a first aspect, the present application discloses a hardware verification method, including:
verifying the hardware to be tested by using a random test method, and recording the random states of all functional blocks in a hardware design and verification language corresponding to the hardware to be tested in the test process to a first list;
acquiring the verified coverage rate, and judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule;
if yes, generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by utilizing the new random state until the verified coverage rate reaches the target coverage rate.
Optionally, generating a new non-repeated random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by using the new random state until the verified coverage rate reaches the target coverage rate, including:
generating a non-repeated new random state for each functional block according to the used random state of each functional block, and simulating the hardware to be tested by utilizing the new random state;
judging whether the current coverage rate reaches the target coverage rate or not;
if the current coverage rate reaches the target coverage rate, ending the verification;
and if the current coverage rate does not reach the target coverage rate, executing the step of generating a non-repeated new random state for each functional block according to the used random state of each functional block and simulating the hardware to be tested by utilizing the new random state.
Optionally, after the current coverage rate does not reach the target coverage rate, the method further includes:
judging whether the coverage rate is improved or not by comparing the current coverage rate with the last coverage rate;
if yes, recording the random state corresponding to the function block in the first list;
if not, recording the random state corresponding to the function block in a second list.
Optionally, the verifying the hardware to be tested by using the new random state until the verified coverage rate reaches the target coverage rate further includes:
and carrying out regression testing on the hardware to be tested by sequentially utilizing the random states recorded in the first list.
Optionally, the recording the random state of each functional block in the hardware design and verification language corresponding to the hardware to be tested in the test process to the first list includes:
capturing names of all the functional blocks, and acquiring handles of random number generators corresponding to the functional blocks according to the names;
and acquiring a random state corresponding to each functional block according to the handle.
Optionally, the determining, according to the coverage rate and a preset determination rule, whether the coverage rate convergence speed is less than a preset threshold value includes:
judging whether the coverage rate convergence speed is smaller than a preset threshold value or not by comparing the coverage rate acquired by the latest preset times;
if not, continuing to execute the step of verifying the hardware to be tested by using the random test method.
Optionally, before the step of judging whether the coverage rate convergence speed is less than the preset threshold according to the coverage rate and the preset judgment rule, the method further includes:
judging whether the coverage rate reaches a target coverage rate or not;
if the current coverage rate reaches the target coverage rate, ending the verification;
and if the current coverage rate does not reach the target coverage rate, executing the step of judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule.
In a second aspect, the present application discloses a hardware verification device, comprising:
the first verification module is used for verifying the hardware to be tested by utilizing a random test method, and recording the random states of all functional blocks in the hardware design and verification language corresponding to the hardware to be tested in the test process to a first list;
the judging module is used for acquiring the coverage rate of verification and judging whether the convergence speed of the coverage rate is smaller than a preset threshold value according to the coverage rate and a preset judging rule;
and the second verification module is used for generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list if the judging result of the judging module is yes, and verifying the hardware to be tested by utilizing the new random state until the verified coverage rate reaches the target coverage rate.
In a third aspect, the present application discloses an electronic device comprising:
a memory for storing a computer program;
and a processor for executing the computer program to implement the hardware verification method.
In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by the processor, implements the hardware verification method described previously.
In the application, a random test method is utilized to verify hardware to be tested, and the random states of all functional blocks in hardware design and verification language corresponding to the hardware to be tested in the test process are recorded to a first list; acquiring the verified coverage rate, and judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule; if yes, generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by utilizing the new random state until the verified coverage rate reaches the target coverage rate. It can be seen that by covering
After the rate convergence rate is smaller than a preset threshold value, generating a non-repeated new random state for each functional block according to the random state used by each functional block before, and then simulating hardware to be tested by using the new random state, thereby avoiding the problem that the convergence rate is reduced due to the fact that the used random state is used for simulation after the coverage rate is converged to a certain degree by controlling the random state of each functional block, and further realizing the rapid improvement of the coverage rate and the reduction of the time required by the convergence of the coverage rate.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only embodiments of the present invention, and other drawings may be obtained according to the provided drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a hardware verification method provided in the present application;
FIG. 2 is a schematic diagram of a specific hardware verification system provided in the present application;
FIG. 3 is a flowchart of a specific hardware verification method provided in the present application;
fig. 4 is a schematic structural diagram of a hardware verification device provided in the present application;
fig. 5 is a block diagram of an electronic device provided in the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the related art, in the chip front-end verification process, a random test is generally used to achieve rapid convergence of coverage rate. The hardware design and verification language uses a random number generator to generate a random number sequence during randomization, and the random number generator completes initialization according to a given random seed. Therefore, different random seeds are selected, RNG can generate different random number sequences, and different random seeds are selected for simulation, so that the coverage rate convergence time can be shortened. However, the random number sequence generated by the random seed after switching may partially overlap with the previous random number sequence, which affects the rate of coverage rate convergence. In order to overcome the above-mentioned technical problems,
the hardware verification method can improve coverage rate rapidly and reduce time required by coverage rate convergence.
The embodiment of the application discloses a hardware verification method, referring to fig. 1, the method may include the following steps:
step S11: and verifying the hardware to be tested by using a random test method, and recording the random states of the corresponding hardware design of the hardware to be tested and each functional block in the verification language in the test process to a first list.
In this embodiment, a random test method is used to verify the hardware to be tested, that is, a random test method is used to perform a simulation test on the hardware to be tested to verify each function of the hardware, and at the same time, the random states of the hardware design corresponding to the hardware to be tested and each functional block in the verification language in the test process are recorded to the first list. The hardware design and verification language may be a systemilog language (SV language), which is a language based on Verilog (Verilog HDL, hardware description language), combines a hardware description language (HDL, hardware Description Language) with a modern high-level verification language (HVL, hardware verification language), and has recently become a language for next-generation hardware design and verification. In the language of the system verilog hardware design and verification, these independent blocks such as program, module, interface, function and task are called as Process, each Process has its own initialized RNG, and each Process' RNG has its own random state.
In this embodiment, the recording, in the testing process, the random state of each functional block in the hardware design and verification language corresponding to the hardware to be tested to the first list may include: capturing names of all the functional blocks, and acquiring handles of random number generators corresponding to the functional blocks according to the names; and acquiring a random state corresponding to each functional block according to the handle. In this embodiment, when the random state of each functional block is obtained, the names of the functional blocks are specifically obtained, the handles of the random number generators corresponding to the functional blocks are obtained according to the names, and then the random state corresponding to each functional block is obtained according to the obtained handles.
Specifically, the simulation environment is analyzed, names of all the processes are grabbed through a preconfigured Python script, name information of all the processes is grabbed and then stored, during simulation, RNG handles of all the processes can be obtained through a static method of Process (), and then a get_randstate () method is called through the handles to obtain a random state. The random state values returned by different simulation tools may behave differently, but are essentially a string of seemingly irregular characters
The character strings represent the next random number to be generated. Likewise, the random state may also be set manually by the set_random () method, changing the random value to be generated next.
Step S12: and acquiring the verified coverage rate, and judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule.
In this embodiment, the coverage rate of verification, that is, the coverage rate of the function verified in the hardware, is obtained after each simulation, and then, whether the coverage rate convergence speed is smaller than a preset threshold value is determined according to the coverage rate and a preset determination rule, where the preset threshold value may be a smaller value or zero, that is, the coverage rate is no longer converged. It should be noted that the coverage rate of the verification is the sum of the coverage rates of the hardware so far, and is not the coverage rate of the simulation at this time; it can be understood that if the first simulation covers the function a and the second simulation covers the function B, the coverage rate verified after the second simulation is a+b; if the first simulation covers the function A+B and the second simulation covers the function B+C, the coverage rate verified after the second simulation is A+B+C.
In this embodiment, before determining whether the coverage rate convergence speed is less than the preset threshold according to the coverage rate and the preset determination rule, the method may further include: judging whether the coverage rate reaches a target coverage rate or not; if the current coverage rate reaches the target coverage rate, ending the verification; and if the current coverage rate does not reach the target coverage rate, executing the step of judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule. Firstly judging whether the coverage rate reaches a target coverage rate or not after acquiring the coverage rate, namely, the coverage rate of the expected functional verification, and ending the verification if the coverage rate reaches the target coverage rate; if the target coverage is not reached, continuing to execute the step of judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule, so that the target coverage rate is judged after the coverage rate is obtained each time, and the result is timely output after the target coverage rate is expected.
In this embodiment, the determining, according to the coverage rate and the preset determination rule, whether the coverage rate convergence speed is less than a preset threshold may include: judging whether the coverage rate convergence speed is smaller than a preset threshold value or not by comparing the coverage rate acquired by the latest preset times; and if the coverage rate convergence speed is not less than the preset threshold value, continuing to execute the step of verifying the hardware to be tested by using the random test method. The coverage rate can be judged by nearly two times or nearly several times, and if the coverage rate convergence rate is not less than a preset threshold value, the coverage rate convergence can still be promoted by the traditional random test method, so that the hardware to be tested is verified by the random test method continuously.
Step S13: if the coverage rate convergence rate is smaller than a preset threshold value, generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by utilizing the new random state until the verified coverage rate reaches a target coverage rate
Cover rate.
In this embodiment, if the coverage rate convergence speed is smaller than the preset threshold, generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list, that is, the generated new random state of any functional block is different from the random state corresponding to the functional block in the first list, and verifying the hardware to be tested by using the new random state until the verified coverage rate reaches the target coverage rate. The coverage rate convergence speed is smaller than a preset threshold value, and the coverage rate is characterized as being not improved or not improved compared with the previous result. It should be noted that the first generated new random state only needs to generate a non-repeated new random state according to the random states recorded in the first list, and then each generation of the new random state needs to refer to all the random states used by the functional block, so that each simulation is performed by using the non-repeated new random state, and in this way, after reaching a certain convergence degree, the simulation is performed by using the new random state which is never used to accelerate convergence. In addition, it should be noted that, the process of verifying the hardware to be tested by using the new random state is to simulate by using the new random state corresponding to each functional block at the same time, that is, each simulation after the coverage rate convergence speed is smaller than the preset threshold value, each functional block uses the used random state.
In this embodiment, generating a new non-repeated random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by using the new random state until the verified coverage rate reaches the target coverage rate may include: generating a non-repeated new random state for each functional block according to the used random state of each functional block, and simulating the hardware to be tested by utilizing the new random state; judging whether the current coverage rate reaches the target coverage rate or not; if the current coverage rate reaches the target coverage rate, ending the verification; and if the current coverage rate does not reach the target coverage rate, executing the step of generating a non-repeated new random state for each functional block according to the used random state of each functional block and simulating the hardware to be tested by utilizing the new random state.
In this embodiment, if the current coverage rate does not reach the target coverage rate, the method may further include: judging whether the coverage rate is improved or not by comparing the current coverage rate with the last coverage rate; if yes, recording the random state corresponding to the function block in the first list; if not, recording the random state corresponding to the function block in a second list. The random state that improves coverage is recorded in the first list and the remainder is recorded in the second list.
In this embodiment, verifying the hardware to be tested by using the new random state until the verified coverage rate reaches the target coverage rate may further include: sequentially utilizing the first list
And carrying out regression testing on the hardware to be tested by the recorded random state. When the regression test is performed, the regression test can be completed quickly by only traversing the random states in the first list.
As can be seen from the above, in this embodiment, a random test method is used to verify the hardware to be tested, and the random states of the hardware design and the functional blocks in the verification language corresponding to the hardware to be tested in the test process are recorded to a first list; acquiring the verified coverage rate, and judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule; if yes, generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by utilizing the new random state until the verified coverage rate reaches the target coverage rate. Therefore, after the coverage rate convergence rate is smaller than a preset threshold value, a non-repeated new random state is generated for each functional block according to the random state used by each functional block before, and then the hardware to be tested is simulated by using the new random state, so that the problem that the convergence rate is reduced due to the fact that the random state used is still used for simulation after the coverage rate is converged to a certain degree is avoided by controlling the random state of each functional block, and the coverage rate is improved rapidly and the time required by the coverage rate convergence is reduced.
The embodiment of the application discloses a specific hardware verification system structure diagram, referring to fig. 2, a dotted line part represents an existing verification platform, a random state control module, a coverage ratio comparison module, a Process control module and a state storage module are added on the basis of the original verification platform without change. The random state control module realizes random state monitoring and random state configuration functions, the coverage rate comparison module realizes coverage rate collection and comparison, the Process control module realizes control of different Process random states, and the state storage module is responsible for recording the random states. The specific hardware verification flow is shown in fig. 3:
in the first simulation stage, the random state control module analyzes the simulation environment and grabs all the names of the Process through the Python script. After the random state control module captures the name information of all the processes, the information is transmitted to the Process control module and is transmitted to the state storage module through the Process control module;
during simulation, the random state control module obtains the RNG handle of each Process through a static method of Process:: self (), and then obtains the random state through calling a get_randstate () method through the handle. Transmitting the random state of each Process to a Process control module, and simultaneously, the Process control module waits for the result of the coverage ratio comparison module and judges the next operation according to the result of the coverage ratio comparison module;
the coverage result contains two aspects of information, one is a simulation phase and the other is a random state operation mode. If the coverage rate is obviously improved compared with the previous merging result, the coverage rate result is compared with the previous coverage rate
And merging the rate results (if the rate results exist), and outputting simulation stage information to finish if the coverage rate of verification obtained after merging reaches a coverage rate target. In this case, the Process control module will record the random state of each Process to the first list (valid column) of the state save module, and the simulation ends. If the coverage rate target is not reached, the simulation stage information is output as the first stage, and the random state operation mode is ignored at the moment, and similarly, the Process control module records the random state of each Process into the valid column of the state storage module. Then the Process control module sends a monitoring instruction to control the random state control module to acquire the next random state;
after multiple simulations in the first simulation stage, if the coverage rate is not improved compared with the previous result, the coverage rate comparison module judges that the output is the second simulation stage, and then the second simulation stage is entered. The Process control module records the random state of each Process to a second list (disable column) of the state save module, then the Process control module randomly generates a random state which is not repeated according to the records of the valid column and the disable column of the state save module, and returns the random state to the random state control module. The random state control module calls a set_random () method to configure a random state through a handle, and simulation is started after the configuration is completed;
in the second simulation stage, the different processing modes of the coverage ratio comparison module are judged by adding a random state operation mode, if the random state can improve the coverage ratio, the random state operation mode is output as a valid column, and otherwise, the random state operation mode is output as a disable column. The Process control module decides in which column of the state saving module the random state is saved according to the random state operation mode. Then continuously generating a random state, carrying out next simulation, and repeating for a plurality of times until the coverage rate reaches the standard;
when the regression test is performed, the regression test can be rapidly completed by only traversing the random state of the valid column in the state storage module.
Therefore, in this embodiment, in the stage of rapid convergence of the coverage rate in the early stage of simulation, each random state of each functional block is recorded. When the rate of coverage convergence becomes slow or even no longer increases, unused random states are configured according to the record of random states. After multiple simulations, the coverage can quickly reach the target value. According to the recorded random state, the control of the random sequence number during regression test can be realized, and the regression test can be completed rapidly.
Correspondingly, the embodiment of the application also discloses a hardware verification device, as shown in fig. 4, which comprises:
the first verification module 11 is configured to verify the hardware to be tested by using a random test method, and record a random state of each functional block in a hardware design and verification language corresponding to the hardware to be tested in a test process to a first list;
the judging module 12 is configured to obtain a coverage rate of the verification, and judge whether a convergence speed of the coverage rate is less than a preset threshold according to the coverage rate and a preset judging rule;
and the second verification module 13 is configured to generate a new non-repeated random state for each functional block according to the random state corresponding to each functional block in the first list if the judgment result of the judgment module is yes, and verify the hardware to be tested by using the new random state until the verified coverage rate reaches the target coverage rate.
As can be seen from the above, in this embodiment, a random test method is used to verify the hardware to be tested, and the random states of the hardware design and the functional blocks in the verification language corresponding to the hardware to be tested in the test process are recorded to a first list; acquiring the verified coverage rate, and judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule; if yes, generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by utilizing the new random state until the verified coverage rate reaches the target coverage rate. Therefore, after the coverage rate convergence rate is smaller than a preset threshold value, a non-repeated new random state is generated for each functional block according to the random state used by each functional block before, and then the hardware to be tested is simulated by using the new random state, so that the problem that the convergence rate is reduced due to the fact that the random state used is still used for simulation after the coverage rate is converged to a certain degree is avoided by controlling the random state of each functional block, and the coverage rate is improved rapidly and the time required by the coverage rate convergence is reduced.
In some specific embodiments, the second verification module 13 may specifically include:
a new random state generating unit, configured to generate a non-repeated new random state for each functional block according to the random state used by each functional block, and simulate the hardware to be tested by using the new random state;
the judging unit is used for judging whether the current coverage rate reaches the target coverage rate or not;
the ending verification unit is used for ending verification if the current coverage rate reaches the target coverage rate;
and the execution unit is used for executing the step of generating a non-repeated new random state for each functional block according to the used random state of each functional block if the current coverage rate does not reach the target coverage rate, and simulating the hardware to be tested by utilizing the new random state.
In some specific embodiments, the second verification module 13 may specifically include:
the coverage rate improvement judging unit is used for judging whether the coverage rate is improved by comparing the current coverage rate with the last coverage rate after the current coverage rate does not reach the target coverage rate;
the first recording unit is used for recording the random state corresponding to the functional block currently in the first list if the judging result of the coverage rate improvement judging unit is yes;
and the second recording unit is used for recording the random state corresponding to the functional block currently in a second list if the judging result of the coverage rate improvement judging unit is negative.
In some specific embodiments, the hardware verification device may specifically include:
and the regression testing unit is used for carrying out regression testing on the hardware to be tested by sequentially utilizing the random states recorded in the first list.
In some specific embodiments, the first verification module 11 may specifically include:
the handle acquisition unit is used for capturing the names of all the functional blocks and acquiring the handle of the random number generator corresponding to each functional block according to the names;
and the random state acquisition unit is used for acquiring the random state corresponding to each functional block according to the handle.
In some specific embodiments, the determining module 12 may specifically include:
the coverage rate convergence speed judging unit is used for judging whether the coverage rate convergence speed is smaller than a preset threshold value or not by comparing the coverage rate acquired by the latest preset times;
and the execution unit is used for continuously executing the step of verifying the hardware to be tested by using the random test method if the judging result of the coverage rate convergence speed judging unit is negative.
In some specific embodiments, the determining module 12 may specifically include:
the target coverage judging unit is used for judging whether the coverage reaches the target coverage before judging whether the coverage convergence speed is smaller than a preset threshold according to the coverage and a preset judging rule;
the ending unit is used for ending verification if the current coverage rate reaches the target coverage rate;
and the execution unit is used for executing the step of judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judgment rule if the current coverage rate does not reach the target coverage rate.
Further, the embodiment of the application further discloses an electronic device, and referring to fig. 5, the content in the drawing should not be considered as any limitation on the scope of use of the application.
Fig. 5 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, communication
An interface 24, an input-output interface 25 and a communication bus 26. Wherein the memory 22 is configured to store a computer program that is loaded and executed by the processor 21 to implement the relevant steps of the hardware verification method disclosed in any of the foregoing embodiments.
In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 25 is used for acquiring external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application requirement, which is not limited herein.
The memory 22 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk, or an optical disk, and the resources stored thereon include an operating system 221, a computer program 222, and data 223 including coverage rate, and the storage may be temporary storage or permanent storage.
The operating system 221 is used for managing and controlling various hardware devices on the electronic device 20 and the computer program 222, so as to implement the operation and processing of the processor 21 on the mass data 223 in the memory 22, which may be Windows Server, netware, unix, linux, etc. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the hardware validation method performed by the electronic device 20 disclosed in any of the previous embodiments.
Further, the embodiment of the application also discloses a computer storage medium, wherein the computer storage medium stores computer executable instructions, and when the computer executable instructions are loaded and executed by a processor, the hardware verification method steps disclosed in any embodiment are realized.
When loaded and executed by a processor, the computer-executable instructions implement the steps of: verifying the hardware to be tested by using a random test method, and recording the random states of all functional blocks in a hardware design and verification language corresponding to the hardware to be tested in the test process to a first list; acquiring the verified coverage rate, and judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule; if yes, generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by utilizing the new random state until the verified coverage rate reaches the target coverage rate.
Generating a non-repeated new random state for each functional block according to the random state used by each functional block after the coverage rate convergence speed is smaller than a preset threshold value, and then simulating the hardware to be tested by using the new random state, thereby avoiding the random states of the functional blocks by controlling the random states of the functional blocks
After the coverage rate converges to a certain degree, the problem of reducing the convergence rate is caused by using the used random state to simulate, so that the coverage rate is rapidly improved, and the time required by the convergence of the coverage rate is reduced.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description of the hardware verification method, device, equipment and medium provided by the present invention applies specific examples to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims (10)

1. A hardware verification method, comprising:
verifying the hardware to be tested by using a random test method, and recording the random states of all functional blocks in a hardware design and verification language corresponding to the hardware to be tested in the test process to a first list;
acquiring the verified coverage rate, and judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule;
if yes, generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by utilizing the new random state until the verified coverage rate reaches the target coverage rate.
2. The hardware verification method according to claim 1, wherein generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list, and verifying the hardware to be tested by using the new random state until the verified coverage reaches a target coverage includes:
generating a non-repeated new random state for each functional block according to the used random state of each functional block, and simulating the hardware to be tested by utilizing the new random state;
judging whether the current coverage rate reaches the target coverage rate or not;
if the current coverage rate reaches the target coverage rate, ending the verification;
and if the current coverage rate does not reach the target coverage rate, executing the step of generating a non-repeated new random state for each functional block according to the used random state of each functional block and simulating the hardware to be tested by utilizing the new random state.
3. The hardware verification method according to claim 2, wherein after the current coverage rate does not reach the target coverage rate, further comprising:
judging whether the coverage rate is improved or not by comparing the current coverage rate with the last coverage rate;
if yes, recording the random state corresponding to the function block in the first list;
if not, recording the random state corresponding to the function block in a second list.
4. The hardware verification method according to claim 3, wherein the verifying the hardware to be tested using the new random state until the verified coverage reaches a target coverage, further comprising:
and carrying out regression testing on the hardware to be tested by sequentially utilizing the random states recorded in the first list.
5. The hardware verification method according to claim 1, wherein recording the random states of the functional blocks in the hardware design and verification language corresponding to the hardware to be tested in the test process to the first list includes:
capturing names of all the functional blocks, and acquiring handles of random number generators corresponding to the functional blocks according to the names;
and acquiring a random state corresponding to each functional block according to the handle.
6. The hardware verification method according to claim 1, wherein the determining whether the coverage rate convergence speed is smaller than a preset threshold according to the coverage rate and a preset determination rule includes:
judging whether the coverage rate convergence speed is smaller than a preset threshold value or not by comparing the coverage rate acquired by the latest preset times;
if not, continuing to execute the step of verifying the hardware to be tested by using the random test method.
7. The hardware verification method according to any one of claims 1 to 6, wherein before the step of determining whether the coverage rate convergence speed is less than a preset threshold according to the coverage rate and a preset determination rule, further comprises:
judging whether the coverage rate reaches a target coverage rate or not;
if the current coverage rate reaches the target coverage rate, ending the verification;
and if the current coverage rate does not reach the target coverage rate, executing the step of judging whether the coverage rate convergence speed is smaller than a preset threshold value according to the coverage rate and a preset judging rule.
8. A hardware verification device, comprising:
the first verification module is used for verifying the hardware to be tested by utilizing a random test method, and recording the random states of all functional blocks in the hardware design and verification language corresponding to the hardware to be tested in the test process to a first list;
the judging module is used for acquiring the coverage rate of verification and judging whether the convergence speed of the coverage rate is smaller than a preset threshold value according to the coverage rate and a preset judging rule;
and the second verification module is used for generating a non-repeated new random state for each functional block according to the random state corresponding to each functional block in the first list if the judging result of the judging module is yes, and verifying the hardware to be tested by utilizing the new random state until the verified coverage rate reaches the target coverage rate.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the hardware verification method of any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program; wherein the computer program when executed by a processor implements the hardware verification method of any one of claims 1 to 7.
CN202310544599.4A 2023-05-12 2023-05-12 Hardware verification method, device, equipment and storage medium Pending CN116542194A (en)

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Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310544599.4A CN116542194A (en) 2023-05-12 2023-05-12 Hardware verification method, device, equipment and storage medium

Publications (1)

Publication Number Publication Date
CN116542194A true CN116542194A (en) 2023-08-04

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