CN116541159A - Program execution method and system, electronic device and storage medium - Google Patents
Program execution method and system, electronic device and storage medium Download PDFInfo
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- CN116541159A CN116541159A CN202210094874.2A CN202210094874A CN116541159A CN 116541159 A CN116541159 A CN 116541159A CN 202210094874 A CN202210094874 A CN 202210094874A CN 116541159 A CN116541159 A CN 116541159A
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- 230000006870 function Effects 0.000 claims description 17
- 238000004590 computer program Methods 0.000 claims description 11
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
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Abstract
The invention discloses a program execution method and system, electronic equipment and a storage medium. The program execution method comprises the following steps: acquiring real-time occupancy rates of at least two processors; determining a target processor according to the real-time occupancy rate; and generating control instructions, wherein the control instructions are used for instructing the target processor to execute a target program. According to the method and the system, the processor for executing the target program, namely the target processor, is dynamically selected according to the real-time occupancy rate of at least two processors, so that the dynamic deployment of the target program is realized, the execution efficiency of the target program is improved, and the overall performance of the system is further improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a program execution method and system, an electronic device, and a storage medium.
Background
The current program deployment in the terminal device comprises the following two schemes: the first scheme is that the program runs fixedly on a CPU (Central Processing Unit ) or a GPU (Graphics Processing Unit, graphics processor), the second scheme is that a program preprocessing part is on the CPU, and a program model is inferred on the GPU. While processors such as a CPU and a GPU in hardware resources on existing terminal devices are generally shared, if the processors are executed according to a program deployment, i.e., a predetermined deployment scheme in the prior art, a situation that part of the processors are highly loaded and the other part of the processors are idle occurs; if the current dependent CPU, GPU or DSP (Digital Signal Process, digital signal processing) is under the condition of high load operation, the running speed of the program model is easy to be slow, the real-time requirement cannot be met, and the reasoning result is easy to be abnormal.
Disclosure of Invention
An object of the present invention is to provide a program execution method and system, an electronic device, and a storage medium, which have the advantages that a processor executing a target program, i.e., a target processor, is dynamically selected according to real-time occupancy rates of at least two processors, so that dynamic deployment of the target program is realized, execution efficiency of the target program is improved, and overall performance of the system is further improved.
Another object of the present invention is to provide a program execution method and system, an electronic device, and a storage medium, which are capable of obtaining real-time occupancy rates of at least two processors in response to starting of a target function, and selecting a processor executing the target program, i.e., a target processor, according to the real-time occupancy rates of the at least two processors, so that the target processor realizes the target function, thereby improving a response rate of the target function.
Another object of the present invention is to provide a program execution method and system, an electronic device, and a storage medium, which have the advantage that a processor with the lowest real-time occupancy rate of at least two processors is used as a target processor, so as to improve the execution efficiency of the target program to the greatest extent possible.
Another object of the present invention is to provide a program execution method and system, an electronic device, and a storage medium, which are advantageous in that, in order to avoid affecting the normal execution of a target program, a processor executing the target program can generate a switching instruction when outputting useless information. And responding to the switching instruction, and generating a control instruction for instructing the target processor to execute the target program, so that the target processor can continue to execute the target program, and stable execution of the target program is ensured.
A first aspect of the present application provides a program execution method, including the steps of:
acquiring real-time occupancy rates of at least two processors;
determining a target processor according to the real-time occupancy rate;
and generating control instructions, wherein the control instructions are used for instructing the target processor to execute a target program.
A second aspect of the present application provides a program execution system, comprising: at least two processors and a memory; the memory is configured to store instructions that, when executed by any one of the processors, cause the any one of the processors to perform steps comprising:
acquiring real-time occupancy rates of at least two processors;
determining a target processor according to the real-time occupancy rate;
and generating control instructions, wherein the control instructions are used for instructing the target processor to execute a target program.
A third aspect of the present application provides an electronic device comprising a memory, at least two processors, and a computer program stored on the memory and executable on any one of the processors, the any one of the processors implementing the program execution method of the first aspect when the computer program is executed.
A fourth aspect of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the program execution method according to the first aspect.
Drawings
Fig. 1 is a flowchart of a program execution method provided in embodiment 1.
Fig. 2 is a block diagram of an electronic device according to embodiment 1.
Fig. 3 is a flowchart of another program execution method provided in embodiment 1.
Fig. 4 is a schematic structural diagram of an electronic device according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.
Example 1
Fig. 1 is a schematic flow chart of a program execution method provided in this embodiment, where the program execution method may be executed by a program execution system, and the program execution system may be implemented by software and/or hardware, and the program execution system may be part or all of an electronic device.
The electronic device may be a personal computer, such as a desktop computer, an integrated machine, a notebook computer, a tablet computer, or a terminal device such as a mobile phone, a wearable device, a palm computer, or a vehicle-mounted device. The vehicle-mounted device can be also called a vehicle machine, and specifically can comprise a vehicle-mounted display device, a vehicle-mounted navigation device, a vehicle-mounted monitoring device and the like.
The program execution method provided in this embodiment is described below with an electronic device as an execution subject. As shown in fig. 1, the program execution method provided in the present embodiment may include the following steps S1 to S3:
and S1, acquiring real-time occupancy rates of at least two processors. The real-time occupancy rate refers to the current resource use condition of the processor, and is larger, so that the current resource use amount of the processor is more, and the processor is in a high-load running state. The real-time occupancy rate is smaller, which means that the current resource usage amount of the processor is smaller and the processor is in a low-load running state.
In the example shown in fig. 2, the electronic device includes three processors, a CPU, a DSP, and a GPU, respectively.
In an alternative embodiment of step S1, the real-time occupancy of the at least two processors is obtained in response to the target function being initiated. Wherein the target function corresponds to at least one target program. In this embodiment, if the target function is started, the acquisition of the real-time occupancy rate of at least the processor is triggered.
The target function may be set according to actual situations, for example, a function consuming more resources may be set as the target function. The number of programs to be executed for realizing the target function may be one or a plurality of. In a specific example, the target function is a smile detection function, and the corresponding target program includes a face detection program and a lip detection program.
In an alternative embodiment of step S1, the real-time occupancy of the at least two processors is obtained in response to the real-time occupancy of the processor that is about to execute or is executing the target program being higher than a preset value. The preset value may be set according to practical situations, for example, may be set to 80%.
In this embodiment, if the real-time occupancy rate of the processor that is about to execute or is executing the target program is higher than a preset value, the real-time occupancy rate of other processors is triggered to be acquired. In a specific example, the real-time occupancy rate of the CPU that is about to execute the target program is 82%, which is higher than 80% of the preset value, and the real-time occupancy rates of the DSP and the GPU are triggered to be acquired.
The real-time occupancy rate of the processor is higher than a preset value, which indicates that the processor is in an overload running state at present, and is easy to be abnormal or fault, and the service life of the processor can be seriously influenced when the processor is in the overload running state for a long time. At the moment, the processor with lower real-time occupancy rate needs to be switched to execute the target program, so that the execution efficiency of the target program can be improved, and the overall performance of the system can be improved.
And S2, determining a target processor according to the real-time occupancy rate.
In an alternative embodiment, the step S2 specifically includes the following steps S21a to S21b:
step S21a, comparing the real-time occupancy rates of the at least two processors.
Step S21b, the processor with the lowest real-time occupancy rate is taken as a target processor.
In this embodiment, the processor with the lowest real-time occupancy rate of the at least two processors is used as the target processor, so that the execution efficiency of the target program is improved as much as possible.
In an alternative embodiment, the step S2 specifically includes the following steps S22a to S22b:
and step S22a, comparing the real-time occupancy rates of the at least two processors with preset thresholds respectively. The preset threshold may be set according to practical situations, for example, may be set to 50%.
Step S22b, taking any processor with the real-time occupancy rate lower than the preset threshold as a target processor.
In this embodiment, the real-time occupancy rate of the processor is lower than the preset threshold, which indicates that the processor is currently in a light-load running state, and one processor is arbitrarily selected from all the processors with the real-time occupancy rates lower than the preset threshold as the target processor.
In a preferred embodiment, if the real-time occupancy rate of a processor that is about to execute or is executing the target program is lower than a preset threshold, the processor is directly used as the target processor, and switching of the processor is not needed, so that the execution efficiency of the target program is prevented from being reduced. In a specific example, the real-time occupancy rates of the obtained CPU and the GPU are 40% and 30% respectively, which are both lower than the preset threshold value of 50%, and the CPU is directly determined as the target processor when executing the target program, and then the CPU continues to execute the target program, so that the switching processor is prevented from reducing the execution efficiency of the target program.
And step S3, generating a control instruction, wherein the control instruction is used for instructing the target processor to execute a target program. Wherein instructing the target processor to execute the target program may also be referred to as deploying the target program on the target processor.
In this embodiment, the processor executing the target program, that is, the target processor is dynamically selected according to the real-time occupancy rates of at least two processors, so that the dynamic deployment of the target program is realized, so as to improve the execution efficiency of the target program, and further improve the overall performance of the system.
In an alternative embodiment of step S3, the control instruction is generated in response to a processor-generated switching instruction that is executing the target program. In this embodiment, the timing of generating the control instruction depends on the processor executing the target program, and the processor executing the target program may generate the switching instruction according to the actual situation.
To avoid affecting the normal execution of the target program, the processor that is executing the target program may generate a switch instruction when outputting the useless information. And responding to the switching instruction, and generating a control instruction for instructing the target processor to execute the target program, so that the target processor can continue to execute the target program, and stable execution of the target program is ensured. Wherein, outputting the garbage information may be outputting information that does not have any influence on the user.
In an alternative embodiment, as shown in fig. 3, the following step S4 is further included after the step S3: and sending the control instruction to the target processor. And the target processor executes the target program after receiving the control instruction.
It should be noted that, the above-mentioned program execution method may be executed in any processor in the electronic device, where the processor executing the above-mentioned program execution method may send the obtained real-time occupancy rate to other processors, so that each processor may share the real-time occupancy rate.
In a specific example, the program execution method described above is executed by a DSP in an electronic device. Specifically, the DSP acquires the CPU and the GPU with real-time occupancy rates of 40% and 85% respectively, determines the CPU with real-time occupancy rate lower than 80% as a target processor, generates a control instruction, and sends the control instruction to the CPU to instruct the CPU to execute a target program.
In another specific example, the above-described program execution method is executed by a CPU in the electronic apparatus. Specifically, the real-time occupancy rate X of the CPU is obtained, if X exceeds 80%, the real-time occupancy rate Y of the GPU is obtained, if Y is smaller than X, the GPU is determined to be a target processor, a control instruction is generated, and the control instruction is sent to the GPU to instruct the GPU to execute a target program. If Y is greater than X, determining the CPU as a target processor, generating a control instruction, and executing a target program by the CPU in response to the control instruction.
The present embodiment also provides a program execution system, including: at least two processors and a memory; the memory is configured to store instructions that, when executed by any one of the processors, cause the any one of the processors to perform steps comprising:
acquiring real-time occupancy rates of at least two processors;
determining a target processor according to the real-time occupancy rate;
and generating control instructions, wherein the control instructions are used for instructing the target processor to execute a target program.
In an optional implementation manner, the step of acquiring the real-time occupancy rate of the at least two processors specifically includes: and responding to the starting of the target function, and acquiring the real-time occupancy rate of at least two processors. Wherein the target function corresponds to at least one target program.
In an optional implementation manner, the step of determining the target processor according to the real-time occupancy rate specifically includes: comparing the real-time occupancy of the at least two processors; and taking the processor with the lowest real-time occupancy rate as a target processor.
In an optional implementation manner, the step of determining the target processor according to the real-time occupancy rate specifically includes: comparing the real-time occupancy rates of the at least two processors with preset thresholds respectively; and taking any processor with the real-time occupancy rate lower than the preset threshold value as a target processor.
In an optional implementation manner, the step of generating the control instruction specifically includes: control instructions are generated in response to a processor-generated switching instruction that is executing the target program.
In an alternative embodiment, after the step of generating the control instruction, the method further includes: and sending the control instruction to the target processor.
It should be noted that, in this embodiment, the program execution system may be a separate chip, a chip module or an electronic device, or may be a chip or a chip module integrated in the electronic device.
Regarding each module/unit included in the program execution system described in the present embodiment, it may be a software module/unit, a hardware module/unit, or a software module/unit partially, and a hardware module/unit partially.
Example 2
Fig. 4 is a schematic structural diagram of an electronic device according to the present embodiment. The electronic device includes at least two processors and a memory communicatively coupled to the at least two processors. Wherein the memory stores a computer program executable by any one of the processors, the computer program being executable by any one of the processors to enable execution of the program execution method of embodiment 1. The electronic device may be a personal computer, such as a desktop computer, an integrated machine, a notebook computer, a tablet computer, or a terminal device such as a mobile phone, a wearable device, a palm computer, or a vehicle-mounted device. The vehicle-mounted device can be also called a vehicle machine, and specifically can comprise a vehicle-mounted display device, a vehicle-mounted navigation device, a vehicle-mounted monitoring device and the like. The electronic device 3 shown in fig. 4 is only an example and should not be construed as limiting the functionality and scope of use of the embodiments of the invention.
The components of the electronic device 3 may include, but are not limited to: the at least two processors 4, the at least one memory 5, a bus 6 connecting the different system components, including the memory 5 and the processors 4.
The bus 6 includes a data bus, an address bus, and a control bus.
The memory 5 may include volatile memory such as Random Access Memory (RAM) 51 and/or cache memory 52, and may further include Read Only Memory (ROM) 53.
The memory 5 may also include a program/utility 55 having a set (at least one) of program modules 54, such program modules 54 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.
The processor 4 executes various functional applications and data processing, such as the program execution method described above, by running a computer program stored in the memory 5.
The electronic device 3 may also communicate with one or more external devices 7, such as a keyboard, pointing device, etc. Such communication may be through an input/output (I/O) interface 8. And the electronic device 3 may also communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the internet, via the network adapter 9. As shown in fig. 4, the network adapter 9 communicates with other modules of the electronic device 3 via the bus 6. It should be appreciated that although not shown in fig. 4, other hardware and/or software modules may be used in connection with the electronic device 3, including, but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, data backup storage systems, and the like.
It should be noted that although several units/modules or sub-units/modules of an electronic device are mentioned in the above detailed description, such a division is merely exemplary and not mandatory. Indeed, the features and functionality of two or more units/modules described above may be embodied in one unit/module in accordance with embodiments of the present invention. Conversely, the features and functions of one unit/module described above may be further divided into ones that are embodied by a plurality of units/modules.
Example 3
The present embodiment provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the program execution method in embodiment 1.
More specifically, among others, readable storage media may be employed including, but not limited to: portable disk, hard disk, random access memory, read only memory, erasable programmable read only memory, optical storage device, magnetic storage device, or any suitable combination of the foregoing.
In a possible embodiment, the invention may also be implemented in the form of a program product comprising program code for causing an electronic device to carry out the program execution method of embodiment 1 when said program product is run on the electronic device.
Wherein the program code for carrying out the invention may be written in any combination of one or more programming languages, such that the program code is executable entirely on an electronic device, partially on an electronic device, as a stand-alone software package, partially on an electronic device, partially on a remote device, or entirely on a remote device.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.
Claims (10)
1. A program execution method, characterized by comprising the steps of:
acquiring real-time occupancy rates of at least two processors;
determining a target processor according to the real-time occupancy rate;
and generating control instructions, wherein the control instructions are used for instructing the target processor to execute a target program.
2. The program execution method as claimed in claim 1, wherein the step of obtaining real-time occupancy rates of the at least two processors specifically comprises:
responding to the starting of a target function, and acquiring real-time occupancy rates of at least two processors;
wherein the target function corresponds to at least one target program.
3. The program execution method as claimed in claim 1, wherein the step of determining the target processor according to the real-time occupancy rate specifically comprises:
comparing the real-time occupancy of the at least two processors;
and taking the processor with the lowest real-time occupancy rate as a target processor.
4. The program execution method as claimed in claim 1, wherein the step of determining the target processor according to the real-time occupancy rate specifically comprises:
comparing the real-time occupancy rates of the at least two processors with preset thresholds respectively;
and taking any processor with the real-time occupancy rate lower than the preset threshold value as a target processor.
5. The program execution method as claimed in claim 1, wherein the step of generating the control instruction specifically includes:
control instructions are generated in response to a processor-generated switching instruction that is executing the target program.
6. The program execution method of claim 1, further comprising, after the step of generating control instructions:
and sending the control instruction to the target processor.
7. The program execution method of any one of claims 1-6, wherein the target processor is a CPU, GPU, or DSP.
8. A program execution system, comprising: at least two processors and a memory; the memory is configured to store instructions that, when executed by any one of the processors, cause the any one of the processors to perform steps comprising:
acquiring real-time occupancy rates of at least two processors;
determining a target processor according to the real-time occupancy rate;
and generating control instructions, wherein the control instructions are used for instructing the target processor to execute a target program.
9. An electronic device comprising a memory, at least two processors, and a computer program stored on the memory and executable on any one of the processors, wherein the program execution method of any one of claims 1-7 is implemented when the computer program is executed by any one of the processors.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the program execution method according to any one of claims 1-7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210094874.2A CN116541159A (en) | 2022-01-26 | 2022-01-26 | Program execution method and system, electronic device and storage medium |
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| CN202210094874.2A CN116541159A (en) | 2022-01-26 | 2022-01-26 | Program execution method and system, electronic device and storage medium |
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| CN116541159A true CN116541159A (en) | 2023-08-04 |
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