CN116541151A - Thread scheduling method, device, electronic equipment and medium - Google Patents

Thread scheduling method, device, electronic equipment and medium Download PDF

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Publication number
CN116541151A
CN116541151A CN202310636399.1A CN202310636399A CN116541151A CN 116541151 A CN116541151 A CN 116541151A CN 202310636399 A CN202310636399 A CN 202310636399A CN 116541151 A CN116541151 A CN 116541151A
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China
Prior art keywords
processor core
thread
target
scheduling
information
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CN202310636399.1A
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Chinese (zh)
Inventor
王彤伟
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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Priority to CN202310636399.1A priority Critical patent/CN116541151A/en
Publication of CN116541151A publication Critical patent/CN116541151A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/451—Execution arrangements for user interfaces
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/5018—Thread allocation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application discloses a thread scheduling method, a thread scheduling device, electronic equipment and a thread scheduling medium, and belongs to the field of communication. The thread scheduling method comprises the following steps: acquiring first information under the condition of displaying a user interface of a target application; scheduling a target thread from a first processor core to a second processor core for running under the condition that the first information indicates that the user interface of the target application is in an interface updating state, wherein the target thread is used for displaying the user interface of the target application; wherein the operating frequency of the first processor core is less than the operating frequency of the second processor core.

Description

Thread scheduling method, device, electronic equipment and medium
Technical Field
The application belongs to the field of communication, and particularly relates to a thread scheduling method, a thread scheduling device, electronic equipment and a thread scheduling medium.
Background
Generally, in a scenario where a user views a user interface using an electronic device, the electronic device may schedule a related thread that displays the user interface to a small core for processing, thereby processing a process that displays the user interface to display content of the user interface.
However, in the related art, there is a problem in that a jam occurs in a process in which a user views a user interface using an electronic device.
Disclosure of Invention
The embodiment of the application aims to provide a thread scheduling method, a thread scheduling device, electronic equipment and a thread scheduling medium, which can improve the smoothness of a user interface displayed by the electronic equipment.
In a first aspect, an embodiment of the present application provides a thread scheduling method, where the method includes: acquiring first information under the condition of displaying a user interface of a target application; scheduling a target thread from a first processor core to a second processor core for running under the condition that the first information indicates that the user interface of the target application is in an interface updating state, wherein the target thread is used for displaying the user interface of the target application; wherein the operating frequency of the first processor core is less than the operating frequency of the second processor core.
In a second aspect, an embodiment of the present application provides a thread scheduling apparatus, including: the device comprises an acquisition module and a scheduling module, wherein: the acquisition module is used for acquiring the first information under the condition of displaying the user interface of the target application; the scheduling module is used for scheduling a target thread from a first processor core to a second processor core for running when the first information acquired by the acquiring module indicates that the user interface of the target application is in an interface updating state, and the target thread is used for displaying the user interface of the target application; wherein the operating frequency of the first processor core is less than the operating frequency of the second processor core.
In a third aspect, embodiments of the present application provide an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method as in the first aspect.
In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement the steps of the method as in the first aspect.
In a fifth aspect, embodiments of the present application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being configured to execute programs or instructions to implement a method as in the first aspect.
In a sixth aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement a method as in the first aspect.
In this embodiment of the present application, the electronic device may obtain first information when displaying a user interface of a target application, and schedule, when the first information indicates that the user interface of the target application is in an interface update state, a target thread to run on a second processor core from a first processor core, where the target thread is used to display the user interface of the target application, and a working frequency of the first processor core is less than a working frequency of the second processor core. Based on the scheme, the target thread is scheduled to run on the second processor core with higher working frequency, so that the problem that a user interface of the target application is blocked in the updating process can be avoided, and the fluency of the electronic equipment in the process of displaying the user interface is improved.
Drawings
FIG. 1 is a schematic flow chart of a thread scheduling method according to an embodiment of the present application;
FIG. 2 is a second flow chart of a thread scheduling method according to the embodiment of the present application;
FIG. 3 is a third flow chart of a thread scheduling method according to the embodiment of the present application;
FIG. 4 is a flowchart illustrating a thread scheduling method according to an embodiment of the present disclosure;
FIG. 5 is a fifth flow chart of a thread scheduling method according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a thread scheduler according to an embodiment of the present disclosure;
FIG. 7 is a second schematic diagram of a thread scheduler according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
fig. 9 is a schematic hardware diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application are within the scope of the protection of the present application.
Terms related to embodiments of the present application will be described below.
With the development of electronic device technology, the architecture design of a central processing unit (Central Processing Unit, CPU) as a core component of an electronic device is also becoming more and more diversified, and currently, the architecture design of the CPU may include an oversized core, a large core and a small core. The oversized core has the strongest performance, highest power and highest working frequency, and secondly the oversized core is the small core, so that the oversized core and the large core can accelerate task processing speed and are responsible for running some high-load scenes, such as: running multiple applications simultaneously, running gaming applications, etc. The corelet is responsible for running some low load scenarios, such as: networking of applications, background running, etc.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or otherwise described herein, and that the objects identified by "first," "second," etc. are generally of a type and do not limit the number of objects, for example, the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The thread scheduling method, the thread scheduling device, the electronic equipment and the medium provided by the embodiment of the application are described in detail below through specific embodiments and application scenes thereof with reference to the accompanying drawings.
The thread scheduling method provided by the embodiment of the application is applied to a scene that a certain application user interface is blocked in an updated state, and the specific application scene can be determined according to the use requirement, so that the application is not limited.
In general, in a scenario where a user views a user interface, such as a web page, using an electronic device, the electronic device may schedule relevant threads for displaying the web page to a small core for processing, thereby processing the progress of displaying the web page to display the page content of the web page. However, in the process of viewing the web page by the user using the electronic device, a situation that the user slides the list quickly may occur, and at this time, it may take a long time to display the content of the page after sliding, so that a jam may occur in the process of sliding the page.
In this embodiment of the present application, the electronic device may obtain first information when displaying a user interface of a target application, and schedule, when the first information indicates that the user interface of the target application is in an interface update state, a target thread to run on a second processor core from a first processor core, where the target thread is used to display the user interface of the target application, and a working frequency of the first processor core is less than a working frequency of the second processor core. Based on the scheme, the target thread is scheduled to run on the second processor core with higher working frequency, so that the problem that a user interface of the target application is blocked in the updating process can be avoided, and the fluency of the electronic equipment in the process of displaying the user interface is improved.
The execution main body of the thread scheduling method provided by the embodiment of the invention can be electronic equipment, and also can be a functional module and/or a functional entity capable of realizing the thread scheduling method in the electronic equipment, and the technical scheme provided by the embodiment of the application will be described by taking the electronic equipment as an example.
An embodiment of the present application provides a thread scheduling method, as shown in fig. 1, the thread scheduling method may include the following steps 201 and 202:
step 201: and the electronic equipment acquires the first information under the condition of displaying the user interface of the target application.
In this embodiment of the present application, the first information is used to indicate an interface update status of a user interface of a target application.
In some embodiments of the present application, the first information includes: the first operating frequency of the first processor core, the first interface information and the second interface information of the user interface.
The first interface information and the second interface information are interface information of a user interface of the target application, which are acquired at different times.
In this embodiment of the present application, the target application may be an application running in the foreground.
In some embodiments of the present application, the target application may be any one of the following: video class applications, communication class applications, editing class applications, search class applications, document class applications, and the like.
In some embodiments of the present application, the user interface may be a page including list content in the target application or an interface including a scroll bar.
In this embodiment of the present invention, the electronic device may, when displaying the desktop, obtain the first information according to a click input of an application identifier of the target application by the user, for example, a click input of an application icon of the target application, so that the electronic device displays a user interface corresponding to the target application.
Step 202: and the electronic equipment dispatches the target thread from the first processor core to the second processor core for running under the condition that the first information indicates that the user interface of the target application is in an interface updating state.
In this embodiment of the present application, the target thread is used to display a user interface of a target application.
In this embodiment of the present application, the operating frequency of the first processor core is smaller than the operating frequency of the second processor core.
In some embodiments of the present application, the CPU may include at least two processor cores. It will be appreciated that the processor core described above is the core of the CPU.
In an embodiment of the present application, the at least two processor cores may be at least one first processor core, at least one second processor core, and at least one third processor core.
In this embodiment of the present application, the operating frequency of the first processor core is greater than the operating frequency of the third processor core.
It should be noted that, if the electronic device determines that the user interface of the target application is in a high-load scenario such as an interface update state, for example, in a process of the user rapidly sliding the user interface of the target application, the processing may be performed by the second processor core with a higher working frequency, so as to improve the processing performance of the CPU; if the electronic device determines that the target application is in a low-load scene such as background running, for example, the application program is in a networking process, the target application can be processed through the second processor core or the third processor core with lower working frequency, so that the efficiency of the CPU is improved.
In the embodiment of the application, the electronic device may run the thread related to the starting of the target application through the first processor core or the third processor core of the CPU under the condition of starting the running target application, so that a user interface of the target application may be displayed.
In this embodiment of the present application, the first information indicates that the user interface of the target application is in an interface update state, for example, the user interface of the target application may be in a sliding state.
In this embodiment of the present application, the operating frequency is an actual frequency of the processor core when it is currently running.
In some embodiments of the present application, the above-described operating frequency may be associated with at least one of: computing power, transient response capability, power consumption, etc.
It will be appreciated that the higher the operating frequency of the processor core, the higher the computing power, transient response capability, and power consumption of the processor core.
It should be noted that, when the electronic device determines that the user interface of the target application is in the updated state, the electronic device obtains a target thread displaying the user interface of the target application, and then dispatches the target thread from the first processor core to the second processor core for running.
In this embodiment of the present invention, the electronic device may obtain first information when displaying the user interface of the target application, and determine whether the user interface of the target application is in an interface update state based on the first information, if the user interface of the target application is in the interface update state, it indicates that the target application is in a high-load running scenario, if the first processor core with a lower working frequency is continuously adopted, a situation that the computing power and the transient response capability of the target thread displaying the user interface of the target application and the CPU are not matched may occur, so that the updated user interface needs to be displayed for a long time, and therefore, the target thread is scheduled to be run on the second processor core by the first processor core when the first information indicates that the user interface of the target application is in the interface update state, so as to improve the performance of the CPU.
Optionally, in an embodiment of the present application, as shown in fig. 2, the first information includes: the step 202 may be implemented by the following step 202a1, specifically, at the first operating frequency of the first processor core:
step 202a1: and the electronic equipment dispatches the target thread from the first processor core to the second processor core for running under the condition that the first working frequency is greater than or equal to the second working frequency.
In this embodiment of the present application, the second operating frequency includes any one of the following: the method comprises the steps of presetting a working frequency and obtaining the working frequency of a first processor core before the first working frequency.
In some embodiments of the present application, the preset frequency may be an operating frequency when the CPU of the electronic device cannot smoothly process the multithreaded task.
In this embodiment of the present application, if the first operating frequency of the first processor core is greater than or equal to the second operating frequency, the user interface of the target application may be considered to be in an interface update state.
Optionally, in this embodiment of the present application, as shown in fig. 3, the first information includes first interface information and second interface information of a user interface, where the first interface information and the second interface information are interface information of a user interface of a target application acquired at different moments, and the step 202 may be specifically implemented by the following step 202b1:
step 202b1: and the electronic equipment dispatches the target thread from the first processor core to the second processor core for running under the condition that the first interface information and the second interface information are not matched.
In some embodiments of the present application, the time of acquiring the first interface information may be earlier than the time of acquiring the second interface information, or may be later than the time of acquiring the second interface information.
In this embodiment of the present application, the first interface information and the second interface information are not matched, which may be understood that the first interface information and the second interface information are different.
In the embodiment of the application, if the first interface information and the second interface information are not matched, it is indicated that the user interface of the target application is in an interface update state.
It should be noted that, when the user interface of the target application is in the updated state, the user performs the sliding input on the user interface of the target application, so that the first interface information and the second interface information of the user interface of the target application, which are acquired by the electronic device at different times, are not matched, that is, the user interface of the target application is in the updated state.
In this embodiment of the present application, the electronic device may obtain first information when displaying a user interface of a target application, and schedule, when the first information indicates that the user interface of the target application is in an interface update state, a target thread to run on a second processor core from a first processor core, where the target thread is used to display the user interface of the target application, and a working frequency of the first processor core is less than a working frequency of the second processor core. Based on the scheme, the target thread is scheduled to run on the second processor core with higher working frequency, so that the problem that a user interface of the target application is blocked in the updating process can be avoided, and the fluency of the electronic equipment in the process of displaying the user interface is improved.
Optionally, in an embodiment of the present application, the "target thread" in step 202 may include at least one of the following: a main thread and a rendering thread.
In this embodiment of the present application, the main thread is used for obtaining a thread of related data of display content in an application page, and the rendering thread is used for rendering the display content in the application page. The main thread and the rendering thread are synchronous, and the electronic device acquires the main thread and the rendering thread at the same time, in other words, the electronic device acquires the rendering thread and the main thread at the same time.
In the embodiment of the application, the electronic device may acquire the target thread according to the thread identifier.
Optionally, in the embodiment of the present application, as shown in fig. 4, before "scheduling the target thread to run on the second processor core by the first processor core" in step 202, the thread scheduling method provided in the embodiment of the present application further includes the following steps 301 and 302:
step 301: and the electronic equipment acquires the target thread identification under the condition that the first information indicates that the user interface of the target application is in an interface updating state.
In this embodiment of the present application, the target thread identifier is used to indicate a target thread.
In some embodiments of the present application, the target thread identification may include at least one of: target thread ID, target thread number, etc.
Step 302: and the electronic equipment acquires the target thread according to the target thread identification.
In the embodiment of the application, one thread identifier corresponds to one thread.
In some embodiments of the present application, the electronic device may obtain all thread identifiers related to the target application from the CPU, obtain, based on the thread identifiers, a target thread identifier for displaying a user interface of the target application, and then determine a target thread according to the target thread identifier.
Therefore, the electronic device can acquire the target thread according to the target thread identification, so that the target thread used for displaying the user interface of the target application can be accurately found out from the multiple threads, and the accuracy of acquiring the target thread by the electronic device can be improved.
Optionally, in the embodiment of the present application, as shown in fig. 5, before "scheduling the target thread to run on the second processor core by the first processor core" in step 202, the thread scheduling method provided in the embodiment of the present application further includes the following step 401:
step 401: and the electronic equipment increases the first priority of the target thread under the condition that the first information indicates that the user interface of the target application is in an interface updating state.
In an embodiment of the present application, the first priority includes at least one of: scheduling priority of execution scheduled to the second processor core, execution priority after being scheduled to the second processor core.
Example 1, the electronic device increases a scheduling priority of a target thread for displaying a user interface of a target application, that is, increases a scheduling priority of the target thread scheduled to run on a second processor core before scheduling the target thread to run on the second processor core, in a case where the user interface of the target application is in an updated state, so that the target thread may be scheduled to run on the second processor core preferentially.
Example 2, the electronic device increases the execution priority of the target thread for displaying the user interface of the target application in a case where the user interface of the target application is in an updated state, that is, increases the priority of execution of the target thread on the second processor core after the target thread is scheduled to the second processor core, so that the target thread may execute preferentially on the second processor core.
As such, the electronic device may prioritize the target thread such that the target thread may be preferentially scheduled to run on the second processor core or preferentially run on the second processor core. Therefore, task scheduling response corresponding to the target thread can be accelerated, and computational power of the second processor core is fully supported, so that task execution speed corresponding to the target thread of the electronic equipment is improved.
Optionally, in the embodiment of the present application, the CPU further includes a third processor core, and after step 201, the thread scheduling method provided in the embodiment of the present application further includes the following step 501.
Step 501: and the electronic equipment dispatches the target thread from the first processor core to the third processor core for running under the condition that the first information indicates that the user interface of the target application is not in an interface updating state.
In this embodiment of the present application, the operating frequency of the third processor core is smaller than the operating frequency of the first processor core.
In this embodiment of the present application, the first information indicates that the user interface of the target application is not in an interface update state, which may be understood that the first information indicates that the user interface of the target application is in an interface static state.
In some embodiments of the present application, the first information includes a first operating frequency of the first processor core, and if the first operating frequency is less than the second operating frequency, it indicates that the user interface of the target application is not in the interface update state.
In some embodiments of the present application, the first information includes first interface information and second interface information, and if the first interface information does not match the second interface information, it indicates that the user interface of the target application is not in an interface update state.
In some embodiments of the present application, if the first information indicates that the user interface of the target application is not in the interface update state, the first priority of the target thread may be adjusted down, so that the power consumption of the CPU may be reduced.
Therefore, the electronic device schedules the target thread from the first processor core to the third processor core with the working frequency smaller than that of the first processor core to run under the condition that the first information indicates that the user interface of the target application is not in the interface updating state, so that the power consumption of the CPU can be reduced under the condition that the CPU processes the thread tasks orderly.
According to the thread scheduling method provided by the embodiment of the application, the execution main body can be a thread scheduling device. In the embodiment of the present application, a thread scheduling device provided in the embodiment of the present application is described by taking a method for executing a thread scheduling by a thread scheduling device as an example.
An embodiment of the present application provides a thread scheduling apparatus, as shown in fig. 6, the thread scheduling apparatus 400 includes: an acquisition module 401 and a scheduling module 402, wherein: the acquiring module 401 is configured to acquire first information when a user interface of a target application is displayed; the scheduling module 402 is configured to schedule, when the first information obtained by the obtaining module indicates that the user interface of the target application is in an interface update state, a target thread to run on the second processor core from the first processor core, where the target thread is used to display the user interface of the target application; wherein the operating frequency of the first processor core is less than the operating frequency of the second processor core.
According to the thread scheduling device provided by the embodiment of the application, the target thread is scheduled to run on the second processor core with higher working frequency, so that the problem that a user interface of a target application is blocked in the updating process can be avoided, and the fluency of the electronic equipment in the process of displaying the user interface is improved.
Optionally, in an embodiment of the present application, the first information includes a first operating frequency of the first processor core; the scheduling module 402 is specifically configured to schedule, when the first operating frequency is greater than or equal to the second operating frequency, the target thread from the first processor core to run on the second processor core; wherein the second operating frequency comprises any one of: the method comprises the steps of presetting a working frequency and obtaining the working frequency of a first processor core before the first working frequency.
Optionally, in this embodiment of the present application, the first information includes first interface information and second interface information of a user interface, where the first interface information and the second interface information are interface information of a user interface of a target application acquired at different moments; the scheduling module 402 is specifically configured to schedule, when the first interface information and the second interface information are not matched, the target thread from the first processor core to the second processor core for running.
Optionally, in an embodiment of the present application, the target thread includes at least one of: a main thread and a rendering thread.
Optionally, in the embodiment of the present application, the obtaining module 401 is further configured to obtain the target thread identifier before the target thread is scheduled to run on the second processor core by the first processor core; acquiring a target thread according to the target thread identification; the target thread identification is used to indicate the target thread.
Therefore, the thread scheduling device can acquire the target thread according to the target thread identification, so that the target thread used for displaying the user interface of the target application can be accurately found out from the plurality of threads, and the accuracy of the thread scheduling device in acquiring the target thread can be improved.
Optionally, in an embodiment of the present application, as shown in fig. 7, the apparatus further includes: a raising module 403, where the raising module 403 is configured to raise a first priority of a target thread before the target thread is scheduled to run on a second processor core by a first processor core; wherein the first priority comprises at least one of: scheduling priority of execution scheduled to the second processor core, execution priority after being scheduled to the second processor core.
As such, the thread scheduler may be configured to prioritize the target thread such that the target thread may be preferentially scheduled to run on the second processor core or preferentially run on the second processor core. Therefore, the task scheduling response corresponding to the target thread can be accelerated, and the computational power of the second processor core is fully supported, so that the task execution speed corresponding to the target thread of the thread scheduling device is improved.
The thread scheduling device in the embodiment of the application may be an electronic device, or may be a component in the electronic device, for example, an integrated circuit or a chip. The electronic device may be a terminal, or may be other devices than a terminal. By way of example, the electronic device may be a mobile phone, tablet computer, notebook computer, palm computer, vehicle-mounted electronic device, mobile internet appliance (Mobile Internet Device, MID), augmented reality (augmented reality, AR)/Virtual Reality (VR) device, robot, wearable device, ultra-mobile personal computer, UMPC, netbook or personal digital assistant (personal digital assistant, PDA), etc., but may also be a server, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (TV), teller machine or self-service machine, etc., and the embodiments of the present application are not limited in particular.
The thread scheduling device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiments of the present application.
The thread scheduling device provided in the embodiment of the present application can implement each process implemented by the above method embodiment, and can achieve the same technical effect, so that repetition is avoided, and details are not repeated here.
Optionally, as shown in fig. 8, the embodiment of the present application further provides an electronic device 600, including a processor 601 and a memory 602, where a program or an instruction capable of running on the processor 601 is stored in the memory 602, and the program or the instruction implements each step of the above-mentioned thread scheduling method embodiment when executed by the processor 601, and the steps can achieve the same technical effect, so that repetition is avoided, and no further description is given here.
The electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device.
Fig. 8 is a schematic hardware structure of an electronic device implementing an embodiment of the present application.
The electronic device 100 includes, but is not limited to: radio frequency unit 101, network module 102, audio output unit 103, input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, and processor 110.
Those skilled in the art will appreciate that the electronic device 100 may further include a power source (e.g., a battery) for powering the various components, and that the power source may be logically coupled to the processor 110 via a power management system to perform functions such as managing charging, discharging, and power consumption via the power management system. The electronic device structure shown in fig. 9 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than shown, or may combine certain components, or may be arranged in different components, which are not described in detail herein.
Wherein, the processor 110 is configured to obtain the first information when a user interface of the target application is displayed; under the condition that the first information indicates that the user interface of the target application is in an interface updating state, scheduling a target thread from a first processor core to a second processor core for running, wherein the target thread is used for displaying the user interface of the target application; wherein the operating frequency of the first processor core is less than the operating frequency of the second processor core.
According to the electronic device provided by the embodiment of the application, the target thread is scheduled to run on the second processor core with higher working frequency, so that the problem that a user interface of a target application is blocked in the updating process can be avoided, and the fluency of the electronic device in the process of displaying the user interface is improved.
Optionally, in an embodiment of the present application, the first information includes a first operating frequency of the first processor core; the processor 110 is specifically configured to schedule, when the first operating frequency is greater than or equal to the second operating frequency, the target thread from the first processor core to the second processor core for running; wherein the second operating frequency comprises any one of: the method comprises the steps of presetting a working frequency and obtaining the working frequency of a first processor core before the first working frequency.
Optionally, in this embodiment of the present application, the first information includes first interface information and second interface information of a user interface, where the first interface information and the second interface information are interface information of a user interface of a target application acquired at different moments; the processor 110 is specifically configured to schedule the target thread from the first processor core to run on the second processor core when the first interface information and the second interface information are not matched.
Optionally, in an embodiment of the present application, the target thread includes at least one of: a main thread and a rendering thread.
Optionally, in an embodiment of the present application, the processor 110 is further configured to obtain a target thread identifier before the target thread is scheduled to run on the second processor core by the first processor core; acquiring a target thread according to the target thread identification; the target thread identification is used to indicate the target thread.
Therefore, the electronic device can acquire the target thread according to the target thread identification, so that the target thread used for displaying the user interface of the target application can be accurately found out from the multiple threads, and the accuracy of acquiring the target thread by the electronic device can be improved.
Optionally, in an embodiment of the present application, the processor 110 is further configured to, before scheduling the target thread to run on the second processor core by the first processor core, raise a first priority of the target thread; wherein the first priority comprises at least one of: scheduling priority of execution scheduled to the second processor core, execution priority after being scheduled to the second processor core.
As such, the electronic device may prioritize the target thread such that the target thread may be preferentially scheduled to run on the second processor core or preferentially run on the second processor core. Therefore, task scheduling response corresponding to the target thread can be accelerated, and computational power of the second processor core is fully supported, so that task execution speed corresponding to the target thread of the electronic equipment is improved.
It should be appreciated that in embodiments of the present application, the input unit 104 may include a graphics processor (Graphics Processing Unit, GPU) 1041 and a microphone 1042, the graphics processor 1041 processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also referred to as a touch screen. The touch panel 1071 may include two parts of a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein.
Memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a first memory area storing programs or instructions and a second memory area storing data, wherein the first memory area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 109 may include volatile memory or nonvolatile memory, or the memory 109 may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (ddr SDRAM), enhanced SDRAM (Enhanced SDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DRRAM). Memory 109 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.
Processor 110 may include one or more processing units; optionally, the processor 110 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, etc., and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 110.
The embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored, and when the program or the instruction is executed by a processor, the program or the instruction implements each process of the embodiment of the thread scheduling method, and the same technical effect can be achieved, so that repetition is avoided, and no redundant description is provided herein.
Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes computer readable storage medium such as computer readable memory ROM, random access memory RAM, magnetic or optical disk, etc.
The embodiment of the application further provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled with the processor, and the processor is used for running a program or an instruction, so as to implement each process of the above thread scheduling method embodiment, and achieve the same technical effect, so that repetition is avoided, and no redundant description is provided here.
It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.
The embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the respective processes of the embodiments of the thread scheduling method described above, and achieve the same technical effects, and are not repeated herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solutions of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), comprising several instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the methods described in the embodiments of the present application.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.

Claims (14)

1. A method of thread scheduling, the method comprising:
acquiring first information under the condition of displaying a user interface of a target application;
scheduling a target thread from a first processor core to a second processor core for running under the condition that the first information indicates that the user interface of the target application is in an interface updating state, wherein the target thread is used for displaying the user interface of the target application;
wherein the operating frequency of the first processor core is less than the operating frequency of the second processor core.
2. The method of claim 1, wherein the first information comprises a first operating frequency of the first processor core;
the scheduling, by the first processor core to run on the second processor core, the target thread if the first information indicates that the user interface of the target application is in an interface update state, includes:
scheduling the target thread from a first processor core to run on the second processor core when the first operating frequency is greater than or equal to a second operating frequency;
wherein the second operating frequency comprises any one of: presetting a working frequency and acquiring the working frequency of the first processor core before the first working frequency.
3. The method of claim 1, wherein the first information includes first interface information and second interface information of the user interface, the first interface information and the second interface information being interface information of a user interface of the target application acquired at different times;
the scheduling, by the first processor core to run on the second processor core, the target thread if the first information indicates that the user interface of the target application is in an interface update state, includes:
and under the condition that the first interface information and the second interface information are not matched, scheduling the target thread to run on a second processor core by the first processor core.
4. The method of claim 1, wherein the target thread comprises at least one of: a main thread and a rendering thread.
5. The method of claim 1, wherein prior to said scheduling the target thread to run on the second processor core by the first processor core, the method further comprises:
acquiring a target thread identifier; the target thread identifier is used for indicating the target thread;
and acquiring the target thread according to the target thread identification.
6. The method of claim 1, wherein prior to said scheduling the target thread to run on a second processor core by a first processor core, the method further comprises;
raising a first priority of the target thread;
wherein the first priority comprises at least one of: scheduling priority of operation scheduled to the second processor core, and operation priority after being scheduled to the second processor core.
7. A thread scheduling apparatus, the apparatus comprising: the device comprises an acquisition module and a scheduling module, wherein:
the acquisition module is used for acquiring first information under the condition of displaying a user interface of a target application;
the scheduling module is used for scheduling a target thread from a first processor core to a second processor core for running when the first information acquired by the acquiring module indicates that the user interface of the target application is in an interface updating state, and the target thread is used for displaying the user interface of the target application;
wherein the operating frequency of the first processor core is less than the operating frequency of the second processor core.
8. The apparatus of claim 7, wherein the first information comprises a first operating frequency of the first processor core;
the scheduling module is specifically configured to schedule, when the first working frequency is greater than or equal to the second working frequency, the target thread to run on the second processor core from the first processor core;
wherein the second operating frequency comprises any one of: presetting a working frequency and acquiring the working frequency of the first processor core before the first working frequency.
9. The apparatus of claim 7, wherein the first information comprises first interface information and second interface information of the user interface, the first interface information and the second interface information being interface information of a user interface of the target application acquired at different times;
the scheduling module is specifically configured to schedule the target thread from the first processor core to the second processor core for running when the first interface information and the second interface information are not matched.
10. The apparatus of claim 7, wherein the target thread comprises at least one of: a main thread and a rendering thread.
11. The apparatus of claim 7, wherein the means for obtaining is further configured to obtain a target thread identification prior to the scheduling the target thread to run on a second processor core by a first processor core; acquiring the target thread according to the target thread identification; the target thread identification is used for indicating the target thread.
12. The apparatus of claim 7, wherein the apparatus further comprises: the heightening module is used for heightening the first priority of the target thread before the target thread is scheduled to run on the second processor core by the first processor core;
wherein the first priority comprises at least one of: scheduling priority of operation scheduled to the second processor core, and operation priority after being scheduled to the second processor core.
13. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the thread scheduling method of any one of claims 1 to 6.
14. A readable storage medium, characterized in that it stores thereon a program or instructions which, when executed by a processor, implement the steps of the thread scheduling method of any one of claims 1 to 6.
CN202310636399.1A 2023-05-31 2023-05-31 Thread scheduling method, device, electronic equipment and medium Pending CN116541151A (en)

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